1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 #include <linux/of_mdio.h> 56 #include "dwmac1000.h" 57 58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 60 61 /* Module parameters */ 62 #define TX_TIMEO 5000 63 static int watchdog = TX_TIMEO; 64 module_param(watchdog, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 66 67 static int debug = -1; 68 module_param(debug, int, S_IRUGO | S_IWUSR); 69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 70 71 static int phyaddr = -1; 72 module_param(phyaddr, int, S_IRUGO); 73 MODULE_PARM_DESC(phyaddr, "Physical device address"); 74 75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 77 78 static int flow_ctrl = FLOW_OFF; 79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 81 82 static int pause = PAUSE_TIME; 83 module_param(pause, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 85 86 #define TC_DEFAULT 64 87 static int tc = TC_DEFAULT; 88 module_param(tc, int, S_IRUGO | S_IWUSR); 89 MODULE_PARM_DESC(tc, "DMA threshold control value"); 90 91 #define DEFAULT_BUFSIZE 1536 92 static int buf_sz = DEFAULT_BUFSIZE; 93 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 94 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 95 96 #define STMMAC_RX_COPYBREAK 256 97 98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 99 NETIF_MSG_LINK | NETIF_MSG_IFUP | 100 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 101 102 #define STMMAC_DEFAULT_LPI_TIMER 1000 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 107 108 /* By default the driver will use the ring mode to manage tx and rx descriptors 109 * but passing this value so user can force to use the chain instead of the ring 110 */ 111 static unsigned int chain_mode; 112 module_param(chain_mode, int, S_IRUGO); 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 114 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 116 117 #ifdef CONFIG_DEBUG_FS 118 static int stmmac_init_fs(struct net_device *dev); 119 static void stmmac_exit_fs(struct net_device *dev); 120 #endif 121 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 123 124 /** 125 * stmmac_verify_args - verify the driver parameters. 126 * Description: it checks the driver parameters and set a default in case of 127 * errors. 128 */ 129 static void stmmac_verify_args(void) 130 { 131 if (unlikely(watchdog < 0)) 132 watchdog = TX_TIMEO; 133 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 134 buf_sz = DEFAULT_BUFSIZE; 135 if (unlikely(flow_ctrl > 1)) 136 flow_ctrl = FLOW_AUTO; 137 else if (likely(flow_ctrl < 0)) 138 flow_ctrl = FLOW_OFF; 139 if (unlikely((pause < 0) || (pause > 0xffff))) 140 pause = PAUSE_TIME; 141 if (eee_timer < 0) 142 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 143 } 144 145 /** 146 * stmmac_clk_csr_set - dynamically set the MDC clock 147 * @priv: driver private structure 148 * Description: this is to dynamically set the MDC clock according to the csr 149 * clock input. 150 * Note: 151 * If a specific clk_csr value is passed from the platform 152 * this means that the CSR Clock Range selection cannot be 153 * changed at run-time and it is fixed (as reported in the driver 154 * documentation). Viceversa the driver will try to set the MDC 155 * clock dynamically according to the actual clock input. 156 */ 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 158 { 159 u32 clk_rate; 160 161 clk_rate = clk_get_rate(priv->stmmac_clk); 162 163 /* Platform provided default clk_csr would be assumed valid 164 * for all other cases except for the below mentioned ones. 165 * For values higher than the IEEE 802.3 specified frequency 166 * we can not estimate the proper divider as it is not known 167 * the frequency of clk_csr_i. So we do not change the default 168 * divider. 169 */ 170 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 171 if (clk_rate < CSR_F_35M) 172 priv->clk_csr = STMMAC_CSR_20_35M; 173 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 174 priv->clk_csr = STMMAC_CSR_35_60M; 175 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 176 priv->clk_csr = STMMAC_CSR_60_100M; 177 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 178 priv->clk_csr = STMMAC_CSR_100_150M; 179 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 180 priv->clk_csr = STMMAC_CSR_150_250M; 181 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 182 priv->clk_csr = STMMAC_CSR_250_300M; 183 } 184 } 185 186 static void print_pkt(unsigned char *buf, int len) 187 { 188 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 190 } 191 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 193 { 194 unsigned avail; 195 196 if (priv->dirty_tx > priv->cur_tx) 197 avail = priv->dirty_tx - priv->cur_tx - 1; 198 else 199 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; 200 201 return avail; 202 } 203 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) 205 { 206 unsigned dirty; 207 208 if (priv->dirty_rx <= priv->cur_rx) 209 dirty = priv->cur_rx - priv->dirty_rx; 210 else 211 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; 212 213 return dirty; 214 } 215 216 /** 217 * stmmac_hw_fix_mac_speed - callback for speed selection 218 * @priv: driver private structure 219 * Description: on some platforms (e.g. ST), some HW system configuraton 220 * registers have to be set according to the link speed negotiated. 221 */ 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 223 { 224 struct net_device *ndev = priv->dev; 225 struct phy_device *phydev = ndev->phydev; 226 227 if (likely(priv->plat->fix_mac_speed)) 228 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 229 } 230 231 /** 232 * stmmac_enable_eee_mode - check and enter in LPI mode 233 * @priv: driver private structure 234 * Description: this function is to verify and enter in LPI mode in case of 235 * EEE. 236 */ 237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 238 { 239 /* Check and enter in LPI mode */ 240 if ((priv->dirty_tx == priv->cur_tx) && 241 (priv->tx_path_in_lpi_mode == false)) 242 priv->hw->mac->set_eee_mode(priv->hw); 243 } 244 245 /** 246 * stmmac_disable_eee_mode - disable and exit from LPI mode 247 * @priv: driver private structure 248 * Description: this function is to exit and disable EEE in case of 249 * LPI state is true. This is called by the xmit. 250 */ 251 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 252 { 253 priv->hw->mac->reset_eee_mode(priv->hw); 254 del_timer_sync(&priv->eee_ctrl_timer); 255 priv->tx_path_in_lpi_mode = false; 256 } 257 258 /** 259 * stmmac_eee_ctrl_timer - EEE TX SW timer. 260 * @arg : data hook 261 * Description: 262 * if there is no data transfer and if we are not in LPI state, 263 * then MAC Transmitter can be moved to LPI state. 264 */ 265 static void stmmac_eee_ctrl_timer(unsigned long arg) 266 { 267 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 268 269 stmmac_enable_eee_mode(priv); 270 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 271 } 272 273 /** 274 * stmmac_eee_init - init EEE 275 * @priv: driver private structure 276 * Description: 277 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 278 * can also manage EEE, this function enable the LPI state and start related 279 * timer. 280 */ 281 bool stmmac_eee_init(struct stmmac_priv *priv) 282 { 283 struct net_device *ndev = priv->dev; 284 unsigned long flags; 285 bool ret = false; 286 287 /* Using PCS we cannot dial with the phy registers at this stage 288 * so we do not support extra feature like EEE. 289 */ 290 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 291 (priv->hw->pcs == STMMAC_PCS_TBI) || 292 (priv->hw->pcs == STMMAC_PCS_RTBI)) 293 goto out; 294 295 /* MAC core supports the EEE feature. */ 296 if (priv->dma_cap.eee) { 297 int tx_lpi_timer = priv->tx_lpi_timer; 298 299 /* Check if the PHY supports EEE */ 300 if (phy_init_eee(ndev->phydev, 1)) { 301 /* To manage at run-time if the EEE cannot be supported 302 * anymore (for example because the lp caps have been 303 * changed). 304 * In that case the driver disable own timers. 305 */ 306 spin_lock_irqsave(&priv->lock, flags); 307 if (priv->eee_active) { 308 pr_debug("stmmac: disable EEE\n"); 309 del_timer_sync(&priv->eee_ctrl_timer); 310 priv->hw->mac->set_eee_timer(priv->hw, 0, 311 tx_lpi_timer); 312 } 313 priv->eee_active = 0; 314 spin_unlock_irqrestore(&priv->lock, flags); 315 goto out; 316 } 317 /* Activate the EEE and start timers */ 318 spin_lock_irqsave(&priv->lock, flags); 319 if (!priv->eee_active) { 320 priv->eee_active = 1; 321 setup_timer(&priv->eee_ctrl_timer, 322 stmmac_eee_ctrl_timer, 323 (unsigned long)priv); 324 mod_timer(&priv->eee_ctrl_timer, 325 STMMAC_LPI_T(eee_timer)); 326 327 priv->hw->mac->set_eee_timer(priv->hw, 328 STMMAC_DEFAULT_LIT_LS, 329 tx_lpi_timer); 330 } 331 /* Set HW EEE according to the speed */ 332 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link); 333 334 ret = true; 335 spin_unlock_irqrestore(&priv->lock, flags); 336 337 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 338 } 339 out: 340 return ret; 341 } 342 343 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 344 * @priv: driver private structure 345 * @entry : descriptor index to be used. 346 * @skb : the socket buffer 347 * Description : 348 * This function will read timestamp from the descriptor & pass it to stack. 349 * and also perform some sanity checks. 350 */ 351 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 352 unsigned int entry, struct sk_buff *skb) 353 { 354 struct skb_shared_hwtstamps shhwtstamp; 355 u64 ns; 356 void *desc = NULL; 357 358 if (!priv->hwts_tx_en) 359 return; 360 361 /* exit if skb doesn't support hw tstamp */ 362 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 363 return; 364 365 if (priv->adv_ts) 366 desc = (priv->dma_etx + entry); 367 else 368 desc = (priv->dma_tx + entry); 369 370 /* check tx tstamp status */ 371 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 372 return; 373 374 /* get the valid tstamp */ 375 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 376 377 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 378 shhwtstamp.hwtstamp = ns_to_ktime(ns); 379 /* pass tstamp to stack */ 380 skb_tstamp_tx(skb, &shhwtstamp); 381 382 return; 383 } 384 385 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 386 * @priv: driver private structure 387 * @entry : descriptor index to be used. 388 * @skb : the socket buffer 389 * Description : 390 * This function will read received packet's timestamp from the descriptor 391 * and pass it to stack. It also perform some sanity checks. 392 */ 393 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 394 unsigned int entry, struct sk_buff *skb) 395 { 396 struct skb_shared_hwtstamps *shhwtstamp = NULL; 397 u64 ns; 398 void *desc = NULL; 399 400 if (!priv->hwts_rx_en) 401 return; 402 403 if (priv->adv_ts) 404 desc = (priv->dma_erx + entry); 405 else 406 desc = (priv->dma_rx + entry); 407 408 /* exit if rx tstamp is not valid */ 409 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 410 return; 411 412 /* get valid tstamp */ 413 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 414 shhwtstamp = skb_hwtstamps(skb); 415 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 416 shhwtstamp->hwtstamp = ns_to_ktime(ns); 417 } 418 419 /** 420 * stmmac_hwtstamp_ioctl - control hardware timestamping. 421 * @dev: device pointer. 422 * @ifr: An IOCTL specefic structure, that can contain a pointer to 423 * a proprietary structure used to pass information to the driver. 424 * Description: 425 * This function configures the MAC to enable/disable both outgoing(TX) 426 * and incoming(RX) packets time stamping based on user input. 427 * Return Value: 428 * 0 on success and an appropriate -ve integer on failure. 429 */ 430 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 431 { 432 struct stmmac_priv *priv = netdev_priv(dev); 433 struct hwtstamp_config config; 434 struct timespec64 now; 435 u64 temp = 0; 436 u32 ptp_v2 = 0; 437 u32 tstamp_all = 0; 438 u32 ptp_over_ipv4_udp = 0; 439 u32 ptp_over_ipv6_udp = 0; 440 u32 ptp_over_ethernet = 0; 441 u32 snap_type_sel = 0; 442 u32 ts_master_en = 0; 443 u32 ts_event_en = 0; 444 u32 value = 0; 445 u32 sec_inc; 446 447 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 448 netdev_alert(priv->dev, "No support for HW time stamping\n"); 449 priv->hwts_tx_en = 0; 450 priv->hwts_rx_en = 0; 451 452 return -EOPNOTSUPP; 453 } 454 455 if (copy_from_user(&config, ifr->ifr_data, 456 sizeof(struct hwtstamp_config))) 457 return -EFAULT; 458 459 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 460 __func__, config.flags, config.tx_type, config.rx_filter); 461 462 /* reserved for future extensions */ 463 if (config.flags) 464 return -EINVAL; 465 466 if (config.tx_type != HWTSTAMP_TX_OFF && 467 config.tx_type != HWTSTAMP_TX_ON) 468 return -ERANGE; 469 470 if (priv->adv_ts) { 471 switch (config.rx_filter) { 472 case HWTSTAMP_FILTER_NONE: 473 /* time stamp no incoming packet at all */ 474 config.rx_filter = HWTSTAMP_FILTER_NONE; 475 break; 476 477 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 478 /* PTP v1, UDP, any kind of event packet */ 479 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 480 /* take time stamp for all event messages */ 481 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 482 483 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 484 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 485 break; 486 487 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 488 /* PTP v1, UDP, Sync packet */ 489 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 490 /* take time stamp for SYNC messages only */ 491 ts_event_en = PTP_TCR_TSEVNTENA; 492 493 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 494 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 495 break; 496 497 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 498 /* PTP v1, UDP, Delay_req packet */ 499 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 500 /* take time stamp for Delay_Req messages only */ 501 ts_master_en = PTP_TCR_TSMSTRENA; 502 ts_event_en = PTP_TCR_TSEVNTENA; 503 504 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 505 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 506 break; 507 508 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 509 /* PTP v2, UDP, any kind of event packet */ 510 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 511 ptp_v2 = PTP_TCR_TSVER2ENA; 512 /* take time stamp for all event messages */ 513 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 514 515 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 516 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 517 break; 518 519 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 520 /* PTP v2, UDP, Sync packet */ 521 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 522 ptp_v2 = PTP_TCR_TSVER2ENA; 523 /* take time stamp for SYNC messages only */ 524 ts_event_en = PTP_TCR_TSEVNTENA; 525 526 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 527 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 528 break; 529 530 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 531 /* PTP v2, UDP, Delay_req packet */ 532 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 533 ptp_v2 = PTP_TCR_TSVER2ENA; 534 /* take time stamp for Delay_Req messages only */ 535 ts_master_en = PTP_TCR_TSMSTRENA; 536 ts_event_en = PTP_TCR_TSEVNTENA; 537 538 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 539 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 540 break; 541 542 case HWTSTAMP_FILTER_PTP_V2_EVENT: 543 /* PTP v2/802.AS1 any layer, any kind of event packet */ 544 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 545 ptp_v2 = PTP_TCR_TSVER2ENA; 546 /* take time stamp for all event messages */ 547 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 548 549 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 550 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 551 ptp_over_ethernet = PTP_TCR_TSIPENA; 552 break; 553 554 case HWTSTAMP_FILTER_PTP_V2_SYNC: 555 /* PTP v2/802.AS1, any layer, Sync packet */ 556 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 557 ptp_v2 = PTP_TCR_TSVER2ENA; 558 /* take time stamp for SYNC messages only */ 559 ts_event_en = PTP_TCR_TSEVNTENA; 560 561 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 562 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 563 ptp_over_ethernet = PTP_TCR_TSIPENA; 564 break; 565 566 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 567 /* PTP v2/802.AS1, any layer, Delay_req packet */ 568 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 569 ptp_v2 = PTP_TCR_TSVER2ENA; 570 /* take time stamp for Delay_Req messages only */ 571 ts_master_en = PTP_TCR_TSMSTRENA; 572 ts_event_en = PTP_TCR_TSEVNTENA; 573 574 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 575 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 576 ptp_over_ethernet = PTP_TCR_TSIPENA; 577 break; 578 579 case HWTSTAMP_FILTER_ALL: 580 /* time stamp any incoming packet */ 581 config.rx_filter = HWTSTAMP_FILTER_ALL; 582 tstamp_all = PTP_TCR_TSENALL; 583 break; 584 585 default: 586 return -ERANGE; 587 } 588 } else { 589 switch (config.rx_filter) { 590 case HWTSTAMP_FILTER_NONE: 591 config.rx_filter = HWTSTAMP_FILTER_NONE; 592 break; 593 default: 594 /* PTP v1, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 596 break; 597 } 598 } 599 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 600 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 601 602 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 603 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 604 else { 605 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 606 tstamp_all | ptp_v2 | ptp_over_ethernet | 607 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 608 ts_master_en | snap_type_sel); 609 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 610 611 /* program Sub Second Increment reg */ 612 sec_inc = priv->hw->ptp->config_sub_second_increment( 613 priv->ioaddr, priv->clk_ptp_rate); 614 temp = div_u64(1000000000ULL, sec_inc); 615 616 /* calculate default added value: 617 * formula is : 618 * addend = (2^32)/freq_div_ratio; 619 * where, freq_div_ratio = 1e9ns/sec_inc 620 */ 621 temp = (u64)(temp << 32); 622 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 623 priv->hw->ptp->config_addend(priv->ioaddr, 624 priv->default_addend); 625 626 /* initialize system time */ 627 ktime_get_real_ts64(&now); 628 629 /* lower 32 bits of tv_sec are safe until y2106 */ 630 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec, 631 now.tv_nsec); 632 } 633 634 return copy_to_user(ifr->ifr_data, &config, 635 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 636 } 637 638 /** 639 * stmmac_init_ptp - init PTP 640 * @priv: driver private structure 641 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 642 * This is done by looking at the HW cap. register. 643 * This function also registers the ptp driver. 644 */ 645 static int stmmac_init_ptp(struct stmmac_priv *priv) 646 { 647 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 648 return -EOPNOTSUPP; 649 650 /* Fall-back to main clock in case of no PTP ref is passed */ 651 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 652 if (IS_ERR(priv->clk_ptp_ref)) { 653 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 654 priv->clk_ptp_ref = NULL; 655 netdev_dbg(priv->dev, "PTP uses main clock\n"); 656 } else { 657 clk_prepare_enable(priv->clk_ptp_ref); 658 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 659 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate); 660 } 661 662 priv->adv_ts = 0; 663 /* Check if adv_ts can be enabled for dwmac 4.x core */ 664 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) 665 priv->adv_ts = 1; 666 /* Dwmac 3.x core with extend_desc can support adv_ts */ 667 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 668 priv->adv_ts = 1; 669 670 if (priv->dma_cap.time_stamp) 671 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 672 673 if (priv->adv_ts) 674 netdev_info(priv->dev, 675 "IEEE 1588-2008 Advanced Timestamp supported\n"); 676 677 priv->hw->ptp = &stmmac_ptp; 678 priv->hwts_tx_en = 0; 679 priv->hwts_rx_en = 0; 680 681 return stmmac_ptp_register(priv); 682 } 683 684 static void stmmac_release_ptp(struct stmmac_priv *priv) 685 { 686 if (priv->clk_ptp_ref) 687 clk_disable_unprepare(priv->clk_ptp_ref); 688 stmmac_ptp_unregister(priv); 689 } 690 691 /** 692 * stmmac_adjust_link - adjusts the link parameters 693 * @dev: net device structure 694 * Description: this is the helper called by the physical abstraction layer 695 * drivers to communicate the phy link status. According the speed and duplex 696 * this driver can invoke registered glue-logic as well. 697 * It also invoke the eee initialization because it could happen when switch 698 * on different networks (that are eee capable). 699 */ 700 static void stmmac_adjust_link(struct net_device *dev) 701 { 702 struct stmmac_priv *priv = netdev_priv(dev); 703 struct phy_device *phydev = dev->phydev; 704 unsigned long flags; 705 int new_state = 0; 706 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 707 708 if (phydev == NULL) 709 return; 710 711 spin_lock_irqsave(&priv->lock, flags); 712 713 if (phydev->link) { 714 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 715 716 /* Now we make sure that we can be in full duplex mode. 717 * If not, we operate in half-duplex mode. */ 718 if (phydev->duplex != priv->oldduplex) { 719 new_state = 1; 720 if (!(phydev->duplex)) 721 ctrl &= ~priv->hw->link.duplex; 722 else 723 ctrl |= priv->hw->link.duplex; 724 priv->oldduplex = phydev->duplex; 725 } 726 /* Flow Control operation */ 727 if (phydev->pause) 728 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 729 fc, pause_time); 730 731 if (phydev->speed != priv->speed) { 732 new_state = 1; 733 switch (phydev->speed) { 734 case 1000: 735 if (likely((priv->plat->has_gmac) || 736 (priv->plat->has_gmac4))) 737 ctrl &= ~priv->hw->link.port; 738 stmmac_hw_fix_mac_speed(priv); 739 break; 740 case 100: 741 case 10: 742 if (likely((priv->plat->has_gmac) || 743 (priv->plat->has_gmac4))) { 744 ctrl |= priv->hw->link.port; 745 if (phydev->speed == SPEED_100) { 746 ctrl |= priv->hw->link.speed; 747 } else { 748 ctrl &= ~(priv->hw->link.speed); 749 } 750 } else { 751 ctrl &= ~priv->hw->link.port; 752 } 753 stmmac_hw_fix_mac_speed(priv); 754 break; 755 default: 756 if (netif_msg_link(priv)) 757 pr_warn("%s: Speed (%d) not 10/100\n", 758 dev->name, phydev->speed); 759 break; 760 } 761 762 priv->speed = phydev->speed; 763 } 764 765 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 766 767 if (!priv->oldlink) { 768 new_state = 1; 769 priv->oldlink = 1; 770 } 771 } else if (priv->oldlink) { 772 new_state = 1; 773 priv->oldlink = 0; 774 priv->speed = 0; 775 priv->oldduplex = -1; 776 } 777 778 if (new_state && netif_msg_link(priv)) 779 phy_print_status(phydev); 780 781 spin_unlock_irqrestore(&priv->lock, flags); 782 783 if (phydev->is_pseudo_fixed_link) 784 /* Stop PHY layer to call the hook to adjust the link in case 785 * of a switch is attached to the stmmac driver. 786 */ 787 phydev->irq = PHY_IGNORE_INTERRUPT; 788 else 789 /* At this stage, init the EEE if supported. 790 * Never called in case of fixed_link. 791 */ 792 priv->eee_enabled = stmmac_eee_init(priv); 793 } 794 795 /** 796 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 797 * @priv: driver private structure 798 * Description: this is to verify if the HW supports the PCS. 799 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 800 * configured for the TBI, RTBI, or SGMII PHY interface. 801 */ 802 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 803 { 804 int interface = priv->plat->interface; 805 806 if (priv->dma_cap.pcs) { 807 if ((interface == PHY_INTERFACE_MODE_RGMII) || 808 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 809 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 810 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 811 pr_debug("STMMAC: PCS RGMII support enable\n"); 812 priv->hw->pcs = STMMAC_PCS_RGMII; 813 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 814 pr_debug("STMMAC: PCS SGMII support enable\n"); 815 priv->hw->pcs = STMMAC_PCS_SGMII; 816 } 817 } 818 } 819 820 /** 821 * stmmac_init_phy - PHY initialization 822 * @dev: net device structure 823 * Description: it initializes the driver's PHY state, and attaches the PHY 824 * to the mac driver. 825 * Return value: 826 * 0 on success 827 */ 828 static int stmmac_init_phy(struct net_device *dev) 829 { 830 struct stmmac_priv *priv = netdev_priv(dev); 831 struct phy_device *phydev; 832 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 833 char bus_id[MII_BUS_ID_SIZE]; 834 int interface = priv->plat->interface; 835 int max_speed = priv->plat->max_speed; 836 priv->oldlink = 0; 837 priv->speed = 0; 838 priv->oldduplex = -1; 839 840 if (priv->plat->phy_node) { 841 phydev = of_phy_connect(dev, priv->plat->phy_node, 842 &stmmac_adjust_link, 0, interface); 843 } else { 844 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 845 priv->plat->bus_id); 846 847 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 848 priv->plat->phy_addr); 849 pr_debug("stmmac_init_phy: trying to attach to %s\n", 850 phy_id_fmt); 851 852 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 853 interface); 854 } 855 856 if (IS_ERR_OR_NULL(phydev)) { 857 pr_err("%s: Could not attach to PHY\n", dev->name); 858 if (!phydev) 859 return -ENODEV; 860 861 return PTR_ERR(phydev); 862 } 863 864 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 865 if ((interface == PHY_INTERFACE_MODE_MII) || 866 (interface == PHY_INTERFACE_MODE_RMII) || 867 (max_speed < 1000 && max_speed > 0)) 868 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 869 SUPPORTED_1000baseT_Full); 870 871 /* 872 * Broken HW is sometimes missing the pull-up resistor on the 873 * MDIO line, which results in reads to non-existent devices returning 874 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 875 * device as well. 876 * Note: phydev->phy_id is the result of reading the UID PHY registers. 877 */ 878 if (!priv->plat->phy_node && phydev->phy_id == 0) { 879 phy_disconnect(phydev); 880 return -ENODEV; 881 } 882 883 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 884 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 885 886 return 0; 887 } 888 889 static void stmmac_display_rings(struct stmmac_priv *priv) 890 { 891 void *head_rx, *head_tx; 892 893 if (priv->extend_desc) { 894 head_rx = (void *)priv->dma_erx; 895 head_tx = (void *)priv->dma_etx; 896 } else { 897 head_rx = (void *)priv->dma_rx; 898 head_tx = (void *)priv->dma_tx; 899 } 900 901 /* Display Rx ring */ 902 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); 903 /* Display Tx ring */ 904 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); 905 } 906 907 static int stmmac_set_bfsize(int mtu, int bufsize) 908 { 909 int ret = bufsize; 910 911 if (mtu >= BUF_SIZE_4KiB) 912 ret = BUF_SIZE_8KiB; 913 else if (mtu >= BUF_SIZE_2KiB) 914 ret = BUF_SIZE_4KiB; 915 else if (mtu > DEFAULT_BUFSIZE) 916 ret = BUF_SIZE_2KiB; 917 else 918 ret = DEFAULT_BUFSIZE; 919 920 return ret; 921 } 922 923 /** 924 * stmmac_clear_descriptors - clear descriptors 925 * @priv: driver private structure 926 * Description: this function is called to clear the tx and rx descriptors 927 * in case of both basic and extended descriptors are used. 928 */ 929 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 930 { 931 int i; 932 933 /* Clear the Rx/Tx descriptors */ 934 for (i = 0; i < DMA_RX_SIZE; i++) 935 if (priv->extend_desc) 936 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 937 priv->use_riwt, priv->mode, 938 (i == DMA_RX_SIZE - 1)); 939 else 940 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 941 priv->use_riwt, priv->mode, 942 (i == DMA_RX_SIZE - 1)); 943 for (i = 0; i < DMA_TX_SIZE; i++) 944 if (priv->extend_desc) 945 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 946 priv->mode, 947 (i == DMA_TX_SIZE - 1)); 948 else 949 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 950 priv->mode, 951 (i == DMA_TX_SIZE - 1)); 952 } 953 954 /** 955 * stmmac_init_rx_buffers - init the RX descriptor buffer. 956 * @priv: driver private structure 957 * @p: descriptor pointer 958 * @i: descriptor index 959 * @flags: gfp flag. 960 * Description: this function is called to allocate a receive buffer, perform 961 * the DMA mapping and init the descriptor. 962 */ 963 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 964 int i, gfp_t flags) 965 { 966 struct sk_buff *skb; 967 968 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); 969 if (!skb) { 970 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 971 return -ENOMEM; 972 } 973 priv->rx_skbuff[i] = skb; 974 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 975 priv->dma_buf_sz, 976 DMA_FROM_DEVICE); 977 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 978 pr_err("%s: DMA mapping error\n", __func__); 979 dev_kfree_skb_any(skb); 980 return -EINVAL; 981 } 982 983 if (priv->synopsys_id >= DWMAC_CORE_4_00) 984 p->des0 = priv->rx_skbuff_dma[i]; 985 else 986 p->des2 = priv->rx_skbuff_dma[i]; 987 988 if ((priv->hw->mode->init_desc3) && 989 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 990 priv->hw->mode->init_desc3(p); 991 992 return 0; 993 } 994 995 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 996 { 997 if (priv->rx_skbuff[i]) { 998 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 999 priv->dma_buf_sz, DMA_FROM_DEVICE); 1000 dev_kfree_skb_any(priv->rx_skbuff[i]); 1001 } 1002 priv->rx_skbuff[i] = NULL; 1003 } 1004 1005 /** 1006 * init_dma_desc_rings - init the RX/TX descriptor rings 1007 * @dev: net device structure 1008 * @flags: gfp flag. 1009 * Description: this function initializes the DMA RX/TX descriptors 1010 * and allocates the socket buffers. It suppors the chained and ring 1011 * modes. 1012 */ 1013 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1014 { 1015 int i; 1016 struct stmmac_priv *priv = netdev_priv(dev); 1017 unsigned int bfsize = 0; 1018 int ret = -ENOMEM; 1019 1020 if (priv->hw->mode->set_16kib_bfsize) 1021 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1022 1023 if (bfsize < BUF_SIZE_16KiB) 1024 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1025 1026 priv->dma_buf_sz = bfsize; 1027 1028 if (netif_msg_probe(priv)) { 1029 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1030 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1031 1032 /* RX INITIALIZATION */ 1033 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1034 } 1035 for (i = 0; i < DMA_RX_SIZE; i++) { 1036 struct dma_desc *p; 1037 if (priv->extend_desc) 1038 p = &((priv->dma_erx + i)->basic); 1039 else 1040 p = priv->dma_rx + i; 1041 1042 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1043 if (ret) 1044 goto err_init_rx_buffers; 1045 1046 if (netif_msg_probe(priv)) 1047 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1048 priv->rx_skbuff[i]->data, 1049 (unsigned int)priv->rx_skbuff_dma[i]); 1050 } 1051 priv->cur_rx = 0; 1052 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1053 buf_sz = bfsize; 1054 1055 /* Setup the chained descriptor addresses */ 1056 if (priv->mode == STMMAC_CHAIN_MODE) { 1057 if (priv->extend_desc) { 1058 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1059 DMA_RX_SIZE, 1); 1060 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1061 DMA_TX_SIZE, 1); 1062 } else { 1063 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1064 DMA_RX_SIZE, 0); 1065 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1066 DMA_TX_SIZE, 0); 1067 } 1068 } 1069 1070 /* TX INITIALIZATION */ 1071 for (i = 0; i < DMA_TX_SIZE; i++) { 1072 struct dma_desc *p; 1073 if (priv->extend_desc) 1074 p = &((priv->dma_etx + i)->basic); 1075 else 1076 p = priv->dma_tx + i; 1077 1078 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1079 p->des0 = 0; 1080 p->des1 = 0; 1081 p->des2 = 0; 1082 p->des3 = 0; 1083 } else { 1084 p->des2 = 0; 1085 } 1086 1087 priv->tx_skbuff_dma[i].buf = 0; 1088 priv->tx_skbuff_dma[i].map_as_page = false; 1089 priv->tx_skbuff_dma[i].len = 0; 1090 priv->tx_skbuff_dma[i].last_segment = false; 1091 priv->tx_skbuff[i] = NULL; 1092 } 1093 1094 priv->dirty_tx = 0; 1095 priv->cur_tx = 0; 1096 netdev_reset_queue(priv->dev); 1097 1098 stmmac_clear_descriptors(priv); 1099 1100 if (netif_msg_hw(priv)) 1101 stmmac_display_rings(priv); 1102 1103 return 0; 1104 err_init_rx_buffers: 1105 while (--i >= 0) 1106 stmmac_free_rx_buffers(priv, i); 1107 return ret; 1108 } 1109 1110 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1111 { 1112 int i; 1113 1114 for (i = 0; i < DMA_RX_SIZE; i++) 1115 stmmac_free_rx_buffers(priv, i); 1116 } 1117 1118 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1119 { 1120 int i; 1121 1122 for (i = 0; i < DMA_TX_SIZE; i++) { 1123 struct dma_desc *p; 1124 1125 if (priv->extend_desc) 1126 p = &((priv->dma_etx + i)->basic); 1127 else 1128 p = priv->dma_tx + i; 1129 1130 if (priv->tx_skbuff_dma[i].buf) { 1131 if (priv->tx_skbuff_dma[i].map_as_page) 1132 dma_unmap_page(priv->device, 1133 priv->tx_skbuff_dma[i].buf, 1134 priv->tx_skbuff_dma[i].len, 1135 DMA_TO_DEVICE); 1136 else 1137 dma_unmap_single(priv->device, 1138 priv->tx_skbuff_dma[i].buf, 1139 priv->tx_skbuff_dma[i].len, 1140 DMA_TO_DEVICE); 1141 } 1142 1143 if (priv->tx_skbuff[i] != NULL) { 1144 dev_kfree_skb_any(priv->tx_skbuff[i]); 1145 priv->tx_skbuff[i] = NULL; 1146 priv->tx_skbuff_dma[i].buf = 0; 1147 priv->tx_skbuff_dma[i].map_as_page = false; 1148 } 1149 } 1150 } 1151 1152 /** 1153 * alloc_dma_desc_resources - alloc TX/RX resources. 1154 * @priv: private structure 1155 * Description: according to which descriptor can be used (extend or basic) 1156 * this function allocates the resources for TX and RX paths. In case of 1157 * reception, for example, it pre-allocated the RX socket buffer in order to 1158 * allow zero-copy mechanism. 1159 */ 1160 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1161 { 1162 int ret = -ENOMEM; 1163 1164 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), 1165 GFP_KERNEL); 1166 if (!priv->rx_skbuff_dma) 1167 return -ENOMEM; 1168 1169 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), 1170 GFP_KERNEL); 1171 if (!priv->rx_skbuff) 1172 goto err_rx_skbuff; 1173 1174 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, 1175 sizeof(*priv->tx_skbuff_dma), 1176 GFP_KERNEL); 1177 if (!priv->tx_skbuff_dma) 1178 goto err_tx_skbuff_dma; 1179 1180 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), 1181 GFP_KERNEL); 1182 if (!priv->tx_skbuff) 1183 goto err_tx_skbuff; 1184 1185 if (priv->extend_desc) { 1186 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1187 sizeof(struct 1188 dma_extended_desc), 1189 &priv->dma_rx_phy, 1190 GFP_KERNEL); 1191 if (!priv->dma_erx) 1192 goto err_dma; 1193 1194 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1195 sizeof(struct 1196 dma_extended_desc), 1197 &priv->dma_tx_phy, 1198 GFP_KERNEL); 1199 if (!priv->dma_etx) { 1200 dma_free_coherent(priv->device, DMA_RX_SIZE * 1201 sizeof(struct dma_extended_desc), 1202 priv->dma_erx, priv->dma_rx_phy); 1203 goto err_dma; 1204 } 1205 } else { 1206 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1207 sizeof(struct dma_desc), 1208 &priv->dma_rx_phy, 1209 GFP_KERNEL); 1210 if (!priv->dma_rx) 1211 goto err_dma; 1212 1213 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1214 sizeof(struct dma_desc), 1215 &priv->dma_tx_phy, 1216 GFP_KERNEL); 1217 if (!priv->dma_tx) { 1218 dma_free_coherent(priv->device, DMA_RX_SIZE * 1219 sizeof(struct dma_desc), 1220 priv->dma_rx, priv->dma_rx_phy); 1221 goto err_dma; 1222 } 1223 } 1224 1225 return 0; 1226 1227 err_dma: 1228 kfree(priv->tx_skbuff); 1229 err_tx_skbuff: 1230 kfree(priv->tx_skbuff_dma); 1231 err_tx_skbuff_dma: 1232 kfree(priv->rx_skbuff); 1233 err_rx_skbuff: 1234 kfree(priv->rx_skbuff_dma); 1235 return ret; 1236 } 1237 1238 static void free_dma_desc_resources(struct stmmac_priv *priv) 1239 { 1240 /* Release the DMA TX/RX socket buffers */ 1241 dma_free_rx_skbufs(priv); 1242 dma_free_tx_skbufs(priv); 1243 1244 /* Free DMA regions of consistent memory previously allocated */ 1245 if (!priv->extend_desc) { 1246 dma_free_coherent(priv->device, 1247 DMA_TX_SIZE * sizeof(struct dma_desc), 1248 priv->dma_tx, priv->dma_tx_phy); 1249 dma_free_coherent(priv->device, 1250 DMA_RX_SIZE * sizeof(struct dma_desc), 1251 priv->dma_rx, priv->dma_rx_phy); 1252 } else { 1253 dma_free_coherent(priv->device, DMA_TX_SIZE * 1254 sizeof(struct dma_extended_desc), 1255 priv->dma_etx, priv->dma_tx_phy); 1256 dma_free_coherent(priv->device, DMA_RX_SIZE * 1257 sizeof(struct dma_extended_desc), 1258 priv->dma_erx, priv->dma_rx_phy); 1259 } 1260 kfree(priv->rx_skbuff_dma); 1261 kfree(priv->rx_skbuff); 1262 kfree(priv->tx_skbuff_dma); 1263 kfree(priv->tx_skbuff); 1264 } 1265 1266 /** 1267 * stmmac_dma_operation_mode - HW DMA operation mode 1268 * @priv: driver private structure 1269 * Description: it is used for configuring the DMA operation mode register in 1270 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1271 */ 1272 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1273 { 1274 int rxfifosz = priv->plat->rx_fifo_size; 1275 1276 if (priv->plat->force_thresh_dma_mode) 1277 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); 1278 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1279 /* 1280 * In case of GMAC, SF mode can be enabled 1281 * to perform the TX COE in HW. This depends on: 1282 * 1) TX COE if actually supported 1283 * 2) There is no bugged Jumbo frame support 1284 * that needs to not insert csum in the TDES. 1285 */ 1286 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, 1287 rxfifosz); 1288 priv->xstats.threshold = SF_DMA_MODE; 1289 } else 1290 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, 1291 rxfifosz); 1292 } 1293 1294 /** 1295 * stmmac_tx_clean - to manage the transmission completion 1296 * @priv: driver private structure 1297 * Description: it reclaims the transmit resources after transmission completes. 1298 */ 1299 static void stmmac_tx_clean(struct stmmac_priv *priv) 1300 { 1301 unsigned int bytes_compl = 0, pkts_compl = 0; 1302 unsigned int entry = priv->dirty_tx; 1303 1304 spin_lock(&priv->tx_lock); 1305 1306 priv->xstats.tx_clean++; 1307 1308 while (entry != priv->cur_tx) { 1309 struct sk_buff *skb = priv->tx_skbuff[entry]; 1310 struct dma_desc *p; 1311 int status; 1312 1313 if (priv->extend_desc) 1314 p = (struct dma_desc *)(priv->dma_etx + entry); 1315 else 1316 p = priv->dma_tx + entry; 1317 1318 status = priv->hw->desc->tx_status(&priv->dev->stats, 1319 &priv->xstats, p, 1320 priv->ioaddr); 1321 /* Check if the descriptor is owned by the DMA */ 1322 if (unlikely(status & tx_dma_own)) 1323 break; 1324 1325 /* Just consider the last segment and ...*/ 1326 if (likely(!(status & tx_not_ls))) { 1327 /* ... verify the status error condition */ 1328 if (unlikely(status & tx_err)) { 1329 priv->dev->stats.tx_errors++; 1330 } else { 1331 priv->dev->stats.tx_packets++; 1332 priv->xstats.tx_pkt_n++; 1333 } 1334 stmmac_get_tx_hwtstamp(priv, entry, skb); 1335 } 1336 1337 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1338 if (priv->tx_skbuff_dma[entry].map_as_page) 1339 dma_unmap_page(priv->device, 1340 priv->tx_skbuff_dma[entry].buf, 1341 priv->tx_skbuff_dma[entry].len, 1342 DMA_TO_DEVICE); 1343 else 1344 dma_unmap_single(priv->device, 1345 priv->tx_skbuff_dma[entry].buf, 1346 priv->tx_skbuff_dma[entry].len, 1347 DMA_TO_DEVICE); 1348 priv->tx_skbuff_dma[entry].buf = 0; 1349 priv->tx_skbuff_dma[entry].len = 0; 1350 priv->tx_skbuff_dma[entry].map_as_page = false; 1351 } 1352 1353 if (priv->hw->mode->clean_desc3) 1354 priv->hw->mode->clean_desc3(priv, p); 1355 1356 priv->tx_skbuff_dma[entry].last_segment = false; 1357 priv->tx_skbuff_dma[entry].is_jumbo = false; 1358 1359 if (likely(skb != NULL)) { 1360 pkts_compl++; 1361 bytes_compl += skb->len; 1362 dev_consume_skb_any(skb); 1363 priv->tx_skbuff[entry] = NULL; 1364 } 1365 1366 priv->hw->desc->release_tx_desc(p, priv->mode); 1367 1368 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1369 } 1370 priv->dirty_tx = entry; 1371 1372 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); 1373 1374 if (unlikely(netif_queue_stopped(priv->dev) && 1375 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { 1376 netif_tx_lock(priv->dev); 1377 if (netif_queue_stopped(priv->dev) && 1378 stmmac_tx_avail(priv) > STMMAC_TX_THRESH) { 1379 if (netif_msg_tx_done(priv)) 1380 pr_debug("%s: restart transmit\n", __func__); 1381 netif_wake_queue(priv->dev); 1382 } 1383 netif_tx_unlock(priv->dev); 1384 } 1385 1386 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1387 stmmac_enable_eee_mode(priv); 1388 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1389 } 1390 spin_unlock(&priv->tx_lock); 1391 } 1392 1393 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1394 { 1395 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1396 } 1397 1398 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1399 { 1400 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1401 } 1402 1403 /** 1404 * stmmac_tx_err - to manage the tx error 1405 * @priv: driver private structure 1406 * Description: it cleans the descriptors and restarts the transmission 1407 * in case of transmission errors. 1408 */ 1409 static void stmmac_tx_err(struct stmmac_priv *priv) 1410 { 1411 int i; 1412 netif_stop_queue(priv->dev); 1413 1414 priv->hw->dma->stop_tx(priv->ioaddr); 1415 dma_free_tx_skbufs(priv); 1416 for (i = 0; i < DMA_TX_SIZE; i++) 1417 if (priv->extend_desc) 1418 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1419 priv->mode, 1420 (i == DMA_TX_SIZE - 1)); 1421 else 1422 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1423 priv->mode, 1424 (i == DMA_TX_SIZE - 1)); 1425 priv->dirty_tx = 0; 1426 priv->cur_tx = 0; 1427 netdev_reset_queue(priv->dev); 1428 priv->hw->dma->start_tx(priv->ioaddr); 1429 1430 priv->dev->stats.tx_errors++; 1431 netif_wake_queue(priv->dev); 1432 } 1433 1434 /** 1435 * stmmac_dma_interrupt - DMA ISR 1436 * @priv: driver private structure 1437 * Description: this is the DMA ISR. It is called by the main ISR. 1438 * It calls the dwmac dma routine and schedule poll method in case of some 1439 * work can be done. 1440 */ 1441 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1442 { 1443 int status; 1444 int rxfifosz = priv->plat->rx_fifo_size; 1445 1446 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1447 if (likely((status & handle_rx)) || (status & handle_tx)) { 1448 if (likely(napi_schedule_prep(&priv->napi))) { 1449 stmmac_disable_dma_irq(priv); 1450 __napi_schedule(&priv->napi); 1451 } 1452 } 1453 if (unlikely(status & tx_hard_error_bump_tc)) { 1454 /* Try to bump up the dma threshold on this failure */ 1455 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 1456 (tc <= 256)) { 1457 tc += 64; 1458 if (priv->plat->force_thresh_dma_mode) 1459 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, 1460 rxfifosz); 1461 else 1462 priv->hw->dma->dma_mode(priv->ioaddr, tc, 1463 SF_DMA_MODE, rxfifosz); 1464 priv->xstats.threshold = tc; 1465 } 1466 } else if (unlikely(status == tx_hard_error)) 1467 stmmac_tx_err(priv); 1468 } 1469 1470 /** 1471 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1472 * @priv: driver private structure 1473 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1474 */ 1475 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1476 { 1477 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1478 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1479 1480 if (priv->synopsys_id >= DWMAC_CORE_4_00) 1481 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; 1482 else 1483 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; 1484 1485 dwmac_mmc_intr_all_mask(priv->mmcaddr); 1486 1487 if (priv->dma_cap.rmon) { 1488 dwmac_mmc_ctrl(priv->mmcaddr, mode); 1489 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1490 } else 1491 pr_info(" No MAC Management Counters available\n"); 1492 } 1493 1494 /** 1495 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1496 * @priv: driver private structure 1497 * Description: select the Enhanced/Alternate or Normal descriptors. 1498 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1499 * supported by the HW capability register. 1500 */ 1501 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1502 { 1503 if (priv->plat->enh_desc) { 1504 pr_info(" Enhanced/Alternate descriptors\n"); 1505 1506 /* GMAC older than 3.50 has no extended descriptors */ 1507 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1508 pr_info("\tEnabled extended descriptors\n"); 1509 priv->extend_desc = 1; 1510 } else 1511 pr_warn("Extended descriptors not supported\n"); 1512 1513 priv->hw->desc = &enh_desc_ops; 1514 } else { 1515 pr_info(" Normal descriptors\n"); 1516 priv->hw->desc = &ndesc_ops; 1517 } 1518 } 1519 1520 /** 1521 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1522 * @priv: driver private structure 1523 * Description: 1524 * new GMAC chip generations have a new register to indicate the 1525 * presence of the optional feature/functions. 1526 * This can be also used to override the value passed through the 1527 * platform and necessary for old MAC10/100 and GMAC chips. 1528 */ 1529 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1530 { 1531 u32 ret = 0; 1532 1533 if (priv->hw->dma->get_hw_feature) { 1534 priv->hw->dma->get_hw_feature(priv->ioaddr, 1535 &priv->dma_cap); 1536 ret = 1; 1537 } 1538 1539 return ret; 1540 } 1541 1542 /** 1543 * stmmac_check_ether_addr - check if the MAC addr is valid 1544 * @priv: driver private structure 1545 * Description: 1546 * it is to verify if the MAC address is valid, in case of failures it 1547 * generates a random MAC address 1548 */ 1549 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1550 { 1551 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1552 priv->hw->mac->get_umac_addr(priv->hw, 1553 priv->dev->dev_addr, 0); 1554 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1555 eth_hw_addr_random(priv->dev); 1556 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1557 priv->dev->dev_addr); 1558 } 1559 } 1560 1561 /** 1562 * stmmac_init_dma_engine - DMA init. 1563 * @priv: driver private structure 1564 * Description: 1565 * It inits the DMA invoking the specific MAC/GMAC callback. 1566 * Some DMA parameters can be passed from the platform; 1567 * in case of these are not passed a default is kept for the MAC or GMAC. 1568 */ 1569 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1570 { 1571 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0; 1572 int mixed_burst = 0; 1573 int atds = 0; 1574 int ret = 0; 1575 1576 if (priv->plat->dma_cfg) { 1577 pbl = priv->plat->dma_cfg->pbl; 1578 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1579 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1580 aal = priv->plat->dma_cfg->aal; 1581 } 1582 1583 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1584 atds = 1; 1585 1586 ret = priv->hw->dma->reset(priv->ioaddr); 1587 if (ret) { 1588 dev_err(priv->device, "Failed to reset the dma\n"); 1589 return ret; 1590 } 1591 1592 priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1593 aal, priv->dma_tx_phy, priv->dma_rx_phy, atds); 1594 1595 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1596 priv->rx_tail_addr = priv->dma_rx_phy + 1597 (DMA_RX_SIZE * sizeof(struct dma_desc)); 1598 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr, 1599 STMMAC_CHAN0); 1600 1601 priv->tx_tail_addr = priv->dma_tx_phy + 1602 (DMA_TX_SIZE * sizeof(struct dma_desc)); 1603 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 1604 STMMAC_CHAN0); 1605 } 1606 1607 if (priv->plat->axi && priv->hw->dma->axi) 1608 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); 1609 1610 return ret; 1611 } 1612 1613 /** 1614 * stmmac_tx_timer - mitigation sw timer for tx. 1615 * @data: data pointer 1616 * Description: 1617 * This is the timer handler to directly invoke the stmmac_tx_clean. 1618 */ 1619 static void stmmac_tx_timer(unsigned long data) 1620 { 1621 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1622 1623 stmmac_tx_clean(priv); 1624 } 1625 1626 /** 1627 * stmmac_init_tx_coalesce - init tx mitigation options. 1628 * @priv: driver private structure 1629 * Description: 1630 * This inits the transmit coalesce parameters: i.e. timer rate, 1631 * timer handler and default threshold used for enabling the 1632 * interrupt on completion bit. 1633 */ 1634 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1635 { 1636 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1637 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1638 init_timer(&priv->txtimer); 1639 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1640 priv->txtimer.data = (unsigned long)priv; 1641 priv->txtimer.function = stmmac_tx_timer; 1642 add_timer(&priv->txtimer); 1643 } 1644 1645 /** 1646 * stmmac_hw_setup - setup mac in a usable state. 1647 * @dev : pointer to the device structure. 1648 * Description: 1649 * this is the main function to setup the HW in a usable state because the 1650 * dma engine is reset, the core registers are configured (e.g. AXI, 1651 * Checksum features, timers). The DMA is ready to start receiving and 1652 * transmitting. 1653 * Return value: 1654 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1655 * file on failure. 1656 */ 1657 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 1658 { 1659 struct stmmac_priv *priv = netdev_priv(dev); 1660 int ret; 1661 1662 /* DMA initialization and SW reset */ 1663 ret = stmmac_init_dma_engine(priv); 1664 if (ret < 0) { 1665 pr_err("%s: DMA engine initialization failed\n", __func__); 1666 return ret; 1667 } 1668 1669 /* Copy the MAC addr into the HW */ 1670 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1671 1672 /* If required, perform hw setup of the bus. */ 1673 if (priv->plat->bus_setup) 1674 priv->plat->bus_setup(priv->ioaddr); 1675 1676 /* PS and related bits will be programmed according to the speed */ 1677 if (priv->hw->pcs) { 1678 int speed = priv->plat->mac_port_sel_speed; 1679 1680 if ((speed == SPEED_10) || (speed == SPEED_100) || 1681 (speed == SPEED_1000)) { 1682 priv->hw->ps = speed; 1683 } else { 1684 dev_warn(priv->device, "invalid port speed\n"); 1685 priv->hw->ps = 0; 1686 } 1687 } 1688 1689 /* Initialize the MAC Core */ 1690 priv->hw->mac->core_init(priv->hw, dev->mtu); 1691 1692 ret = priv->hw->mac->rx_ipc(priv->hw); 1693 if (!ret) { 1694 pr_warn(" RX IPC Checksum Offload disabled\n"); 1695 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1696 priv->hw->rx_csum = 0; 1697 } 1698 1699 /* Enable the MAC Rx/Tx */ 1700 if (priv->synopsys_id >= DWMAC_CORE_4_00) 1701 stmmac_dwmac4_set_mac(priv->ioaddr, true); 1702 else 1703 stmmac_set_mac(priv->ioaddr, true); 1704 1705 /* Set the HW DMA mode and the COE */ 1706 stmmac_dma_operation_mode(priv); 1707 1708 stmmac_mmc_setup(priv); 1709 1710 if (init_ptp) { 1711 ret = stmmac_init_ptp(priv); 1712 if (ret) 1713 netdev_warn(priv->dev, "PTP support cannot init.\n"); 1714 } 1715 1716 #ifdef CONFIG_DEBUG_FS 1717 ret = stmmac_init_fs(dev); 1718 if (ret < 0) 1719 pr_warn("%s: failed debugFS registration\n", __func__); 1720 #endif 1721 /* Start the ball rolling... */ 1722 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1723 priv->hw->dma->start_tx(priv->ioaddr); 1724 priv->hw->dma->start_rx(priv->ioaddr); 1725 1726 /* Dump DMA/MAC registers */ 1727 if (netif_msg_hw(priv)) { 1728 priv->hw->mac->dump_regs(priv->hw); 1729 priv->hw->dma->dump_regs(priv->ioaddr); 1730 } 1731 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1732 1733 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1734 priv->rx_riwt = MAX_DMA_RIWT; 1735 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1736 } 1737 1738 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) 1739 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); 1740 1741 /* set TX ring length */ 1742 if (priv->hw->dma->set_tx_ring_len) 1743 priv->hw->dma->set_tx_ring_len(priv->ioaddr, 1744 (DMA_TX_SIZE - 1)); 1745 /* set RX ring length */ 1746 if (priv->hw->dma->set_rx_ring_len) 1747 priv->hw->dma->set_rx_ring_len(priv->ioaddr, 1748 (DMA_RX_SIZE - 1)); 1749 /* Enable TSO */ 1750 if (priv->tso) 1751 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0); 1752 1753 return 0; 1754 } 1755 1756 /** 1757 * stmmac_open - open entry point of the driver 1758 * @dev : pointer to the device structure. 1759 * Description: 1760 * This function is the open entry point of the driver. 1761 * Return value: 1762 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1763 * file on failure. 1764 */ 1765 static int stmmac_open(struct net_device *dev) 1766 { 1767 struct stmmac_priv *priv = netdev_priv(dev); 1768 int ret; 1769 1770 stmmac_check_ether_addr(priv); 1771 1772 if (priv->hw->pcs != STMMAC_PCS_RGMII && 1773 priv->hw->pcs != STMMAC_PCS_TBI && 1774 priv->hw->pcs != STMMAC_PCS_RTBI) { 1775 ret = stmmac_init_phy(dev); 1776 if (ret) { 1777 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1778 __func__, ret); 1779 return ret; 1780 } 1781 } 1782 1783 /* Extra statistics */ 1784 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1785 priv->xstats.threshold = tc; 1786 1787 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1788 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 1789 1790 ret = alloc_dma_desc_resources(priv); 1791 if (ret < 0) { 1792 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1793 goto dma_desc_error; 1794 } 1795 1796 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1797 if (ret < 0) { 1798 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1799 goto init_error; 1800 } 1801 1802 ret = stmmac_hw_setup(dev, true); 1803 if (ret < 0) { 1804 pr_err("%s: Hw setup failed\n", __func__); 1805 goto init_error; 1806 } 1807 1808 stmmac_init_tx_coalesce(priv); 1809 1810 if (dev->phydev) 1811 phy_start(dev->phydev); 1812 1813 /* Request the IRQ lines */ 1814 ret = request_irq(dev->irq, stmmac_interrupt, 1815 IRQF_SHARED, dev->name, dev); 1816 if (unlikely(ret < 0)) { 1817 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1818 __func__, dev->irq, ret); 1819 goto init_error; 1820 } 1821 1822 /* Request the Wake IRQ in case of another line is used for WoL */ 1823 if (priv->wol_irq != dev->irq) { 1824 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1825 IRQF_SHARED, dev->name, dev); 1826 if (unlikely(ret < 0)) { 1827 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1828 __func__, priv->wol_irq, ret); 1829 goto wolirq_error; 1830 } 1831 } 1832 1833 /* Request the IRQ lines */ 1834 if (priv->lpi_irq > 0) { 1835 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1836 dev->name, dev); 1837 if (unlikely(ret < 0)) { 1838 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1839 __func__, priv->lpi_irq, ret); 1840 goto lpiirq_error; 1841 } 1842 } 1843 1844 napi_enable(&priv->napi); 1845 netif_start_queue(dev); 1846 1847 return 0; 1848 1849 lpiirq_error: 1850 if (priv->wol_irq != dev->irq) 1851 free_irq(priv->wol_irq, dev); 1852 wolirq_error: 1853 free_irq(dev->irq, dev); 1854 1855 init_error: 1856 free_dma_desc_resources(priv); 1857 dma_desc_error: 1858 if (dev->phydev) 1859 phy_disconnect(dev->phydev); 1860 1861 return ret; 1862 } 1863 1864 /** 1865 * stmmac_release - close entry point of the driver 1866 * @dev : device pointer. 1867 * Description: 1868 * This is the stop entry point of the driver. 1869 */ 1870 static int stmmac_release(struct net_device *dev) 1871 { 1872 struct stmmac_priv *priv = netdev_priv(dev); 1873 1874 if (priv->eee_enabled) 1875 del_timer_sync(&priv->eee_ctrl_timer); 1876 1877 /* Stop and disconnect the PHY */ 1878 if (dev->phydev) { 1879 phy_stop(dev->phydev); 1880 phy_disconnect(dev->phydev); 1881 } 1882 1883 netif_stop_queue(dev); 1884 1885 napi_disable(&priv->napi); 1886 1887 del_timer_sync(&priv->txtimer); 1888 1889 /* Free the IRQ lines */ 1890 free_irq(dev->irq, dev); 1891 if (priv->wol_irq != dev->irq) 1892 free_irq(priv->wol_irq, dev); 1893 if (priv->lpi_irq > 0) 1894 free_irq(priv->lpi_irq, dev); 1895 1896 /* Stop TX/RX DMA and clear the descriptors */ 1897 priv->hw->dma->stop_tx(priv->ioaddr); 1898 priv->hw->dma->stop_rx(priv->ioaddr); 1899 1900 /* Release and free the Rx/Tx resources */ 1901 free_dma_desc_resources(priv); 1902 1903 /* Disable the MAC Rx/Tx */ 1904 stmmac_set_mac(priv->ioaddr, false); 1905 1906 netif_carrier_off(dev); 1907 1908 #ifdef CONFIG_DEBUG_FS 1909 stmmac_exit_fs(dev); 1910 #endif 1911 1912 stmmac_release_ptp(priv); 1913 1914 return 0; 1915 } 1916 1917 /** 1918 * stmmac_tso_allocator - close entry point of the driver 1919 * @priv: driver private structure 1920 * @des: buffer start address 1921 * @total_len: total length to fill in descriptors 1922 * @last_segmant: condition for the last descriptor 1923 * Description: 1924 * This function fills descriptor and request new descriptors according to 1925 * buffer length to fill 1926 */ 1927 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, 1928 int total_len, bool last_segment) 1929 { 1930 struct dma_desc *desc; 1931 int tmp_len; 1932 u32 buff_size; 1933 1934 tmp_len = total_len; 1935 1936 while (tmp_len > 0) { 1937 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 1938 desc = priv->dma_tx + priv->cur_tx; 1939 1940 desc->des0 = des + (total_len - tmp_len); 1941 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 1942 TSO_MAX_BUFF_SIZE : tmp_len; 1943 1944 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, 1945 0, 1, 1946 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), 1947 0, 0); 1948 1949 tmp_len -= TSO_MAX_BUFF_SIZE; 1950 } 1951 } 1952 1953 /** 1954 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 1955 * @skb : the socket buffer 1956 * @dev : device pointer 1957 * Description: this is the transmit function that is called on TSO frames 1958 * (support available on GMAC4 and newer chips). 1959 * Diagram below show the ring programming in case of TSO frames: 1960 * 1961 * First Descriptor 1962 * -------- 1963 * | DES0 |---> buffer1 = L2/L3/L4 header 1964 * | DES1 |---> TCP Payload (can continue on next descr...) 1965 * | DES2 |---> buffer 1 and 2 len 1966 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 1967 * -------- 1968 * | 1969 * ... 1970 * | 1971 * -------- 1972 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 1973 * | DES1 | --| 1974 * | DES2 | --> buffer 1 and 2 len 1975 * | DES3 | 1976 * -------- 1977 * 1978 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 1979 */ 1980 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 1981 { 1982 u32 pay_len, mss; 1983 int tmp_pay_len = 0; 1984 struct stmmac_priv *priv = netdev_priv(dev); 1985 int nfrags = skb_shinfo(skb)->nr_frags; 1986 unsigned int first_entry, des; 1987 struct dma_desc *desc, *first, *mss_desc = NULL; 1988 u8 proto_hdr_len; 1989 int i; 1990 1991 spin_lock(&priv->tx_lock); 1992 1993 /* Compute header lengths */ 1994 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1995 1996 /* Desc availability based on threshold should be enough safe */ 1997 if (unlikely(stmmac_tx_avail(priv) < 1998 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 1999 if (!netif_queue_stopped(dev)) { 2000 netif_stop_queue(dev); 2001 /* This is a hard error, log it. */ 2002 pr_err("%s: Tx Ring full when queue awake\n", __func__); 2003 } 2004 spin_unlock(&priv->tx_lock); 2005 return NETDEV_TX_BUSY; 2006 } 2007 2008 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2009 2010 mss = skb_shinfo(skb)->gso_size; 2011 2012 /* set new MSS value if needed */ 2013 if (mss != priv->mss) { 2014 mss_desc = priv->dma_tx + priv->cur_tx; 2015 priv->hw->desc->set_mss(mss_desc, mss); 2016 priv->mss = mss; 2017 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2018 } 2019 2020 if (netif_msg_tx_queued(priv)) { 2021 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2022 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2023 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2024 skb->data_len); 2025 } 2026 2027 first_entry = priv->cur_tx; 2028 2029 desc = priv->dma_tx + first_entry; 2030 first = desc; 2031 2032 /* first descriptor: fill Headers on Buf1 */ 2033 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2034 DMA_TO_DEVICE); 2035 if (dma_mapping_error(priv->device, des)) 2036 goto dma_map_err; 2037 2038 priv->tx_skbuff_dma[first_entry].buf = des; 2039 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2040 priv->tx_skbuff[first_entry] = skb; 2041 2042 first->des0 = des; 2043 2044 /* Fill start of payload in buff2 of first descriptor */ 2045 if (pay_len) 2046 first->des1 = des + proto_hdr_len; 2047 2048 /* If needed take extra descriptors to fill the remaining payload */ 2049 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2050 2051 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0)); 2052 2053 /* Prepare fragments */ 2054 for (i = 0; i < nfrags; i++) { 2055 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2056 2057 des = skb_frag_dma_map(priv->device, frag, 0, 2058 skb_frag_size(frag), 2059 DMA_TO_DEVICE); 2060 2061 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 2062 (i == nfrags - 1)); 2063 2064 priv->tx_skbuff_dma[priv->cur_tx].buf = des; 2065 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag); 2066 priv->tx_skbuff[priv->cur_tx] = NULL; 2067 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true; 2068 } 2069 2070 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true; 2071 2072 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2073 2074 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2075 if (netif_msg_hw(priv)) 2076 pr_debug("%s: stop transmitted packets\n", __func__); 2077 netif_stop_queue(dev); 2078 } 2079 2080 dev->stats.tx_bytes += skb->len; 2081 priv->xstats.tx_tso_frames++; 2082 priv->xstats.tx_tso_nfrags += nfrags; 2083 2084 /* Manage tx mitigation */ 2085 priv->tx_count_frames += nfrags + 1; 2086 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2087 mod_timer(&priv->txtimer, 2088 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2089 } else { 2090 priv->tx_count_frames = 0; 2091 priv->hw->desc->set_tx_ic(desc); 2092 priv->xstats.tx_set_ic_bit++; 2093 } 2094 2095 if (!priv->hwts_tx_en) 2096 skb_tx_timestamp(skb); 2097 2098 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2099 priv->hwts_tx_en)) { 2100 /* declare that device is doing timestamping */ 2101 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2102 priv->hw->desc->enable_tx_timestamp(first); 2103 } 2104 2105 /* Complete the first descriptor before granting the DMA */ 2106 priv->hw->desc->prepare_tso_tx_desc(first, 1, 2107 proto_hdr_len, 2108 pay_len, 2109 1, priv->tx_skbuff_dma[first_entry].last_segment, 2110 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2111 2112 /* If context desc is used to change MSS */ 2113 if (mss_desc) 2114 priv->hw->desc->set_tx_owner(mss_desc); 2115 2116 /* The own bit must be the latest setting done when prepare the 2117 * descriptor and then barrier is needed to make sure that 2118 * all is coherent before granting the DMA engine. 2119 */ 2120 smp_wmb(); 2121 2122 if (netif_msg_pktdata(priv)) { 2123 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 2124 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2125 priv->cur_tx, first, nfrags); 2126 2127 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 2128 0); 2129 2130 pr_info(">>> frame to be transmitted: "); 2131 print_pkt(skb->data, skb_headlen(skb)); 2132 } 2133 2134 netdev_sent_queue(dev, skb->len); 2135 2136 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2137 STMMAC_CHAN0); 2138 2139 spin_unlock(&priv->tx_lock); 2140 return NETDEV_TX_OK; 2141 2142 dma_map_err: 2143 spin_unlock(&priv->tx_lock); 2144 dev_err(priv->device, "Tx dma map failed\n"); 2145 dev_kfree_skb(skb); 2146 priv->dev->stats.tx_dropped++; 2147 return NETDEV_TX_OK; 2148 } 2149 2150 /** 2151 * stmmac_xmit - Tx entry point of the driver 2152 * @skb : the socket buffer 2153 * @dev : device pointer 2154 * Description : this is the tx entry point of the driver. 2155 * It programs the chain or the ring and supports oversized frames 2156 * and SG feature. 2157 */ 2158 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 2159 { 2160 struct stmmac_priv *priv = netdev_priv(dev); 2161 unsigned int nopaged_len = skb_headlen(skb); 2162 int i, csum_insertion = 0, is_jumbo = 0; 2163 int nfrags = skb_shinfo(skb)->nr_frags; 2164 unsigned int entry, first_entry; 2165 struct dma_desc *desc, *first; 2166 unsigned int enh_desc; 2167 unsigned int des; 2168 2169 /* Manage oversized TCP frames for GMAC4 device */ 2170 if (skb_is_gso(skb) && priv->tso) { 2171 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 2172 return stmmac_tso_xmit(skb, dev); 2173 } 2174 2175 spin_lock(&priv->tx_lock); 2176 2177 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 2178 spin_unlock(&priv->tx_lock); 2179 if (!netif_queue_stopped(dev)) { 2180 netif_stop_queue(dev); 2181 /* This is a hard error, log it. */ 2182 pr_err("%s: Tx Ring full when queue awake\n", __func__); 2183 } 2184 return NETDEV_TX_BUSY; 2185 } 2186 2187 if (priv->tx_path_in_lpi_mode) 2188 stmmac_disable_eee_mode(priv); 2189 2190 entry = priv->cur_tx; 2191 first_entry = entry; 2192 2193 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 2194 2195 if (likely(priv->extend_desc)) 2196 desc = (struct dma_desc *)(priv->dma_etx + entry); 2197 else 2198 desc = priv->dma_tx + entry; 2199 2200 first = desc; 2201 2202 priv->tx_skbuff[first_entry] = skb; 2203 2204 enh_desc = priv->plat->enh_desc; 2205 /* To program the descriptors according to the size of the frame */ 2206 if (enh_desc) 2207 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 2208 2209 if (unlikely(is_jumbo) && likely(priv->synopsys_id < 2210 DWMAC_CORE_4_00)) { 2211 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 2212 if (unlikely(entry < 0)) 2213 goto dma_map_err; 2214 } 2215 2216 for (i = 0; i < nfrags; i++) { 2217 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2218 int len = skb_frag_size(frag); 2219 bool last_segment = (i == (nfrags - 1)); 2220 2221 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2222 2223 if (likely(priv->extend_desc)) 2224 desc = (struct dma_desc *)(priv->dma_etx + entry); 2225 else 2226 desc = priv->dma_tx + entry; 2227 2228 des = skb_frag_dma_map(priv->device, frag, 0, len, 2229 DMA_TO_DEVICE); 2230 if (dma_mapping_error(priv->device, des)) 2231 goto dma_map_err; /* should reuse desc w/o issues */ 2232 2233 priv->tx_skbuff[entry] = NULL; 2234 2235 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2236 desc->des0 = des; 2237 priv->tx_skbuff_dma[entry].buf = desc->des0; 2238 } else { 2239 desc->des2 = des; 2240 priv->tx_skbuff_dma[entry].buf = desc->des2; 2241 } 2242 2243 priv->tx_skbuff_dma[entry].map_as_page = true; 2244 priv->tx_skbuff_dma[entry].len = len; 2245 priv->tx_skbuff_dma[entry].last_segment = last_segment; 2246 2247 /* Prepare the descriptor and set the own bit too */ 2248 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 2249 priv->mode, 1, last_segment); 2250 } 2251 2252 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2253 2254 priv->cur_tx = entry; 2255 2256 if (netif_msg_pktdata(priv)) { 2257 void *tx_head; 2258 2259 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 2260 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2261 entry, first, nfrags); 2262 2263 if (priv->extend_desc) 2264 tx_head = (void *)priv->dma_etx; 2265 else 2266 tx_head = (void *)priv->dma_tx; 2267 2268 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); 2269 2270 pr_debug(">>> frame to be transmitted: "); 2271 print_pkt(skb->data, skb->len); 2272 } 2273 2274 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2275 if (netif_msg_hw(priv)) 2276 pr_debug("%s: stop transmitted packets\n", __func__); 2277 netif_stop_queue(dev); 2278 } 2279 2280 dev->stats.tx_bytes += skb->len; 2281 2282 /* According to the coalesce parameter the IC bit for the latest 2283 * segment is reset and the timer re-started to clean the tx status. 2284 * This approach takes care about the fragments: desc is the first 2285 * element in case of no SG. 2286 */ 2287 priv->tx_count_frames += nfrags + 1; 2288 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2289 mod_timer(&priv->txtimer, 2290 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2291 } else { 2292 priv->tx_count_frames = 0; 2293 priv->hw->desc->set_tx_ic(desc); 2294 priv->xstats.tx_set_ic_bit++; 2295 } 2296 2297 if (!priv->hwts_tx_en) 2298 skb_tx_timestamp(skb); 2299 2300 /* Ready to fill the first descriptor and set the OWN bit w/o any 2301 * problems because all the descriptors are actually ready to be 2302 * passed to the DMA engine. 2303 */ 2304 if (likely(!is_jumbo)) { 2305 bool last_segment = (nfrags == 0); 2306 2307 des = dma_map_single(priv->device, skb->data, 2308 nopaged_len, DMA_TO_DEVICE); 2309 if (dma_mapping_error(priv->device, des)) 2310 goto dma_map_err; 2311 2312 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2313 first->des0 = des; 2314 priv->tx_skbuff_dma[first_entry].buf = first->des0; 2315 } else { 2316 first->des2 = des; 2317 priv->tx_skbuff_dma[first_entry].buf = first->des2; 2318 } 2319 2320 priv->tx_skbuff_dma[first_entry].len = nopaged_len; 2321 priv->tx_skbuff_dma[first_entry].last_segment = last_segment; 2322 2323 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2324 priv->hwts_tx_en)) { 2325 /* declare that device is doing timestamping */ 2326 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2327 priv->hw->desc->enable_tx_timestamp(first); 2328 } 2329 2330 /* Prepare the first descriptor setting the OWN bit too */ 2331 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, 2332 csum_insertion, priv->mode, 1, 2333 last_segment); 2334 2335 /* The own bit must be the latest setting done when prepare the 2336 * descriptor and then barrier is needed to make sure that 2337 * all is coherent before granting the DMA engine. 2338 */ 2339 smp_wmb(); 2340 } 2341 2342 netdev_sent_queue(dev, skb->len); 2343 2344 if (priv->synopsys_id < DWMAC_CORE_4_00) 2345 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2346 else 2347 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2348 STMMAC_CHAN0); 2349 2350 spin_unlock(&priv->tx_lock); 2351 return NETDEV_TX_OK; 2352 2353 dma_map_err: 2354 spin_unlock(&priv->tx_lock); 2355 dev_err(priv->device, "Tx dma map failed\n"); 2356 dev_kfree_skb(skb); 2357 priv->dev->stats.tx_dropped++; 2358 return NETDEV_TX_OK; 2359 } 2360 2361 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2362 { 2363 struct ethhdr *ehdr; 2364 u16 vlanid; 2365 2366 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2367 NETIF_F_HW_VLAN_CTAG_RX && 2368 !__vlan_get_tag(skb, &vlanid)) { 2369 /* pop the vlan tag */ 2370 ehdr = (struct ethhdr *)skb->data; 2371 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2372 skb_pull(skb, VLAN_HLEN); 2373 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2374 } 2375 } 2376 2377 2378 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv) 2379 { 2380 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH) 2381 return 0; 2382 2383 return 1; 2384 } 2385 2386 /** 2387 * stmmac_rx_refill - refill used skb preallocated buffers 2388 * @priv: driver private structure 2389 * Description : this is to reallocate the skb for the reception process 2390 * that is based on zero-copy. 2391 */ 2392 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2393 { 2394 int bfsize = priv->dma_buf_sz; 2395 unsigned int entry = priv->dirty_rx; 2396 int dirty = stmmac_rx_dirty(priv); 2397 2398 while (dirty-- > 0) { 2399 struct dma_desc *p; 2400 2401 if (priv->extend_desc) 2402 p = (struct dma_desc *)(priv->dma_erx + entry); 2403 else 2404 p = priv->dma_rx + entry; 2405 2406 if (likely(priv->rx_skbuff[entry] == NULL)) { 2407 struct sk_buff *skb; 2408 2409 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2410 if (unlikely(!skb)) { 2411 /* so for a while no zero-copy! */ 2412 priv->rx_zeroc_thresh = STMMAC_RX_THRESH; 2413 if (unlikely(net_ratelimit())) 2414 dev_err(priv->device, 2415 "fail to alloc skb entry %d\n", 2416 entry); 2417 break; 2418 } 2419 2420 priv->rx_skbuff[entry] = skb; 2421 priv->rx_skbuff_dma[entry] = 2422 dma_map_single(priv->device, skb->data, bfsize, 2423 DMA_FROM_DEVICE); 2424 if (dma_mapping_error(priv->device, 2425 priv->rx_skbuff_dma[entry])) { 2426 dev_err(priv->device, "Rx dma map failed\n"); 2427 dev_kfree_skb(skb); 2428 break; 2429 } 2430 2431 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2432 p->des0 = priv->rx_skbuff_dma[entry]; 2433 p->des1 = 0; 2434 } else { 2435 p->des2 = priv->rx_skbuff_dma[entry]; 2436 } 2437 if (priv->hw->mode->refill_desc3) 2438 priv->hw->mode->refill_desc3(priv, p); 2439 2440 if (priv->rx_zeroc_thresh > 0) 2441 priv->rx_zeroc_thresh--; 2442 2443 if (netif_msg_rx_status(priv)) 2444 pr_debug("\trefill entry #%d\n", entry); 2445 } 2446 wmb(); 2447 2448 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2449 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0); 2450 else 2451 priv->hw->desc->set_rx_owner(p); 2452 2453 wmb(); 2454 2455 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 2456 } 2457 priv->dirty_rx = entry; 2458 } 2459 2460 /** 2461 * stmmac_rx - manage the receive process 2462 * @priv: driver private structure 2463 * @limit: napi bugget. 2464 * Description : this the function called by the napi poll method. 2465 * It gets all the frames inside the ring. 2466 */ 2467 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2468 { 2469 unsigned int entry = priv->cur_rx; 2470 unsigned int next_entry; 2471 unsigned int count = 0; 2472 int coe = priv->hw->rx_csum; 2473 2474 if (netif_msg_rx_status(priv)) { 2475 void *rx_head; 2476 2477 pr_debug("%s: descriptor ring:\n", __func__); 2478 if (priv->extend_desc) 2479 rx_head = (void *)priv->dma_erx; 2480 else 2481 rx_head = (void *)priv->dma_rx; 2482 2483 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true); 2484 } 2485 while (count < limit) { 2486 int status; 2487 struct dma_desc *p; 2488 2489 if (priv->extend_desc) 2490 p = (struct dma_desc *)(priv->dma_erx + entry); 2491 else 2492 p = priv->dma_rx + entry; 2493 2494 /* read the status of the incoming frame */ 2495 status = priv->hw->desc->rx_status(&priv->dev->stats, 2496 &priv->xstats, p); 2497 /* check if managed by the DMA otherwise go ahead */ 2498 if (unlikely(status & dma_own)) 2499 break; 2500 2501 count++; 2502 2503 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); 2504 next_entry = priv->cur_rx; 2505 2506 if (priv->extend_desc) 2507 prefetch(priv->dma_erx + next_entry); 2508 else 2509 prefetch(priv->dma_rx + next_entry); 2510 2511 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2512 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2513 &priv->xstats, 2514 priv->dma_erx + 2515 entry); 2516 if (unlikely(status == discard_frame)) { 2517 priv->dev->stats.rx_errors++; 2518 if (priv->hwts_rx_en && !priv->extend_desc) { 2519 /* DESC2 & DESC3 will be overwitten by device 2520 * with timestamp value, hence reinitialize 2521 * them in stmmac_rx_refill() function so that 2522 * device can reuse it. 2523 */ 2524 priv->rx_skbuff[entry] = NULL; 2525 dma_unmap_single(priv->device, 2526 priv->rx_skbuff_dma[entry], 2527 priv->dma_buf_sz, 2528 DMA_FROM_DEVICE); 2529 } 2530 } else { 2531 struct sk_buff *skb; 2532 int frame_len; 2533 unsigned int des; 2534 2535 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2536 des = p->des0; 2537 else 2538 des = p->des2; 2539 2540 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2541 2542 /* If frame length is greather than skb buffer size 2543 * (preallocated during init) then the packet is 2544 * ignored 2545 */ 2546 if (frame_len > priv->dma_buf_sz) { 2547 pr_err("%s: len %d larger than size (%d)\n", 2548 priv->dev->name, frame_len, 2549 priv->dma_buf_sz); 2550 priv->dev->stats.rx_length_errors++; 2551 break; 2552 } 2553 2554 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2555 * Type frames (LLC/LLC-SNAP) 2556 */ 2557 if (unlikely(status != llc_snap)) 2558 frame_len -= ETH_FCS_LEN; 2559 2560 if (netif_msg_rx_status(priv)) { 2561 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2562 p, entry, des); 2563 if (frame_len > ETH_FRAME_LEN) 2564 pr_debug("\tframe size %d, COE: %d\n", 2565 frame_len, status); 2566 } 2567 2568 /* The zero-copy is always used for all the sizes 2569 * in case of GMAC4 because it needs 2570 * to refill the used descriptors, always. 2571 */ 2572 if (unlikely(!priv->plat->has_gmac4 && 2573 ((frame_len < priv->rx_copybreak) || 2574 stmmac_rx_threshold_count(priv)))) { 2575 skb = netdev_alloc_skb_ip_align(priv->dev, 2576 frame_len); 2577 if (unlikely(!skb)) { 2578 if (net_ratelimit()) 2579 dev_warn(priv->device, 2580 "packet dropped\n"); 2581 priv->dev->stats.rx_dropped++; 2582 break; 2583 } 2584 2585 dma_sync_single_for_cpu(priv->device, 2586 priv->rx_skbuff_dma 2587 [entry], frame_len, 2588 DMA_FROM_DEVICE); 2589 skb_copy_to_linear_data(skb, 2590 priv-> 2591 rx_skbuff[entry]->data, 2592 frame_len); 2593 2594 skb_put(skb, frame_len); 2595 dma_sync_single_for_device(priv->device, 2596 priv->rx_skbuff_dma 2597 [entry], frame_len, 2598 DMA_FROM_DEVICE); 2599 } else { 2600 skb = priv->rx_skbuff[entry]; 2601 if (unlikely(!skb)) { 2602 pr_err("%s: Inconsistent Rx chain\n", 2603 priv->dev->name); 2604 priv->dev->stats.rx_dropped++; 2605 break; 2606 } 2607 prefetch(skb->data - NET_IP_ALIGN); 2608 priv->rx_skbuff[entry] = NULL; 2609 priv->rx_zeroc_thresh++; 2610 2611 skb_put(skb, frame_len); 2612 dma_unmap_single(priv->device, 2613 priv->rx_skbuff_dma[entry], 2614 priv->dma_buf_sz, 2615 DMA_FROM_DEVICE); 2616 } 2617 2618 stmmac_get_rx_hwtstamp(priv, entry, skb); 2619 2620 if (netif_msg_pktdata(priv)) { 2621 pr_debug("frame received (%dbytes)", frame_len); 2622 print_pkt(skb->data, frame_len); 2623 } 2624 2625 stmmac_rx_vlan(priv->dev, skb); 2626 2627 skb->protocol = eth_type_trans(skb, priv->dev); 2628 2629 if (unlikely(!coe)) 2630 skb_checksum_none_assert(skb); 2631 else 2632 skb->ip_summed = CHECKSUM_UNNECESSARY; 2633 2634 napi_gro_receive(&priv->napi, skb); 2635 2636 priv->dev->stats.rx_packets++; 2637 priv->dev->stats.rx_bytes += frame_len; 2638 } 2639 entry = next_entry; 2640 } 2641 2642 stmmac_rx_refill(priv); 2643 2644 priv->xstats.rx_pkt_n += count; 2645 2646 return count; 2647 } 2648 2649 /** 2650 * stmmac_poll - stmmac poll method (NAPI) 2651 * @napi : pointer to the napi structure. 2652 * @budget : maximum number of packets that the current CPU can receive from 2653 * all interfaces. 2654 * Description : 2655 * To look at the incoming frames and clear the tx resources. 2656 */ 2657 static int stmmac_poll(struct napi_struct *napi, int budget) 2658 { 2659 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2660 int work_done = 0; 2661 2662 priv->xstats.napi_poll++; 2663 stmmac_tx_clean(priv); 2664 2665 work_done = stmmac_rx(priv, budget); 2666 if (work_done < budget) { 2667 napi_complete(napi); 2668 stmmac_enable_dma_irq(priv); 2669 } 2670 return work_done; 2671 } 2672 2673 /** 2674 * stmmac_tx_timeout 2675 * @dev : Pointer to net device structure 2676 * Description: this function is called when a packet transmission fails to 2677 * complete within a reasonable time. The driver will mark the error in the 2678 * netdev structure and arrange for the device to be reset to a sane state 2679 * in order to transmit a new packet. 2680 */ 2681 static void stmmac_tx_timeout(struct net_device *dev) 2682 { 2683 struct stmmac_priv *priv = netdev_priv(dev); 2684 2685 /* Clear Tx resources and restart transmitting again */ 2686 stmmac_tx_err(priv); 2687 } 2688 2689 /** 2690 * stmmac_set_rx_mode - entry point for multicast addressing 2691 * @dev : pointer to the device structure 2692 * Description: 2693 * This function is a driver entry point which gets called by the kernel 2694 * whenever multicast addresses must be enabled/disabled. 2695 * Return value: 2696 * void. 2697 */ 2698 static void stmmac_set_rx_mode(struct net_device *dev) 2699 { 2700 struct stmmac_priv *priv = netdev_priv(dev); 2701 2702 priv->hw->mac->set_filter(priv->hw, dev); 2703 } 2704 2705 /** 2706 * stmmac_change_mtu - entry point to change MTU size for the device. 2707 * @dev : device pointer. 2708 * @new_mtu : the new MTU size for the device. 2709 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2710 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2711 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2712 * Return value: 2713 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2714 * file on failure. 2715 */ 2716 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2717 { 2718 struct stmmac_priv *priv = netdev_priv(dev); 2719 int max_mtu; 2720 2721 if (netif_running(dev)) { 2722 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2723 return -EBUSY; 2724 } 2725 2726 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 2727 max_mtu = JUMBO_LEN; 2728 else 2729 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2730 2731 if (priv->plat->maxmtu < max_mtu) 2732 max_mtu = priv->plat->maxmtu; 2733 2734 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2735 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2736 return -EINVAL; 2737 } 2738 2739 dev->mtu = new_mtu; 2740 2741 netdev_update_features(dev); 2742 2743 return 0; 2744 } 2745 2746 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2747 netdev_features_t features) 2748 { 2749 struct stmmac_priv *priv = netdev_priv(dev); 2750 2751 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2752 features &= ~NETIF_F_RXCSUM; 2753 2754 if (!priv->plat->tx_coe) 2755 features &= ~NETIF_F_CSUM_MASK; 2756 2757 /* Some GMAC devices have a bugged Jumbo frame support that 2758 * needs to have the Tx COE disabled for oversized frames 2759 * (due to limited buffer sizes). In this case we disable 2760 * the TX csum insertionin the TDES and not use SF. 2761 */ 2762 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2763 features &= ~NETIF_F_CSUM_MASK; 2764 2765 /* Disable tso if asked by ethtool */ 2766 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 2767 if (features & NETIF_F_TSO) 2768 priv->tso = true; 2769 else 2770 priv->tso = false; 2771 } 2772 2773 return features; 2774 } 2775 2776 static int stmmac_set_features(struct net_device *netdev, 2777 netdev_features_t features) 2778 { 2779 struct stmmac_priv *priv = netdev_priv(netdev); 2780 2781 /* Keep the COE Type in case of csum is supporting */ 2782 if (features & NETIF_F_RXCSUM) 2783 priv->hw->rx_csum = priv->plat->rx_coe; 2784 else 2785 priv->hw->rx_csum = 0; 2786 /* No check needed because rx_coe has been set before and it will be 2787 * fixed in case of issue. 2788 */ 2789 priv->hw->mac->rx_ipc(priv->hw); 2790 2791 return 0; 2792 } 2793 2794 /** 2795 * stmmac_interrupt - main ISR 2796 * @irq: interrupt number. 2797 * @dev_id: to pass the net device pointer. 2798 * Description: this is the main driver interrupt service routine. 2799 * It can call: 2800 * o DMA service routine (to manage incoming frame reception and transmission 2801 * status) 2802 * o Core interrupts to manage: remote wake-up, management counter, LPI 2803 * interrupts. 2804 */ 2805 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2806 { 2807 struct net_device *dev = (struct net_device *)dev_id; 2808 struct stmmac_priv *priv = netdev_priv(dev); 2809 2810 if (priv->irq_wake) 2811 pm_wakeup_event(priv->device, 0); 2812 2813 if (unlikely(!dev)) { 2814 pr_err("%s: invalid dev pointer\n", __func__); 2815 return IRQ_NONE; 2816 } 2817 2818 /* To handle GMAC own interrupts */ 2819 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { 2820 int status = priv->hw->mac->host_irq_status(priv->hw, 2821 &priv->xstats); 2822 if (unlikely(status)) { 2823 /* For LPI we need to save the tx status */ 2824 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2825 priv->tx_path_in_lpi_mode = true; 2826 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2827 priv->tx_path_in_lpi_mode = false; 2828 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr) 2829 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, 2830 priv->rx_tail_addr, 2831 STMMAC_CHAN0); 2832 } 2833 2834 /* PCS link status */ 2835 if (priv->hw->pcs) { 2836 if (priv->xstats.pcs_link) 2837 netif_carrier_on(dev); 2838 else 2839 netif_carrier_off(dev); 2840 } 2841 } 2842 2843 /* To handle DMA interrupts */ 2844 stmmac_dma_interrupt(priv); 2845 2846 return IRQ_HANDLED; 2847 } 2848 2849 #ifdef CONFIG_NET_POLL_CONTROLLER 2850 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2851 * to allow network I/O with interrupts disabled. 2852 */ 2853 static void stmmac_poll_controller(struct net_device *dev) 2854 { 2855 disable_irq(dev->irq); 2856 stmmac_interrupt(dev->irq, dev); 2857 enable_irq(dev->irq); 2858 } 2859 #endif 2860 2861 /** 2862 * stmmac_ioctl - Entry point for the Ioctl 2863 * @dev: Device pointer. 2864 * @rq: An IOCTL specefic structure, that can contain a pointer to 2865 * a proprietary structure used to pass information to the driver. 2866 * @cmd: IOCTL command 2867 * Description: 2868 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2869 */ 2870 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2871 { 2872 int ret = -EOPNOTSUPP; 2873 2874 if (!netif_running(dev)) 2875 return -EINVAL; 2876 2877 switch (cmd) { 2878 case SIOCGMIIPHY: 2879 case SIOCGMIIREG: 2880 case SIOCSMIIREG: 2881 if (!dev->phydev) 2882 return -EINVAL; 2883 ret = phy_mii_ioctl(dev->phydev, rq, cmd); 2884 break; 2885 case SIOCSHWTSTAMP: 2886 ret = stmmac_hwtstamp_ioctl(dev, rq); 2887 break; 2888 default: 2889 break; 2890 } 2891 2892 return ret; 2893 } 2894 2895 #ifdef CONFIG_DEBUG_FS 2896 static struct dentry *stmmac_fs_dir; 2897 2898 static void sysfs_display_ring(void *head, int size, int extend_desc, 2899 struct seq_file *seq) 2900 { 2901 int i; 2902 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2903 struct dma_desc *p = (struct dma_desc *)head; 2904 2905 for (i = 0; i < size; i++) { 2906 u64 x; 2907 if (extend_desc) { 2908 x = *(u64 *) ep; 2909 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2910 i, (unsigned int)virt_to_phys(ep), 2911 ep->basic.des0, ep->basic.des1, 2912 ep->basic.des2, ep->basic.des3); 2913 ep++; 2914 } else { 2915 x = *(u64 *) p; 2916 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2917 i, (unsigned int)virt_to_phys(ep), 2918 p->des0, p->des1, p->des2, p->des3); 2919 p++; 2920 } 2921 seq_printf(seq, "\n"); 2922 } 2923 } 2924 2925 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2926 { 2927 struct net_device *dev = seq->private; 2928 struct stmmac_priv *priv = netdev_priv(dev); 2929 2930 if (priv->extend_desc) { 2931 seq_printf(seq, "Extended RX descriptor ring:\n"); 2932 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); 2933 seq_printf(seq, "Extended TX descriptor ring:\n"); 2934 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); 2935 } else { 2936 seq_printf(seq, "RX descriptor ring:\n"); 2937 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); 2938 seq_printf(seq, "TX descriptor ring:\n"); 2939 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); 2940 } 2941 2942 return 0; 2943 } 2944 2945 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2946 { 2947 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2948 } 2949 2950 static const struct file_operations stmmac_rings_status_fops = { 2951 .owner = THIS_MODULE, 2952 .open = stmmac_sysfs_ring_open, 2953 .read = seq_read, 2954 .llseek = seq_lseek, 2955 .release = single_release, 2956 }; 2957 2958 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2959 { 2960 struct net_device *dev = seq->private; 2961 struct stmmac_priv *priv = netdev_priv(dev); 2962 2963 if (!priv->hw_cap_support) { 2964 seq_printf(seq, "DMA HW features not supported\n"); 2965 return 0; 2966 } 2967 2968 seq_printf(seq, "==============================\n"); 2969 seq_printf(seq, "\tDMA HW features\n"); 2970 seq_printf(seq, "==============================\n"); 2971 2972 seq_printf(seq, "\t10/100 Mbps %s\n", 2973 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2974 seq_printf(seq, "\t1000 Mbps %s\n", 2975 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2976 seq_printf(seq, "\tHalf duple %s\n", 2977 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2978 seq_printf(seq, "\tHash Filter: %s\n", 2979 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2980 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2981 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2982 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2983 (priv->dma_cap.pcs) ? "Y" : "N"); 2984 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2985 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2986 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2987 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2988 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2989 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2990 seq_printf(seq, "\tRMON module: %s\n", 2991 (priv->dma_cap.rmon) ? "Y" : "N"); 2992 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2993 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2994 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2995 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2996 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2997 (priv->dma_cap.eee) ? "Y" : "N"); 2998 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2999 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 3000 (priv->dma_cap.tx_coe) ? "Y" : "N"); 3001 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3002 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 3003 (priv->dma_cap.rx_coe) ? "Y" : "N"); 3004 } else { 3005 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 3006 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 3007 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 3008 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 3009 } 3010 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 3011 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 3012 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 3013 priv->dma_cap.number_rx_channel); 3014 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 3015 priv->dma_cap.number_tx_channel); 3016 seq_printf(seq, "\tEnhanced descriptors: %s\n", 3017 (priv->dma_cap.enh_desc) ? "Y" : "N"); 3018 3019 return 0; 3020 } 3021 3022 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 3023 { 3024 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 3025 } 3026 3027 static const struct file_operations stmmac_dma_cap_fops = { 3028 .owner = THIS_MODULE, 3029 .open = stmmac_sysfs_dma_cap_open, 3030 .read = seq_read, 3031 .llseek = seq_lseek, 3032 .release = single_release, 3033 }; 3034 3035 static int stmmac_init_fs(struct net_device *dev) 3036 { 3037 struct stmmac_priv *priv = netdev_priv(dev); 3038 3039 /* Create per netdev entries */ 3040 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 3041 3042 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 3043 pr_err("ERROR %s/%s, debugfs create directory failed\n", 3044 STMMAC_RESOURCE_NAME, dev->name); 3045 3046 return -ENOMEM; 3047 } 3048 3049 /* Entry to report DMA RX/TX rings */ 3050 priv->dbgfs_rings_status = 3051 debugfs_create_file("descriptors_status", S_IRUGO, 3052 priv->dbgfs_dir, dev, 3053 &stmmac_rings_status_fops); 3054 3055 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 3056 pr_info("ERROR creating stmmac ring debugfs file\n"); 3057 debugfs_remove_recursive(priv->dbgfs_dir); 3058 3059 return -ENOMEM; 3060 } 3061 3062 /* Entry to report the DMA HW features */ 3063 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, 3064 priv->dbgfs_dir, 3065 dev, &stmmac_dma_cap_fops); 3066 3067 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 3068 pr_info("ERROR creating stmmac MMC debugfs file\n"); 3069 debugfs_remove_recursive(priv->dbgfs_dir); 3070 3071 return -ENOMEM; 3072 } 3073 3074 return 0; 3075 } 3076 3077 static void stmmac_exit_fs(struct net_device *dev) 3078 { 3079 struct stmmac_priv *priv = netdev_priv(dev); 3080 3081 debugfs_remove_recursive(priv->dbgfs_dir); 3082 } 3083 #endif /* CONFIG_DEBUG_FS */ 3084 3085 static const struct net_device_ops stmmac_netdev_ops = { 3086 .ndo_open = stmmac_open, 3087 .ndo_start_xmit = stmmac_xmit, 3088 .ndo_stop = stmmac_release, 3089 .ndo_change_mtu = stmmac_change_mtu, 3090 .ndo_fix_features = stmmac_fix_features, 3091 .ndo_set_features = stmmac_set_features, 3092 .ndo_set_rx_mode = stmmac_set_rx_mode, 3093 .ndo_tx_timeout = stmmac_tx_timeout, 3094 .ndo_do_ioctl = stmmac_ioctl, 3095 #ifdef CONFIG_NET_POLL_CONTROLLER 3096 .ndo_poll_controller = stmmac_poll_controller, 3097 #endif 3098 .ndo_set_mac_address = eth_mac_addr, 3099 }; 3100 3101 /** 3102 * stmmac_hw_init - Init the MAC device 3103 * @priv: driver private structure 3104 * Description: this function is to configure the MAC device according to 3105 * some platform parameters or the HW capability register. It prepares the 3106 * driver to use either ring or chain modes and to setup either enhanced or 3107 * normal descriptors. 3108 */ 3109 static int stmmac_hw_init(struct stmmac_priv *priv) 3110 { 3111 struct mac_device_info *mac; 3112 3113 /* Identify the MAC HW device */ 3114 if (priv->plat->has_gmac) { 3115 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3116 mac = dwmac1000_setup(priv->ioaddr, 3117 priv->plat->multicast_filter_bins, 3118 priv->plat->unicast_filter_entries, 3119 &priv->synopsys_id); 3120 } else if (priv->plat->has_gmac4) { 3121 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3122 mac = dwmac4_setup(priv->ioaddr, 3123 priv->plat->multicast_filter_bins, 3124 priv->plat->unicast_filter_entries, 3125 &priv->synopsys_id); 3126 } else { 3127 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id); 3128 } 3129 if (!mac) 3130 return -ENOMEM; 3131 3132 priv->hw = mac; 3133 3134 /* To use the chained or ring mode */ 3135 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3136 priv->hw->mode = &dwmac4_ring_mode_ops; 3137 } else { 3138 if (chain_mode) { 3139 priv->hw->mode = &chain_mode_ops; 3140 pr_info(" Chain mode enabled\n"); 3141 priv->mode = STMMAC_CHAIN_MODE; 3142 } else { 3143 priv->hw->mode = &ring_mode_ops; 3144 pr_info(" Ring mode enabled\n"); 3145 priv->mode = STMMAC_RING_MODE; 3146 } 3147 } 3148 3149 /* Get the HW capability (new GMAC newer than 3.50a) */ 3150 priv->hw_cap_support = stmmac_get_hw_features(priv); 3151 if (priv->hw_cap_support) { 3152 pr_info(" DMA HW capability register supported"); 3153 3154 /* We can override some gmac/dma configuration fields: e.g. 3155 * enh_desc, tx_coe (e.g. that are passed through the 3156 * platform) with the values from the HW capability 3157 * register (if supported). 3158 */ 3159 priv->plat->enh_desc = priv->dma_cap.enh_desc; 3160 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 3161 priv->hw->pmt = priv->plat->pmt; 3162 3163 /* TXCOE doesn't work in thresh DMA mode */ 3164 if (priv->plat->force_thresh_dma_mode) 3165 priv->plat->tx_coe = 0; 3166 else 3167 priv->plat->tx_coe = priv->dma_cap.tx_coe; 3168 3169 /* In case of GMAC4 rx_coe is from HW cap register. */ 3170 priv->plat->rx_coe = priv->dma_cap.rx_coe; 3171 3172 if (priv->dma_cap.rx_coe_type2) 3173 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 3174 else if (priv->dma_cap.rx_coe_type1) 3175 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 3176 3177 } else 3178 pr_info(" No HW DMA feature register supported"); 3179 3180 /* To use alternate (extended), normal or GMAC4 descriptor structures */ 3181 if (priv->synopsys_id >= DWMAC_CORE_4_00) 3182 priv->hw->desc = &dwmac4_desc_ops; 3183 else 3184 stmmac_selec_desc_mode(priv); 3185 3186 if (priv->plat->rx_coe) { 3187 priv->hw->rx_csum = priv->plat->rx_coe; 3188 pr_info(" RX Checksum Offload Engine supported\n"); 3189 if (priv->synopsys_id < DWMAC_CORE_4_00) 3190 pr_info("\tCOE Type %d\n", priv->hw->rx_csum); 3191 } 3192 if (priv->plat->tx_coe) 3193 pr_info(" TX Checksum insertion supported\n"); 3194 3195 if (priv->plat->pmt) { 3196 pr_info(" Wake-Up On Lan supported\n"); 3197 device_set_wakeup_capable(priv->device, 1); 3198 } 3199 3200 if (priv->dma_cap.tsoen) 3201 pr_info(" TSO supported\n"); 3202 3203 return 0; 3204 } 3205 3206 /** 3207 * stmmac_dvr_probe 3208 * @device: device pointer 3209 * @plat_dat: platform data pointer 3210 * @res: stmmac resource pointer 3211 * Description: this is the main probe function used to 3212 * call the alloc_etherdev, allocate the priv structure. 3213 * Return: 3214 * returns 0 on success, otherwise errno. 3215 */ 3216 int stmmac_dvr_probe(struct device *device, 3217 struct plat_stmmacenet_data *plat_dat, 3218 struct stmmac_resources *res) 3219 { 3220 int ret = 0; 3221 struct net_device *ndev = NULL; 3222 struct stmmac_priv *priv; 3223 3224 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 3225 if (!ndev) 3226 return -ENOMEM; 3227 3228 SET_NETDEV_DEV(ndev, device); 3229 3230 priv = netdev_priv(ndev); 3231 priv->device = device; 3232 priv->dev = ndev; 3233 3234 stmmac_set_ethtool_ops(ndev); 3235 priv->pause = pause; 3236 priv->plat = plat_dat; 3237 priv->ioaddr = res->addr; 3238 priv->dev->base_addr = (unsigned long)res->addr; 3239 3240 priv->dev->irq = res->irq; 3241 priv->wol_irq = res->wol_irq; 3242 priv->lpi_irq = res->lpi_irq; 3243 3244 if (res->mac) 3245 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 3246 3247 dev_set_drvdata(device, priv->dev); 3248 3249 /* Verify driver arguments */ 3250 stmmac_verify_args(); 3251 3252 /* Override with kernel parameters if supplied XXX CRS XXX 3253 * this needs to have multiple instances 3254 */ 3255 if ((phyaddr >= 0) && (phyaddr <= 31)) 3256 priv->plat->phy_addr = phyaddr; 3257 3258 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 3259 if (IS_ERR(priv->stmmac_clk)) { 3260 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 3261 __func__); 3262 /* If failed to obtain stmmac_clk and specific clk_csr value 3263 * is NOT passed from the platform, probe fail. 3264 */ 3265 if (!priv->plat->clk_csr) { 3266 ret = PTR_ERR(priv->stmmac_clk); 3267 goto error_clk_get; 3268 } else { 3269 priv->stmmac_clk = NULL; 3270 } 3271 } 3272 clk_prepare_enable(priv->stmmac_clk); 3273 3274 priv->pclk = devm_clk_get(priv->device, "pclk"); 3275 if (IS_ERR(priv->pclk)) { 3276 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { 3277 ret = -EPROBE_DEFER; 3278 goto error_pclk_get; 3279 } 3280 priv->pclk = NULL; 3281 } 3282 clk_prepare_enable(priv->pclk); 3283 3284 priv->stmmac_rst = devm_reset_control_get(priv->device, 3285 STMMAC_RESOURCE_NAME); 3286 if (IS_ERR(priv->stmmac_rst)) { 3287 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 3288 ret = -EPROBE_DEFER; 3289 goto error_hw_init; 3290 } 3291 dev_info(priv->device, "no reset control found\n"); 3292 priv->stmmac_rst = NULL; 3293 } 3294 if (priv->stmmac_rst) 3295 reset_control_deassert(priv->stmmac_rst); 3296 3297 /* Init MAC and get the capabilities */ 3298 ret = stmmac_hw_init(priv); 3299 if (ret) 3300 goto error_hw_init; 3301 3302 ndev->netdev_ops = &stmmac_netdev_ops; 3303 3304 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3305 NETIF_F_RXCSUM; 3306 3307 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3308 ndev->hw_features |= NETIF_F_TSO; 3309 priv->tso = true; 3310 pr_info(" TSO feature enabled\n"); 3311 } 3312 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 3313 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 3314 #ifdef STMMAC_VLAN_TAG_USED 3315 /* Both mac100 and gmac support receive VLAN tag detection */ 3316 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3317 #endif 3318 priv->msg_enable = netif_msg_init(debug, default_msg_level); 3319 3320 if (flow_ctrl) 3321 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 3322 3323 /* Rx Watchdog is available in the COREs newer than the 3.40. 3324 * In some case, for example on bugged HW this feature 3325 * has to be disable and this can be done by passing the 3326 * riwt_off field from the platform. 3327 */ 3328 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 3329 priv->use_riwt = 1; 3330 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 3331 } 3332 3333 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 3334 3335 spin_lock_init(&priv->lock); 3336 spin_lock_init(&priv->tx_lock); 3337 3338 ret = register_netdev(ndev); 3339 if (ret) { 3340 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 3341 goto error_netdev_register; 3342 } 3343 3344 /* If a specific clk_csr value is passed from the platform 3345 * this means that the CSR Clock Range selection cannot be 3346 * changed at run-time and it is fixed. Viceversa the driver'll try to 3347 * set the MDC clock dynamically according to the csr actual 3348 * clock input. 3349 */ 3350 if (!priv->plat->clk_csr) 3351 stmmac_clk_csr_set(priv); 3352 else 3353 priv->clk_csr = priv->plat->clk_csr; 3354 3355 stmmac_check_pcs_mode(priv); 3356 3357 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3358 priv->hw->pcs != STMMAC_PCS_TBI && 3359 priv->hw->pcs != STMMAC_PCS_RTBI) { 3360 /* MDIO bus Registration */ 3361 ret = stmmac_mdio_register(ndev); 3362 if (ret < 0) { 3363 pr_debug("%s: MDIO bus (id: %d) registration failed", 3364 __func__, priv->plat->bus_id); 3365 goto error_mdio_register; 3366 } 3367 } 3368 3369 return 0; 3370 3371 error_mdio_register: 3372 unregister_netdev(ndev); 3373 error_netdev_register: 3374 netif_napi_del(&priv->napi); 3375 error_hw_init: 3376 clk_disable_unprepare(priv->pclk); 3377 error_pclk_get: 3378 clk_disable_unprepare(priv->stmmac_clk); 3379 error_clk_get: 3380 free_netdev(ndev); 3381 3382 return ret; 3383 } 3384 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 3385 3386 /** 3387 * stmmac_dvr_remove 3388 * @dev: device pointer 3389 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 3390 * changes the link status, releases the DMA descriptor rings. 3391 */ 3392 int stmmac_dvr_remove(struct device *dev) 3393 { 3394 struct net_device *ndev = dev_get_drvdata(dev); 3395 struct stmmac_priv *priv = netdev_priv(ndev); 3396 3397 pr_info("%s:\n\tremoving driver", __func__); 3398 3399 priv->hw->dma->stop_rx(priv->ioaddr); 3400 priv->hw->dma->stop_tx(priv->ioaddr); 3401 3402 stmmac_set_mac(priv->ioaddr, false); 3403 netif_carrier_off(ndev); 3404 unregister_netdev(ndev); 3405 of_node_put(priv->plat->phy_node); 3406 if (priv->stmmac_rst) 3407 reset_control_assert(priv->stmmac_rst); 3408 clk_disable_unprepare(priv->pclk); 3409 clk_disable_unprepare(priv->stmmac_clk); 3410 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3411 priv->hw->pcs != STMMAC_PCS_TBI && 3412 priv->hw->pcs != STMMAC_PCS_RTBI) 3413 stmmac_mdio_unregister(ndev); 3414 free_netdev(ndev); 3415 3416 return 0; 3417 } 3418 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 3419 3420 /** 3421 * stmmac_suspend - suspend callback 3422 * @dev: device pointer 3423 * Description: this is the function to suspend the device and it is called 3424 * by the platform driver to stop the network queue, release the resources, 3425 * program the PMT register (for WoL), clean and release driver resources. 3426 */ 3427 int stmmac_suspend(struct device *dev) 3428 { 3429 struct net_device *ndev = dev_get_drvdata(dev); 3430 struct stmmac_priv *priv = netdev_priv(ndev); 3431 unsigned long flags; 3432 3433 if (!ndev || !netif_running(ndev)) 3434 return 0; 3435 3436 if (ndev->phydev) 3437 phy_stop(ndev->phydev); 3438 3439 spin_lock_irqsave(&priv->lock, flags); 3440 3441 netif_device_detach(ndev); 3442 netif_stop_queue(ndev); 3443 3444 napi_disable(&priv->napi); 3445 3446 /* Stop TX/RX DMA */ 3447 priv->hw->dma->stop_tx(priv->ioaddr); 3448 priv->hw->dma->stop_rx(priv->ioaddr); 3449 3450 /* Enable Power down mode by programming the PMT regs */ 3451 if (device_may_wakeup(priv->device)) { 3452 priv->hw->mac->pmt(priv->hw, priv->wolopts); 3453 priv->irq_wake = 1; 3454 } else { 3455 stmmac_set_mac(priv->ioaddr, false); 3456 pinctrl_pm_select_sleep_state(priv->device); 3457 /* Disable clock in case of PWM is off */ 3458 clk_disable(priv->pclk); 3459 clk_disable(priv->stmmac_clk); 3460 } 3461 spin_unlock_irqrestore(&priv->lock, flags); 3462 3463 priv->oldlink = 0; 3464 priv->speed = 0; 3465 priv->oldduplex = -1; 3466 return 0; 3467 } 3468 EXPORT_SYMBOL_GPL(stmmac_suspend); 3469 3470 /** 3471 * stmmac_resume - resume callback 3472 * @dev: device pointer 3473 * Description: when resume this function is invoked to setup the DMA and CORE 3474 * in a usable state. 3475 */ 3476 int stmmac_resume(struct device *dev) 3477 { 3478 struct net_device *ndev = dev_get_drvdata(dev); 3479 struct stmmac_priv *priv = netdev_priv(ndev); 3480 unsigned long flags; 3481 3482 if (!netif_running(ndev)) 3483 return 0; 3484 3485 /* Power Down bit, into the PM register, is cleared 3486 * automatically as soon as a magic packet or a Wake-up frame 3487 * is received. Anyway, it's better to manually clear 3488 * this bit because it can generate problems while resuming 3489 * from another devices (e.g. serial console). 3490 */ 3491 if (device_may_wakeup(priv->device)) { 3492 spin_lock_irqsave(&priv->lock, flags); 3493 priv->hw->mac->pmt(priv->hw, 0); 3494 spin_unlock_irqrestore(&priv->lock, flags); 3495 priv->irq_wake = 0; 3496 } else { 3497 pinctrl_pm_select_default_state(priv->device); 3498 /* enable the clk prevously disabled */ 3499 clk_enable(priv->stmmac_clk); 3500 clk_enable(priv->pclk); 3501 /* reset the phy so that it's ready */ 3502 if (priv->mii) 3503 stmmac_mdio_reset(priv->mii); 3504 } 3505 3506 netif_device_attach(ndev); 3507 3508 spin_lock_irqsave(&priv->lock, flags); 3509 3510 priv->cur_rx = 0; 3511 priv->dirty_rx = 0; 3512 priv->dirty_tx = 0; 3513 priv->cur_tx = 0; 3514 /* reset private mss value to force mss context settings at 3515 * next tso xmit (only used for gmac4). 3516 */ 3517 priv->mss = 0; 3518 3519 stmmac_clear_descriptors(priv); 3520 3521 stmmac_hw_setup(ndev, false); 3522 stmmac_init_tx_coalesce(priv); 3523 stmmac_set_rx_mode(ndev); 3524 3525 napi_enable(&priv->napi); 3526 3527 netif_start_queue(ndev); 3528 3529 spin_unlock_irqrestore(&priv->lock, flags); 3530 3531 if (ndev->phydev) 3532 phy_start(ndev->phydev); 3533 3534 return 0; 3535 } 3536 EXPORT_SYMBOL_GPL(stmmac_resume); 3537 3538 #ifndef MODULE 3539 static int __init stmmac_cmdline_opt(char *str) 3540 { 3541 char *opt; 3542 3543 if (!str || !*str) 3544 return -EINVAL; 3545 while ((opt = strsep(&str, ",")) != NULL) { 3546 if (!strncmp(opt, "debug:", 6)) { 3547 if (kstrtoint(opt + 6, 0, &debug)) 3548 goto err; 3549 } else if (!strncmp(opt, "phyaddr:", 8)) { 3550 if (kstrtoint(opt + 8, 0, &phyaddr)) 3551 goto err; 3552 } else if (!strncmp(opt, "buf_sz:", 7)) { 3553 if (kstrtoint(opt + 7, 0, &buf_sz)) 3554 goto err; 3555 } else if (!strncmp(opt, "tc:", 3)) { 3556 if (kstrtoint(opt + 3, 0, &tc)) 3557 goto err; 3558 } else if (!strncmp(opt, "watchdog:", 9)) { 3559 if (kstrtoint(opt + 9, 0, &watchdog)) 3560 goto err; 3561 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3562 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3563 goto err; 3564 } else if (!strncmp(opt, "pause:", 6)) { 3565 if (kstrtoint(opt + 6, 0, &pause)) 3566 goto err; 3567 } else if (!strncmp(opt, "eee_timer:", 10)) { 3568 if (kstrtoint(opt + 10, 0, &eee_timer)) 3569 goto err; 3570 } else if (!strncmp(opt, "chain_mode:", 11)) { 3571 if (kstrtoint(opt + 11, 0, &chain_mode)) 3572 goto err; 3573 } 3574 } 3575 return 0; 3576 3577 err: 3578 pr_err("%s: ERROR broken module parameter conversion", __func__); 3579 return -EINVAL; 3580 } 3581 3582 __setup("stmmaceth=", stmmac_cmdline_opt); 3583 #endif /* MODULE */ 3584 3585 static int __init stmmac_init(void) 3586 { 3587 #ifdef CONFIG_DEBUG_FS 3588 /* Create debugfs main directory if it doesn't exist yet */ 3589 if (!stmmac_fs_dir) { 3590 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 3591 3592 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 3593 pr_err("ERROR %s, debugfs create directory failed\n", 3594 STMMAC_RESOURCE_NAME); 3595 3596 return -ENOMEM; 3597 } 3598 } 3599 #endif 3600 3601 return 0; 3602 } 3603 3604 static void __exit stmmac_exit(void) 3605 { 3606 #ifdef CONFIG_DEBUG_FS 3607 debugfs_remove_recursive(stmmac_fs_dir); 3608 #endif 3609 } 3610 3611 module_init(stmmac_init) 3612 module_exit(stmmac_exit) 3613 3614 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3615 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3616 MODULE_LICENSE("GPL"); 3617