1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 if (priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) 992 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); 993 994 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 995 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 996 997 if (interface == PHY_INTERFACE_MODE_USXGMII) { 998 switch (speed) { 999 case SPEED_10000: 1000 ctrl |= priv->hw->link.xgmii.speed10000; 1001 break; 1002 case SPEED_5000: 1003 ctrl |= priv->hw->link.xgmii.speed5000; 1004 break; 1005 case SPEED_2500: 1006 ctrl |= priv->hw->link.xgmii.speed2500; 1007 break; 1008 default: 1009 return; 1010 } 1011 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1012 switch (speed) { 1013 case SPEED_100000: 1014 ctrl |= priv->hw->link.xlgmii.speed100000; 1015 break; 1016 case SPEED_50000: 1017 ctrl |= priv->hw->link.xlgmii.speed50000; 1018 break; 1019 case SPEED_40000: 1020 ctrl |= priv->hw->link.xlgmii.speed40000; 1021 break; 1022 case SPEED_25000: 1023 ctrl |= priv->hw->link.xlgmii.speed25000; 1024 break; 1025 case SPEED_10000: 1026 ctrl |= priv->hw->link.xgmii.speed10000; 1027 break; 1028 case SPEED_2500: 1029 ctrl |= priv->hw->link.speed2500; 1030 break; 1031 case SPEED_1000: 1032 ctrl |= priv->hw->link.speed1000; 1033 break; 1034 default: 1035 return; 1036 } 1037 } else { 1038 switch (speed) { 1039 case SPEED_2500: 1040 ctrl |= priv->hw->link.speed2500; 1041 break; 1042 case SPEED_1000: 1043 ctrl |= priv->hw->link.speed1000; 1044 break; 1045 case SPEED_100: 1046 ctrl |= priv->hw->link.speed100; 1047 break; 1048 case SPEED_10: 1049 ctrl |= priv->hw->link.speed10; 1050 break; 1051 default: 1052 return; 1053 } 1054 } 1055 1056 priv->speed = speed; 1057 1058 if (priv->plat->fix_mac_speed) 1059 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1060 1061 if (!duplex) 1062 ctrl &= ~priv->hw->link.duplex; 1063 else 1064 ctrl |= priv->hw->link.duplex; 1065 1066 /* Flow Control operation */ 1067 if (rx_pause && tx_pause) 1068 priv->flow_ctrl = FLOW_AUTO; 1069 else if (rx_pause && !tx_pause) 1070 priv->flow_ctrl = FLOW_RX; 1071 else if (!rx_pause && tx_pause) 1072 priv->flow_ctrl = FLOW_TX; 1073 else 1074 priv->flow_ctrl = FLOW_OFF; 1075 1076 stmmac_mac_flow_ctrl(priv, duplex); 1077 1078 if (ctrl != old_ctrl) 1079 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1080 1081 stmmac_mac_set(priv, priv->ioaddr, true); 1082 if (phy && priv->dma_cap.eee) { 1083 priv->eee_active = 1084 phy_init_eee(phy, !priv->plat->rx_clk_runs_in_lpi) >= 0; 1085 priv->eee_enabled = stmmac_eee_init(priv); 1086 priv->tx_lpi_enabled = priv->eee_enabled; 1087 stmmac_set_eee_pls(priv, priv->hw, true); 1088 } 1089 1090 if (priv->dma_cap.fpesel) 1091 stmmac_fpe_link_state_handle(priv, true); 1092 } 1093 1094 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1095 .mac_select_pcs = stmmac_mac_select_pcs, 1096 .mac_config = stmmac_mac_config, 1097 .mac_link_down = stmmac_mac_link_down, 1098 .mac_link_up = stmmac_mac_link_up, 1099 }; 1100 1101 /** 1102 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1103 * @priv: driver private structure 1104 * Description: this is to verify if the HW supports the PCS. 1105 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1106 * configured for the TBI, RTBI, or SGMII PHY interface. 1107 */ 1108 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1109 { 1110 int interface = priv->plat->interface; 1111 1112 if (priv->dma_cap.pcs) { 1113 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1114 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1115 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1116 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1117 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1118 priv->hw->pcs = STMMAC_PCS_RGMII; 1119 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1120 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1121 priv->hw->pcs = STMMAC_PCS_SGMII; 1122 } 1123 } 1124 } 1125 1126 /** 1127 * stmmac_init_phy - PHY initialization 1128 * @dev: net device structure 1129 * Description: it initializes the driver's PHY state, and attaches the PHY 1130 * to the mac driver. 1131 * Return value: 1132 * 0 on success 1133 */ 1134 static int stmmac_init_phy(struct net_device *dev) 1135 { 1136 struct stmmac_priv *priv = netdev_priv(dev); 1137 struct fwnode_handle *phy_fwnode; 1138 struct fwnode_handle *fwnode; 1139 int ret; 1140 1141 if (!phylink_expects_phy(priv->phylink)) 1142 return 0; 1143 1144 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1145 if (!fwnode) 1146 fwnode = dev_fwnode(priv->device); 1147 1148 if (fwnode) 1149 phy_fwnode = fwnode_get_phy_node(fwnode); 1150 else 1151 phy_fwnode = NULL; 1152 1153 /* Some DT bindings do not set-up the PHY handle. Let's try to 1154 * manually parse it 1155 */ 1156 if (!phy_fwnode || IS_ERR(phy_fwnode)) { 1157 int addr = priv->plat->phy_addr; 1158 struct phy_device *phydev; 1159 1160 if (addr < 0) { 1161 netdev_err(priv->dev, "no phy found\n"); 1162 return -ENODEV; 1163 } 1164 1165 phydev = mdiobus_get_phy(priv->mii, addr); 1166 if (!phydev) { 1167 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1168 return -ENODEV; 1169 } 1170 1171 ret = phylink_connect_phy(priv->phylink, phydev); 1172 } else { 1173 fwnode_handle_put(phy_fwnode); 1174 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1175 } 1176 1177 if (!priv->plat->pmt) { 1178 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1179 1180 phylink_ethtool_get_wol(priv->phylink, &wol); 1181 device_set_wakeup_capable(priv->device, !!wol.supported); 1182 device_set_wakeup_enable(priv->device, !!wol.wolopts); 1183 } 1184 1185 return ret; 1186 } 1187 1188 static int stmmac_phy_setup(struct stmmac_priv *priv) 1189 { 1190 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1191 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1192 int max_speed = priv->plat->max_speed; 1193 int mode = priv->plat->phy_interface; 1194 struct phylink *phylink; 1195 1196 priv->phylink_config.dev = &priv->dev->dev; 1197 priv->phylink_config.type = PHYLINK_NETDEV; 1198 if (priv->plat->mdio_bus_data) 1199 priv->phylink_config.ovr_an_inband = 1200 mdio_bus_data->xpcs_an_inband; 1201 1202 if (!fwnode) 1203 fwnode = dev_fwnode(priv->device); 1204 1205 /* Set the platform/firmware specified interface mode */ 1206 __set_bit(mode, priv->phylink_config.supported_interfaces); 1207 1208 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1209 if (priv->hw->xpcs) 1210 xpcs_get_interfaces(priv->hw->xpcs, 1211 priv->phylink_config.supported_interfaces); 1212 1213 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1214 MAC_10 | MAC_100; 1215 1216 if (!max_speed || max_speed >= 1000) 1217 priv->phylink_config.mac_capabilities |= MAC_1000; 1218 1219 if (priv->plat->has_gmac4) { 1220 if (!max_speed || max_speed >= 2500) 1221 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1222 } else if (priv->plat->has_xgmac) { 1223 if (!max_speed || max_speed >= 2500) 1224 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1225 if (!max_speed || max_speed >= 5000) 1226 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1227 if (!max_speed || max_speed >= 10000) 1228 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1229 if (!max_speed || max_speed >= 25000) 1230 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1231 if (!max_speed || max_speed >= 40000) 1232 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1233 if (!max_speed || max_speed >= 50000) 1234 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1235 if (!max_speed || max_speed >= 100000) 1236 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1237 } 1238 1239 /* Half-Duplex can only work with single queue */ 1240 if (priv->plat->tx_queues_to_use > 1) 1241 priv->phylink_config.mac_capabilities &= 1242 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1243 priv->phylink_config.mac_managed_pm = true; 1244 1245 phylink = phylink_create(&priv->phylink_config, fwnode, 1246 mode, &stmmac_phylink_mac_ops); 1247 if (IS_ERR(phylink)) 1248 return PTR_ERR(phylink); 1249 1250 priv->phylink = phylink; 1251 return 0; 1252 } 1253 1254 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1255 struct stmmac_dma_conf *dma_conf) 1256 { 1257 u32 rx_cnt = priv->plat->rx_queues_to_use; 1258 unsigned int desc_size; 1259 void *head_rx; 1260 u32 queue; 1261 1262 /* Display RX rings */ 1263 for (queue = 0; queue < rx_cnt; queue++) { 1264 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1265 1266 pr_info("\tRX Queue %u rings\n", queue); 1267 1268 if (priv->extend_desc) { 1269 head_rx = (void *)rx_q->dma_erx; 1270 desc_size = sizeof(struct dma_extended_desc); 1271 } else { 1272 head_rx = (void *)rx_q->dma_rx; 1273 desc_size = sizeof(struct dma_desc); 1274 } 1275 1276 /* Display RX ring */ 1277 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1278 rx_q->dma_rx_phy, desc_size); 1279 } 1280 } 1281 1282 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1283 struct stmmac_dma_conf *dma_conf) 1284 { 1285 u32 tx_cnt = priv->plat->tx_queues_to_use; 1286 unsigned int desc_size; 1287 void *head_tx; 1288 u32 queue; 1289 1290 /* Display TX rings */ 1291 for (queue = 0; queue < tx_cnt; queue++) { 1292 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1293 1294 pr_info("\tTX Queue %d rings\n", queue); 1295 1296 if (priv->extend_desc) { 1297 head_tx = (void *)tx_q->dma_etx; 1298 desc_size = sizeof(struct dma_extended_desc); 1299 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1300 head_tx = (void *)tx_q->dma_entx; 1301 desc_size = sizeof(struct dma_edesc); 1302 } else { 1303 head_tx = (void *)tx_q->dma_tx; 1304 desc_size = sizeof(struct dma_desc); 1305 } 1306 1307 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1308 tx_q->dma_tx_phy, desc_size); 1309 } 1310 } 1311 1312 static void stmmac_display_rings(struct stmmac_priv *priv, 1313 struct stmmac_dma_conf *dma_conf) 1314 { 1315 /* Display RX ring */ 1316 stmmac_display_rx_rings(priv, dma_conf); 1317 1318 /* Display TX ring */ 1319 stmmac_display_tx_rings(priv, dma_conf); 1320 } 1321 1322 static int stmmac_set_bfsize(int mtu, int bufsize) 1323 { 1324 int ret = bufsize; 1325 1326 if (mtu >= BUF_SIZE_8KiB) 1327 ret = BUF_SIZE_16KiB; 1328 else if (mtu >= BUF_SIZE_4KiB) 1329 ret = BUF_SIZE_8KiB; 1330 else if (mtu >= BUF_SIZE_2KiB) 1331 ret = BUF_SIZE_4KiB; 1332 else if (mtu > DEFAULT_BUFSIZE) 1333 ret = BUF_SIZE_2KiB; 1334 else 1335 ret = DEFAULT_BUFSIZE; 1336 1337 return ret; 1338 } 1339 1340 /** 1341 * stmmac_clear_rx_descriptors - clear RX descriptors 1342 * @priv: driver private structure 1343 * @dma_conf: structure to take the dma data 1344 * @queue: RX queue index 1345 * Description: this function is called to clear the RX descriptors 1346 * in case of both basic and extended descriptors are used. 1347 */ 1348 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1349 struct stmmac_dma_conf *dma_conf, 1350 u32 queue) 1351 { 1352 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1353 int i; 1354 1355 /* Clear the RX descriptors */ 1356 for (i = 0; i < dma_conf->dma_rx_size; i++) 1357 if (priv->extend_desc) 1358 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1359 priv->use_riwt, priv->mode, 1360 (i == dma_conf->dma_rx_size - 1), 1361 dma_conf->dma_buf_sz); 1362 else 1363 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1364 priv->use_riwt, priv->mode, 1365 (i == dma_conf->dma_rx_size - 1), 1366 dma_conf->dma_buf_sz); 1367 } 1368 1369 /** 1370 * stmmac_clear_tx_descriptors - clear tx descriptors 1371 * @priv: driver private structure 1372 * @dma_conf: structure to take the dma data 1373 * @queue: TX queue index. 1374 * Description: this function is called to clear the TX descriptors 1375 * in case of both basic and extended descriptors are used. 1376 */ 1377 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1378 struct stmmac_dma_conf *dma_conf, 1379 u32 queue) 1380 { 1381 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1382 int i; 1383 1384 /* Clear the TX descriptors */ 1385 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1386 int last = (i == (dma_conf->dma_tx_size - 1)); 1387 struct dma_desc *p; 1388 1389 if (priv->extend_desc) 1390 p = &tx_q->dma_etx[i].basic; 1391 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1392 p = &tx_q->dma_entx[i].basic; 1393 else 1394 p = &tx_q->dma_tx[i]; 1395 1396 stmmac_init_tx_desc(priv, p, priv->mode, last); 1397 } 1398 } 1399 1400 /** 1401 * stmmac_clear_descriptors - clear descriptors 1402 * @priv: driver private structure 1403 * @dma_conf: structure to take the dma data 1404 * Description: this function is called to clear the TX and RX descriptors 1405 * in case of both basic and extended descriptors are used. 1406 */ 1407 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1408 struct stmmac_dma_conf *dma_conf) 1409 { 1410 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1411 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1412 u32 queue; 1413 1414 /* Clear the RX descriptors */ 1415 for (queue = 0; queue < rx_queue_cnt; queue++) 1416 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1417 1418 /* Clear the TX descriptors */ 1419 for (queue = 0; queue < tx_queue_cnt; queue++) 1420 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1421 } 1422 1423 /** 1424 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1425 * @priv: driver private structure 1426 * @dma_conf: structure to take the dma data 1427 * @p: descriptor pointer 1428 * @i: descriptor index 1429 * @flags: gfp flag 1430 * @queue: RX queue index 1431 * Description: this function is called to allocate a receive buffer, perform 1432 * the DMA mapping and init the descriptor. 1433 */ 1434 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1435 struct stmmac_dma_conf *dma_conf, 1436 struct dma_desc *p, 1437 int i, gfp_t flags, u32 queue) 1438 { 1439 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1440 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1441 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1442 1443 if (priv->dma_cap.host_dma_width <= 32) 1444 gfp |= GFP_DMA32; 1445 1446 if (!buf->page) { 1447 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1448 if (!buf->page) 1449 return -ENOMEM; 1450 buf->page_offset = stmmac_rx_offset(priv); 1451 } 1452 1453 if (priv->sph && !buf->sec_page) { 1454 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1455 if (!buf->sec_page) 1456 return -ENOMEM; 1457 1458 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1459 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1460 } else { 1461 buf->sec_page = NULL; 1462 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1463 } 1464 1465 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1466 1467 stmmac_set_desc_addr(priv, p, buf->addr); 1468 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1469 stmmac_init_desc3(priv, p); 1470 1471 return 0; 1472 } 1473 1474 /** 1475 * stmmac_free_rx_buffer - free RX dma buffers 1476 * @priv: private structure 1477 * @rx_q: RX queue 1478 * @i: buffer index. 1479 */ 1480 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1481 struct stmmac_rx_queue *rx_q, 1482 int i) 1483 { 1484 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1485 1486 if (buf->page) 1487 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1488 buf->page = NULL; 1489 1490 if (buf->sec_page) 1491 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1492 buf->sec_page = NULL; 1493 } 1494 1495 /** 1496 * stmmac_free_tx_buffer - free RX dma buffers 1497 * @priv: private structure 1498 * @dma_conf: structure to take the dma data 1499 * @queue: RX queue index 1500 * @i: buffer index. 1501 */ 1502 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1503 struct stmmac_dma_conf *dma_conf, 1504 u32 queue, int i) 1505 { 1506 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1507 1508 if (tx_q->tx_skbuff_dma[i].buf && 1509 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1510 if (tx_q->tx_skbuff_dma[i].map_as_page) 1511 dma_unmap_page(priv->device, 1512 tx_q->tx_skbuff_dma[i].buf, 1513 tx_q->tx_skbuff_dma[i].len, 1514 DMA_TO_DEVICE); 1515 else 1516 dma_unmap_single(priv->device, 1517 tx_q->tx_skbuff_dma[i].buf, 1518 tx_q->tx_skbuff_dma[i].len, 1519 DMA_TO_DEVICE); 1520 } 1521 1522 if (tx_q->xdpf[i] && 1523 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1524 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1525 xdp_return_frame(tx_q->xdpf[i]); 1526 tx_q->xdpf[i] = NULL; 1527 } 1528 1529 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1530 tx_q->xsk_frames_done++; 1531 1532 if (tx_q->tx_skbuff[i] && 1533 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1534 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1535 tx_q->tx_skbuff[i] = NULL; 1536 } 1537 1538 tx_q->tx_skbuff_dma[i].buf = 0; 1539 tx_q->tx_skbuff_dma[i].map_as_page = false; 1540 } 1541 1542 /** 1543 * dma_free_rx_skbufs - free RX dma buffers 1544 * @priv: private structure 1545 * @dma_conf: structure to take the dma data 1546 * @queue: RX queue index 1547 */ 1548 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1549 struct stmmac_dma_conf *dma_conf, 1550 u32 queue) 1551 { 1552 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1553 int i; 1554 1555 for (i = 0; i < dma_conf->dma_rx_size; i++) 1556 stmmac_free_rx_buffer(priv, rx_q, i); 1557 } 1558 1559 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1560 struct stmmac_dma_conf *dma_conf, 1561 u32 queue, gfp_t flags) 1562 { 1563 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1564 int i; 1565 1566 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1567 struct dma_desc *p; 1568 int ret; 1569 1570 if (priv->extend_desc) 1571 p = &((rx_q->dma_erx + i)->basic); 1572 else 1573 p = rx_q->dma_rx + i; 1574 1575 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1576 queue); 1577 if (ret) 1578 return ret; 1579 1580 rx_q->buf_alloc_num++; 1581 } 1582 1583 return 0; 1584 } 1585 1586 /** 1587 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1588 * @priv: private structure 1589 * @dma_conf: structure to take the dma data 1590 * @queue: RX queue index 1591 */ 1592 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1593 struct stmmac_dma_conf *dma_conf, 1594 u32 queue) 1595 { 1596 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1597 int i; 1598 1599 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1600 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1601 1602 if (!buf->xdp) 1603 continue; 1604 1605 xsk_buff_free(buf->xdp); 1606 buf->xdp = NULL; 1607 } 1608 } 1609 1610 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1611 struct stmmac_dma_conf *dma_conf, 1612 u32 queue) 1613 { 1614 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1615 int i; 1616 1617 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1618 struct stmmac_rx_buffer *buf; 1619 dma_addr_t dma_addr; 1620 struct dma_desc *p; 1621 1622 if (priv->extend_desc) 1623 p = (struct dma_desc *)(rx_q->dma_erx + i); 1624 else 1625 p = rx_q->dma_rx + i; 1626 1627 buf = &rx_q->buf_pool[i]; 1628 1629 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1630 if (!buf->xdp) 1631 return -ENOMEM; 1632 1633 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1634 stmmac_set_desc_addr(priv, p, dma_addr); 1635 rx_q->buf_alloc_num++; 1636 } 1637 1638 return 0; 1639 } 1640 1641 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1642 { 1643 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1644 return NULL; 1645 1646 return xsk_get_pool_from_qid(priv->dev, queue); 1647 } 1648 1649 /** 1650 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1651 * @priv: driver private structure 1652 * @dma_conf: structure to take the dma data 1653 * @queue: RX queue index 1654 * @flags: gfp flag. 1655 * Description: this function initializes the DMA RX descriptors 1656 * and allocates the socket buffers. It supports the chained and ring 1657 * modes. 1658 */ 1659 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1660 struct stmmac_dma_conf *dma_conf, 1661 u32 queue, gfp_t flags) 1662 { 1663 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1664 int ret; 1665 1666 netif_dbg(priv, probe, priv->dev, 1667 "(%s) dma_rx_phy=0x%08x\n", __func__, 1668 (u32)rx_q->dma_rx_phy); 1669 1670 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1671 1672 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1673 1674 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1675 1676 if (rx_q->xsk_pool) { 1677 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1678 MEM_TYPE_XSK_BUFF_POOL, 1679 NULL)); 1680 netdev_info(priv->dev, 1681 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1682 rx_q->queue_index); 1683 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1684 } else { 1685 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1686 MEM_TYPE_PAGE_POOL, 1687 rx_q->page_pool)); 1688 netdev_info(priv->dev, 1689 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1690 rx_q->queue_index); 1691 } 1692 1693 if (rx_q->xsk_pool) { 1694 /* RX XDP ZC buffer pool may not be populated, e.g. 1695 * xdpsock TX-only. 1696 */ 1697 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1698 } else { 1699 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1700 if (ret < 0) 1701 return -ENOMEM; 1702 } 1703 1704 /* Setup the chained descriptor addresses */ 1705 if (priv->mode == STMMAC_CHAIN_MODE) { 1706 if (priv->extend_desc) 1707 stmmac_mode_init(priv, rx_q->dma_erx, 1708 rx_q->dma_rx_phy, 1709 dma_conf->dma_rx_size, 1); 1710 else 1711 stmmac_mode_init(priv, rx_q->dma_rx, 1712 rx_q->dma_rx_phy, 1713 dma_conf->dma_rx_size, 0); 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int init_dma_rx_desc_rings(struct net_device *dev, 1720 struct stmmac_dma_conf *dma_conf, 1721 gfp_t flags) 1722 { 1723 struct stmmac_priv *priv = netdev_priv(dev); 1724 u32 rx_count = priv->plat->rx_queues_to_use; 1725 int queue; 1726 int ret; 1727 1728 /* RX INITIALIZATION */ 1729 netif_dbg(priv, probe, priv->dev, 1730 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1731 1732 for (queue = 0; queue < rx_count; queue++) { 1733 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1734 if (ret) 1735 goto err_init_rx_buffers; 1736 } 1737 1738 return 0; 1739 1740 err_init_rx_buffers: 1741 while (queue >= 0) { 1742 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1743 1744 if (rx_q->xsk_pool) 1745 dma_free_rx_xskbufs(priv, dma_conf, queue); 1746 else 1747 dma_free_rx_skbufs(priv, dma_conf, queue); 1748 1749 rx_q->buf_alloc_num = 0; 1750 rx_q->xsk_pool = NULL; 1751 1752 queue--; 1753 } 1754 1755 return ret; 1756 } 1757 1758 /** 1759 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1760 * @priv: driver private structure 1761 * @dma_conf: structure to take the dma data 1762 * @queue: TX queue index 1763 * Description: this function initializes the DMA TX descriptors 1764 * and allocates the socket buffers. It supports the chained and ring 1765 * modes. 1766 */ 1767 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1768 struct stmmac_dma_conf *dma_conf, 1769 u32 queue) 1770 { 1771 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1772 int i; 1773 1774 netif_dbg(priv, probe, priv->dev, 1775 "(%s) dma_tx_phy=0x%08x\n", __func__, 1776 (u32)tx_q->dma_tx_phy); 1777 1778 /* Setup the chained descriptor addresses */ 1779 if (priv->mode == STMMAC_CHAIN_MODE) { 1780 if (priv->extend_desc) 1781 stmmac_mode_init(priv, tx_q->dma_etx, 1782 tx_q->dma_tx_phy, 1783 dma_conf->dma_tx_size, 1); 1784 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1785 stmmac_mode_init(priv, tx_q->dma_tx, 1786 tx_q->dma_tx_phy, 1787 dma_conf->dma_tx_size, 0); 1788 } 1789 1790 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1791 1792 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1793 struct dma_desc *p; 1794 1795 if (priv->extend_desc) 1796 p = &((tx_q->dma_etx + i)->basic); 1797 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1798 p = &((tx_q->dma_entx + i)->basic); 1799 else 1800 p = tx_q->dma_tx + i; 1801 1802 stmmac_clear_desc(priv, p); 1803 1804 tx_q->tx_skbuff_dma[i].buf = 0; 1805 tx_q->tx_skbuff_dma[i].map_as_page = false; 1806 tx_q->tx_skbuff_dma[i].len = 0; 1807 tx_q->tx_skbuff_dma[i].last_segment = false; 1808 tx_q->tx_skbuff[i] = NULL; 1809 } 1810 1811 return 0; 1812 } 1813 1814 static int init_dma_tx_desc_rings(struct net_device *dev, 1815 struct stmmac_dma_conf *dma_conf) 1816 { 1817 struct stmmac_priv *priv = netdev_priv(dev); 1818 u32 tx_queue_cnt; 1819 u32 queue; 1820 1821 tx_queue_cnt = priv->plat->tx_queues_to_use; 1822 1823 for (queue = 0; queue < tx_queue_cnt; queue++) 1824 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1825 1826 return 0; 1827 } 1828 1829 /** 1830 * init_dma_desc_rings - init the RX/TX descriptor rings 1831 * @dev: net device structure 1832 * @dma_conf: structure to take the dma data 1833 * @flags: gfp flag. 1834 * Description: this function initializes the DMA RX/TX descriptors 1835 * and allocates the socket buffers. It supports the chained and ring 1836 * modes. 1837 */ 1838 static int init_dma_desc_rings(struct net_device *dev, 1839 struct stmmac_dma_conf *dma_conf, 1840 gfp_t flags) 1841 { 1842 struct stmmac_priv *priv = netdev_priv(dev); 1843 int ret; 1844 1845 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1846 if (ret) 1847 return ret; 1848 1849 ret = init_dma_tx_desc_rings(dev, dma_conf); 1850 1851 stmmac_clear_descriptors(priv, dma_conf); 1852 1853 if (netif_msg_hw(priv)) 1854 stmmac_display_rings(priv, dma_conf); 1855 1856 return ret; 1857 } 1858 1859 /** 1860 * dma_free_tx_skbufs - free TX dma buffers 1861 * @priv: private structure 1862 * @dma_conf: structure to take the dma data 1863 * @queue: TX queue index 1864 */ 1865 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1866 struct stmmac_dma_conf *dma_conf, 1867 u32 queue) 1868 { 1869 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1870 int i; 1871 1872 tx_q->xsk_frames_done = 0; 1873 1874 for (i = 0; i < dma_conf->dma_tx_size; i++) 1875 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1876 1877 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1878 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1879 tx_q->xsk_frames_done = 0; 1880 tx_q->xsk_pool = NULL; 1881 } 1882 } 1883 1884 /** 1885 * stmmac_free_tx_skbufs - free TX skb buffers 1886 * @priv: private structure 1887 */ 1888 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1889 { 1890 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1891 u32 queue; 1892 1893 for (queue = 0; queue < tx_queue_cnt; queue++) 1894 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1895 } 1896 1897 /** 1898 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1899 * @priv: private structure 1900 * @dma_conf: structure to take the dma data 1901 * @queue: RX queue index 1902 */ 1903 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1904 struct stmmac_dma_conf *dma_conf, 1905 u32 queue) 1906 { 1907 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1908 1909 /* Release the DMA RX socket buffers */ 1910 if (rx_q->xsk_pool) 1911 dma_free_rx_xskbufs(priv, dma_conf, queue); 1912 else 1913 dma_free_rx_skbufs(priv, dma_conf, queue); 1914 1915 rx_q->buf_alloc_num = 0; 1916 rx_q->xsk_pool = NULL; 1917 1918 /* Free DMA regions of consistent memory previously allocated */ 1919 if (!priv->extend_desc) 1920 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1921 sizeof(struct dma_desc), 1922 rx_q->dma_rx, rx_q->dma_rx_phy); 1923 else 1924 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1925 sizeof(struct dma_extended_desc), 1926 rx_q->dma_erx, rx_q->dma_rx_phy); 1927 1928 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1929 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1930 1931 kfree(rx_q->buf_pool); 1932 if (rx_q->page_pool) 1933 page_pool_destroy(rx_q->page_pool); 1934 } 1935 1936 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1937 struct stmmac_dma_conf *dma_conf) 1938 { 1939 u32 rx_count = priv->plat->rx_queues_to_use; 1940 u32 queue; 1941 1942 /* Free RX queue resources */ 1943 for (queue = 0; queue < rx_count; queue++) 1944 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1945 } 1946 1947 /** 1948 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1949 * @priv: private structure 1950 * @dma_conf: structure to take the dma data 1951 * @queue: TX queue index 1952 */ 1953 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1954 struct stmmac_dma_conf *dma_conf, 1955 u32 queue) 1956 { 1957 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1958 size_t size; 1959 void *addr; 1960 1961 /* Release the DMA TX socket buffers */ 1962 dma_free_tx_skbufs(priv, dma_conf, queue); 1963 1964 if (priv->extend_desc) { 1965 size = sizeof(struct dma_extended_desc); 1966 addr = tx_q->dma_etx; 1967 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1968 size = sizeof(struct dma_edesc); 1969 addr = tx_q->dma_entx; 1970 } else { 1971 size = sizeof(struct dma_desc); 1972 addr = tx_q->dma_tx; 1973 } 1974 1975 size *= dma_conf->dma_tx_size; 1976 1977 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1978 1979 kfree(tx_q->tx_skbuff_dma); 1980 kfree(tx_q->tx_skbuff); 1981 } 1982 1983 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1984 struct stmmac_dma_conf *dma_conf) 1985 { 1986 u32 tx_count = priv->plat->tx_queues_to_use; 1987 u32 queue; 1988 1989 /* Free TX queue resources */ 1990 for (queue = 0; queue < tx_count; queue++) 1991 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1992 } 1993 1994 /** 1995 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1996 * @priv: private structure 1997 * @dma_conf: structure to take the dma data 1998 * @queue: RX queue index 1999 * Description: according to which descriptor can be used (extend or basic) 2000 * this function allocates the resources for TX and RX paths. In case of 2001 * reception, for example, it pre-allocated the RX socket buffer in order to 2002 * allow zero-copy mechanism. 2003 */ 2004 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2005 struct stmmac_dma_conf *dma_conf, 2006 u32 queue) 2007 { 2008 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 2009 struct stmmac_channel *ch = &priv->channel[queue]; 2010 bool xdp_prog = stmmac_xdp_is_enabled(priv); 2011 struct page_pool_params pp_params = { 0 }; 2012 unsigned int num_pages; 2013 unsigned int napi_id; 2014 int ret; 2015 2016 rx_q->queue_index = queue; 2017 rx_q->priv_data = priv; 2018 2019 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2020 pp_params.pool_size = dma_conf->dma_rx_size; 2021 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2022 pp_params.order = ilog2(num_pages); 2023 pp_params.nid = dev_to_node(priv->device); 2024 pp_params.dev = priv->device; 2025 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2026 pp_params.offset = stmmac_rx_offset(priv); 2027 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2028 2029 rx_q->page_pool = page_pool_create(&pp_params); 2030 if (IS_ERR(rx_q->page_pool)) { 2031 ret = PTR_ERR(rx_q->page_pool); 2032 rx_q->page_pool = NULL; 2033 return ret; 2034 } 2035 2036 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2037 sizeof(*rx_q->buf_pool), 2038 GFP_KERNEL); 2039 if (!rx_q->buf_pool) 2040 return -ENOMEM; 2041 2042 if (priv->extend_desc) { 2043 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2044 dma_conf->dma_rx_size * 2045 sizeof(struct dma_extended_desc), 2046 &rx_q->dma_rx_phy, 2047 GFP_KERNEL); 2048 if (!rx_q->dma_erx) 2049 return -ENOMEM; 2050 2051 } else { 2052 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2053 dma_conf->dma_rx_size * 2054 sizeof(struct dma_desc), 2055 &rx_q->dma_rx_phy, 2056 GFP_KERNEL); 2057 if (!rx_q->dma_rx) 2058 return -ENOMEM; 2059 } 2060 2061 if (stmmac_xdp_is_enabled(priv) && 2062 test_bit(queue, priv->af_xdp_zc_qps)) 2063 napi_id = ch->rxtx_napi.napi_id; 2064 else 2065 napi_id = ch->rx_napi.napi_id; 2066 2067 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2068 rx_q->queue_index, 2069 napi_id); 2070 if (ret) { 2071 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2072 return -EINVAL; 2073 } 2074 2075 return 0; 2076 } 2077 2078 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2079 struct stmmac_dma_conf *dma_conf) 2080 { 2081 u32 rx_count = priv->plat->rx_queues_to_use; 2082 u32 queue; 2083 int ret; 2084 2085 /* RX queues buffers and DMA */ 2086 for (queue = 0; queue < rx_count; queue++) { 2087 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2088 if (ret) 2089 goto err_dma; 2090 } 2091 2092 return 0; 2093 2094 err_dma: 2095 free_dma_rx_desc_resources(priv, dma_conf); 2096 2097 return ret; 2098 } 2099 2100 /** 2101 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2102 * @priv: private structure 2103 * @dma_conf: structure to take the dma data 2104 * @queue: TX queue index 2105 * Description: according to which descriptor can be used (extend or basic) 2106 * this function allocates the resources for TX and RX paths. In case of 2107 * reception, for example, it pre-allocated the RX socket buffer in order to 2108 * allow zero-copy mechanism. 2109 */ 2110 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2111 struct stmmac_dma_conf *dma_conf, 2112 u32 queue) 2113 { 2114 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2115 size_t size; 2116 void *addr; 2117 2118 tx_q->queue_index = queue; 2119 tx_q->priv_data = priv; 2120 2121 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2122 sizeof(*tx_q->tx_skbuff_dma), 2123 GFP_KERNEL); 2124 if (!tx_q->tx_skbuff_dma) 2125 return -ENOMEM; 2126 2127 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2128 sizeof(struct sk_buff *), 2129 GFP_KERNEL); 2130 if (!tx_q->tx_skbuff) 2131 return -ENOMEM; 2132 2133 if (priv->extend_desc) 2134 size = sizeof(struct dma_extended_desc); 2135 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2136 size = sizeof(struct dma_edesc); 2137 else 2138 size = sizeof(struct dma_desc); 2139 2140 size *= dma_conf->dma_tx_size; 2141 2142 addr = dma_alloc_coherent(priv->device, size, 2143 &tx_q->dma_tx_phy, GFP_KERNEL); 2144 if (!addr) 2145 return -ENOMEM; 2146 2147 if (priv->extend_desc) 2148 tx_q->dma_etx = addr; 2149 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2150 tx_q->dma_entx = addr; 2151 else 2152 tx_q->dma_tx = addr; 2153 2154 return 0; 2155 } 2156 2157 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2158 struct stmmac_dma_conf *dma_conf) 2159 { 2160 u32 tx_count = priv->plat->tx_queues_to_use; 2161 u32 queue; 2162 int ret; 2163 2164 /* TX queues buffers and DMA */ 2165 for (queue = 0; queue < tx_count; queue++) { 2166 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2167 if (ret) 2168 goto err_dma; 2169 } 2170 2171 return 0; 2172 2173 err_dma: 2174 free_dma_tx_desc_resources(priv, dma_conf); 2175 return ret; 2176 } 2177 2178 /** 2179 * alloc_dma_desc_resources - alloc TX/RX resources. 2180 * @priv: private structure 2181 * @dma_conf: structure to take the dma data 2182 * Description: according to which descriptor can be used (extend or basic) 2183 * this function allocates the resources for TX and RX paths. In case of 2184 * reception, for example, it pre-allocated the RX socket buffer in order to 2185 * allow zero-copy mechanism. 2186 */ 2187 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2188 struct stmmac_dma_conf *dma_conf) 2189 { 2190 /* RX Allocation */ 2191 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2192 2193 if (ret) 2194 return ret; 2195 2196 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2197 2198 return ret; 2199 } 2200 2201 /** 2202 * free_dma_desc_resources - free dma desc resources 2203 * @priv: private structure 2204 * @dma_conf: structure to take the dma data 2205 */ 2206 static void free_dma_desc_resources(struct stmmac_priv *priv, 2207 struct stmmac_dma_conf *dma_conf) 2208 { 2209 /* Release the DMA TX socket buffers */ 2210 free_dma_tx_desc_resources(priv, dma_conf); 2211 2212 /* Release the DMA RX socket buffers later 2213 * to ensure all pending XDP_TX buffers are returned. 2214 */ 2215 free_dma_rx_desc_resources(priv, dma_conf); 2216 } 2217 2218 /** 2219 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2220 * @priv: driver private structure 2221 * Description: It is used for enabling the rx queues in the MAC 2222 */ 2223 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2224 { 2225 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2226 int queue; 2227 u8 mode; 2228 2229 for (queue = 0; queue < rx_queues_count; queue++) { 2230 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2231 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2232 } 2233 } 2234 2235 /** 2236 * stmmac_start_rx_dma - start RX DMA channel 2237 * @priv: driver private structure 2238 * @chan: RX channel index 2239 * Description: 2240 * This starts a RX DMA channel 2241 */ 2242 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2243 { 2244 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2245 stmmac_start_rx(priv, priv->ioaddr, chan); 2246 } 2247 2248 /** 2249 * stmmac_start_tx_dma - start TX DMA channel 2250 * @priv: driver private structure 2251 * @chan: TX channel index 2252 * Description: 2253 * This starts a TX DMA channel 2254 */ 2255 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2256 { 2257 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2258 stmmac_start_tx(priv, priv->ioaddr, chan); 2259 } 2260 2261 /** 2262 * stmmac_stop_rx_dma - stop RX DMA channel 2263 * @priv: driver private structure 2264 * @chan: RX channel index 2265 * Description: 2266 * This stops a RX DMA channel 2267 */ 2268 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2269 { 2270 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2271 stmmac_stop_rx(priv, priv->ioaddr, chan); 2272 } 2273 2274 /** 2275 * stmmac_stop_tx_dma - stop TX DMA channel 2276 * @priv: driver private structure 2277 * @chan: TX channel index 2278 * Description: 2279 * This stops a TX DMA channel 2280 */ 2281 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2282 { 2283 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2284 stmmac_stop_tx(priv, priv->ioaddr, chan); 2285 } 2286 2287 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2288 { 2289 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2290 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2291 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2292 u32 chan; 2293 2294 for (chan = 0; chan < dma_csr_ch; chan++) { 2295 struct stmmac_channel *ch = &priv->channel[chan]; 2296 unsigned long flags; 2297 2298 spin_lock_irqsave(&ch->lock, flags); 2299 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2300 spin_unlock_irqrestore(&ch->lock, flags); 2301 } 2302 } 2303 2304 /** 2305 * stmmac_start_all_dma - start all RX and TX DMA channels 2306 * @priv: driver private structure 2307 * Description: 2308 * This starts all the RX and TX DMA channels 2309 */ 2310 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2311 { 2312 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2313 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2314 u32 chan = 0; 2315 2316 for (chan = 0; chan < rx_channels_count; chan++) 2317 stmmac_start_rx_dma(priv, chan); 2318 2319 for (chan = 0; chan < tx_channels_count; chan++) 2320 stmmac_start_tx_dma(priv, chan); 2321 } 2322 2323 /** 2324 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2325 * @priv: driver private structure 2326 * Description: 2327 * This stops the RX and TX DMA channels 2328 */ 2329 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2330 { 2331 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2332 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2333 u32 chan = 0; 2334 2335 for (chan = 0; chan < rx_channels_count; chan++) 2336 stmmac_stop_rx_dma(priv, chan); 2337 2338 for (chan = 0; chan < tx_channels_count; chan++) 2339 stmmac_stop_tx_dma(priv, chan); 2340 } 2341 2342 /** 2343 * stmmac_dma_operation_mode - HW DMA operation mode 2344 * @priv: driver private structure 2345 * Description: it is used for configuring the DMA operation mode register in 2346 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2347 */ 2348 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2349 { 2350 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2351 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2352 int rxfifosz = priv->plat->rx_fifo_size; 2353 int txfifosz = priv->plat->tx_fifo_size; 2354 u32 txmode = 0; 2355 u32 rxmode = 0; 2356 u32 chan = 0; 2357 u8 qmode = 0; 2358 2359 if (rxfifosz == 0) 2360 rxfifosz = priv->dma_cap.rx_fifo_size; 2361 if (txfifosz == 0) 2362 txfifosz = priv->dma_cap.tx_fifo_size; 2363 2364 /* Adjust for real per queue fifo size */ 2365 rxfifosz /= rx_channels_count; 2366 txfifosz /= tx_channels_count; 2367 2368 if (priv->plat->force_thresh_dma_mode) { 2369 txmode = tc; 2370 rxmode = tc; 2371 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2372 /* 2373 * In case of GMAC, SF mode can be enabled 2374 * to perform the TX COE in HW. This depends on: 2375 * 1) TX COE if actually supported 2376 * 2) There is no bugged Jumbo frame support 2377 * that needs to not insert csum in the TDES. 2378 */ 2379 txmode = SF_DMA_MODE; 2380 rxmode = SF_DMA_MODE; 2381 priv->xstats.threshold = SF_DMA_MODE; 2382 } else { 2383 txmode = tc; 2384 rxmode = SF_DMA_MODE; 2385 } 2386 2387 /* configure all channels */ 2388 for (chan = 0; chan < rx_channels_count; chan++) { 2389 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2390 u32 buf_size; 2391 2392 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2393 2394 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2395 rxfifosz, qmode); 2396 2397 if (rx_q->xsk_pool) { 2398 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2399 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2400 buf_size, 2401 chan); 2402 } else { 2403 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2404 priv->dma_conf.dma_buf_sz, 2405 chan); 2406 } 2407 } 2408 2409 for (chan = 0; chan < tx_channels_count; chan++) { 2410 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2411 2412 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2413 txfifosz, qmode); 2414 } 2415 } 2416 2417 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2418 { 2419 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2420 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2421 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2422 unsigned int entry = tx_q->cur_tx; 2423 struct dma_desc *tx_desc = NULL; 2424 struct xdp_desc xdp_desc; 2425 bool work_done = true; 2426 2427 /* Avoids TX time-out as we are sharing with slow path */ 2428 txq_trans_cond_update(nq); 2429 2430 budget = min(budget, stmmac_tx_avail(priv, queue)); 2431 2432 while (budget-- > 0) { 2433 dma_addr_t dma_addr; 2434 bool set_ic; 2435 2436 /* We are sharing with slow path and stop XSK TX desc submission when 2437 * available TX ring is less than threshold. 2438 */ 2439 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2440 !netif_carrier_ok(priv->dev)) { 2441 work_done = false; 2442 break; 2443 } 2444 2445 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2446 break; 2447 2448 if (likely(priv->extend_desc)) 2449 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2450 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2451 tx_desc = &tx_q->dma_entx[entry].basic; 2452 else 2453 tx_desc = tx_q->dma_tx + entry; 2454 2455 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2456 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2457 2458 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2459 2460 /* To return XDP buffer to XSK pool, we simple call 2461 * xsk_tx_completed(), so we don't need to fill up 2462 * 'buf' and 'xdpf'. 2463 */ 2464 tx_q->tx_skbuff_dma[entry].buf = 0; 2465 tx_q->xdpf[entry] = NULL; 2466 2467 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2468 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2469 tx_q->tx_skbuff_dma[entry].last_segment = true; 2470 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2471 2472 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2473 2474 tx_q->tx_count_frames++; 2475 2476 if (!priv->tx_coal_frames[queue]) 2477 set_ic = false; 2478 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2479 set_ic = true; 2480 else 2481 set_ic = false; 2482 2483 if (set_ic) { 2484 tx_q->tx_count_frames = 0; 2485 stmmac_set_tx_ic(priv, tx_desc); 2486 priv->xstats.tx_set_ic_bit++; 2487 } 2488 2489 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2490 true, priv->mode, true, true, 2491 xdp_desc.len); 2492 2493 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2494 2495 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2496 entry = tx_q->cur_tx; 2497 } 2498 2499 if (tx_desc) { 2500 stmmac_flush_tx_descriptors(priv, queue); 2501 xsk_tx_release(pool); 2502 } 2503 2504 /* Return true if all of the 3 conditions are met 2505 * a) TX Budget is still available 2506 * b) work_done = true when XSK TX desc peek is empty (no more 2507 * pending XSK TX for transmission) 2508 */ 2509 return !!budget && work_done; 2510 } 2511 2512 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2513 { 2514 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2515 tc += 64; 2516 2517 if (priv->plat->force_thresh_dma_mode) 2518 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2519 else 2520 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2521 chan); 2522 2523 priv->xstats.threshold = tc; 2524 } 2525 } 2526 2527 /** 2528 * stmmac_tx_clean - to manage the transmission completion 2529 * @priv: driver private structure 2530 * @budget: napi budget limiting this functions packet handling 2531 * @queue: TX queue index 2532 * Description: it reclaims the transmit resources after transmission completes. 2533 */ 2534 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2535 { 2536 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2537 unsigned int bytes_compl = 0, pkts_compl = 0; 2538 unsigned int entry, xmits = 0, count = 0; 2539 2540 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2541 2542 priv->xstats.tx_clean++; 2543 2544 tx_q->xsk_frames_done = 0; 2545 2546 entry = tx_q->dirty_tx; 2547 2548 /* Try to clean all TX complete frame in 1 shot */ 2549 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2550 struct xdp_frame *xdpf; 2551 struct sk_buff *skb; 2552 struct dma_desc *p; 2553 int status; 2554 2555 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2556 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2557 xdpf = tx_q->xdpf[entry]; 2558 skb = NULL; 2559 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2560 xdpf = NULL; 2561 skb = tx_q->tx_skbuff[entry]; 2562 } else { 2563 xdpf = NULL; 2564 skb = NULL; 2565 } 2566 2567 if (priv->extend_desc) 2568 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2569 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2570 p = &tx_q->dma_entx[entry].basic; 2571 else 2572 p = tx_q->dma_tx + entry; 2573 2574 status = stmmac_tx_status(priv, &priv->dev->stats, 2575 &priv->xstats, p, priv->ioaddr); 2576 /* Check if the descriptor is owned by the DMA */ 2577 if (unlikely(status & tx_dma_own)) 2578 break; 2579 2580 count++; 2581 2582 /* Make sure descriptor fields are read after reading 2583 * the own bit. 2584 */ 2585 dma_rmb(); 2586 2587 /* Just consider the last segment and ...*/ 2588 if (likely(!(status & tx_not_ls))) { 2589 /* ... verify the status error condition */ 2590 if (unlikely(status & tx_err)) { 2591 priv->dev->stats.tx_errors++; 2592 if (unlikely(status & tx_err_bump_tc)) 2593 stmmac_bump_dma_threshold(priv, queue); 2594 } else { 2595 priv->dev->stats.tx_packets++; 2596 priv->xstats.tx_pkt_n++; 2597 priv->xstats.txq_stats[queue].tx_pkt_n++; 2598 } 2599 if (skb) 2600 stmmac_get_tx_hwtstamp(priv, p, skb); 2601 } 2602 2603 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2604 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2605 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2606 dma_unmap_page(priv->device, 2607 tx_q->tx_skbuff_dma[entry].buf, 2608 tx_q->tx_skbuff_dma[entry].len, 2609 DMA_TO_DEVICE); 2610 else 2611 dma_unmap_single(priv->device, 2612 tx_q->tx_skbuff_dma[entry].buf, 2613 tx_q->tx_skbuff_dma[entry].len, 2614 DMA_TO_DEVICE); 2615 tx_q->tx_skbuff_dma[entry].buf = 0; 2616 tx_q->tx_skbuff_dma[entry].len = 0; 2617 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2618 } 2619 2620 stmmac_clean_desc3(priv, tx_q, p); 2621 2622 tx_q->tx_skbuff_dma[entry].last_segment = false; 2623 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2624 2625 if (xdpf && 2626 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2627 xdp_return_frame_rx_napi(xdpf); 2628 tx_q->xdpf[entry] = NULL; 2629 } 2630 2631 if (xdpf && 2632 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2633 xdp_return_frame(xdpf); 2634 tx_q->xdpf[entry] = NULL; 2635 } 2636 2637 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2638 tx_q->xsk_frames_done++; 2639 2640 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2641 if (likely(skb)) { 2642 pkts_compl++; 2643 bytes_compl += skb->len; 2644 dev_consume_skb_any(skb); 2645 tx_q->tx_skbuff[entry] = NULL; 2646 } 2647 } 2648 2649 stmmac_release_tx_desc(priv, p, priv->mode); 2650 2651 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2652 } 2653 tx_q->dirty_tx = entry; 2654 2655 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2656 pkts_compl, bytes_compl); 2657 2658 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2659 queue))) && 2660 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2661 2662 netif_dbg(priv, tx_done, priv->dev, 2663 "%s: restart transmit\n", __func__); 2664 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2665 } 2666 2667 if (tx_q->xsk_pool) { 2668 bool work_done; 2669 2670 if (tx_q->xsk_frames_done) 2671 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2672 2673 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2674 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2675 2676 /* For XSK TX, we try to send as many as possible. 2677 * If XSK work done (XSK TX desc empty and budget still 2678 * available), return "budget - 1" to reenable TX IRQ. 2679 * Else, return "budget" to make NAPI continue polling. 2680 */ 2681 work_done = stmmac_xdp_xmit_zc(priv, queue, 2682 STMMAC_XSK_TX_BUDGET_MAX); 2683 if (work_done) 2684 xmits = budget - 1; 2685 else 2686 xmits = budget; 2687 } 2688 2689 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2690 priv->eee_sw_timer_en) { 2691 if (stmmac_enable_eee_mode(priv)) 2692 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2693 } 2694 2695 /* We still have pending packets, let's call for a new scheduling */ 2696 if (tx_q->dirty_tx != tx_q->cur_tx) 2697 hrtimer_start(&tx_q->txtimer, 2698 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2699 HRTIMER_MODE_REL); 2700 2701 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2702 2703 /* Combine decisions from TX clean and XSK TX */ 2704 return max(count, xmits); 2705 } 2706 2707 /** 2708 * stmmac_tx_err - to manage the tx error 2709 * @priv: driver private structure 2710 * @chan: channel index 2711 * Description: it cleans the descriptors and restarts the transmission 2712 * in case of transmission errors. 2713 */ 2714 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2715 { 2716 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2717 2718 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2719 2720 stmmac_stop_tx_dma(priv, chan); 2721 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2722 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2723 stmmac_reset_tx_queue(priv, chan); 2724 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2725 tx_q->dma_tx_phy, chan); 2726 stmmac_start_tx_dma(priv, chan); 2727 2728 priv->dev->stats.tx_errors++; 2729 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2730 } 2731 2732 /** 2733 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2734 * @priv: driver private structure 2735 * @txmode: TX operating mode 2736 * @rxmode: RX operating mode 2737 * @chan: channel index 2738 * Description: it is used for configuring of the DMA operation mode in 2739 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2740 * mode. 2741 */ 2742 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2743 u32 rxmode, u32 chan) 2744 { 2745 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2746 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2747 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2748 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2749 int rxfifosz = priv->plat->rx_fifo_size; 2750 int txfifosz = priv->plat->tx_fifo_size; 2751 2752 if (rxfifosz == 0) 2753 rxfifosz = priv->dma_cap.rx_fifo_size; 2754 if (txfifosz == 0) 2755 txfifosz = priv->dma_cap.tx_fifo_size; 2756 2757 /* Adjust for real per queue fifo size */ 2758 rxfifosz /= rx_channels_count; 2759 txfifosz /= tx_channels_count; 2760 2761 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2762 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2763 } 2764 2765 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2766 { 2767 int ret; 2768 2769 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2770 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2771 if (ret && (ret != -EINVAL)) { 2772 stmmac_global_err(priv); 2773 return true; 2774 } 2775 2776 return false; 2777 } 2778 2779 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2780 { 2781 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2782 &priv->xstats, chan, dir); 2783 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2784 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2785 struct stmmac_channel *ch = &priv->channel[chan]; 2786 struct napi_struct *rx_napi; 2787 struct napi_struct *tx_napi; 2788 unsigned long flags; 2789 2790 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2791 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2792 2793 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2794 if (napi_schedule_prep(rx_napi)) { 2795 spin_lock_irqsave(&ch->lock, flags); 2796 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2797 spin_unlock_irqrestore(&ch->lock, flags); 2798 __napi_schedule(rx_napi); 2799 } 2800 } 2801 2802 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2803 if (napi_schedule_prep(tx_napi)) { 2804 spin_lock_irqsave(&ch->lock, flags); 2805 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2806 spin_unlock_irqrestore(&ch->lock, flags); 2807 __napi_schedule(tx_napi); 2808 } 2809 } 2810 2811 return status; 2812 } 2813 2814 /** 2815 * stmmac_dma_interrupt - DMA ISR 2816 * @priv: driver private structure 2817 * Description: this is the DMA ISR. It is called by the main ISR. 2818 * It calls the dwmac dma routine and schedule poll method in case of some 2819 * work can be done. 2820 */ 2821 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2822 { 2823 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2824 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2825 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2826 tx_channel_count : rx_channel_count; 2827 u32 chan; 2828 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2829 2830 /* Make sure we never check beyond our status buffer. */ 2831 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2832 channels_to_check = ARRAY_SIZE(status); 2833 2834 for (chan = 0; chan < channels_to_check; chan++) 2835 status[chan] = stmmac_napi_check(priv, chan, 2836 DMA_DIR_RXTX); 2837 2838 for (chan = 0; chan < tx_channel_count; chan++) { 2839 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2840 /* Try to bump up the dma threshold on this failure */ 2841 stmmac_bump_dma_threshold(priv, chan); 2842 } else if (unlikely(status[chan] == tx_hard_error)) { 2843 stmmac_tx_err(priv, chan); 2844 } 2845 } 2846 } 2847 2848 /** 2849 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2850 * @priv: driver private structure 2851 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2852 */ 2853 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2854 { 2855 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2856 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2857 2858 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2859 2860 if (priv->dma_cap.rmon) { 2861 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2862 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2863 } else 2864 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2865 } 2866 2867 /** 2868 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2869 * @priv: driver private structure 2870 * Description: 2871 * new GMAC chip generations have a new register to indicate the 2872 * presence of the optional feature/functions. 2873 * This can be also used to override the value passed through the 2874 * platform and necessary for old MAC10/100 and GMAC chips. 2875 */ 2876 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2877 { 2878 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2879 } 2880 2881 /** 2882 * stmmac_check_ether_addr - check if the MAC addr is valid 2883 * @priv: driver private structure 2884 * Description: 2885 * it is to verify if the MAC address is valid, in case of failures it 2886 * generates a random MAC address 2887 */ 2888 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2889 { 2890 u8 addr[ETH_ALEN]; 2891 2892 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2893 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2894 if (is_valid_ether_addr(addr)) 2895 eth_hw_addr_set(priv->dev, addr); 2896 else 2897 eth_hw_addr_random(priv->dev); 2898 dev_info(priv->device, "device MAC address %pM\n", 2899 priv->dev->dev_addr); 2900 } 2901 } 2902 2903 /** 2904 * stmmac_init_dma_engine - DMA init. 2905 * @priv: driver private structure 2906 * Description: 2907 * It inits the DMA invoking the specific MAC/GMAC callback. 2908 * Some DMA parameters can be passed from the platform; 2909 * in case of these are not passed a default is kept for the MAC or GMAC. 2910 */ 2911 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2912 { 2913 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2914 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2915 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2916 struct stmmac_rx_queue *rx_q; 2917 struct stmmac_tx_queue *tx_q; 2918 u32 chan = 0; 2919 int atds = 0; 2920 int ret = 0; 2921 2922 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2923 dev_err(priv->device, "Invalid DMA configuration\n"); 2924 return -EINVAL; 2925 } 2926 2927 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2928 atds = 1; 2929 2930 ret = stmmac_reset(priv, priv->ioaddr); 2931 if (ret) { 2932 dev_err(priv->device, "Failed to reset the dma\n"); 2933 return ret; 2934 } 2935 2936 /* DMA Configuration */ 2937 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2938 2939 if (priv->plat->axi) 2940 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2941 2942 /* DMA CSR Channel configuration */ 2943 for (chan = 0; chan < dma_csr_ch; chan++) { 2944 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2945 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2946 } 2947 2948 /* DMA RX Channel Configuration */ 2949 for (chan = 0; chan < rx_channels_count; chan++) { 2950 rx_q = &priv->dma_conf.rx_queue[chan]; 2951 2952 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2953 rx_q->dma_rx_phy, chan); 2954 2955 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2956 (rx_q->buf_alloc_num * 2957 sizeof(struct dma_desc)); 2958 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2959 rx_q->rx_tail_addr, chan); 2960 } 2961 2962 /* DMA TX Channel Configuration */ 2963 for (chan = 0; chan < tx_channels_count; chan++) { 2964 tx_q = &priv->dma_conf.tx_queue[chan]; 2965 2966 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2967 tx_q->dma_tx_phy, chan); 2968 2969 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2970 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2971 tx_q->tx_tail_addr, chan); 2972 } 2973 2974 return ret; 2975 } 2976 2977 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2978 { 2979 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2980 2981 hrtimer_start(&tx_q->txtimer, 2982 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2983 HRTIMER_MODE_REL); 2984 } 2985 2986 /** 2987 * stmmac_tx_timer - mitigation sw timer for tx. 2988 * @t: data pointer 2989 * Description: 2990 * This is the timer handler to directly invoke the stmmac_tx_clean. 2991 */ 2992 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2993 { 2994 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2995 struct stmmac_priv *priv = tx_q->priv_data; 2996 struct stmmac_channel *ch; 2997 struct napi_struct *napi; 2998 2999 ch = &priv->channel[tx_q->queue_index]; 3000 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 3001 3002 if (likely(napi_schedule_prep(napi))) { 3003 unsigned long flags; 3004 3005 spin_lock_irqsave(&ch->lock, flags); 3006 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 3007 spin_unlock_irqrestore(&ch->lock, flags); 3008 __napi_schedule(napi); 3009 } 3010 3011 return HRTIMER_NORESTART; 3012 } 3013 3014 /** 3015 * stmmac_init_coalesce - init mitigation options. 3016 * @priv: driver private structure 3017 * Description: 3018 * This inits the coalesce parameters: i.e. timer rate, 3019 * timer handler and default threshold used for enabling the 3020 * interrupt on completion bit. 3021 */ 3022 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3023 { 3024 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3025 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3026 u32 chan; 3027 3028 for (chan = 0; chan < tx_channel_count; chan++) { 3029 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3030 3031 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3032 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3033 3034 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3035 tx_q->txtimer.function = stmmac_tx_timer; 3036 } 3037 3038 for (chan = 0; chan < rx_channel_count; chan++) 3039 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3040 } 3041 3042 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3043 { 3044 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3045 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3046 u32 chan; 3047 3048 /* set TX ring length */ 3049 for (chan = 0; chan < tx_channels_count; chan++) 3050 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3051 (priv->dma_conf.dma_tx_size - 1), chan); 3052 3053 /* set RX ring length */ 3054 for (chan = 0; chan < rx_channels_count; chan++) 3055 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3056 (priv->dma_conf.dma_rx_size - 1), chan); 3057 } 3058 3059 /** 3060 * stmmac_set_tx_queue_weight - Set TX queue weight 3061 * @priv: driver private structure 3062 * Description: It is used for setting TX queues weight 3063 */ 3064 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3065 { 3066 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3067 u32 weight; 3068 u32 queue; 3069 3070 for (queue = 0; queue < tx_queues_count; queue++) { 3071 weight = priv->plat->tx_queues_cfg[queue].weight; 3072 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3073 } 3074 } 3075 3076 /** 3077 * stmmac_configure_cbs - Configure CBS in TX queue 3078 * @priv: driver private structure 3079 * Description: It is used for configuring CBS in AVB TX queues 3080 */ 3081 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3082 { 3083 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3084 u32 mode_to_use; 3085 u32 queue; 3086 3087 /* queue 0 is reserved for legacy traffic */ 3088 for (queue = 1; queue < tx_queues_count; queue++) { 3089 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3090 if (mode_to_use == MTL_QUEUE_DCB) 3091 continue; 3092 3093 stmmac_config_cbs(priv, priv->hw, 3094 priv->plat->tx_queues_cfg[queue].send_slope, 3095 priv->plat->tx_queues_cfg[queue].idle_slope, 3096 priv->plat->tx_queues_cfg[queue].high_credit, 3097 priv->plat->tx_queues_cfg[queue].low_credit, 3098 queue); 3099 } 3100 } 3101 3102 /** 3103 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3104 * @priv: driver private structure 3105 * Description: It is used for mapping RX queues to RX dma channels 3106 */ 3107 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3108 { 3109 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3110 u32 queue; 3111 u32 chan; 3112 3113 for (queue = 0; queue < rx_queues_count; queue++) { 3114 chan = priv->plat->rx_queues_cfg[queue].chan; 3115 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3116 } 3117 } 3118 3119 /** 3120 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3121 * @priv: driver private structure 3122 * Description: It is used for configuring the RX Queue Priority 3123 */ 3124 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3125 { 3126 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3127 u32 queue; 3128 u32 prio; 3129 3130 for (queue = 0; queue < rx_queues_count; queue++) { 3131 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3132 continue; 3133 3134 prio = priv->plat->rx_queues_cfg[queue].prio; 3135 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3136 } 3137 } 3138 3139 /** 3140 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3141 * @priv: driver private structure 3142 * Description: It is used for configuring the TX Queue Priority 3143 */ 3144 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3145 { 3146 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3147 u32 queue; 3148 u32 prio; 3149 3150 for (queue = 0; queue < tx_queues_count; queue++) { 3151 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3152 continue; 3153 3154 prio = priv->plat->tx_queues_cfg[queue].prio; 3155 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3156 } 3157 } 3158 3159 /** 3160 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3161 * @priv: driver private structure 3162 * Description: It is used for configuring the RX queue routing 3163 */ 3164 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3165 { 3166 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3167 u32 queue; 3168 u8 packet; 3169 3170 for (queue = 0; queue < rx_queues_count; queue++) { 3171 /* no specific packet type routing specified for the queue */ 3172 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3173 continue; 3174 3175 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3176 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3177 } 3178 } 3179 3180 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3181 { 3182 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3183 priv->rss.enable = false; 3184 return; 3185 } 3186 3187 if (priv->dev->features & NETIF_F_RXHASH) 3188 priv->rss.enable = true; 3189 else 3190 priv->rss.enable = false; 3191 3192 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3193 priv->plat->rx_queues_to_use); 3194 } 3195 3196 /** 3197 * stmmac_mtl_configuration - Configure MTL 3198 * @priv: driver private structure 3199 * Description: It is used for configurring MTL 3200 */ 3201 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3202 { 3203 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3204 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3205 3206 if (tx_queues_count > 1) 3207 stmmac_set_tx_queue_weight(priv); 3208 3209 /* Configure MTL RX algorithms */ 3210 if (rx_queues_count > 1) 3211 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3212 priv->plat->rx_sched_algorithm); 3213 3214 /* Configure MTL TX algorithms */ 3215 if (tx_queues_count > 1) 3216 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3217 priv->plat->tx_sched_algorithm); 3218 3219 /* Configure CBS in AVB TX queues */ 3220 if (tx_queues_count > 1) 3221 stmmac_configure_cbs(priv); 3222 3223 /* Map RX MTL to DMA channels */ 3224 stmmac_rx_queue_dma_chan_map(priv); 3225 3226 /* Enable MAC RX Queues */ 3227 stmmac_mac_enable_rx_queues(priv); 3228 3229 /* Set RX priorities */ 3230 if (rx_queues_count > 1) 3231 stmmac_mac_config_rx_queues_prio(priv); 3232 3233 /* Set TX priorities */ 3234 if (tx_queues_count > 1) 3235 stmmac_mac_config_tx_queues_prio(priv); 3236 3237 /* Set RX routing */ 3238 if (rx_queues_count > 1) 3239 stmmac_mac_config_rx_queues_routing(priv); 3240 3241 /* Receive Side Scaling */ 3242 if (rx_queues_count > 1) 3243 stmmac_mac_config_rss(priv); 3244 } 3245 3246 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3247 { 3248 if (priv->dma_cap.asp) { 3249 netdev_info(priv->dev, "Enabling Safety Features\n"); 3250 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3251 priv->plat->safety_feat_cfg); 3252 } else { 3253 netdev_info(priv->dev, "No Safety Features support found\n"); 3254 } 3255 } 3256 3257 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3258 { 3259 char *name; 3260 3261 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3262 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3263 3264 name = priv->wq_name; 3265 sprintf(name, "%s-fpe", priv->dev->name); 3266 3267 priv->fpe_wq = create_singlethread_workqueue(name); 3268 if (!priv->fpe_wq) { 3269 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3270 3271 return -ENOMEM; 3272 } 3273 netdev_info(priv->dev, "FPE workqueue start"); 3274 3275 return 0; 3276 } 3277 3278 /** 3279 * stmmac_hw_setup - setup mac in a usable state. 3280 * @dev : pointer to the device structure. 3281 * @ptp_register: register PTP if set 3282 * Description: 3283 * this is the main function to setup the HW in a usable state because the 3284 * dma engine is reset, the core registers are configured (e.g. AXI, 3285 * Checksum features, timers). The DMA is ready to start receiving and 3286 * transmitting. 3287 * Return value: 3288 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3289 * file on failure. 3290 */ 3291 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3292 { 3293 struct stmmac_priv *priv = netdev_priv(dev); 3294 u32 rx_cnt = priv->plat->rx_queues_to_use; 3295 u32 tx_cnt = priv->plat->tx_queues_to_use; 3296 bool sph_en; 3297 u32 chan; 3298 int ret; 3299 3300 /* DMA initialization and SW reset */ 3301 ret = stmmac_init_dma_engine(priv); 3302 if (ret < 0) { 3303 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3304 __func__); 3305 return ret; 3306 } 3307 3308 /* Copy the MAC addr into the HW */ 3309 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3310 3311 /* PS and related bits will be programmed according to the speed */ 3312 if (priv->hw->pcs) { 3313 int speed = priv->plat->mac_port_sel_speed; 3314 3315 if ((speed == SPEED_10) || (speed == SPEED_100) || 3316 (speed == SPEED_1000)) { 3317 priv->hw->ps = speed; 3318 } else { 3319 dev_warn(priv->device, "invalid port speed\n"); 3320 priv->hw->ps = 0; 3321 } 3322 } 3323 3324 /* Initialize the MAC Core */ 3325 stmmac_core_init(priv, priv->hw, dev); 3326 3327 /* Initialize MTL*/ 3328 stmmac_mtl_configuration(priv); 3329 3330 /* Initialize Safety Features */ 3331 stmmac_safety_feat_configuration(priv); 3332 3333 ret = stmmac_rx_ipc(priv, priv->hw); 3334 if (!ret) { 3335 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3336 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3337 priv->hw->rx_csum = 0; 3338 } 3339 3340 /* Enable the MAC Rx/Tx */ 3341 stmmac_mac_set(priv, priv->ioaddr, true); 3342 3343 /* Set the HW DMA mode and the COE */ 3344 stmmac_dma_operation_mode(priv); 3345 3346 stmmac_mmc_setup(priv); 3347 3348 if (ptp_register) { 3349 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3350 if (ret < 0) 3351 netdev_warn(priv->dev, 3352 "failed to enable PTP reference clock: %pe\n", 3353 ERR_PTR(ret)); 3354 } 3355 3356 ret = stmmac_init_ptp(priv); 3357 if (ret == -EOPNOTSUPP) 3358 netdev_info(priv->dev, "PTP not supported by HW\n"); 3359 else if (ret) 3360 netdev_warn(priv->dev, "PTP init failed\n"); 3361 else if (ptp_register) 3362 stmmac_ptp_register(priv); 3363 3364 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3365 3366 /* Convert the timer from msec to usec */ 3367 if (!priv->tx_lpi_timer) 3368 priv->tx_lpi_timer = eee_timer * 1000; 3369 3370 if (priv->use_riwt) { 3371 u32 queue; 3372 3373 for (queue = 0; queue < rx_cnt; queue++) { 3374 if (!priv->rx_riwt[queue]) 3375 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3376 3377 stmmac_rx_watchdog(priv, priv->ioaddr, 3378 priv->rx_riwt[queue], queue); 3379 } 3380 } 3381 3382 if (priv->hw->pcs) 3383 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3384 3385 /* set TX and RX rings length */ 3386 stmmac_set_rings_length(priv); 3387 3388 /* Enable TSO */ 3389 if (priv->tso) { 3390 for (chan = 0; chan < tx_cnt; chan++) { 3391 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3392 3393 /* TSO and TBS cannot co-exist */ 3394 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3395 continue; 3396 3397 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3398 } 3399 } 3400 3401 /* Enable Split Header */ 3402 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3403 for (chan = 0; chan < rx_cnt; chan++) 3404 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3405 3406 3407 /* VLAN Tag Insertion */ 3408 if (priv->dma_cap.vlins) 3409 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3410 3411 /* TBS */ 3412 for (chan = 0; chan < tx_cnt; chan++) { 3413 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3414 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3415 3416 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3417 } 3418 3419 /* Configure real RX and TX queues */ 3420 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3421 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3422 3423 /* Start the ball rolling... */ 3424 stmmac_start_all_dma(priv); 3425 3426 if (priv->dma_cap.fpesel) { 3427 stmmac_fpe_start_wq(priv); 3428 3429 if (priv->plat->fpe_cfg->enable) 3430 stmmac_fpe_handshake(priv, true); 3431 } 3432 3433 return 0; 3434 } 3435 3436 static void stmmac_hw_teardown(struct net_device *dev) 3437 { 3438 struct stmmac_priv *priv = netdev_priv(dev); 3439 3440 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3441 } 3442 3443 static void stmmac_free_irq(struct net_device *dev, 3444 enum request_irq_err irq_err, int irq_idx) 3445 { 3446 struct stmmac_priv *priv = netdev_priv(dev); 3447 int j; 3448 3449 switch (irq_err) { 3450 case REQ_IRQ_ERR_ALL: 3451 irq_idx = priv->plat->tx_queues_to_use; 3452 fallthrough; 3453 case REQ_IRQ_ERR_TX: 3454 for (j = irq_idx - 1; j >= 0; j--) { 3455 if (priv->tx_irq[j] > 0) { 3456 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3457 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3458 } 3459 } 3460 irq_idx = priv->plat->rx_queues_to_use; 3461 fallthrough; 3462 case REQ_IRQ_ERR_RX: 3463 for (j = irq_idx - 1; j >= 0; j--) { 3464 if (priv->rx_irq[j] > 0) { 3465 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3466 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3467 } 3468 } 3469 3470 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3471 free_irq(priv->sfty_ue_irq, dev); 3472 fallthrough; 3473 case REQ_IRQ_ERR_SFTY_UE: 3474 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3475 free_irq(priv->sfty_ce_irq, dev); 3476 fallthrough; 3477 case REQ_IRQ_ERR_SFTY_CE: 3478 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3479 free_irq(priv->lpi_irq, dev); 3480 fallthrough; 3481 case REQ_IRQ_ERR_LPI: 3482 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3483 free_irq(priv->wol_irq, dev); 3484 fallthrough; 3485 case REQ_IRQ_ERR_WOL: 3486 free_irq(dev->irq, dev); 3487 fallthrough; 3488 case REQ_IRQ_ERR_MAC: 3489 case REQ_IRQ_ERR_NO: 3490 /* If MAC IRQ request error, no more IRQ to free */ 3491 break; 3492 } 3493 } 3494 3495 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3496 { 3497 struct stmmac_priv *priv = netdev_priv(dev); 3498 enum request_irq_err irq_err; 3499 cpumask_t cpu_mask; 3500 int irq_idx = 0; 3501 char *int_name; 3502 int ret; 3503 int i; 3504 3505 /* For common interrupt */ 3506 int_name = priv->int_name_mac; 3507 sprintf(int_name, "%s:%s", dev->name, "mac"); 3508 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3509 0, int_name, dev); 3510 if (unlikely(ret < 0)) { 3511 netdev_err(priv->dev, 3512 "%s: alloc mac MSI %d (error: %d)\n", 3513 __func__, dev->irq, ret); 3514 irq_err = REQ_IRQ_ERR_MAC; 3515 goto irq_error; 3516 } 3517 3518 /* Request the Wake IRQ in case of another line 3519 * is used for WoL 3520 */ 3521 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3522 int_name = priv->int_name_wol; 3523 sprintf(int_name, "%s:%s", dev->name, "wol"); 3524 ret = request_irq(priv->wol_irq, 3525 stmmac_mac_interrupt, 3526 0, int_name, dev); 3527 if (unlikely(ret < 0)) { 3528 netdev_err(priv->dev, 3529 "%s: alloc wol MSI %d (error: %d)\n", 3530 __func__, priv->wol_irq, ret); 3531 irq_err = REQ_IRQ_ERR_WOL; 3532 goto irq_error; 3533 } 3534 } 3535 3536 /* Request the LPI IRQ in case of another line 3537 * is used for LPI 3538 */ 3539 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3540 int_name = priv->int_name_lpi; 3541 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3542 ret = request_irq(priv->lpi_irq, 3543 stmmac_mac_interrupt, 3544 0, int_name, dev); 3545 if (unlikely(ret < 0)) { 3546 netdev_err(priv->dev, 3547 "%s: alloc lpi MSI %d (error: %d)\n", 3548 __func__, priv->lpi_irq, ret); 3549 irq_err = REQ_IRQ_ERR_LPI; 3550 goto irq_error; 3551 } 3552 } 3553 3554 /* Request the Safety Feature Correctible Error line in 3555 * case of another line is used 3556 */ 3557 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3558 int_name = priv->int_name_sfty_ce; 3559 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3560 ret = request_irq(priv->sfty_ce_irq, 3561 stmmac_safety_interrupt, 3562 0, int_name, dev); 3563 if (unlikely(ret < 0)) { 3564 netdev_err(priv->dev, 3565 "%s: alloc sfty ce MSI %d (error: %d)\n", 3566 __func__, priv->sfty_ce_irq, ret); 3567 irq_err = REQ_IRQ_ERR_SFTY_CE; 3568 goto irq_error; 3569 } 3570 } 3571 3572 /* Request the Safety Feature Uncorrectible Error line in 3573 * case of another line is used 3574 */ 3575 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3576 int_name = priv->int_name_sfty_ue; 3577 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3578 ret = request_irq(priv->sfty_ue_irq, 3579 stmmac_safety_interrupt, 3580 0, int_name, dev); 3581 if (unlikely(ret < 0)) { 3582 netdev_err(priv->dev, 3583 "%s: alloc sfty ue MSI %d (error: %d)\n", 3584 __func__, priv->sfty_ue_irq, ret); 3585 irq_err = REQ_IRQ_ERR_SFTY_UE; 3586 goto irq_error; 3587 } 3588 } 3589 3590 /* Request Rx MSI irq */ 3591 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3592 if (i >= MTL_MAX_RX_QUEUES) 3593 break; 3594 if (priv->rx_irq[i] == 0) 3595 continue; 3596 3597 int_name = priv->int_name_rx_irq[i]; 3598 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3599 ret = request_irq(priv->rx_irq[i], 3600 stmmac_msi_intr_rx, 3601 0, int_name, &priv->dma_conf.rx_queue[i]); 3602 if (unlikely(ret < 0)) { 3603 netdev_err(priv->dev, 3604 "%s: alloc rx-%d MSI %d (error: %d)\n", 3605 __func__, i, priv->rx_irq[i], ret); 3606 irq_err = REQ_IRQ_ERR_RX; 3607 irq_idx = i; 3608 goto irq_error; 3609 } 3610 cpumask_clear(&cpu_mask); 3611 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3612 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3613 } 3614 3615 /* Request Tx MSI irq */ 3616 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3617 if (i >= MTL_MAX_TX_QUEUES) 3618 break; 3619 if (priv->tx_irq[i] == 0) 3620 continue; 3621 3622 int_name = priv->int_name_tx_irq[i]; 3623 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3624 ret = request_irq(priv->tx_irq[i], 3625 stmmac_msi_intr_tx, 3626 0, int_name, &priv->dma_conf.tx_queue[i]); 3627 if (unlikely(ret < 0)) { 3628 netdev_err(priv->dev, 3629 "%s: alloc tx-%d MSI %d (error: %d)\n", 3630 __func__, i, priv->tx_irq[i], ret); 3631 irq_err = REQ_IRQ_ERR_TX; 3632 irq_idx = i; 3633 goto irq_error; 3634 } 3635 cpumask_clear(&cpu_mask); 3636 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3637 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3638 } 3639 3640 return 0; 3641 3642 irq_error: 3643 stmmac_free_irq(dev, irq_err, irq_idx); 3644 return ret; 3645 } 3646 3647 static int stmmac_request_irq_single(struct net_device *dev) 3648 { 3649 struct stmmac_priv *priv = netdev_priv(dev); 3650 enum request_irq_err irq_err; 3651 int ret; 3652 3653 ret = request_irq(dev->irq, stmmac_interrupt, 3654 IRQF_SHARED, dev->name, dev); 3655 if (unlikely(ret < 0)) { 3656 netdev_err(priv->dev, 3657 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3658 __func__, dev->irq, ret); 3659 irq_err = REQ_IRQ_ERR_MAC; 3660 goto irq_error; 3661 } 3662 3663 /* Request the Wake IRQ in case of another line 3664 * is used for WoL 3665 */ 3666 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3667 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3668 IRQF_SHARED, dev->name, dev); 3669 if (unlikely(ret < 0)) { 3670 netdev_err(priv->dev, 3671 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3672 __func__, priv->wol_irq, ret); 3673 irq_err = REQ_IRQ_ERR_WOL; 3674 goto irq_error; 3675 } 3676 } 3677 3678 /* Request the IRQ lines */ 3679 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3680 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3681 IRQF_SHARED, dev->name, dev); 3682 if (unlikely(ret < 0)) { 3683 netdev_err(priv->dev, 3684 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3685 __func__, priv->lpi_irq, ret); 3686 irq_err = REQ_IRQ_ERR_LPI; 3687 goto irq_error; 3688 } 3689 } 3690 3691 return 0; 3692 3693 irq_error: 3694 stmmac_free_irq(dev, irq_err, 0); 3695 return ret; 3696 } 3697 3698 static int stmmac_request_irq(struct net_device *dev) 3699 { 3700 struct stmmac_priv *priv = netdev_priv(dev); 3701 int ret; 3702 3703 /* Request the IRQ lines */ 3704 if (priv->plat->multi_msi_en) 3705 ret = stmmac_request_irq_multi_msi(dev); 3706 else 3707 ret = stmmac_request_irq_single(dev); 3708 3709 return ret; 3710 } 3711 3712 /** 3713 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3714 * @priv: driver private structure 3715 * @mtu: MTU to setup the dma queue and buf with 3716 * Description: Allocate and generate a dma_conf based on the provided MTU. 3717 * Allocate the Tx/Rx DMA queue and init them. 3718 * Return value: 3719 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3720 */ 3721 static struct stmmac_dma_conf * 3722 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3723 { 3724 struct stmmac_dma_conf *dma_conf; 3725 int chan, bfsize, ret; 3726 3727 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3728 if (!dma_conf) { 3729 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3730 __func__); 3731 return ERR_PTR(-ENOMEM); 3732 } 3733 3734 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3735 if (bfsize < 0) 3736 bfsize = 0; 3737 3738 if (bfsize < BUF_SIZE_16KiB) 3739 bfsize = stmmac_set_bfsize(mtu, 0); 3740 3741 dma_conf->dma_buf_sz = bfsize; 3742 /* Chose the tx/rx size from the already defined one in the 3743 * priv struct. (if defined) 3744 */ 3745 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3746 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3747 3748 if (!dma_conf->dma_tx_size) 3749 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3750 if (!dma_conf->dma_rx_size) 3751 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3752 3753 /* Earlier check for TBS */ 3754 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3755 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3756 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3757 3758 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3759 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3760 } 3761 3762 ret = alloc_dma_desc_resources(priv, dma_conf); 3763 if (ret < 0) { 3764 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3765 __func__); 3766 goto alloc_error; 3767 } 3768 3769 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3770 if (ret < 0) { 3771 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3772 __func__); 3773 goto init_error; 3774 } 3775 3776 return dma_conf; 3777 3778 init_error: 3779 free_dma_desc_resources(priv, dma_conf); 3780 alloc_error: 3781 kfree(dma_conf); 3782 return ERR_PTR(ret); 3783 } 3784 3785 /** 3786 * __stmmac_open - open entry point of the driver 3787 * @dev : pointer to the device structure. 3788 * @dma_conf : structure to take the dma data 3789 * Description: 3790 * This function is the open entry point of the driver. 3791 * Return value: 3792 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3793 * file on failure. 3794 */ 3795 static int __stmmac_open(struct net_device *dev, 3796 struct stmmac_dma_conf *dma_conf) 3797 { 3798 struct stmmac_priv *priv = netdev_priv(dev); 3799 int mode = priv->plat->phy_interface; 3800 u32 chan; 3801 int ret; 3802 3803 ret = pm_runtime_resume_and_get(priv->device); 3804 if (ret < 0) 3805 return ret; 3806 3807 if (priv->hw->pcs != STMMAC_PCS_TBI && 3808 priv->hw->pcs != STMMAC_PCS_RTBI && 3809 (!priv->hw->xpcs || 3810 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3811 ret = stmmac_init_phy(dev); 3812 if (ret) { 3813 netdev_err(priv->dev, 3814 "%s: Cannot attach to PHY (error: %d)\n", 3815 __func__, ret); 3816 goto init_phy_error; 3817 } 3818 } 3819 3820 /* Extra statistics */ 3821 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3822 priv->xstats.threshold = tc; 3823 3824 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3825 3826 buf_sz = dma_conf->dma_buf_sz; 3827 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3828 3829 stmmac_reset_queues_param(priv); 3830 3831 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 3832 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3833 if (ret < 0) { 3834 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3835 __func__); 3836 goto init_error; 3837 } 3838 } 3839 3840 ret = stmmac_hw_setup(dev, true); 3841 if (ret < 0) { 3842 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3843 goto init_error; 3844 } 3845 3846 stmmac_init_coalesce(priv); 3847 3848 phylink_start(priv->phylink); 3849 /* We may have called phylink_speed_down before */ 3850 phylink_speed_up(priv->phylink); 3851 3852 ret = stmmac_request_irq(dev); 3853 if (ret) 3854 goto irq_error; 3855 3856 stmmac_enable_all_queues(priv); 3857 netif_tx_start_all_queues(priv->dev); 3858 stmmac_enable_all_dma_irq(priv); 3859 3860 return 0; 3861 3862 irq_error: 3863 phylink_stop(priv->phylink); 3864 3865 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3866 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3867 3868 stmmac_hw_teardown(dev); 3869 init_error: 3870 free_dma_desc_resources(priv, &priv->dma_conf); 3871 phylink_disconnect_phy(priv->phylink); 3872 init_phy_error: 3873 pm_runtime_put(priv->device); 3874 return ret; 3875 } 3876 3877 static int stmmac_open(struct net_device *dev) 3878 { 3879 struct stmmac_priv *priv = netdev_priv(dev); 3880 struct stmmac_dma_conf *dma_conf; 3881 int ret; 3882 3883 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3884 if (IS_ERR(dma_conf)) 3885 return PTR_ERR(dma_conf); 3886 3887 ret = __stmmac_open(dev, dma_conf); 3888 kfree(dma_conf); 3889 return ret; 3890 } 3891 3892 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3893 { 3894 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3895 3896 if (priv->fpe_wq) 3897 destroy_workqueue(priv->fpe_wq); 3898 3899 netdev_info(priv->dev, "FPE workqueue stop"); 3900 } 3901 3902 /** 3903 * stmmac_release - close entry point of the driver 3904 * @dev : device pointer. 3905 * Description: 3906 * This is the stop entry point of the driver. 3907 */ 3908 static int stmmac_release(struct net_device *dev) 3909 { 3910 struct stmmac_priv *priv = netdev_priv(dev); 3911 u32 chan; 3912 3913 if (device_may_wakeup(priv->device)) 3914 phylink_speed_down(priv->phylink, false); 3915 /* Stop and disconnect the PHY */ 3916 phylink_stop(priv->phylink); 3917 phylink_disconnect_phy(priv->phylink); 3918 3919 stmmac_disable_all_queues(priv); 3920 3921 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3922 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3923 3924 netif_tx_disable(dev); 3925 3926 /* Free the IRQ lines */ 3927 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3928 3929 if (priv->eee_enabled) { 3930 priv->tx_path_in_lpi_mode = false; 3931 del_timer_sync(&priv->eee_ctrl_timer); 3932 } 3933 3934 /* Stop TX/RX DMA and clear the descriptors */ 3935 stmmac_stop_all_dma(priv); 3936 3937 /* Release and free the Rx/Tx resources */ 3938 free_dma_desc_resources(priv, &priv->dma_conf); 3939 3940 /* Disable the MAC Rx/Tx */ 3941 stmmac_mac_set(priv, priv->ioaddr, false); 3942 3943 /* Powerdown Serdes if there is */ 3944 if (priv->plat->serdes_powerdown) 3945 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3946 3947 netif_carrier_off(dev); 3948 3949 stmmac_release_ptp(priv); 3950 3951 pm_runtime_put(priv->device); 3952 3953 if (priv->dma_cap.fpesel) 3954 stmmac_fpe_stop_wq(priv); 3955 3956 return 0; 3957 } 3958 3959 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3960 struct stmmac_tx_queue *tx_q) 3961 { 3962 u16 tag = 0x0, inner_tag = 0x0; 3963 u32 inner_type = 0x0; 3964 struct dma_desc *p; 3965 3966 if (!priv->dma_cap.vlins) 3967 return false; 3968 if (!skb_vlan_tag_present(skb)) 3969 return false; 3970 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3971 inner_tag = skb_vlan_tag_get(skb); 3972 inner_type = STMMAC_VLAN_INSERT; 3973 } 3974 3975 tag = skb_vlan_tag_get(skb); 3976 3977 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3978 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3979 else 3980 p = &tx_q->dma_tx[tx_q->cur_tx]; 3981 3982 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3983 return false; 3984 3985 stmmac_set_tx_owner(priv, p); 3986 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3987 return true; 3988 } 3989 3990 /** 3991 * stmmac_tso_allocator - close entry point of the driver 3992 * @priv: driver private structure 3993 * @des: buffer start address 3994 * @total_len: total length to fill in descriptors 3995 * @last_segment: condition for the last descriptor 3996 * @queue: TX queue index 3997 * Description: 3998 * This function fills descriptor and request new descriptors according to 3999 * buffer length to fill 4000 */ 4001 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 4002 int total_len, bool last_segment, u32 queue) 4003 { 4004 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4005 struct dma_desc *desc; 4006 u32 buff_size; 4007 int tmp_len; 4008 4009 tmp_len = total_len; 4010 4011 while (tmp_len > 0) { 4012 dma_addr_t curr_addr; 4013 4014 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4015 priv->dma_conf.dma_tx_size); 4016 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4017 4018 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4019 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4020 else 4021 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4022 4023 curr_addr = des + (total_len - tmp_len); 4024 if (priv->dma_cap.addr64 <= 32) 4025 desc->des0 = cpu_to_le32(curr_addr); 4026 else 4027 stmmac_set_desc_addr(priv, desc, curr_addr); 4028 4029 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4030 TSO_MAX_BUFF_SIZE : tmp_len; 4031 4032 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4033 0, 1, 4034 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4035 0, 0); 4036 4037 tmp_len -= TSO_MAX_BUFF_SIZE; 4038 } 4039 } 4040 4041 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4042 { 4043 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4044 int desc_size; 4045 4046 if (likely(priv->extend_desc)) 4047 desc_size = sizeof(struct dma_extended_desc); 4048 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4049 desc_size = sizeof(struct dma_edesc); 4050 else 4051 desc_size = sizeof(struct dma_desc); 4052 4053 /* The own bit must be the latest setting done when prepare the 4054 * descriptor and then barrier is needed to make sure that 4055 * all is coherent before granting the DMA engine. 4056 */ 4057 wmb(); 4058 4059 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4060 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4061 } 4062 4063 /** 4064 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4065 * @skb : the socket buffer 4066 * @dev : device pointer 4067 * Description: this is the transmit function that is called on TSO frames 4068 * (support available on GMAC4 and newer chips). 4069 * Diagram below show the ring programming in case of TSO frames: 4070 * 4071 * First Descriptor 4072 * -------- 4073 * | DES0 |---> buffer1 = L2/L3/L4 header 4074 * | DES1 |---> TCP Payload (can continue on next descr...) 4075 * | DES2 |---> buffer 1 and 2 len 4076 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4077 * -------- 4078 * | 4079 * ... 4080 * | 4081 * -------- 4082 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4083 * | DES1 | --| 4084 * | DES2 | --> buffer 1 and 2 len 4085 * | DES3 | 4086 * -------- 4087 * 4088 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4089 */ 4090 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4091 { 4092 struct dma_desc *desc, *first, *mss_desc = NULL; 4093 struct stmmac_priv *priv = netdev_priv(dev); 4094 int nfrags = skb_shinfo(skb)->nr_frags; 4095 u32 queue = skb_get_queue_mapping(skb); 4096 unsigned int first_entry, tx_packets; 4097 int tmp_pay_len = 0, first_tx; 4098 struct stmmac_tx_queue *tx_q; 4099 bool has_vlan, set_ic; 4100 u8 proto_hdr_len, hdr; 4101 u32 pay_len, mss; 4102 dma_addr_t des; 4103 int i; 4104 4105 tx_q = &priv->dma_conf.tx_queue[queue]; 4106 first_tx = tx_q->cur_tx; 4107 4108 /* Compute header lengths */ 4109 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4110 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4111 hdr = sizeof(struct udphdr); 4112 } else { 4113 proto_hdr_len = skb_tcp_all_headers(skb); 4114 hdr = tcp_hdrlen(skb); 4115 } 4116 4117 /* Desc availability based on threshold should be enough safe */ 4118 if (unlikely(stmmac_tx_avail(priv, queue) < 4119 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4120 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4121 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4122 queue)); 4123 /* This is a hard error, log it. */ 4124 netdev_err(priv->dev, 4125 "%s: Tx Ring full when queue awake\n", 4126 __func__); 4127 } 4128 return NETDEV_TX_BUSY; 4129 } 4130 4131 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4132 4133 mss = skb_shinfo(skb)->gso_size; 4134 4135 /* set new MSS value if needed */ 4136 if (mss != tx_q->mss) { 4137 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4138 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4139 else 4140 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4141 4142 stmmac_set_mss(priv, mss_desc, mss); 4143 tx_q->mss = mss; 4144 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4145 priv->dma_conf.dma_tx_size); 4146 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4147 } 4148 4149 if (netif_msg_tx_queued(priv)) { 4150 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4151 __func__, hdr, proto_hdr_len, pay_len, mss); 4152 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4153 skb->data_len); 4154 } 4155 4156 /* Check if VLAN can be inserted by HW */ 4157 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4158 4159 first_entry = tx_q->cur_tx; 4160 WARN_ON(tx_q->tx_skbuff[first_entry]); 4161 4162 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4163 desc = &tx_q->dma_entx[first_entry].basic; 4164 else 4165 desc = &tx_q->dma_tx[first_entry]; 4166 first = desc; 4167 4168 if (has_vlan) 4169 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4170 4171 /* first descriptor: fill Headers on Buf1 */ 4172 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4173 DMA_TO_DEVICE); 4174 if (dma_mapping_error(priv->device, des)) 4175 goto dma_map_err; 4176 4177 tx_q->tx_skbuff_dma[first_entry].buf = des; 4178 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4179 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4180 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4181 4182 if (priv->dma_cap.addr64 <= 32) { 4183 first->des0 = cpu_to_le32(des); 4184 4185 /* Fill start of payload in buff2 of first descriptor */ 4186 if (pay_len) 4187 first->des1 = cpu_to_le32(des + proto_hdr_len); 4188 4189 /* If needed take extra descriptors to fill the remaining payload */ 4190 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4191 } else { 4192 stmmac_set_desc_addr(priv, first, des); 4193 tmp_pay_len = pay_len; 4194 des += proto_hdr_len; 4195 pay_len = 0; 4196 } 4197 4198 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4199 4200 /* Prepare fragments */ 4201 for (i = 0; i < nfrags; i++) { 4202 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4203 4204 des = skb_frag_dma_map(priv->device, frag, 0, 4205 skb_frag_size(frag), 4206 DMA_TO_DEVICE); 4207 if (dma_mapping_error(priv->device, des)) 4208 goto dma_map_err; 4209 4210 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4211 (i == nfrags - 1), queue); 4212 4213 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4214 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4215 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4216 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4217 } 4218 4219 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4220 4221 /* Only the last descriptor gets to point to the skb. */ 4222 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4223 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4224 4225 /* Manage tx mitigation */ 4226 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4227 tx_q->tx_count_frames += tx_packets; 4228 4229 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4230 set_ic = true; 4231 else if (!priv->tx_coal_frames[queue]) 4232 set_ic = false; 4233 else if (tx_packets > priv->tx_coal_frames[queue]) 4234 set_ic = true; 4235 else if ((tx_q->tx_count_frames % 4236 priv->tx_coal_frames[queue]) < tx_packets) 4237 set_ic = true; 4238 else 4239 set_ic = false; 4240 4241 if (set_ic) { 4242 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4243 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4244 else 4245 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4246 4247 tx_q->tx_count_frames = 0; 4248 stmmac_set_tx_ic(priv, desc); 4249 priv->xstats.tx_set_ic_bit++; 4250 } 4251 4252 /* We've used all descriptors we need for this skb, however, 4253 * advance cur_tx so that it references a fresh descriptor. 4254 * ndo_start_xmit will fill this descriptor the next time it's 4255 * called and stmmac_tx_clean may clean up to this descriptor. 4256 */ 4257 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4258 4259 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4260 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4261 __func__); 4262 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4263 } 4264 4265 dev->stats.tx_bytes += skb->len; 4266 priv->xstats.tx_tso_frames++; 4267 priv->xstats.tx_tso_nfrags += nfrags; 4268 4269 if (priv->sarc_type) 4270 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4271 4272 skb_tx_timestamp(skb); 4273 4274 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4275 priv->hwts_tx_en)) { 4276 /* declare that device is doing timestamping */ 4277 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4278 stmmac_enable_tx_timestamp(priv, first); 4279 } 4280 4281 /* Complete the first descriptor before granting the DMA */ 4282 stmmac_prepare_tso_tx_desc(priv, first, 1, 4283 proto_hdr_len, 4284 pay_len, 4285 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4286 hdr / 4, (skb->len - proto_hdr_len)); 4287 4288 /* If context desc is used to change MSS */ 4289 if (mss_desc) { 4290 /* Make sure that first descriptor has been completely 4291 * written, including its own bit. This is because MSS is 4292 * actually before first descriptor, so we need to make 4293 * sure that MSS's own bit is the last thing written. 4294 */ 4295 dma_wmb(); 4296 stmmac_set_tx_owner(priv, mss_desc); 4297 } 4298 4299 if (netif_msg_pktdata(priv)) { 4300 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4301 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4302 tx_q->cur_tx, first, nfrags); 4303 pr_info(">>> frame to be transmitted: "); 4304 print_pkt(skb->data, skb_headlen(skb)); 4305 } 4306 4307 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4308 4309 stmmac_flush_tx_descriptors(priv, queue); 4310 stmmac_tx_timer_arm(priv, queue); 4311 4312 return NETDEV_TX_OK; 4313 4314 dma_map_err: 4315 dev_err(priv->device, "Tx dma map failed\n"); 4316 dev_kfree_skb(skb); 4317 priv->dev->stats.tx_dropped++; 4318 return NETDEV_TX_OK; 4319 } 4320 4321 /** 4322 * stmmac_xmit - Tx entry point of the driver 4323 * @skb : the socket buffer 4324 * @dev : device pointer 4325 * Description : this is the tx entry point of the driver. 4326 * It programs the chain or the ring and supports oversized frames 4327 * and SG feature. 4328 */ 4329 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4330 { 4331 unsigned int first_entry, tx_packets, enh_desc; 4332 struct stmmac_priv *priv = netdev_priv(dev); 4333 unsigned int nopaged_len = skb_headlen(skb); 4334 int i, csum_insertion = 0, is_jumbo = 0; 4335 u32 queue = skb_get_queue_mapping(skb); 4336 int nfrags = skb_shinfo(skb)->nr_frags; 4337 int gso = skb_shinfo(skb)->gso_type; 4338 struct dma_edesc *tbs_desc = NULL; 4339 struct dma_desc *desc, *first; 4340 struct stmmac_tx_queue *tx_q; 4341 bool has_vlan, set_ic; 4342 int entry, first_tx; 4343 dma_addr_t des; 4344 4345 tx_q = &priv->dma_conf.tx_queue[queue]; 4346 first_tx = tx_q->cur_tx; 4347 4348 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4349 stmmac_disable_eee_mode(priv); 4350 4351 /* Manage oversized TCP frames for GMAC4 device */ 4352 if (skb_is_gso(skb) && priv->tso) { 4353 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4354 return stmmac_tso_xmit(skb, dev); 4355 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4356 return stmmac_tso_xmit(skb, dev); 4357 } 4358 4359 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4360 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4361 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4362 queue)); 4363 /* This is a hard error, log it. */ 4364 netdev_err(priv->dev, 4365 "%s: Tx Ring full when queue awake\n", 4366 __func__); 4367 } 4368 return NETDEV_TX_BUSY; 4369 } 4370 4371 /* Check if VLAN can be inserted by HW */ 4372 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4373 4374 entry = tx_q->cur_tx; 4375 first_entry = entry; 4376 WARN_ON(tx_q->tx_skbuff[first_entry]); 4377 4378 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4379 4380 if (likely(priv->extend_desc)) 4381 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4382 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4383 desc = &tx_q->dma_entx[entry].basic; 4384 else 4385 desc = tx_q->dma_tx + entry; 4386 4387 first = desc; 4388 4389 if (has_vlan) 4390 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4391 4392 enh_desc = priv->plat->enh_desc; 4393 /* To program the descriptors according to the size of the frame */ 4394 if (enh_desc) 4395 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4396 4397 if (unlikely(is_jumbo)) { 4398 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4399 if (unlikely(entry < 0) && (entry != -EINVAL)) 4400 goto dma_map_err; 4401 } 4402 4403 for (i = 0; i < nfrags; i++) { 4404 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4405 int len = skb_frag_size(frag); 4406 bool last_segment = (i == (nfrags - 1)); 4407 4408 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4409 WARN_ON(tx_q->tx_skbuff[entry]); 4410 4411 if (likely(priv->extend_desc)) 4412 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4413 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4414 desc = &tx_q->dma_entx[entry].basic; 4415 else 4416 desc = tx_q->dma_tx + entry; 4417 4418 des = skb_frag_dma_map(priv->device, frag, 0, len, 4419 DMA_TO_DEVICE); 4420 if (dma_mapping_error(priv->device, des)) 4421 goto dma_map_err; /* should reuse desc w/o issues */ 4422 4423 tx_q->tx_skbuff_dma[entry].buf = des; 4424 4425 stmmac_set_desc_addr(priv, desc, des); 4426 4427 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4428 tx_q->tx_skbuff_dma[entry].len = len; 4429 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4430 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4431 4432 /* Prepare the descriptor and set the own bit too */ 4433 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4434 priv->mode, 1, last_segment, skb->len); 4435 } 4436 4437 /* Only the last descriptor gets to point to the skb. */ 4438 tx_q->tx_skbuff[entry] = skb; 4439 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4440 4441 /* According to the coalesce parameter the IC bit for the latest 4442 * segment is reset and the timer re-started to clean the tx status. 4443 * This approach takes care about the fragments: desc is the first 4444 * element in case of no SG. 4445 */ 4446 tx_packets = (entry + 1) - first_tx; 4447 tx_q->tx_count_frames += tx_packets; 4448 4449 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4450 set_ic = true; 4451 else if (!priv->tx_coal_frames[queue]) 4452 set_ic = false; 4453 else if (tx_packets > priv->tx_coal_frames[queue]) 4454 set_ic = true; 4455 else if ((tx_q->tx_count_frames % 4456 priv->tx_coal_frames[queue]) < tx_packets) 4457 set_ic = true; 4458 else 4459 set_ic = false; 4460 4461 if (set_ic) { 4462 if (likely(priv->extend_desc)) 4463 desc = &tx_q->dma_etx[entry].basic; 4464 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4465 desc = &tx_q->dma_entx[entry].basic; 4466 else 4467 desc = &tx_q->dma_tx[entry]; 4468 4469 tx_q->tx_count_frames = 0; 4470 stmmac_set_tx_ic(priv, desc); 4471 priv->xstats.tx_set_ic_bit++; 4472 } 4473 4474 /* We've used all descriptors we need for this skb, however, 4475 * advance cur_tx so that it references a fresh descriptor. 4476 * ndo_start_xmit will fill this descriptor the next time it's 4477 * called and stmmac_tx_clean may clean up to this descriptor. 4478 */ 4479 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4480 tx_q->cur_tx = entry; 4481 4482 if (netif_msg_pktdata(priv)) { 4483 netdev_dbg(priv->dev, 4484 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4485 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4486 entry, first, nfrags); 4487 4488 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4489 print_pkt(skb->data, skb->len); 4490 } 4491 4492 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4493 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4494 __func__); 4495 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4496 } 4497 4498 dev->stats.tx_bytes += skb->len; 4499 4500 if (priv->sarc_type) 4501 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4502 4503 skb_tx_timestamp(skb); 4504 4505 /* Ready to fill the first descriptor and set the OWN bit w/o any 4506 * problems because all the descriptors are actually ready to be 4507 * passed to the DMA engine. 4508 */ 4509 if (likely(!is_jumbo)) { 4510 bool last_segment = (nfrags == 0); 4511 4512 des = dma_map_single(priv->device, skb->data, 4513 nopaged_len, DMA_TO_DEVICE); 4514 if (dma_mapping_error(priv->device, des)) 4515 goto dma_map_err; 4516 4517 tx_q->tx_skbuff_dma[first_entry].buf = des; 4518 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4519 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4520 4521 stmmac_set_desc_addr(priv, first, des); 4522 4523 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4524 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4525 4526 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4527 priv->hwts_tx_en)) { 4528 /* declare that device is doing timestamping */ 4529 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4530 stmmac_enable_tx_timestamp(priv, first); 4531 } 4532 4533 /* Prepare the first descriptor setting the OWN bit too */ 4534 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4535 csum_insertion, priv->mode, 0, last_segment, 4536 skb->len); 4537 } 4538 4539 if (tx_q->tbs & STMMAC_TBS_EN) { 4540 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4541 4542 tbs_desc = &tx_q->dma_entx[first_entry]; 4543 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4544 } 4545 4546 stmmac_set_tx_owner(priv, first); 4547 4548 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4549 4550 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4551 4552 stmmac_flush_tx_descriptors(priv, queue); 4553 stmmac_tx_timer_arm(priv, queue); 4554 4555 return NETDEV_TX_OK; 4556 4557 dma_map_err: 4558 netdev_err(priv->dev, "Tx DMA map failed\n"); 4559 dev_kfree_skb(skb); 4560 priv->dev->stats.tx_dropped++; 4561 return NETDEV_TX_OK; 4562 } 4563 4564 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4565 { 4566 struct vlan_ethhdr *veth; 4567 __be16 vlan_proto; 4568 u16 vlanid; 4569 4570 veth = (struct vlan_ethhdr *)skb->data; 4571 vlan_proto = veth->h_vlan_proto; 4572 4573 if ((vlan_proto == htons(ETH_P_8021Q) && 4574 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4575 (vlan_proto == htons(ETH_P_8021AD) && 4576 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4577 /* pop the vlan tag */ 4578 vlanid = ntohs(veth->h_vlan_TCI); 4579 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4580 skb_pull(skb, VLAN_HLEN); 4581 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4582 } 4583 } 4584 4585 /** 4586 * stmmac_rx_refill - refill used skb preallocated buffers 4587 * @priv: driver private structure 4588 * @queue: RX queue index 4589 * Description : this is to reallocate the skb for the reception process 4590 * that is based on zero-copy. 4591 */ 4592 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4593 { 4594 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4595 int dirty = stmmac_rx_dirty(priv, queue); 4596 unsigned int entry = rx_q->dirty_rx; 4597 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4598 4599 if (priv->dma_cap.host_dma_width <= 32) 4600 gfp |= GFP_DMA32; 4601 4602 while (dirty-- > 0) { 4603 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4604 struct dma_desc *p; 4605 bool use_rx_wd; 4606 4607 if (priv->extend_desc) 4608 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4609 else 4610 p = rx_q->dma_rx + entry; 4611 4612 if (!buf->page) { 4613 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4614 if (!buf->page) 4615 break; 4616 } 4617 4618 if (priv->sph && !buf->sec_page) { 4619 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4620 if (!buf->sec_page) 4621 break; 4622 4623 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4624 } 4625 4626 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4627 4628 stmmac_set_desc_addr(priv, p, buf->addr); 4629 if (priv->sph) 4630 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4631 else 4632 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4633 stmmac_refill_desc3(priv, rx_q, p); 4634 4635 rx_q->rx_count_frames++; 4636 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4637 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4638 rx_q->rx_count_frames = 0; 4639 4640 use_rx_wd = !priv->rx_coal_frames[queue]; 4641 use_rx_wd |= rx_q->rx_count_frames > 0; 4642 if (!priv->use_riwt) 4643 use_rx_wd = false; 4644 4645 dma_wmb(); 4646 stmmac_set_rx_owner(priv, p, use_rx_wd); 4647 4648 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4649 } 4650 rx_q->dirty_rx = entry; 4651 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4652 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4653 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4654 } 4655 4656 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4657 struct dma_desc *p, 4658 int status, unsigned int len) 4659 { 4660 unsigned int plen = 0, hlen = 0; 4661 int coe = priv->hw->rx_csum; 4662 4663 /* Not first descriptor, buffer is always zero */ 4664 if (priv->sph && len) 4665 return 0; 4666 4667 /* First descriptor, get split header length */ 4668 stmmac_get_rx_header_len(priv, p, &hlen); 4669 if (priv->sph && hlen) { 4670 priv->xstats.rx_split_hdr_pkt_n++; 4671 return hlen; 4672 } 4673 4674 /* First descriptor, not last descriptor and not split header */ 4675 if (status & rx_not_ls) 4676 return priv->dma_conf.dma_buf_sz; 4677 4678 plen = stmmac_get_rx_frame_len(priv, p, coe); 4679 4680 /* First descriptor and last descriptor and not split header */ 4681 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4682 } 4683 4684 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4685 struct dma_desc *p, 4686 int status, unsigned int len) 4687 { 4688 int coe = priv->hw->rx_csum; 4689 unsigned int plen = 0; 4690 4691 /* Not split header, buffer is not available */ 4692 if (!priv->sph) 4693 return 0; 4694 4695 /* Not last descriptor */ 4696 if (status & rx_not_ls) 4697 return priv->dma_conf.dma_buf_sz; 4698 4699 plen = stmmac_get_rx_frame_len(priv, p, coe); 4700 4701 /* Last descriptor */ 4702 return plen - len; 4703 } 4704 4705 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4706 struct xdp_frame *xdpf, bool dma_map) 4707 { 4708 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4709 unsigned int entry = tx_q->cur_tx; 4710 struct dma_desc *tx_desc; 4711 dma_addr_t dma_addr; 4712 bool set_ic; 4713 4714 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4715 return STMMAC_XDP_CONSUMED; 4716 4717 if (likely(priv->extend_desc)) 4718 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4719 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4720 tx_desc = &tx_q->dma_entx[entry].basic; 4721 else 4722 tx_desc = tx_q->dma_tx + entry; 4723 4724 if (dma_map) { 4725 dma_addr = dma_map_single(priv->device, xdpf->data, 4726 xdpf->len, DMA_TO_DEVICE); 4727 if (dma_mapping_error(priv->device, dma_addr)) 4728 return STMMAC_XDP_CONSUMED; 4729 4730 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4731 } else { 4732 struct page *page = virt_to_page(xdpf->data); 4733 4734 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4735 xdpf->headroom; 4736 dma_sync_single_for_device(priv->device, dma_addr, 4737 xdpf->len, DMA_BIDIRECTIONAL); 4738 4739 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4740 } 4741 4742 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4743 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4744 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4745 tx_q->tx_skbuff_dma[entry].last_segment = true; 4746 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4747 4748 tx_q->xdpf[entry] = xdpf; 4749 4750 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4751 4752 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4753 true, priv->mode, true, true, 4754 xdpf->len); 4755 4756 tx_q->tx_count_frames++; 4757 4758 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4759 set_ic = true; 4760 else 4761 set_ic = false; 4762 4763 if (set_ic) { 4764 tx_q->tx_count_frames = 0; 4765 stmmac_set_tx_ic(priv, tx_desc); 4766 priv->xstats.tx_set_ic_bit++; 4767 } 4768 4769 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4770 4771 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4772 tx_q->cur_tx = entry; 4773 4774 return STMMAC_XDP_TX; 4775 } 4776 4777 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4778 int cpu) 4779 { 4780 int index = cpu; 4781 4782 if (unlikely(index < 0)) 4783 index = 0; 4784 4785 while (index >= priv->plat->tx_queues_to_use) 4786 index -= priv->plat->tx_queues_to_use; 4787 4788 return index; 4789 } 4790 4791 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4792 struct xdp_buff *xdp) 4793 { 4794 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4795 int cpu = smp_processor_id(); 4796 struct netdev_queue *nq; 4797 int queue; 4798 int res; 4799 4800 if (unlikely(!xdpf)) 4801 return STMMAC_XDP_CONSUMED; 4802 4803 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4804 nq = netdev_get_tx_queue(priv->dev, queue); 4805 4806 __netif_tx_lock(nq, cpu); 4807 /* Avoids TX time-out as we are sharing with slow path */ 4808 txq_trans_cond_update(nq); 4809 4810 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4811 if (res == STMMAC_XDP_TX) 4812 stmmac_flush_tx_descriptors(priv, queue); 4813 4814 __netif_tx_unlock(nq); 4815 4816 return res; 4817 } 4818 4819 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4820 struct bpf_prog *prog, 4821 struct xdp_buff *xdp) 4822 { 4823 u32 act; 4824 int res; 4825 4826 act = bpf_prog_run_xdp(prog, xdp); 4827 switch (act) { 4828 case XDP_PASS: 4829 res = STMMAC_XDP_PASS; 4830 break; 4831 case XDP_TX: 4832 res = stmmac_xdp_xmit_back(priv, xdp); 4833 break; 4834 case XDP_REDIRECT: 4835 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4836 res = STMMAC_XDP_CONSUMED; 4837 else 4838 res = STMMAC_XDP_REDIRECT; 4839 break; 4840 default: 4841 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4842 fallthrough; 4843 case XDP_ABORTED: 4844 trace_xdp_exception(priv->dev, prog, act); 4845 fallthrough; 4846 case XDP_DROP: 4847 res = STMMAC_XDP_CONSUMED; 4848 break; 4849 } 4850 4851 return res; 4852 } 4853 4854 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4855 struct xdp_buff *xdp) 4856 { 4857 struct bpf_prog *prog; 4858 int res; 4859 4860 prog = READ_ONCE(priv->xdp_prog); 4861 if (!prog) { 4862 res = STMMAC_XDP_PASS; 4863 goto out; 4864 } 4865 4866 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4867 out: 4868 return ERR_PTR(-res); 4869 } 4870 4871 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4872 int xdp_status) 4873 { 4874 int cpu = smp_processor_id(); 4875 int queue; 4876 4877 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4878 4879 if (xdp_status & STMMAC_XDP_TX) 4880 stmmac_tx_timer_arm(priv, queue); 4881 4882 if (xdp_status & STMMAC_XDP_REDIRECT) 4883 xdp_do_flush(); 4884 } 4885 4886 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4887 struct xdp_buff *xdp) 4888 { 4889 unsigned int metasize = xdp->data - xdp->data_meta; 4890 unsigned int datasize = xdp->data_end - xdp->data; 4891 struct sk_buff *skb; 4892 4893 skb = __napi_alloc_skb(&ch->rxtx_napi, 4894 xdp->data_end - xdp->data_hard_start, 4895 GFP_ATOMIC | __GFP_NOWARN); 4896 if (unlikely(!skb)) 4897 return NULL; 4898 4899 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4900 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4901 if (metasize) 4902 skb_metadata_set(skb, metasize); 4903 4904 return skb; 4905 } 4906 4907 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4908 struct dma_desc *p, struct dma_desc *np, 4909 struct xdp_buff *xdp) 4910 { 4911 struct stmmac_channel *ch = &priv->channel[queue]; 4912 unsigned int len = xdp->data_end - xdp->data; 4913 enum pkt_hash_types hash_type; 4914 int coe = priv->hw->rx_csum; 4915 struct sk_buff *skb; 4916 u32 hash; 4917 4918 skb = stmmac_construct_skb_zc(ch, xdp); 4919 if (!skb) { 4920 priv->dev->stats.rx_dropped++; 4921 return; 4922 } 4923 4924 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4925 stmmac_rx_vlan(priv->dev, skb); 4926 skb->protocol = eth_type_trans(skb, priv->dev); 4927 4928 if (unlikely(!coe)) 4929 skb_checksum_none_assert(skb); 4930 else 4931 skb->ip_summed = CHECKSUM_UNNECESSARY; 4932 4933 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4934 skb_set_hash(skb, hash, hash_type); 4935 4936 skb_record_rx_queue(skb, queue); 4937 napi_gro_receive(&ch->rxtx_napi, skb); 4938 4939 priv->dev->stats.rx_packets++; 4940 priv->dev->stats.rx_bytes += len; 4941 } 4942 4943 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4944 { 4945 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4946 unsigned int entry = rx_q->dirty_rx; 4947 struct dma_desc *rx_desc = NULL; 4948 bool ret = true; 4949 4950 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4951 4952 while (budget-- > 0 && entry != rx_q->cur_rx) { 4953 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4954 dma_addr_t dma_addr; 4955 bool use_rx_wd; 4956 4957 if (!buf->xdp) { 4958 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4959 if (!buf->xdp) { 4960 ret = false; 4961 break; 4962 } 4963 } 4964 4965 if (priv->extend_desc) 4966 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4967 else 4968 rx_desc = rx_q->dma_rx + entry; 4969 4970 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4971 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4972 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4973 stmmac_refill_desc3(priv, rx_q, rx_desc); 4974 4975 rx_q->rx_count_frames++; 4976 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4977 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4978 rx_q->rx_count_frames = 0; 4979 4980 use_rx_wd = !priv->rx_coal_frames[queue]; 4981 use_rx_wd |= rx_q->rx_count_frames > 0; 4982 if (!priv->use_riwt) 4983 use_rx_wd = false; 4984 4985 dma_wmb(); 4986 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4987 4988 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4989 } 4990 4991 if (rx_desc) { 4992 rx_q->dirty_rx = entry; 4993 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4994 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4995 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4996 } 4997 4998 return ret; 4999 } 5000 5001 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 5002 { 5003 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5004 unsigned int count = 0, error = 0, len = 0; 5005 int dirty = stmmac_rx_dirty(priv, queue); 5006 unsigned int next_entry = rx_q->cur_rx; 5007 unsigned int desc_size; 5008 struct bpf_prog *prog; 5009 bool failure = false; 5010 int xdp_status = 0; 5011 int status = 0; 5012 5013 if (netif_msg_rx_status(priv)) { 5014 void *rx_head; 5015 5016 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5017 if (priv->extend_desc) { 5018 rx_head = (void *)rx_q->dma_erx; 5019 desc_size = sizeof(struct dma_extended_desc); 5020 } else { 5021 rx_head = (void *)rx_q->dma_rx; 5022 desc_size = sizeof(struct dma_desc); 5023 } 5024 5025 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5026 rx_q->dma_rx_phy, desc_size); 5027 } 5028 while (count < limit) { 5029 struct stmmac_rx_buffer *buf; 5030 unsigned int buf1_len = 0; 5031 struct dma_desc *np, *p; 5032 int entry; 5033 int res; 5034 5035 if (!count && rx_q->state_saved) { 5036 error = rx_q->state.error; 5037 len = rx_q->state.len; 5038 } else { 5039 rx_q->state_saved = false; 5040 error = 0; 5041 len = 0; 5042 } 5043 5044 if (count >= limit) 5045 break; 5046 5047 read_again: 5048 buf1_len = 0; 5049 entry = next_entry; 5050 buf = &rx_q->buf_pool[entry]; 5051 5052 if (dirty >= STMMAC_RX_FILL_BATCH) { 5053 failure = failure || 5054 !stmmac_rx_refill_zc(priv, queue, dirty); 5055 dirty = 0; 5056 } 5057 5058 if (priv->extend_desc) 5059 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5060 else 5061 p = rx_q->dma_rx + entry; 5062 5063 /* read the status of the incoming frame */ 5064 status = stmmac_rx_status(priv, &priv->dev->stats, 5065 &priv->xstats, p); 5066 /* check if managed by the DMA otherwise go ahead */ 5067 if (unlikely(status & dma_own)) 5068 break; 5069 5070 /* Prefetch the next RX descriptor */ 5071 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5072 priv->dma_conf.dma_rx_size); 5073 next_entry = rx_q->cur_rx; 5074 5075 if (priv->extend_desc) 5076 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5077 else 5078 np = rx_q->dma_rx + next_entry; 5079 5080 prefetch(np); 5081 5082 /* Ensure a valid XSK buffer before proceed */ 5083 if (!buf->xdp) 5084 break; 5085 5086 if (priv->extend_desc) 5087 stmmac_rx_extended_status(priv, &priv->dev->stats, 5088 &priv->xstats, 5089 rx_q->dma_erx + entry); 5090 if (unlikely(status == discard_frame)) { 5091 xsk_buff_free(buf->xdp); 5092 buf->xdp = NULL; 5093 dirty++; 5094 error = 1; 5095 if (!priv->hwts_rx_en) 5096 priv->dev->stats.rx_errors++; 5097 } 5098 5099 if (unlikely(error && (status & rx_not_ls))) 5100 goto read_again; 5101 if (unlikely(error)) { 5102 count++; 5103 continue; 5104 } 5105 5106 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5107 if (likely(status & rx_not_ls)) { 5108 xsk_buff_free(buf->xdp); 5109 buf->xdp = NULL; 5110 dirty++; 5111 count++; 5112 goto read_again; 5113 } 5114 5115 /* XDP ZC Frame only support primary buffers for now */ 5116 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5117 len += buf1_len; 5118 5119 /* ACS is disabled; strip manually. */ 5120 if (likely(!(status & rx_not_ls))) { 5121 buf1_len -= ETH_FCS_LEN; 5122 len -= ETH_FCS_LEN; 5123 } 5124 5125 /* RX buffer is good and fit into a XSK pool buffer */ 5126 buf->xdp->data_end = buf->xdp->data + buf1_len; 5127 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5128 5129 prog = READ_ONCE(priv->xdp_prog); 5130 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5131 5132 switch (res) { 5133 case STMMAC_XDP_PASS: 5134 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5135 xsk_buff_free(buf->xdp); 5136 break; 5137 case STMMAC_XDP_CONSUMED: 5138 xsk_buff_free(buf->xdp); 5139 priv->dev->stats.rx_dropped++; 5140 break; 5141 case STMMAC_XDP_TX: 5142 case STMMAC_XDP_REDIRECT: 5143 xdp_status |= res; 5144 break; 5145 } 5146 5147 buf->xdp = NULL; 5148 dirty++; 5149 count++; 5150 } 5151 5152 if (status & rx_not_ls) { 5153 rx_q->state_saved = true; 5154 rx_q->state.error = error; 5155 rx_q->state.len = len; 5156 } 5157 5158 stmmac_finalize_xdp_rx(priv, xdp_status); 5159 5160 priv->xstats.rx_pkt_n += count; 5161 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5162 5163 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5164 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5165 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5166 else 5167 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5168 5169 return (int)count; 5170 } 5171 5172 return failure ? limit : (int)count; 5173 } 5174 5175 /** 5176 * stmmac_rx - manage the receive process 5177 * @priv: driver private structure 5178 * @limit: napi bugget 5179 * @queue: RX queue index. 5180 * Description : this the function called by the napi poll method. 5181 * It gets all the frames inside the ring. 5182 */ 5183 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5184 { 5185 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5186 struct stmmac_channel *ch = &priv->channel[queue]; 5187 unsigned int count = 0, error = 0, len = 0; 5188 int status = 0, coe = priv->hw->rx_csum; 5189 unsigned int next_entry = rx_q->cur_rx; 5190 enum dma_data_direction dma_dir; 5191 unsigned int desc_size; 5192 struct sk_buff *skb = NULL; 5193 struct xdp_buff xdp; 5194 int xdp_status = 0; 5195 int buf_sz; 5196 5197 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5198 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5199 5200 if (netif_msg_rx_status(priv)) { 5201 void *rx_head; 5202 5203 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5204 if (priv->extend_desc) { 5205 rx_head = (void *)rx_q->dma_erx; 5206 desc_size = sizeof(struct dma_extended_desc); 5207 } else { 5208 rx_head = (void *)rx_q->dma_rx; 5209 desc_size = sizeof(struct dma_desc); 5210 } 5211 5212 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5213 rx_q->dma_rx_phy, desc_size); 5214 } 5215 while (count < limit) { 5216 unsigned int buf1_len = 0, buf2_len = 0; 5217 enum pkt_hash_types hash_type; 5218 struct stmmac_rx_buffer *buf; 5219 struct dma_desc *np, *p; 5220 int entry; 5221 u32 hash; 5222 5223 if (!count && rx_q->state_saved) { 5224 skb = rx_q->state.skb; 5225 error = rx_q->state.error; 5226 len = rx_q->state.len; 5227 } else { 5228 rx_q->state_saved = false; 5229 skb = NULL; 5230 error = 0; 5231 len = 0; 5232 } 5233 5234 if (count >= limit) 5235 break; 5236 5237 read_again: 5238 buf1_len = 0; 5239 buf2_len = 0; 5240 entry = next_entry; 5241 buf = &rx_q->buf_pool[entry]; 5242 5243 if (priv->extend_desc) 5244 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5245 else 5246 p = rx_q->dma_rx + entry; 5247 5248 /* read the status of the incoming frame */ 5249 status = stmmac_rx_status(priv, &priv->dev->stats, 5250 &priv->xstats, p); 5251 /* check if managed by the DMA otherwise go ahead */ 5252 if (unlikely(status & dma_own)) 5253 break; 5254 5255 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5256 priv->dma_conf.dma_rx_size); 5257 next_entry = rx_q->cur_rx; 5258 5259 if (priv->extend_desc) 5260 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5261 else 5262 np = rx_q->dma_rx + next_entry; 5263 5264 prefetch(np); 5265 5266 if (priv->extend_desc) 5267 stmmac_rx_extended_status(priv, &priv->dev->stats, 5268 &priv->xstats, rx_q->dma_erx + entry); 5269 if (unlikely(status == discard_frame)) { 5270 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5271 buf->page = NULL; 5272 error = 1; 5273 if (!priv->hwts_rx_en) 5274 priv->dev->stats.rx_errors++; 5275 } 5276 5277 if (unlikely(error && (status & rx_not_ls))) 5278 goto read_again; 5279 if (unlikely(error)) { 5280 dev_kfree_skb(skb); 5281 skb = NULL; 5282 count++; 5283 continue; 5284 } 5285 5286 /* Buffer is good. Go on. */ 5287 5288 prefetch(page_address(buf->page) + buf->page_offset); 5289 if (buf->sec_page) 5290 prefetch(page_address(buf->sec_page)); 5291 5292 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5293 len += buf1_len; 5294 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5295 len += buf2_len; 5296 5297 /* ACS is disabled; strip manually. */ 5298 if (likely(!(status & rx_not_ls))) { 5299 if (buf2_len) { 5300 buf2_len -= ETH_FCS_LEN; 5301 len -= ETH_FCS_LEN; 5302 } else if (buf1_len) { 5303 buf1_len -= ETH_FCS_LEN; 5304 len -= ETH_FCS_LEN; 5305 } 5306 } 5307 5308 if (!skb) { 5309 unsigned int pre_len, sync_len; 5310 5311 dma_sync_single_for_cpu(priv->device, buf->addr, 5312 buf1_len, dma_dir); 5313 5314 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5315 xdp_prepare_buff(&xdp, page_address(buf->page), 5316 buf->page_offset, buf1_len, false); 5317 5318 pre_len = xdp.data_end - xdp.data_hard_start - 5319 buf->page_offset; 5320 skb = stmmac_xdp_run_prog(priv, &xdp); 5321 /* Due xdp_adjust_tail: DMA sync for_device 5322 * cover max len CPU touch 5323 */ 5324 sync_len = xdp.data_end - xdp.data_hard_start - 5325 buf->page_offset; 5326 sync_len = max(sync_len, pre_len); 5327 5328 /* For Not XDP_PASS verdict */ 5329 if (IS_ERR(skb)) { 5330 unsigned int xdp_res = -PTR_ERR(skb); 5331 5332 if (xdp_res & STMMAC_XDP_CONSUMED) { 5333 page_pool_put_page(rx_q->page_pool, 5334 virt_to_head_page(xdp.data), 5335 sync_len, true); 5336 buf->page = NULL; 5337 priv->dev->stats.rx_dropped++; 5338 5339 /* Clear skb as it was set as 5340 * status by XDP program. 5341 */ 5342 skb = NULL; 5343 5344 if (unlikely((status & rx_not_ls))) 5345 goto read_again; 5346 5347 count++; 5348 continue; 5349 } else if (xdp_res & (STMMAC_XDP_TX | 5350 STMMAC_XDP_REDIRECT)) { 5351 xdp_status |= xdp_res; 5352 buf->page = NULL; 5353 skb = NULL; 5354 count++; 5355 continue; 5356 } 5357 } 5358 } 5359 5360 if (!skb) { 5361 /* XDP program may expand or reduce tail */ 5362 buf1_len = xdp.data_end - xdp.data; 5363 5364 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5365 if (!skb) { 5366 priv->dev->stats.rx_dropped++; 5367 count++; 5368 goto drain_data; 5369 } 5370 5371 /* XDP program may adjust header */ 5372 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5373 skb_put(skb, buf1_len); 5374 5375 /* Data payload copied into SKB, page ready for recycle */ 5376 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5377 buf->page = NULL; 5378 } else if (buf1_len) { 5379 dma_sync_single_for_cpu(priv->device, buf->addr, 5380 buf1_len, dma_dir); 5381 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5382 buf->page, buf->page_offset, buf1_len, 5383 priv->dma_conf.dma_buf_sz); 5384 5385 /* Data payload appended into SKB */ 5386 page_pool_release_page(rx_q->page_pool, buf->page); 5387 buf->page = NULL; 5388 } 5389 5390 if (buf2_len) { 5391 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5392 buf2_len, dma_dir); 5393 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5394 buf->sec_page, 0, buf2_len, 5395 priv->dma_conf.dma_buf_sz); 5396 5397 /* Data payload appended into SKB */ 5398 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5399 buf->sec_page = NULL; 5400 } 5401 5402 drain_data: 5403 if (likely(status & rx_not_ls)) 5404 goto read_again; 5405 if (!skb) 5406 continue; 5407 5408 /* Got entire packet into SKB. Finish it. */ 5409 5410 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5411 stmmac_rx_vlan(priv->dev, skb); 5412 skb->protocol = eth_type_trans(skb, priv->dev); 5413 5414 if (unlikely(!coe)) 5415 skb_checksum_none_assert(skb); 5416 else 5417 skb->ip_summed = CHECKSUM_UNNECESSARY; 5418 5419 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5420 skb_set_hash(skb, hash, hash_type); 5421 5422 skb_record_rx_queue(skb, queue); 5423 napi_gro_receive(&ch->rx_napi, skb); 5424 skb = NULL; 5425 5426 priv->dev->stats.rx_packets++; 5427 priv->dev->stats.rx_bytes += len; 5428 count++; 5429 } 5430 5431 if (status & rx_not_ls || skb) { 5432 rx_q->state_saved = true; 5433 rx_q->state.skb = skb; 5434 rx_q->state.error = error; 5435 rx_q->state.len = len; 5436 } 5437 5438 stmmac_finalize_xdp_rx(priv, xdp_status); 5439 5440 stmmac_rx_refill(priv, queue); 5441 5442 priv->xstats.rx_pkt_n += count; 5443 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5444 5445 return count; 5446 } 5447 5448 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5449 { 5450 struct stmmac_channel *ch = 5451 container_of(napi, struct stmmac_channel, rx_napi); 5452 struct stmmac_priv *priv = ch->priv_data; 5453 u32 chan = ch->index; 5454 int work_done; 5455 5456 priv->xstats.napi_poll++; 5457 5458 work_done = stmmac_rx(priv, budget, chan); 5459 if (work_done < budget && napi_complete_done(napi, work_done)) { 5460 unsigned long flags; 5461 5462 spin_lock_irqsave(&ch->lock, flags); 5463 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5464 spin_unlock_irqrestore(&ch->lock, flags); 5465 } 5466 5467 return work_done; 5468 } 5469 5470 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5471 { 5472 struct stmmac_channel *ch = 5473 container_of(napi, struct stmmac_channel, tx_napi); 5474 struct stmmac_priv *priv = ch->priv_data; 5475 u32 chan = ch->index; 5476 int work_done; 5477 5478 priv->xstats.napi_poll++; 5479 5480 work_done = stmmac_tx_clean(priv, budget, chan); 5481 work_done = min(work_done, budget); 5482 5483 if (work_done < budget && napi_complete_done(napi, work_done)) { 5484 unsigned long flags; 5485 5486 spin_lock_irqsave(&ch->lock, flags); 5487 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5488 spin_unlock_irqrestore(&ch->lock, flags); 5489 } 5490 5491 return work_done; 5492 } 5493 5494 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5495 { 5496 struct stmmac_channel *ch = 5497 container_of(napi, struct stmmac_channel, rxtx_napi); 5498 struct stmmac_priv *priv = ch->priv_data; 5499 int rx_done, tx_done, rxtx_done; 5500 u32 chan = ch->index; 5501 5502 priv->xstats.napi_poll++; 5503 5504 tx_done = stmmac_tx_clean(priv, budget, chan); 5505 tx_done = min(tx_done, budget); 5506 5507 rx_done = stmmac_rx_zc(priv, budget, chan); 5508 5509 rxtx_done = max(tx_done, rx_done); 5510 5511 /* If either TX or RX work is not complete, return budget 5512 * and keep pooling 5513 */ 5514 if (rxtx_done >= budget) 5515 return budget; 5516 5517 /* all work done, exit the polling mode */ 5518 if (napi_complete_done(napi, rxtx_done)) { 5519 unsigned long flags; 5520 5521 spin_lock_irqsave(&ch->lock, flags); 5522 /* Both RX and TX work done are compelte, 5523 * so enable both RX & TX IRQs. 5524 */ 5525 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5526 spin_unlock_irqrestore(&ch->lock, flags); 5527 } 5528 5529 return min(rxtx_done, budget - 1); 5530 } 5531 5532 /** 5533 * stmmac_tx_timeout 5534 * @dev : Pointer to net device structure 5535 * @txqueue: the index of the hanging transmit queue 5536 * Description: this function is called when a packet transmission fails to 5537 * complete within a reasonable time. The driver will mark the error in the 5538 * netdev structure and arrange for the device to be reset to a sane state 5539 * in order to transmit a new packet. 5540 */ 5541 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5542 { 5543 struct stmmac_priv *priv = netdev_priv(dev); 5544 5545 stmmac_global_err(priv); 5546 } 5547 5548 /** 5549 * stmmac_set_rx_mode - entry point for multicast addressing 5550 * @dev : pointer to the device structure 5551 * Description: 5552 * This function is a driver entry point which gets called by the kernel 5553 * whenever multicast addresses must be enabled/disabled. 5554 * Return value: 5555 * void. 5556 */ 5557 static void stmmac_set_rx_mode(struct net_device *dev) 5558 { 5559 struct stmmac_priv *priv = netdev_priv(dev); 5560 5561 stmmac_set_filter(priv, priv->hw, dev); 5562 } 5563 5564 /** 5565 * stmmac_change_mtu - entry point to change MTU size for the device. 5566 * @dev : device pointer. 5567 * @new_mtu : the new MTU size for the device. 5568 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5569 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5570 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5571 * Return value: 5572 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5573 * file on failure. 5574 */ 5575 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5576 { 5577 struct stmmac_priv *priv = netdev_priv(dev); 5578 int txfifosz = priv->plat->tx_fifo_size; 5579 struct stmmac_dma_conf *dma_conf; 5580 const int mtu = new_mtu; 5581 int ret; 5582 5583 if (txfifosz == 0) 5584 txfifosz = priv->dma_cap.tx_fifo_size; 5585 5586 txfifosz /= priv->plat->tx_queues_to_use; 5587 5588 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5589 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5590 return -EINVAL; 5591 } 5592 5593 new_mtu = STMMAC_ALIGN(new_mtu); 5594 5595 /* If condition true, FIFO is too small or MTU too large */ 5596 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5597 return -EINVAL; 5598 5599 if (netif_running(dev)) { 5600 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5601 /* Try to allocate the new DMA conf with the new mtu */ 5602 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5603 if (IS_ERR(dma_conf)) { 5604 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5605 mtu); 5606 return PTR_ERR(dma_conf); 5607 } 5608 5609 stmmac_release(dev); 5610 5611 ret = __stmmac_open(dev, dma_conf); 5612 kfree(dma_conf); 5613 if (ret) { 5614 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5615 return ret; 5616 } 5617 5618 stmmac_set_rx_mode(dev); 5619 } 5620 5621 dev->mtu = mtu; 5622 netdev_update_features(dev); 5623 5624 return 0; 5625 } 5626 5627 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5628 netdev_features_t features) 5629 { 5630 struct stmmac_priv *priv = netdev_priv(dev); 5631 5632 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5633 features &= ~NETIF_F_RXCSUM; 5634 5635 if (!priv->plat->tx_coe) 5636 features &= ~NETIF_F_CSUM_MASK; 5637 5638 /* Some GMAC devices have a bugged Jumbo frame support that 5639 * needs to have the Tx COE disabled for oversized frames 5640 * (due to limited buffer sizes). In this case we disable 5641 * the TX csum insertion in the TDES and not use SF. 5642 */ 5643 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5644 features &= ~NETIF_F_CSUM_MASK; 5645 5646 /* Disable tso if asked by ethtool */ 5647 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5648 if (features & NETIF_F_TSO) 5649 priv->tso = true; 5650 else 5651 priv->tso = false; 5652 } 5653 5654 return features; 5655 } 5656 5657 static int stmmac_set_features(struct net_device *netdev, 5658 netdev_features_t features) 5659 { 5660 struct stmmac_priv *priv = netdev_priv(netdev); 5661 5662 /* Keep the COE Type in case of csum is supporting */ 5663 if (features & NETIF_F_RXCSUM) 5664 priv->hw->rx_csum = priv->plat->rx_coe; 5665 else 5666 priv->hw->rx_csum = 0; 5667 /* No check needed because rx_coe has been set before and it will be 5668 * fixed in case of issue. 5669 */ 5670 stmmac_rx_ipc(priv, priv->hw); 5671 5672 if (priv->sph_cap) { 5673 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5674 u32 chan; 5675 5676 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5677 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5678 } 5679 5680 return 0; 5681 } 5682 5683 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5684 { 5685 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5686 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5687 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5688 bool *hs_enable = &fpe_cfg->hs_enable; 5689 5690 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5691 return; 5692 5693 /* If LP has sent verify mPacket, LP is FPE capable */ 5694 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5695 if (*lp_state < FPE_STATE_CAPABLE) 5696 *lp_state = FPE_STATE_CAPABLE; 5697 5698 /* If user has requested FPE enable, quickly response */ 5699 if (*hs_enable) 5700 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5701 MPACKET_RESPONSE); 5702 } 5703 5704 /* If Local has sent verify mPacket, Local is FPE capable */ 5705 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5706 if (*lo_state < FPE_STATE_CAPABLE) 5707 *lo_state = FPE_STATE_CAPABLE; 5708 } 5709 5710 /* If LP has sent response mPacket, LP is entering FPE ON */ 5711 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5712 *lp_state = FPE_STATE_ENTERING_ON; 5713 5714 /* If Local has sent response mPacket, Local is entering FPE ON */ 5715 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5716 *lo_state = FPE_STATE_ENTERING_ON; 5717 5718 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5719 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5720 priv->fpe_wq) { 5721 queue_work(priv->fpe_wq, &priv->fpe_task); 5722 } 5723 } 5724 5725 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5726 { 5727 u32 rx_cnt = priv->plat->rx_queues_to_use; 5728 u32 tx_cnt = priv->plat->tx_queues_to_use; 5729 u32 queues_count; 5730 u32 queue; 5731 bool xmac; 5732 5733 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5734 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5735 5736 if (priv->irq_wake) 5737 pm_wakeup_event(priv->device, 0); 5738 5739 if (priv->dma_cap.estsel) 5740 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5741 &priv->xstats, tx_cnt); 5742 5743 if (priv->dma_cap.fpesel) { 5744 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5745 priv->dev); 5746 5747 stmmac_fpe_event_status(priv, status); 5748 } 5749 5750 /* To handle GMAC own interrupts */ 5751 if ((priv->plat->has_gmac) || xmac) { 5752 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5753 5754 if (unlikely(status)) { 5755 /* For LPI we need to save the tx status */ 5756 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5757 priv->tx_path_in_lpi_mode = true; 5758 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5759 priv->tx_path_in_lpi_mode = false; 5760 } 5761 5762 for (queue = 0; queue < queues_count; queue++) { 5763 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5764 queue); 5765 } 5766 5767 /* PCS link status */ 5768 if (priv->hw->pcs) { 5769 if (priv->xstats.pcs_link) 5770 netif_carrier_on(priv->dev); 5771 else 5772 netif_carrier_off(priv->dev); 5773 } 5774 5775 stmmac_timestamp_interrupt(priv, priv); 5776 } 5777 } 5778 5779 /** 5780 * stmmac_interrupt - main ISR 5781 * @irq: interrupt number. 5782 * @dev_id: to pass the net device pointer. 5783 * Description: this is the main driver interrupt service routine. 5784 * It can call: 5785 * o DMA service routine (to manage incoming frame reception and transmission 5786 * status) 5787 * o Core interrupts to manage: remote wake-up, management counter, LPI 5788 * interrupts. 5789 */ 5790 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5791 { 5792 struct net_device *dev = (struct net_device *)dev_id; 5793 struct stmmac_priv *priv = netdev_priv(dev); 5794 5795 /* Check if adapter is up */ 5796 if (test_bit(STMMAC_DOWN, &priv->state)) 5797 return IRQ_HANDLED; 5798 5799 /* Check if a fatal error happened */ 5800 if (stmmac_safety_feat_interrupt(priv)) 5801 return IRQ_HANDLED; 5802 5803 /* To handle Common interrupts */ 5804 stmmac_common_interrupt(priv); 5805 5806 /* To handle DMA interrupts */ 5807 stmmac_dma_interrupt(priv); 5808 5809 return IRQ_HANDLED; 5810 } 5811 5812 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5813 { 5814 struct net_device *dev = (struct net_device *)dev_id; 5815 struct stmmac_priv *priv = netdev_priv(dev); 5816 5817 if (unlikely(!dev)) { 5818 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5819 return IRQ_NONE; 5820 } 5821 5822 /* Check if adapter is up */ 5823 if (test_bit(STMMAC_DOWN, &priv->state)) 5824 return IRQ_HANDLED; 5825 5826 /* To handle Common interrupts */ 5827 stmmac_common_interrupt(priv); 5828 5829 return IRQ_HANDLED; 5830 } 5831 5832 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5833 { 5834 struct net_device *dev = (struct net_device *)dev_id; 5835 struct stmmac_priv *priv = netdev_priv(dev); 5836 5837 if (unlikely(!dev)) { 5838 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5839 return IRQ_NONE; 5840 } 5841 5842 /* Check if adapter is up */ 5843 if (test_bit(STMMAC_DOWN, &priv->state)) 5844 return IRQ_HANDLED; 5845 5846 /* Check if a fatal error happened */ 5847 stmmac_safety_feat_interrupt(priv); 5848 5849 return IRQ_HANDLED; 5850 } 5851 5852 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5853 { 5854 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5855 struct stmmac_dma_conf *dma_conf; 5856 int chan = tx_q->queue_index; 5857 struct stmmac_priv *priv; 5858 int status; 5859 5860 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5861 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5862 5863 if (unlikely(!data)) { 5864 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5865 return IRQ_NONE; 5866 } 5867 5868 /* Check if adapter is up */ 5869 if (test_bit(STMMAC_DOWN, &priv->state)) 5870 return IRQ_HANDLED; 5871 5872 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5873 5874 if (unlikely(status & tx_hard_error_bump_tc)) { 5875 /* Try to bump up the dma threshold on this failure */ 5876 stmmac_bump_dma_threshold(priv, chan); 5877 } else if (unlikely(status == tx_hard_error)) { 5878 stmmac_tx_err(priv, chan); 5879 } 5880 5881 return IRQ_HANDLED; 5882 } 5883 5884 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5885 { 5886 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5887 struct stmmac_dma_conf *dma_conf; 5888 int chan = rx_q->queue_index; 5889 struct stmmac_priv *priv; 5890 5891 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5892 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5893 5894 if (unlikely(!data)) { 5895 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5896 return IRQ_NONE; 5897 } 5898 5899 /* Check if adapter is up */ 5900 if (test_bit(STMMAC_DOWN, &priv->state)) 5901 return IRQ_HANDLED; 5902 5903 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5904 5905 return IRQ_HANDLED; 5906 } 5907 5908 #ifdef CONFIG_NET_POLL_CONTROLLER 5909 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5910 * to allow network I/O with interrupts disabled. 5911 */ 5912 static void stmmac_poll_controller(struct net_device *dev) 5913 { 5914 struct stmmac_priv *priv = netdev_priv(dev); 5915 int i; 5916 5917 /* If adapter is down, do nothing */ 5918 if (test_bit(STMMAC_DOWN, &priv->state)) 5919 return; 5920 5921 if (priv->plat->multi_msi_en) { 5922 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5923 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5924 5925 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5926 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5927 } else { 5928 disable_irq(dev->irq); 5929 stmmac_interrupt(dev->irq, dev); 5930 enable_irq(dev->irq); 5931 } 5932 } 5933 #endif 5934 5935 /** 5936 * stmmac_ioctl - Entry point for the Ioctl 5937 * @dev: Device pointer. 5938 * @rq: An IOCTL specefic structure, that can contain a pointer to 5939 * a proprietary structure used to pass information to the driver. 5940 * @cmd: IOCTL command 5941 * Description: 5942 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5943 */ 5944 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5945 { 5946 struct stmmac_priv *priv = netdev_priv (dev); 5947 int ret = -EOPNOTSUPP; 5948 5949 if (!netif_running(dev)) 5950 return -EINVAL; 5951 5952 switch (cmd) { 5953 case SIOCGMIIPHY: 5954 case SIOCGMIIREG: 5955 case SIOCSMIIREG: 5956 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5957 break; 5958 case SIOCSHWTSTAMP: 5959 ret = stmmac_hwtstamp_set(dev, rq); 5960 break; 5961 case SIOCGHWTSTAMP: 5962 ret = stmmac_hwtstamp_get(dev, rq); 5963 break; 5964 default: 5965 break; 5966 } 5967 5968 return ret; 5969 } 5970 5971 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5972 void *cb_priv) 5973 { 5974 struct stmmac_priv *priv = cb_priv; 5975 int ret = -EOPNOTSUPP; 5976 5977 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5978 return ret; 5979 5980 __stmmac_disable_all_queues(priv); 5981 5982 switch (type) { 5983 case TC_SETUP_CLSU32: 5984 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5985 break; 5986 case TC_SETUP_CLSFLOWER: 5987 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5988 break; 5989 default: 5990 break; 5991 } 5992 5993 stmmac_enable_all_queues(priv); 5994 return ret; 5995 } 5996 5997 static LIST_HEAD(stmmac_block_cb_list); 5998 5999 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 6000 void *type_data) 6001 { 6002 struct stmmac_priv *priv = netdev_priv(ndev); 6003 6004 switch (type) { 6005 case TC_QUERY_CAPS: 6006 return stmmac_tc_query_caps(priv, priv, type_data); 6007 case TC_SETUP_BLOCK: 6008 return flow_block_cb_setup_simple(type_data, 6009 &stmmac_block_cb_list, 6010 stmmac_setup_tc_block_cb, 6011 priv, priv, true); 6012 case TC_SETUP_QDISC_CBS: 6013 return stmmac_tc_setup_cbs(priv, priv, type_data); 6014 case TC_SETUP_QDISC_TAPRIO: 6015 return stmmac_tc_setup_taprio(priv, priv, type_data); 6016 case TC_SETUP_QDISC_ETF: 6017 return stmmac_tc_setup_etf(priv, priv, type_data); 6018 default: 6019 return -EOPNOTSUPP; 6020 } 6021 } 6022 6023 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6024 struct net_device *sb_dev) 6025 { 6026 int gso = skb_shinfo(skb)->gso_type; 6027 6028 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6029 /* 6030 * There is no way to determine the number of TSO/USO 6031 * capable Queues. Let's use always the Queue 0 6032 * because if TSO/USO is supported then at least this 6033 * one will be capable. 6034 */ 6035 return 0; 6036 } 6037 6038 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6039 } 6040 6041 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6042 { 6043 struct stmmac_priv *priv = netdev_priv(ndev); 6044 int ret = 0; 6045 6046 ret = pm_runtime_resume_and_get(priv->device); 6047 if (ret < 0) 6048 return ret; 6049 6050 ret = eth_mac_addr(ndev, addr); 6051 if (ret) 6052 goto set_mac_error; 6053 6054 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6055 6056 set_mac_error: 6057 pm_runtime_put(priv->device); 6058 6059 return ret; 6060 } 6061 6062 #ifdef CONFIG_DEBUG_FS 6063 static struct dentry *stmmac_fs_dir; 6064 6065 static void sysfs_display_ring(void *head, int size, int extend_desc, 6066 struct seq_file *seq, dma_addr_t dma_phy_addr) 6067 { 6068 int i; 6069 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6070 struct dma_desc *p = (struct dma_desc *)head; 6071 dma_addr_t dma_addr; 6072 6073 for (i = 0; i < size; i++) { 6074 if (extend_desc) { 6075 dma_addr = dma_phy_addr + i * sizeof(*ep); 6076 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6077 i, &dma_addr, 6078 le32_to_cpu(ep->basic.des0), 6079 le32_to_cpu(ep->basic.des1), 6080 le32_to_cpu(ep->basic.des2), 6081 le32_to_cpu(ep->basic.des3)); 6082 ep++; 6083 } else { 6084 dma_addr = dma_phy_addr + i * sizeof(*p); 6085 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6086 i, &dma_addr, 6087 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6088 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6089 p++; 6090 } 6091 seq_printf(seq, "\n"); 6092 } 6093 } 6094 6095 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6096 { 6097 struct net_device *dev = seq->private; 6098 struct stmmac_priv *priv = netdev_priv(dev); 6099 u32 rx_count = priv->plat->rx_queues_to_use; 6100 u32 tx_count = priv->plat->tx_queues_to_use; 6101 u32 queue; 6102 6103 if ((dev->flags & IFF_UP) == 0) 6104 return 0; 6105 6106 for (queue = 0; queue < rx_count; queue++) { 6107 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6108 6109 seq_printf(seq, "RX Queue %d:\n", queue); 6110 6111 if (priv->extend_desc) { 6112 seq_printf(seq, "Extended descriptor ring:\n"); 6113 sysfs_display_ring((void *)rx_q->dma_erx, 6114 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6115 } else { 6116 seq_printf(seq, "Descriptor ring:\n"); 6117 sysfs_display_ring((void *)rx_q->dma_rx, 6118 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6119 } 6120 } 6121 6122 for (queue = 0; queue < tx_count; queue++) { 6123 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6124 6125 seq_printf(seq, "TX Queue %d:\n", queue); 6126 6127 if (priv->extend_desc) { 6128 seq_printf(seq, "Extended descriptor ring:\n"); 6129 sysfs_display_ring((void *)tx_q->dma_etx, 6130 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6131 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6132 seq_printf(seq, "Descriptor ring:\n"); 6133 sysfs_display_ring((void *)tx_q->dma_tx, 6134 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6135 } 6136 } 6137 6138 return 0; 6139 } 6140 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6141 6142 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6143 { 6144 struct net_device *dev = seq->private; 6145 struct stmmac_priv *priv = netdev_priv(dev); 6146 6147 if (!priv->hw_cap_support) { 6148 seq_printf(seq, "DMA HW features not supported\n"); 6149 return 0; 6150 } 6151 6152 seq_printf(seq, "==============================\n"); 6153 seq_printf(seq, "\tDMA HW features\n"); 6154 seq_printf(seq, "==============================\n"); 6155 6156 seq_printf(seq, "\t10/100 Mbps: %s\n", 6157 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6158 seq_printf(seq, "\t1000 Mbps: %s\n", 6159 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6160 seq_printf(seq, "\tHalf duplex: %s\n", 6161 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6162 seq_printf(seq, "\tHash Filter: %s\n", 6163 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6164 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6165 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6166 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6167 (priv->dma_cap.pcs) ? "Y" : "N"); 6168 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6169 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6170 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6171 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6172 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6173 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6174 seq_printf(seq, "\tRMON module: %s\n", 6175 (priv->dma_cap.rmon) ? "Y" : "N"); 6176 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6177 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6178 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6179 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6180 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6181 (priv->dma_cap.eee) ? "Y" : "N"); 6182 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6183 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6184 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6185 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6186 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6187 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6188 } else { 6189 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6190 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6191 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6192 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6193 } 6194 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6195 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6196 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6197 priv->dma_cap.number_rx_channel); 6198 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6199 priv->dma_cap.number_tx_channel); 6200 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6201 priv->dma_cap.number_rx_queues); 6202 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6203 priv->dma_cap.number_tx_queues); 6204 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6205 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6206 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6207 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6208 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6209 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6210 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6211 priv->dma_cap.pps_out_num); 6212 seq_printf(seq, "\tSafety Features: %s\n", 6213 priv->dma_cap.asp ? "Y" : "N"); 6214 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6215 priv->dma_cap.frpsel ? "Y" : "N"); 6216 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6217 priv->dma_cap.host_dma_width); 6218 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6219 priv->dma_cap.rssen ? "Y" : "N"); 6220 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6221 priv->dma_cap.vlhash ? "Y" : "N"); 6222 seq_printf(seq, "\tSplit Header: %s\n", 6223 priv->dma_cap.sphen ? "Y" : "N"); 6224 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6225 priv->dma_cap.vlins ? "Y" : "N"); 6226 seq_printf(seq, "\tDouble VLAN: %s\n", 6227 priv->dma_cap.dvlan ? "Y" : "N"); 6228 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6229 priv->dma_cap.l3l4fnum); 6230 seq_printf(seq, "\tARP Offloading: %s\n", 6231 priv->dma_cap.arpoffsel ? "Y" : "N"); 6232 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6233 priv->dma_cap.estsel ? "Y" : "N"); 6234 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6235 priv->dma_cap.fpesel ? "Y" : "N"); 6236 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6237 priv->dma_cap.tbssel ? "Y" : "N"); 6238 return 0; 6239 } 6240 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6241 6242 /* Use network device events to rename debugfs file entries. 6243 */ 6244 static int stmmac_device_event(struct notifier_block *unused, 6245 unsigned long event, void *ptr) 6246 { 6247 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6248 struct stmmac_priv *priv = netdev_priv(dev); 6249 6250 if (dev->netdev_ops != &stmmac_netdev_ops) 6251 goto done; 6252 6253 switch (event) { 6254 case NETDEV_CHANGENAME: 6255 if (priv->dbgfs_dir) 6256 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6257 priv->dbgfs_dir, 6258 stmmac_fs_dir, 6259 dev->name); 6260 break; 6261 } 6262 done: 6263 return NOTIFY_DONE; 6264 } 6265 6266 static struct notifier_block stmmac_notifier = { 6267 .notifier_call = stmmac_device_event, 6268 }; 6269 6270 static void stmmac_init_fs(struct net_device *dev) 6271 { 6272 struct stmmac_priv *priv = netdev_priv(dev); 6273 6274 rtnl_lock(); 6275 6276 /* Create per netdev entries */ 6277 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6278 6279 /* Entry to report DMA RX/TX rings */ 6280 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6281 &stmmac_rings_status_fops); 6282 6283 /* Entry to report the DMA HW features */ 6284 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6285 &stmmac_dma_cap_fops); 6286 6287 rtnl_unlock(); 6288 } 6289 6290 static void stmmac_exit_fs(struct net_device *dev) 6291 { 6292 struct stmmac_priv *priv = netdev_priv(dev); 6293 6294 debugfs_remove_recursive(priv->dbgfs_dir); 6295 } 6296 #endif /* CONFIG_DEBUG_FS */ 6297 6298 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6299 { 6300 unsigned char *data = (unsigned char *)&vid_le; 6301 unsigned char data_byte = 0; 6302 u32 crc = ~0x0; 6303 u32 temp = 0; 6304 int i, bits; 6305 6306 bits = get_bitmask_order(VLAN_VID_MASK); 6307 for (i = 0; i < bits; i++) { 6308 if ((i % 8) == 0) 6309 data_byte = data[i / 8]; 6310 6311 temp = ((crc & 1) ^ data_byte) & 1; 6312 crc >>= 1; 6313 data_byte >>= 1; 6314 6315 if (temp) 6316 crc ^= 0xedb88320; 6317 } 6318 6319 return crc; 6320 } 6321 6322 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6323 { 6324 u32 crc, hash = 0; 6325 __le16 pmatch = 0; 6326 int count = 0; 6327 u16 vid = 0; 6328 6329 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6330 __le16 vid_le = cpu_to_le16(vid); 6331 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6332 hash |= (1 << crc); 6333 count++; 6334 } 6335 6336 if (!priv->dma_cap.vlhash) { 6337 if (count > 2) /* VID = 0 always passes filter */ 6338 return -EOPNOTSUPP; 6339 6340 pmatch = cpu_to_le16(vid); 6341 hash = 0; 6342 } 6343 6344 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6345 } 6346 6347 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6348 { 6349 struct stmmac_priv *priv = netdev_priv(ndev); 6350 bool is_double = false; 6351 int ret; 6352 6353 if (be16_to_cpu(proto) == ETH_P_8021AD) 6354 is_double = true; 6355 6356 set_bit(vid, priv->active_vlans); 6357 ret = stmmac_vlan_update(priv, is_double); 6358 if (ret) { 6359 clear_bit(vid, priv->active_vlans); 6360 return ret; 6361 } 6362 6363 if (priv->hw->num_vlan) { 6364 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6365 if (ret) 6366 return ret; 6367 } 6368 6369 return 0; 6370 } 6371 6372 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6373 { 6374 struct stmmac_priv *priv = netdev_priv(ndev); 6375 bool is_double = false; 6376 int ret; 6377 6378 ret = pm_runtime_resume_and_get(priv->device); 6379 if (ret < 0) 6380 return ret; 6381 6382 if (be16_to_cpu(proto) == ETH_P_8021AD) 6383 is_double = true; 6384 6385 clear_bit(vid, priv->active_vlans); 6386 6387 if (priv->hw->num_vlan) { 6388 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6389 if (ret) 6390 goto del_vlan_error; 6391 } 6392 6393 ret = stmmac_vlan_update(priv, is_double); 6394 6395 del_vlan_error: 6396 pm_runtime_put(priv->device); 6397 6398 return ret; 6399 } 6400 6401 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6402 { 6403 struct stmmac_priv *priv = netdev_priv(dev); 6404 6405 switch (bpf->command) { 6406 case XDP_SETUP_PROG: 6407 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6408 case XDP_SETUP_XSK_POOL: 6409 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6410 bpf->xsk.queue_id); 6411 default: 6412 return -EOPNOTSUPP; 6413 } 6414 } 6415 6416 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6417 struct xdp_frame **frames, u32 flags) 6418 { 6419 struct stmmac_priv *priv = netdev_priv(dev); 6420 int cpu = smp_processor_id(); 6421 struct netdev_queue *nq; 6422 int i, nxmit = 0; 6423 int queue; 6424 6425 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6426 return -ENETDOWN; 6427 6428 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6429 return -EINVAL; 6430 6431 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6432 nq = netdev_get_tx_queue(priv->dev, queue); 6433 6434 __netif_tx_lock(nq, cpu); 6435 /* Avoids TX time-out as we are sharing with slow path */ 6436 txq_trans_cond_update(nq); 6437 6438 for (i = 0; i < num_frames; i++) { 6439 int res; 6440 6441 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6442 if (res == STMMAC_XDP_CONSUMED) 6443 break; 6444 6445 nxmit++; 6446 } 6447 6448 if (flags & XDP_XMIT_FLUSH) { 6449 stmmac_flush_tx_descriptors(priv, queue); 6450 stmmac_tx_timer_arm(priv, queue); 6451 } 6452 6453 __netif_tx_unlock(nq); 6454 6455 return nxmit; 6456 } 6457 6458 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6459 { 6460 struct stmmac_channel *ch = &priv->channel[queue]; 6461 unsigned long flags; 6462 6463 spin_lock_irqsave(&ch->lock, flags); 6464 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6465 spin_unlock_irqrestore(&ch->lock, flags); 6466 6467 stmmac_stop_rx_dma(priv, queue); 6468 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6469 } 6470 6471 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6472 { 6473 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6474 struct stmmac_channel *ch = &priv->channel[queue]; 6475 unsigned long flags; 6476 u32 buf_size; 6477 int ret; 6478 6479 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6480 if (ret) { 6481 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6482 return; 6483 } 6484 6485 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6486 if (ret) { 6487 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6488 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6489 return; 6490 } 6491 6492 stmmac_reset_rx_queue(priv, queue); 6493 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6494 6495 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6496 rx_q->dma_rx_phy, rx_q->queue_index); 6497 6498 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6499 sizeof(struct dma_desc)); 6500 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6501 rx_q->rx_tail_addr, rx_q->queue_index); 6502 6503 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6504 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6505 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6506 buf_size, 6507 rx_q->queue_index); 6508 } else { 6509 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6510 priv->dma_conf.dma_buf_sz, 6511 rx_q->queue_index); 6512 } 6513 6514 stmmac_start_rx_dma(priv, queue); 6515 6516 spin_lock_irqsave(&ch->lock, flags); 6517 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6518 spin_unlock_irqrestore(&ch->lock, flags); 6519 } 6520 6521 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6522 { 6523 struct stmmac_channel *ch = &priv->channel[queue]; 6524 unsigned long flags; 6525 6526 spin_lock_irqsave(&ch->lock, flags); 6527 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6528 spin_unlock_irqrestore(&ch->lock, flags); 6529 6530 stmmac_stop_tx_dma(priv, queue); 6531 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6532 } 6533 6534 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6535 { 6536 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6537 struct stmmac_channel *ch = &priv->channel[queue]; 6538 unsigned long flags; 6539 int ret; 6540 6541 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6542 if (ret) { 6543 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6544 return; 6545 } 6546 6547 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6548 if (ret) { 6549 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6550 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6551 return; 6552 } 6553 6554 stmmac_reset_tx_queue(priv, queue); 6555 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6556 6557 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6558 tx_q->dma_tx_phy, tx_q->queue_index); 6559 6560 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6561 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6562 6563 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6564 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6565 tx_q->tx_tail_addr, tx_q->queue_index); 6566 6567 stmmac_start_tx_dma(priv, queue); 6568 6569 spin_lock_irqsave(&ch->lock, flags); 6570 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6571 spin_unlock_irqrestore(&ch->lock, flags); 6572 } 6573 6574 void stmmac_xdp_release(struct net_device *dev) 6575 { 6576 struct stmmac_priv *priv = netdev_priv(dev); 6577 u32 chan; 6578 6579 /* Ensure tx function is not running */ 6580 netif_tx_disable(dev); 6581 6582 /* Disable NAPI process */ 6583 stmmac_disable_all_queues(priv); 6584 6585 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6586 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6587 6588 /* Free the IRQ lines */ 6589 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6590 6591 /* Stop TX/RX DMA channels */ 6592 stmmac_stop_all_dma(priv); 6593 6594 /* Release and free the Rx/Tx resources */ 6595 free_dma_desc_resources(priv, &priv->dma_conf); 6596 6597 /* Disable the MAC Rx/Tx */ 6598 stmmac_mac_set(priv, priv->ioaddr, false); 6599 6600 /* set trans_start so we don't get spurious 6601 * watchdogs during reset 6602 */ 6603 netif_trans_update(dev); 6604 netif_carrier_off(dev); 6605 } 6606 6607 int stmmac_xdp_open(struct net_device *dev) 6608 { 6609 struct stmmac_priv *priv = netdev_priv(dev); 6610 u32 rx_cnt = priv->plat->rx_queues_to_use; 6611 u32 tx_cnt = priv->plat->tx_queues_to_use; 6612 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6613 struct stmmac_rx_queue *rx_q; 6614 struct stmmac_tx_queue *tx_q; 6615 u32 buf_size; 6616 bool sph_en; 6617 u32 chan; 6618 int ret; 6619 6620 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6621 if (ret < 0) { 6622 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6623 __func__); 6624 goto dma_desc_error; 6625 } 6626 6627 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6628 if (ret < 0) { 6629 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6630 __func__); 6631 goto init_error; 6632 } 6633 6634 stmmac_reset_queues_param(priv); 6635 6636 /* DMA CSR Channel configuration */ 6637 for (chan = 0; chan < dma_csr_ch; chan++) { 6638 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6639 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6640 } 6641 6642 /* Adjust Split header */ 6643 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6644 6645 /* DMA RX Channel Configuration */ 6646 for (chan = 0; chan < rx_cnt; chan++) { 6647 rx_q = &priv->dma_conf.rx_queue[chan]; 6648 6649 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6650 rx_q->dma_rx_phy, chan); 6651 6652 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6653 (rx_q->buf_alloc_num * 6654 sizeof(struct dma_desc)); 6655 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6656 rx_q->rx_tail_addr, chan); 6657 6658 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6659 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6660 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6661 buf_size, 6662 rx_q->queue_index); 6663 } else { 6664 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6665 priv->dma_conf.dma_buf_sz, 6666 rx_q->queue_index); 6667 } 6668 6669 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6670 } 6671 6672 /* DMA TX Channel Configuration */ 6673 for (chan = 0; chan < tx_cnt; chan++) { 6674 tx_q = &priv->dma_conf.tx_queue[chan]; 6675 6676 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6677 tx_q->dma_tx_phy, chan); 6678 6679 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6680 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6681 tx_q->tx_tail_addr, chan); 6682 6683 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6684 tx_q->txtimer.function = stmmac_tx_timer; 6685 } 6686 6687 /* Enable the MAC Rx/Tx */ 6688 stmmac_mac_set(priv, priv->ioaddr, true); 6689 6690 /* Start Rx & Tx DMA Channels */ 6691 stmmac_start_all_dma(priv); 6692 6693 ret = stmmac_request_irq(dev); 6694 if (ret) 6695 goto irq_error; 6696 6697 /* Enable NAPI process*/ 6698 stmmac_enable_all_queues(priv); 6699 netif_carrier_on(dev); 6700 netif_tx_start_all_queues(dev); 6701 stmmac_enable_all_dma_irq(priv); 6702 6703 return 0; 6704 6705 irq_error: 6706 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6707 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6708 6709 stmmac_hw_teardown(dev); 6710 init_error: 6711 free_dma_desc_resources(priv, &priv->dma_conf); 6712 dma_desc_error: 6713 return ret; 6714 } 6715 6716 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6717 { 6718 struct stmmac_priv *priv = netdev_priv(dev); 6719 struct stmmac_rx_queue *rx_q; 6720 struct stmmac_tx_queue *tx_q; 6721 struct stmmac_channel *ch; 6722 6723 if (test_bit(STMMAC_DOWN, &priv->state) || 6724 !netif_carrier_ok(priv->dev)) 6725 return -ENETDOWN; 6726 6727 if (!stmmac_xdp_is_enabled(priv)) 6728 return -EINVAL; 6729 6730 if (queue >= priv->plat->rx_queues_to_use || 6731 queue >= priv->plat->tx_queues_to_use) 6732 return -EINVAL; 6733 6734 rx_q = &priv->dma_conf.rx_queue[queue]; 6735 tx_q = &priv->dma_conf.tx_queue[queue]; 6736 ch = &priv->channel[queue]; 6737 6738 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6739 return -EINVAL; 6740 6741 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6742 /* EQoS does not have per-DMA channel SW interrupt, 6743 * so we schedule RX Napi straight-away. 6744 */ 6745 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6746 __napi_schedule(&ch->rxtx_napi); 6747 } 6748 6749 return 0; 6750 } 6751 6752 static const struct net_device_ops stmmac_netdev_ops = { 6753 .ndo_open = stmmac_open, 6754 .ndo_start_xmit = stmmac_xmit, 6755 .ndo_stop = stmmac_release, 6756 .ndo_change_mtu = stmmac_change_mtu, 6757 .ndo_fix_features = stmmac_fix_features, 6758 .ndo_set_features = stmmac_set_features, 6759 .ndo_set_rx_mode = stmmac_set_rx_mode, 6760 .ndo_tx_timeout = stmmac_tx_timeout, 6761 .ndo_eth_ioctl = stmmac_ioctl, 6762 .ndo_setup_tc = stmmac_setup_tc, 6763 .ndo_select_queue = stmmac_select_queue, 6764 #ifdef CONFIG_NET_POLL_CONTROLLER 6765 .ndo_poll_controller = stmmac_poll_controller, 6766 #endif 6767 .ndo_set_mac_address = stmmac_set_mac_address, 6768 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6769 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6770 .ndo_bpf = stmmac_bpf, 6771 .ndo_xdp_xmit = stmmac_xdp_xmit, 6772 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6773 }; 6774 6775 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6776 { 6777 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6778 return; 6779 if (test_bit(STMMAC_DOWN, &priv->state)) 6780 return; 6781 6782 netdev_err(priv->dev, "Reset adapter.\n"); 6783 6784 rtnl_lock(); 6785 netif_trans_update(priv->dev); 6786 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6787 usleep_range(1000, 2000); 6788 6789 set_bit(STMMAC_DOWN, &priv->state); 6790 dev_close(priv->dev); 6791 dev_open(priv->dev, NULL); 6792 clear_bit(STMMAC_DOWN, &priv->state); 6793 clear_bit(STMMAC_RESETING, &priv->state); 6794 rtnl_unlock(); 6795 } 6796 6797 static void stmmac_service_task(struct work_struct *work) 6798 { 6799 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6800 service_task); 6801 6802 stmmac_reset_subtask(priv); 6803 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6804 } 6805 6806 /** 6807 * stmmac_hw_init - Init the MAC device 6808 * @priv: driver private structure 6809 * Description: this function is to configure the MAC device according to 6810 * some platform parameters or the HW capability register. It prepares the 6811 * driver to use either ring or chain modes and to setup either enhanced or 6812 * normal descriptors. 6813 */ 6814 static int stmmac_hw_init(struct stmmac_priv *priv) 6815 { 6816 int ret; 6817 6818 /* dwmac-sun8i only work in chain mode */ 6819 if (priv->plat->has_sun8i) 6820 chain_mode = 1; 6821 priv->chain_mode = chain_mode; 6822 6823 /* Initialize HW Interface */ 6824 ret = stmmac_hwif_init(priv); 6825 if (ret) 6826 return ret; 6827 6828 /* Get the HW capability (new GMAC newer than 3.50a) */ 6829 priv->hw_cap_support = stmmac_get_hw_features(priv); 6830 if (priv->hw_cap_support) { 6831 dev_info(priv->device, "DMA HW capability register supported\n"); 6832 6833 /* We can override some gmac/dma configuration fields: e.g. 6834 * enh_desc, tx_coe (e.g. that are passed through the 6835 * platform) with the values from the HW capability 6836 * register (if supported). 6837 */ 6838 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6839 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6840 !priv->plat->use_phy_wol; 6841 priv->hw->pmt = priv->plat->pmt; 6842 if (priv->dma_cap.hash_tb_sz) { 6843 priv->hw->multicast_filter_bins = 6844 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6845 priv->hw->mcast_bits_log2 = 6846 ilog2(priv->hw->multicast_filter_bins); 6847 } 6848 6849 /* TXCOE doesn't work in thresh DMA mode */ 6850 if (priv->plat->force_thresh_dma_mode) 6851 priv->plat->tx_coe = 0; 6852 else 6853 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6854 6855 /* In case of GMAC4 rx_coe is from HW cap register. */ 6856 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6857 6858 if (priv->dma_cap.rx_coe_type2) 6859 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6860 else if (priv->dma_cap.rx_coe_type1) 6861 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6862 6863 } else { 6864 dev_info(priv->device, "No HW DMA feature register supported\n"); 6865 } 6866 6867 if (priv->plat->rx_coe) { 6868 priv->hw->rx_csum = priv->plat->rx_coe; 6869 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6870 if (priv->synopsys_id < DWMAC_CORE_4_00) 6871 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6872 } 6873 if (priv->plat->tx_coe) 6874 dev_info(priv->device, "TX Checksum insertion supported\n"); 6875 6876 if (priv->plat->pmt) { 6877 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6878 device_set_wakeup_capable(priv->device, 1); 6879 } 6880 6881 if (priv->dma_cap.tsoen) 6882 dev_info(priv->device, "TSO supported\n"); 6883 6884 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6885 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6886 6887 /* Run HW quirks, if any */ 6888 if (priv->hwif_quirks) { 6889 ret = priv->hwif_quirks(priv); 6890 if (ret) 6891 return ret; 6892 } 6893 6894 /* Rx Watchdog is available in the COREs newer than the 3.40. 6895 * In some case, for example on bugged HW this feature 6896 * has to be disable and this can be done by passing the 6897 * riwt_off field from the platform. 6898 */ 6899 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6900 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6901 priv->use_riwt = 1; 6902 dev_info(priv->device, 6903 "Enable RX Mitigation via HW Watchdog Timer\n"); 6904 } 6905 6906 return 0; 6907 } 6908 6909 static void stmmac_napi_add(struct net_device *dev) 6910 { 6911 struct stmmac_priv *priv = netdev_priv(dev); 6912 u32 queue, maxq; 6913 6914 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6915 6916 for (queue = 0; queue < maxq; queue++) { 6917 struct stmmac_channel *ch = &priv->channel[queue]; 6918 6919 ch->priv_data = priv; 6920 ch->index = queue; 6921 spin_lock_init(&ch->lock); 6922 6923 if (queue < priv->plat->rx_queues_to_use) { 6924 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 6925 } 6926 if (queue < priv->plat->tx_queues_to_use) { 6927 netif_napi_add_tx(dev, &ch->tx_napi, 6928 stmmac_napi_poll_tx); 6929 } 6930 if (queue < priv->plat->rx_queues_to_use && 6931 queue < priv->plat->tx_queues_to_use) { 6932 netif_napi_add(dev, &ch->rxtx_napi, 6933 stmmac_napi_poll_rxtx); 6934 } 6935 } 6936 } 6937 6938 static void stmmac_napi_del(struct net_device *dev) 6939 { 6940 struct stmmac_priv *priv = netdev_priv(dev); 6941 u32 queue, maxq; 6942 6943 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6944 6945 for (queue = 0; queue < maxq; queue++) { 6946 struct stmmac_channel *ch = &priv->channel[queue]; 6947 6948 if (queue < priv->plat->rx_queues_to_use) 6949 netif_napi_del(&ch->rx_napi); 6950 if (queue < priv->plat->tx_queues_to_use) 6951 netif_napi_del(&ch->tx_napi); 6952 if (queue < priv->plat->rx_queues_to_use && 6953 queue < priv->plat->tx_queues_to_use) { 6954 netif_napi_del(&ch->rxtx_napi); 6955 } 6956 } 6957 } 6958 6959 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6960 { 6961 struct stmmac_priv *priv = netdev_priv(dev); 6962 int ret = 0, i; 6963 6964 if (netif_running(dev)) 6965 stmmac_release(dev); 6966 6967 stmmac_napi_del(dev); 6968 6969 priv->plat->rx_queues_to_use = rx_cnt; 6970 priv->plat->tx_queues_to_use = tx_cnt; 6971 if (!netif_is_rxfh_configured(dev)) 6972 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 6973 priv->rss.table[i] = ethtool_rxfh_indir_default(i, 6974 rx_cnt); 6975 6976 stmmac_napi_add(dev); 6977 6978 if (netif_running(dev)) 6979 ret = stmmac_open(dev); 6980 6981 return ret; 6982 } 6983 6984 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6985 { 6986 struct stmmac_priv *priv = netdev_priv(dev); 6987 int ret = 0; 6988 6989 if (netif_running(dev)) 6990 stmmac_release(dev); 6991 6992 priv->dma_conf.dma_rx_size = rx_size; 6993 priv->dma_conf.dma_tx_size = tx_size; 6994 6995 if (netif_running(dev)) 6996 ret = stmmac_open(dev); 6997 6998 return ret; 6999 } 7000 7001 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 7002 static void stmmac_fpe_lp_task(struct work_struct *work) 7003 { 7004 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 7005 fpe_task); 7006 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 7007 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 7008 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 7009 bool *hs_enable = &fpe_cfg->hs_enable; 7010 bool *enable = &fpe_cfg->enable; 7011 int retries = 20; 7012 7013 while (retries-- > 0) { 7014 /* Bail out immediately if FPE handshake is OFF */ 7015 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 7016 break; 7017 7018 if (*lo_state == FPE_STATE_ENTERING_ON && 7019 *lp_state == FPE_STATE_ENTERING_ON) { 7020 stmmac_fpe_configure(priv, priv->ioaddr, 7021 priv->plat->tx_queues_to_use, 7022 priv->plat->rx_queues_to_use, 7023 *enable); 7024 7025 netdev_info(priv->dev, "configured FPE\n"); 7026 7027 *lo_state = FPE_STATE_ON; 7028 *lp_state = FPE_STATE_ON; 7029 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7030 break; 7031 } 7032 7033 if ((*lo_state == FPE_STATE_CAPABLE || 7034 *lo_state == FPE_STATE_ENTERING_ON) && 7035 *lp_state != FPE_STATE_ON) { 7036 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7037 *lo_state, *lp_state); 7038 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7039 MPACKET_VERIFY); 7040 } 7041 /* Sleep then retry */ 7042 msleep(500); 7043 } 7044 7045 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7046 } 7047 7048 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7049 { 7050 if (priv->plat->fpe_cfg->hs_enable != enable) { 7051 if (enable) { 7052 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7053 MPACKET_VERIFY); 7054 } else { 7055 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7056 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7057 } 7058 7059 priv->plat->fpe_cfg->hs_enable = enable; 7060 } 7061 } 7062 7063 /** 7064 * stmmac_dvr_probe 7065 * @device: device pointer 7066 * @plat_dat: platform data pointer 7067 * @res: stmmac resource pointer 7068 * Description: this is the main probe function used to 7069 * call the alloc_etherdev, allocate the priv structure. 7070 * Return: 7071 * returns 0 on success, otherwise errno. 7072 */ 7073 int stmmac_dvr_probe(struct device *device, 7074 struct plat_stmmacenet_data *plat_dat, 7075 struct stmmac_resources *res) 7076 { 7077 struct net_device *ndev = NULL; 7078 struct stmmac_priv *priv; 7079 u32 rxq; 7080 int i, ret = 0; 7081 7082 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7083 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7084 if (!ndev) 7085 return -ENOMEM; 7086 7087 SET_NETDEV_DEV(ndev, device); 7088 7089 priv = netdev_priv(ndev); 7090 priv->device = device; 7091 priv->dev = ndev; 7092 7093 stmmac_set_ethtool_ops(ndev); 7094 priv->pause = pause; 7095 priv->plat = plat_dat; 7096 priv->ioaddr = res->addr; 7097 priv->dev->base_addr = (unsigned long)res->addr; 7098 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7099 7100 priv->dev->irq = res->irq; 7101 priv->wol_irq = res->wol_irq; 7102 priv->lpi_irq = res->lpi_irq; 7103 priv->sfty_ce_irq = res->sfty_ce_irq; 7104 priv->sfty_ue_irq = res->sfty_ue_irq; 7105 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7106 priv->rx_irq[i] = res->rx_irq[i]; 7107 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7108 priv->tx_irq[i] = res->tx_irq[i]; 7109 7110 if (!is_zero_ether_addr(res->mac)) 7111 eth_hw_addr_set(priv->dev, res->mac); 7112 7113 dev_set_drvdata(device, priv->dev); 7114 7115 /* Verify driver arguments */ 7116 stmmac_verify_args(); 7117 7118 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7119 if (!priv->af_xdp_zc_qps) 7120 return -ENOMEM; 7121 7122 /* Allocate workqueue */ 7123 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7124 if (!priv->wq) { 7125 dev_err(priv->device, "failed to create workqueue\n"); 7126 ret = -ENOMEM; 7127 goto error_wq_init; 7128 } 7129 7130 INIT_WORK(&priv->service_task, stmmac_service_task); 7131 7132 /* Initialize Link Partner FPE workqueue */ 7133 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7134 7135 /* Override with kernel parameters if supplied XXX CRS XXX 7136 * this needs to have multiple instances 7137 */ 7138 if ((phyaddr >= 0) && (phyaddr <= 31)) 7139 priv->plat->phy_addr = phyaddr; 7140 7141 if (priv->plat->stmmac_rst) { 7142 ret = reset_control_assert(priv->plat->stmmac_rst); 7143 reset_control_deassert(priv->plat->stmmac_rst); 7144 /* Some reset controllers have only reset callback instead of 7145 * assert + deassert callbacks pair. 7146 */ 7147 if (ret == -ENOTSUPP) 7148 reset_control_reset(priv->plat->stmmac_rst); 7149 } 7150 7151 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7152 if (ret == -ENOTSUPP) 7153 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7154 ERR_PTR(ret)); 7155 7156 /* Init MAC and get the capabilities */ 7157 ret = stmmac_hw_init(priv); 7158 if (ret) 7159 goto error_hw_init; 7160 7161 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7162 */ 7163 if (priv->synopsys_id < DWMAC_CORE_5_20) 7164 priv->plat->dma_cfg->dche = false; 7165 7166 stmmac_check_ether_addr(priv); 7167 7168 ndev->netdev_ops = &stmmac_netdev_ops; 7169 7170 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7171 NETIF_F_RXCSUM; 7172 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 7173 NETDEV_XDP_ACT_XSK_ZEROCOPY | 7174 NETDEV_XDP_ACT_NDO_XMIT; 7175 7176 ret = stmmac_tc_init(priv, priv); 7177 if (!ret) { 7178 ndev->hw_features |= NETIF_F_HW_TC; 7179 } 7180 7181 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7182 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7183 if (priv->plat->has_gmac4) 7184 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7185 priv->tso = true; 7186 dev_info(priv->device, "TSO feature enabled\n"); 7187 } 7188 7189 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7190 ndev->hw_features |= NETIF_F_GRO; 7191 priv->sph_cap = true; 7192 priv->sph = priv->sph_cap; 7193 dev_info(priv->device, "SPH feature enabled\n"); 7194 } 7195 7196 /* Ideally our host DMA address width is the same as for the 7197 * device. However, it may differ and then we have to use our 7198 * host DMA width for allocation and the device DMA width for 7199 * register handling. 7200 */ 7201 if (priv->plat->host_dma_width) 7202 priv->dma_cap.host_dma_width = priv->plat->host_dma_width; 7203 else 7204 priv->dma_cap.host_dma_width = priv->dma_cap.addr64; 7205 7206 if (priv->dma_cap.host_dma_width) { 7207 ret = dma_set_mask_and_coherent(device, 7208 DMA_BIT_MASK(priv->dma_cap.host_dma_width)); 7209 if (!ret) { 7210 dev_info(priv->device, "Using %d/%d bits DMA host/device width\n", 7211 priv->dma_cap.host_dma_width, priv->dma_cap.addr64); 7212 7213 /* 7214 * If more than 32 bits can be addressed, make sure to 7215 * enable enhanced addressing mode. 7216 */ 7217 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7218 priv->plat->dma_cfg->eame = true; 7219 } else { 7220 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7221 if (ret) { 7222 dev_err(priv->device, "Failed to set DMA Mask\n"); 7223 goto error_hw_init; 7224 } 7225 7226 priv->dma_cap.host_dma_width = 32; 7227 } 7228 } 7229 7230 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7231 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7232 #ifdef STMMAC_VLAN_TAG_USED 7233 /* Both mac100 and gmac support receive VLAN tag detection */ 7234 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7235 if (priv->dma_cap.vlhash) { 7236 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7237 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7238 } 7239 if (priv->dma_cap.vlins) { 7240 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7241 if (priv->dma_cap.dvlan) 7242 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7243 } 7244 #endif 7245 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7246 7247 /* Initialize RSS */ 7248 rxq = priv->plat->rx_queues_to_use; 7249 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7250 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7251 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7252 7253 if (priv->dma_cap.rssen && priv->plat->rss_en) 7254 ndev->features |= NETIF_F_RXHASH; 7255 7256 /* MTU range: 46 - hw-specific max */ 7257 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7258 if (priv->plat->has_xgmac) 7259 ndev->max_mtu = XGMAC_JUMBO_LEN; 7260 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7261 ndev->max_mtu = JUMBO_LEN; 7262 else 7263 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7264 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7265 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7266 */ 7267 if ((priv->plat->maxmtu < ndev->max_mtu) && 7268 (priv->plat->maxmtu >= ndev->min_mtu)) 7269 ndev->max_mtu = priv->plat->maxmtu; 7270 else if (priv->plat->maxmtu < ndev->min_mtu) 7271 dev_warn(priv->device, 7272 "%s: warning: maxmtu having invalid value (%d)\n", 7273 __func__, priv->plat->maxmtu); 7274 7275 if (flow_ctrl) 7276 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7277 7278 /* Setup channels NAPI */ 7279 stmmac_napi_add(ndev); 7280 7281 mutex_init(&priv->lock); 7282 7283 /* If a specific clk_csr value is passed from the platform 7284 * this means that the CSR Clock Range selection cannot be 7285 * changed at run-time and it is fixed. Viceversa the driver'll try to 7286 * set the MDC clock dynamically according to the csr actual 7287 * clock input. 7288 */ 7289 if (priv->plat->clk_csr >= 0) 7290 priv->clk_csr = priv->plat->clk_csr; 7291 else 7292 stmmac_clk_csr_set(priv); 7293 7294 stmmac_check_pcs_mode(priv); 7295 7296 pm_runtime_get_noresume(device); 7297 pm_runtime_set_active(device); 7298 if (!pm_runtime_enabled(device)) 7299 pm_runtime_enable(device); 7300 7301 if (priv->hw->pcs != STMMAC_PCS_TBI && 7302 priv->hw->pcs != STMMAC_PCS_RTBI) { 7303 /* MDIO bus Registration */ 7304 ret = stmmac_mdio_register(ndev); 7305 if (ret < 0) { 7306 dev_err_probe(priv->device, ret, 7307 "%s: MDIO bus (id: %d) registration failed\n", 7308 __func__, priv->plat->bus_id); 7309 goto error_mdio_register; 7310 } 7311 } 7312 7313 if (priv->plat->speed_mode_2500) 7314 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7315 7316 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7317 ret = stmmac_xpcs_setup(priv->mii); 7318 if (ret) 7319 goto error_xpcs_setup; 7320 } 7321 7322 ret = stmmac_phy_setup(priv); 7323 if (ret) { 7324 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7325 goto error_phy_setup; 7326 } 7327 7328 ret = register_netdev(ndev); 7329 if (ret) { 7330 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7331 __func__, ret); 7332 goto error_netdev_register; 7333 } 7334 7335 #ifdef CONFIG_DEBUG_FS 7336 stmmac_init_fs(ndev); 7337 #endif 7338 7339 if (priv->plat->dump_debug_regs) 7340 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7341 7342 /* Let pm_runtime_put() disable the clocks. 7343 * If CONFIG_PM is not enabled, the clocks will stay powered. 7344 */ 7345 pm_runtime_put(device); 7346 7347 return ret; 7348 7349 error_netdev_register: 7350 phylink_destroy(priv->phylink); 7351 error_xpcs_setup: 7352 error_phy_setup: 7353 if (priv->hw->pcs != STMMAC_PCS_TBI && 7354 priv->hw->pcs != STMMAC_PCS_RTBI) 7355 stmmac_mdio_unregister(ndev); 7356 error_mdio_register: 7357 stmmac_napi_del(ndev); 7358 error_hw_init: 7359 destroy_workqueue(priv->wq); 7360 error_wq_init: 7361 bitmap_free(priv->af_xdp_zc_qps); 7362 7363 return ret; 7364 } 7365 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7366 7367 /** 7368 * stmmac_dvr_remove 7369 * @dev: device pointer 7370 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7371 * changes the link status, releases the DMA descriptor rings. 7372 */ 7373 void stmmac_dvr_remove(struct device *dev) 7374 { 7375 struct net_device *ndev = dev_get_drvdata(dev); 7376 struct stmmac_priv *priv = netdev_priv(ndev); 7377 7378 netdev_info(priv->dev, "%s: removing driver", __func__); 7379 7380 pm_runtime_get_sync(dev); 7381 7382 stmmac_stop_all_dma(priv); 7383 stmmac_mac_set(priv, priv->ioaddr, false); 7384 netif_carrier_off(ndev); 7385 unregister_netdev(ndev); 7386 7387 /* Serdes power down needs to happen after VLAN filter 7388 * is deleted that is triggered by unregister_netdev(). 7389 */ 7390 if (priv->plat->serdes_powerdown) 7391 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7392 7393 #ifdef CONFIG_DEBUG_FS 7394 stmmac_exit_fs(ndev); 7395 #endif 7396 phylink_destroy(priv->phylink); 7397 if (priv->plat->stmmac_rst) 7398 reset_control_assert(priv->plat->stmmac_rst); 7399 reset_control_assert(priv->plat->stmmac_ahb_rst); 7400 if (priv->hw->pcs != STMMAC_PCS_TBI && 7401 priv->hw->pcs != STMMAC_PCS_RTBI) 7402 stmmac_mdio_unregister(ndev); 7403 destroy_workqueue(priv->wq); 7404 mutex_destroy(&priv->lock); 7405 bitmap_free(priv->af_xdp_zc_qps); 7406 7407 pm_runtime_disable(dev); 7408 pm_runtime_put_noidle(dev); 7409 } 7410 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7411 7412 /** 7413 * stmmac_suspend - suspend callback 7414 * @dev: device pointer 7415 * Description: this is the function to suspend the device and it is called 7416 * by the platform driver to stop the network queue, release the resources, 7417 * program the PMT register (for WoL), clean and release driver resources. 7418 */ 7419 int stmmac_suspend(struct device *dev) 7420 { 7421 struct net_device *ndev = dev_get_drvdata(dev); 7422 struct stmmac_priv *priv = netdev_priv(ndev); 7423 u32 chan; 7424 7425 if (!ndev || !netif_running(ndev)) 7426 return 0; 7427 7428 mutex_lock(&priv->lock); 7429 7430 netif_device_detach(ndev); 7431 7432 stmmac_disable_all_queues(priv); 7433 7434 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7435 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7436 7437 if (priv->eee_enabled) { 7438 priv->tx_path_in_lpi_mode = false; 7439 del_timer_sync(&priv->eee_ctrl_timer); 7440 } 7441 7442 /* Stop TX/RX DMA */ 7443 stmmac_stop_all_dma(priv); 7444 7445 if (priv->plat->serdes_powerdown) 7446 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7447 7448 /* Enable Power down mode by programming the PMT regs */ 7449 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7450 stmmac_pmt(priv, priv->hw, priv->wolopts); 7451 priv->irq_wake = 1; 7452 } else { 7453 stmmac_mac_set(priv, priv->ioaddr, false); 7454 pinctrl_pm_select_sleep_state(priv->device); 7455 } 7456 7457 mutex_unlock(&priv->lock); 7458 7459 rtnl_lock(); 7460 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7461 phylink_suspend(priv->phylink, true); 7462 } else { 7463 if (device_may_wakeup(priv->device)) 7464 phylink_speed_down(priv->phylink, false); 7465 phylink_suspend(priv->phylink, false); 7466 } 7467 rtnl_unlock(); 7468 7469 if (priv->dma_cap.fpesel) { 7470 /* Disable FPE */ 7471 stmmac_fpe_configure(priv, priv->ioaddr, 7472 priv->plat->tx_queues_to_use, 7473 priv->plat->rx_queues_to_use, false); 7474 7475 stmmac_fpe_handshake(priv, false); 7476 stmmac_fpe_stop_wq(priv); 7477 } 7478 7479 priv->speed = SPEED_UNKNOWN; 7480 return 0; 7481 } 7482 EXPORT_SYMBOL_GPL(stmmac_suspend); 7483 7484 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7485 { 7486 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7487 7488 rx_q->cur_rx = 0; 7489 rx_q->dirty_rx = 0; 7490 } 7491 7492 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7493 { 7494 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7495 7496 tx_q->cur_tx = 0; 7497 tx_q->dirty_tx = 0; 7498 tx_q->mss = 0; 7499 7500 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7501 } 7502 7503 /** 7504 * stmmac_reset_queues_param - reset queue parameters 7505 * @priv: device pointer 7506 */ 7507 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7508 { 7509 u32 rx_cnt = priv->plat->rx_queues_to_use; 7510 u32 tx_cnt = priv->plat->tx_queues_to_use; 7511 u32 queue; 7512 7513 for (queue = 0; queue < rx_cnt; queue++) 7514 stmmac_reset_rx_queue(priv, queue); 7515 7516 for (queue = 0; queue < tx_cnt; queue++) 7517 stmmac_reset_tx_queue(priv, queue); 7518 } 7519 7520 /** 7521 * stmmac_resume - resume callback 7522 * @dev: device pointer 7523 * Description: when resume this function is invoked to setup the DMA and CORE 7524 * in a usable state. 7525 */ 7526 int stmmac_resume(struct device *dev) 7527 { 7528 struct net_device *ndev = dev_get_drvdata(dev); 7529 struct stmmac_priv *priv = netdev_priv(ndev); 7530 int ret; 7531 7532 if (!netif_running(ndev)) 7533 return 0; 7534 7535 /* Power Down bit, into the PM register, is cleared 7536 * automatically as soon as a magic packet or a Wake-up frame 7537 * is received. Anyway, it's better to manually clear 7538 * this bit because it can generate problems while resuming 7539 * from another devices (e.g. serial console). 7540 */ 7541 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7542 mutex_lock(&priv->lock); 7543 stmmac_pmt(priv, priv->hw, 0); 7544 mutex_unlock(&priv->lock); 7545 priv->irq_wake = 0; 7546 } else { 7547 pinctrl_pm_select_default_state(priv->device); 7548 /* reset the phy so that it's ready */ 7549 if (priv->mii) 7550 stmmac_mdio_reset(priv->mii); 7551 } 7552 7553 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 7554 ret = priv->plat->serdes_powerup(ndev, 7555 priv->plat->bsp_priv); 7556 7557 if (ret < 0) 7558 return ret; 7559 } 7560 7561 rtnl_lock(); 7562 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7563 phylink_resume(priv->phylink); 7564 } else { 7565 phylink_resume(priv->phylink); 7566 if (device_may_wakeup(priv->device)) 7567 phylink_speed_up(priv->phylink); 7568 } 7569 rtnl_unlock(); 7570 7571 rtnl_lock(); 7572 mutex_lock(&priv->lock); 7573 7574 stmmac_reset_queues_param(priv); 7575 7576 stmmac_free_tx_skbufs(priv); 7577 stmmac_clear_descriptors(priv, &priv->dma_conf); 7578 7579 stmmac_hw_setup(ndev, false); 7580 stmmac_init_coalesce(priv); 7581 stmmac_set_rx_mode(ndev); 7582 7583 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7584 7585 stmmac_enable_all_queues(priv); 7586 stmmac_enable_all_dma_irq(priv); 7587 7588 mutex_unlock(&priv->lock); 7589 rtnl_unlock(); 7590 7591 netif_device_attach(ndev); 7592 7593 return 0; 7594 } 7595 EXPORT_SYMBOL_GPL(stmmac_resume); 7596 7597 #ifndef MODULE 7598 static int __init stmmac_cmdline_opt(char *str) 7599 { 7600 char *opt; 7601 7602 if (!str || !*str) 7603 return 1; 7604 while ((opt = strsep(&str, ",")) != NULL) { 7605 if (!strncmp(opt, "debug:", 6)) { 7606 if (kstrtoint(opt + 6, 0, &debug)) 7607 goto err; 7608 } else if (!strncmp(opt, "phyaddr:", 8)) { 7609 if (kstrtoint(opt + 8, 0, &phyaddr)) 7610 goto err; 7611 } else if (!strncmp(opt, "buf_sz:", 7)) { 7612 if (kstrtoint(opt + 7, 0, &buf_sz)) 7613 goto err; 7614 } else if (!strncmp(opt, "tc:", 3)) { 7615 if (kstrtoint(opt + 3, 0, &tc)) 7616 goto err; 7617 } else if (!strncmp(opt, "watchdog:", 9)) { 7618 if (kstrtoint(opt + 9, 0, &watchdog)) 7619 goto err; 7620 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7621 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7622 goto err; 7623 } else if (!strncmp(opt, "pause:", 6)) { 7624 if (kstrtoint(opt + 6, 0, &pause)) 7625 goto err; 7626 } else if (!strncmp(opt, "eee_timer:", 10)) { 7627 if (kstrtoint(opt + 10, 0, &eee_timer)) 7628 goto err; 7629 } else if (!strncmp(opt, "chain_mode:", 11)) { 7630 if (kstrtoint(opt + 11, 0, &chain_mode)) 7631 goto err; 7632 } 7633 } 7634 return 1; 7635 7636 err: 7637 pr_err("%s: ERROR broken module parameter conversion", __func__); 7638 return 1; 7639 } 7640 7641 __setup("stmmaceth=", stmmac_cmdline_opt); 7642 #endif /* MODULE */ 7643 7644 static int __init stmmac_init(void) 7645 { 7646 #ifdef CONFIG_DEBUG_FS 7647 /* Create debugfs main directory if it doesn't exist yet */ 7648 if (!stmmac_fs_dir) 7649 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7650 register_netdevice_notifier(&stmmac_notifier); 7651 #endif 7652 7653 return 0; 7654 } 7655 7656 static void __exit stmmac_exit(void) 7657 { 7658 #ifdef CONFIG_DEBUG_FS 7659 unregister_netdevice_notifier(&stmmac_notifier); 7660 debugfs_remove_recursive(stmmac_fs_dir); 7661 #endif 7662 } 7663 7664 module_init(stmmac_init) 7665 module_exit(stmmac_exit) 7666 7667 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7668 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7669 MODULE_LICENSE("GPL"); 7670