1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 67 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 /** 180 * stmmac_stop_all_queues - Stop all queues 181 * @priv: driver private structure 182 */ 183 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 184 { 185 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 186 u32 queue; 187 188 for (queue = 0; queue < tx_queues_cnt; queue++) 189 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 190 } 191 192 /** 193 * stmmac_start_all_queues - Start all queues 194 * @priv: driver private structure 195 */ 196 static void stmmac_start_all_queues(struct stmmac_priv *priv) 197 { 198 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 199 u32 queue; 200 201 for (queue = 0; queue < tx_queues_cnt; queue++) 202 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 203 } 204 205 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 206 { 207 if (!test_bit(STMMAC_DOWN, &priv->state) && 208 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 209 queue_work(priv->wq, &priv->service_task); 210 } 211 212 static void stmmac_global_err(struct stmmac_priv *priv) 213 { 214 netif_carrier_off(priv->dev); 215 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 216 stmmac_service_event_schedule(priv); 217 } 218 219 /** 220 * stmmac_clk_csr_set - dynamically set the MDC clock 221 * @priv: driver private structure 222 * Description: this is to dynamically set the MDC clock according to the csr 223 * clock input. 224 * Note: 225 * If a specific clk_csr value is passed from the platform 226 * this means that the CSR Clock Range selection cannot be 227 * changed at run-time and it is fixed (as reported in the driver 228 * documentation). Viceversa the driver will try to set the MDC 229 * clock dynamically according to the actual clock input. 230 */ 231 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 232 { 233 u32 clk_rate; 234 235 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 236 237 /* Platform provided default clk_csr would be assumed valid 238 * for all other cases except for the below mentioned ones. 239 * For values higher than the IEEE 802.3 specified frequency 240 * we can not estimate the proper divider as it is not known 241 * the frequency of clk_csr_i. So we do not change the default 242 * divider. 243 */ 244 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 245 if (clk_rate < CSR_F_35M) 246 priv->clk_csr = STMMAC_CSR_20_35M; 247 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 248 priv->clk_csr = STMMAC_CSR_35_60M; 249 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 250 priv->clk_csr = STMMAC_CSR_60_100M; 251 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 252 priv->clk_csr = STMMAC_CSR_100_150M; 253 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 254 priv->clk_csr = STMMAC_CSR_150_250M; 255 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 256 priv->clk_csr = STMMAC_CSR_250_300M; 257 } 258 259 if (priv->plat->has_sun8i) { 260 if (clk_rate > 160000000) 261 priv->clk_csr = 0x03; 262 else if (clk_rate > 80000000) 263 priv->clk_csr = 0x02; 264 else if (clk_rate > 40000000) 265 priv->clk_csr = 0x01; 266 else 267 priv->clk_csr = 0; 268 } 269 270 if (priv->plat->has_xgmac) { 271 if (clk_rate > 400000000) 272 priv->clk_csr = 0x5; 273 else if (clk_rate > 350000000) 274 priv->clk_csr = 0x4; 275 else if (clk_rate > 300000000) 276 priv->clk_csr = 0x3; 277 else if (clk_rate > 250000000) 278 priv->clk_csr = 0x2; 279 else if (clk_rate > 150000000) 280 priv->clk_csr = 0x1; 281 else 282 priv->clk_csr = 0x0; 283 } 284 } 285 286 static void print_pkt(unsigned char *buf, int len) 287 { 288 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 289 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 290 } 291 292 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 293 { 294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 295 u32 avail; 296 297 if (tx_q->dirty_tx > tx_q->cur_tx) 298 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 299 else 300 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 301 302 return avail; 303 } 304 305 /** 306 * stmmac_rx_dirty - Get RX queue dirty 307 * @priv: driver private structure 308 * @queue: RX queue index 309 */ 310 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 311 { 312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 313 u32 dirty; 314 315 if (rx_q->dirty_rx <= rx_q->cur_rx) 316 dirty = rx_q->cur_rx - rx_q->dirty_rx; 317 else 318 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 319 320 return dirty; 321 } 322 323 /** 324 * stmmac_enable_eee_mode - check and enter in LPI mode 325 * @priv: driver private structure 326 * Description: this function is to verify and enter in LPI mode in case of 327 * EEE. 328 */ 329 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 330 { 331 u32 tx_cnt = priv->plat->tx_queues_to_use; 332 u32 queue; 333 334 /* check if all TX queues have the work finished */ 335 for (queue = 0; queue < tx_cnt; queue++) { 336 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 337 338 if (tx_q->dirty_tx != tx_q->cur_tx) 339 return; /* still unfinished work */ 340 } 341 342 /* Check and enter in LPI mode */ 343 if (!priv->tx_path_in_lpi_mode) 344 stmmac_set_eee_mode(priv, priv->hw, 345 priv->plat->en_tx_lpi_clockgating); 346 } 347 348 /** 349 * stmmac_disable_eee_mode - disable and exit from LPI mode 350 * @priv: driver private structure 351 * Description: this function is to exit and disable EEE in case of 352 * LPI state is true. This is called by the xmit. 353 */ 354 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 355 { 356 stmmac_reset_eee_mode(priv, priv->hw); 357 del_timer_sync(&priv->eee_ctrl_timer); 358 priv->tx_path_in_lpi_mode = false; 359 } 360 361 /** 362 * stmmac_eee_ctrl_timer - EEE TX SW timer. 363 * @arg : data hook 364 * Description: 365 * if there is no data transfer and if we are not in LPI state, 366 * then MAC Transmitter can be moved to LPI state. 367 */ 368 static void stmmac_eee_ctrl_timer(struct timer_list *t) 369 { 370 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 371 372 stmmac_enable_eee_mode(priv); 373 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 374 } 375 376 /** 377 * stmmac_eee_init - init EEE 378 * @priv: driver private structure 379 * Description: 380 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 381 * can also manage EEE, this function enable the LPI state and start related 382 * timer. 383 */ 384 bool stmmac_eee_init(struct stmmac_priv *priv) 385 { 386 int tx_lpi_timer = priv->tx_lpi_timer; 387 388 /* Using PCS we cannot dial with the phy registers at this stage 389 * so we do not support extra feature like EEE. 390 */ 391 if (priv->hw->pcs == STMMAC_PCS_TBI || 392 priv->hw->pcs == STMMAC_PCS_RTBI) 393 return false; 394 395 /* Check if MAC core supports the EEE feature. */ 396 if (!priv->dma_cap.eee) 397 return false; 398 399 mutex_lock(&priv->lock); 400 401 /* Check if it needs to be deactivated */ 402 if (!priv->eee_active) { 403 if (priv->eee_enabled) { 404 netdev_dbg(priv->dev, "disable EEE\n"); 405 del_timer_sync(&priv->eee_ctrl_timer); 406 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 407 } 408 mutex_unlock(&priv->lock); 409 return false; 410 } 411 412 if (priv->eee_active && !priv->eee_enabled) { 413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 414 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 415 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 416 tx_lpi_timer); 417 } 418 419 mutex_unlock(&priv->lock); 420 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 421 return true; 422 } 423 424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 425 * @priv: driver private structure 426 * @p : descriptor pointer 427 * @skb : the socket buffer 428 * Description : 429 * This function will read timestamp from the descriptor & pass it to stack. 430 * and also perform some sanity checks. 431 */ 432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 433 struct dma_desc *p, struct sk_buff *skb) 434 { 435 struct skb_shared_hwtstamps shhwtstamp; 436 bool found = false; 437 u64 ns = 0; 438 439 if (!priv->hwts_tx_en) 440 return; 441 442 /* exit if skb doesn't support hw tstamp */ 443 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 444 return; 445 446 /* check tx tstamp status */ 447 if (stmmac_get_tx_timestamp_status(priv, p)) { 448 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 449 found = true; 450 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 451 found = true; 452 } 453 454 if (found) { 455 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 456 shhwtstamp.hwtstamp = ns_to_ktime(ns); 457 458 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 459 /* pass tstamp to stack */ 460 skb_tstamp_tx(skb, &shhwtstamp); 461 } 462 } 463 464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 465 * @priv: driver private structure 466 * @p : descriptor pointer 467 * @np : next descriptor pointer 468 * @skb : the socket buffer 469 * Description : 470 * This function will read received packet's timestamp from the descriptor 471 * and pass it to stack. It also perform some sanity checks. 472 */ 473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 474 struct dma_desc *np, struct sk_buff *skb) 475 { 476 struct skb_shared_hwtstamps *shhwtstamp = NULL; 477 struct dma_desc *desc = p; 478 u64 ns = 0; 479 480 if (!priv->hwts_rx_en) 481 return; 482 /* For GMAC4, the valid timestamp is from CTX next desc. */ 483 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 484 desc = np; 485 486 /* Check if timestamp is available */ 487 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 488 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 489 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 490 shhwtstamp = skb_hwtstamps(skb); 491 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 492 shhwtstamp->hwtstamp = ns_to_ktime(ns); 493 } else { 494 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 495 } 496 } 497 498 /** 499 * stmmac_hwtstamp_set - control hardware timestamping. 500 * @dev: device pointer. 501 * @ifr: An IOCTL specific structure, that can contain a pointer to 502 * a proprietary structure used to pass information to the driver. 503 * Description: 504 * This function configures the MAC to enable/disable both outgoing(TX) 505 * and incoming(RX) packets time stamping based on user input. 506 * Return Value: 507 * 0 on success and an appropriate -ve integer on failure. 508 */ 509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 510 { 511 struct stmmac_priv *priv = netdev_priv(dev); 512 struct hwtstamp_config config; 513 struct timespec64 now; 514 u64 temp = 0; 515 u32 ptp_v2 = 0; 516 u32 tstamp_all = 0; 517 u32 ptp_over_ipv4_udp = 0; 518 u32 ptp_over_ipv6_udp = 0; 519 u32 ptp_over_ethernet = 0; 520 u32 snap_type_sel = 0; 521 u32 ts_master_en = 0; 522 u32 ts_event_en = 0; 523 u32 sec_inc = 0; 524 u32 value = 0; 525 bool xmac; 526 527 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 528 529 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 530 netdev_alert(priv->dev, "No support for HW time stamping\n"); 531 priv->hwts_tx_en = 0; 532 priv->hwts_rx_en = 0; 533 534 return -EOPNOTSUPP; 535 } 536 537 if (copy_from_user(&config, ifr->ifr_data, 538 sizeof(config))) 539 return -EFAULT; 540 541 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 542 __func__, config.flags, config.tx_type, config.rx_filter); 543 544 /* reserved for future extensions */ 545 if (config.flags) 546 return -EINVAL; 547 548 if (config.tx_type != HWTSTAMP_TX_OFF && 549 config.tx_type != HWTSTAMP_TX_ON) 550 return -ERANGE; 551 552 if (priv->adv_ts) { 553 switch (config.rx_filter) { 554 case HWTSTAMP_FILTER_NONE: 555 /* time stamp no incoming packet at all */ 556 config.rx_filter = HWTSTAMP_FILTER_NONE; 557 break; 558 559 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 560 /* PTP v1, UDP, any kind of event packet */ 561 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 562 /* 'xmac' hardware can support Sync, Pdelay_Req and 563 * Pdelay_resp by setting bit14 and bits17/16 to 01 564 * This leaves Delay_Req timestamps out. 565 * Enable all events *and* general purpose message 566 * timestamping 567 */ 568 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 571 break; 572 573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 574 /* PTP v1, UDP, Sync packet */ 575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 576 /* take time stamp for SYNC messages only */ 577 ts_event_en = PTP_TCR_TSEVNTENA; 578 579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 581 break; 582 583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 584 /* PTP v1, UDP, Delay_req packet */ 585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 586 /* take time stamp for Delay_Req messages only */ 587 ts_master_en = PTP_TCR_TSMSTRENA; 588 ts_event_en = PTP_TCR_TSEVNTENA; 589 590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 592 break; 593 594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 595 /* PTP v2, UDP, any kind of event packet */ 596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 597 ptp_v2 = PTP_TCR_TSVER2ENA; 598 /* take time stamp for all event messages */ 599 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 600 601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 603 break; 604 605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 606 /* PTP v2, UDP, Sync packet */ 607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 608 ptp_v2 = PTP_TCR_TSVER2ENA; 609 /* take time stamp for SYNC messages only */ 610 ts_event_en = PTP_TCR_TSEVNTENA; 611 612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 614 break; 615 616 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 617 /* PTP v2, UDP, Delay_req packet */ 618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 619 ptp_v2 = PTP_TCR_TSVER2ENA; 620 /* take time stamp for Delay_Req messages only */ 621 ts_master_en = PTP_TCR_TSMSTRENA; 622 ts_event_en = PTP_TCR_TSEVNTENA; 623 624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 626 break; 627 628 case HWTSTAMP_FILTER_PTP_V2_EVENT: 629 /* PTP v2/802.AS1 any layer, any kind of event packet */ 630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 631 ptp_v2 = PTP_TCR_TSVER2ENA; 632 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 633 ts_event_en = PTP_TCR_TSEVNTENA; 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 636 ptp_over_ethernet = PTP_TCR_TSIPENA; 637 break; 638 639 case HWTSTAMP_FILTER_PTP_V2_SYNC: 640 /* PTP v2/802.AS1, any layer, Sync packet */ 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 642 ptp_v2 = PTP_TCR_TSVER2ENA; 643 /* take time stamp for SYNC messages only */ 644 ts_event_en = PTP_TCR_TSEVNTENA; 645 646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 648 ptp_over_ethernet = PTP_TCR_TSIPENA; 649 break; 650 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 652 /* PTP v2/802.AS1, any layer, Delay_req packet */ 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 654 ptp_v2 = PTP_TCR_TSVER2ENA; 655 /* take time stamp for Delay_Req messages only */ 656 ts_master_en = PTP_TCR_TSMSTRENA; 657 ts_event_en = PTP_TCR_TSEVNTENA; 658 659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 661 ptp_over_ethernet = PTP_TCR_TSIPENA; 662 break; 663 664 case HWTSTAMP_FILTER_NTP_ALL: 665 case HWTSTAMP_FILTER_ALL: 666 /* time stamp any incoming packet */ 667 config.rx_filter = HWTSTAMP_FILTER_ALL; 668 tstamp_all = PTP_TCR_TSENALL; 669 break; 670 671 default: 672 return -ERANGE; 673 } 674 } else { 675 switch (config.rx_filter) { 676 case HWTSTAMP_FILTER_NONE: 677 config.rx_filter = HWTSTAMP_FILTER_NONE; 678 break; 679 default: 680 /* PTP v1, UDP, any kind of event packet */ 681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 682 break; 683 } 684 } 685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 687 688 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 690 else { 691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 692 tstamp_all | ptp_v2 | ptp_over_ethernet | 693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 694 ts_master_en | snap_type_sel); 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 696 697 /* program Sub Second Increment reg */ 698 stmmac_config_sub_second_increment(priv, 699 priv->ptpaddr, priv->plat->clk_ptp_rate, 700 xmac, &sec_inc); 701 temp = div_u64(1000000000ULL, sec_inc); 702 703 /* Store sub second increment and flags for later use */ 704 priv->sub_second_inc = sec_inc; 705 priv->systime_flags = value; 706 707 /* calculate default added value: 708 * formula is : 709 * addend = (2^32)/freq_div_ratio; 710 * where, freq_div_ratio = 1e9ns/sec_inc 711 */ 712 temp = (u64)(temp << 32); 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 715 716 /* initialize system time */ 717 ktime_get_real_ts64(&now); 718 719 /* lower 32 bits of tv_sec are safe until y2106 */ 720 stmmac_init_systime(priv, priv->ptpaddr, 721 (u32)now.tv_sec, now.tv_nsec); 722 } 723 724 memcpy(&priv->tstamp_config, &config, sizeof(config)); 725 726 return copy_to_user(ifr->ifr_data, &config, 727 sizeof(config)) ? -EFAULT : 0; 728 } 729 730 /** 731 * stmmac_hwtstamp_get - read hardware timestamping. 732 * @dev: device pointer. 733 * @ifr: An IOCTL specific structure, that can contain a pointer to 734 * a proprietary structure used to pass information to the driver. 735 * Description: 736 * This function obtain the current hardware timestamping settings 737 as requested. 738 */ 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 740 { 741 struct stmmac_priv *priv = netdev_priv(dev); 742 struct hwtstamp_config *config = &priv->tstamp_config; 743 744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 745 return -EOPNOTSUPP; 746 747 return copy_to_user(ifr->ifr_data, config, 748 sizeof(*config)) ? -EFAULT : 0; 749 } 750 751 /** 752 * stmmac_init_ptp - init PTP 753 * @priv: driver private structure 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 755 * This is done by looking at the HW cap. register. 756 * This function also registers the ptp driver. 757 */ 758 static int stmmac_init_ptp(struct stmmac_priv *priv) 759 { 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 761 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 763 return -EOPNOTSUPP; 764 765 priv->adv_ts = 0; 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 767 if (xmac && priv->dma_cap.atime_stamp) 768 priv->adv_ts = 1; 769 /* Dwmac 3.x core with extend_desc can support adv_ts */ 770 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 771 priv->adv_ts = 1; 772 773 if (priv->dma_cap.time_stamp) 774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 775 776 if (priv->adv_ts) 777 netdev_info(priv->dev, 778 "IEEE 1588-2008 Advanced Timestamp supported\n"); 779 780 priv->hwts_tx_en = 0; 781 priv->hwts_rx_en = 0; 782 783 stmmac_ptp_register(priv); 784 785 return 0; 786 } 787 788 static void stmmac_release_ptp(struct stmmac_priv *priv) 789 { 790 if (priv->plat->clk_ptp_ref) 791 clk_disable_unprepare(priv->plat->clk_ptp_ref); 792 stmmac_ptp_unregister(priv); 793 } 794 795 /** 796 * stmmac_mac_flow_ctrl - Configure flow control in all queues 797 * @priv: driver private structure 798 * Description: It is used for configuring the flow control in all queues 799 */ 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 801 { 802 u32 tx_cnt = priv->plat->tx_queues_to_use; 803 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 805 priv->pause, tx_cnt); 806 } 807 808 static void stmmac_validate(struct phylink_config *config, 809 unsigned long *supported, 810 struct phylink_link_state *state) 811 { 812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 815 int tx_cnt = priv->plat->tx_queues_to_use; 816 int max_speed = priv->plat->max_speed; 817 818 phylink_set(mac_supported, 10baseT_Half); 819 phylink_set(mac_supported, 10baseT_Full); 820 phylink_set(mac_supported, 100baseT_Half); 821 phylink_set(mac_supported, 100baseT_Full); 822 phylink_set(mac_supported, 1000baseT_Half); 823 phylink_set(mac_supported, 1000baseT_Full); 824 phylink_set(mac_supported, 1000baseKX_Full); 825 826 phylink_set(mac_supported, Autoneg); 827 phylink_set(mac_supported, Pause); 828 phylink_set(mac_supported, Asym_Pause); 829 phylink_set_port_modes(mac_supported); 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 if (!max_speed || (max_speed >= 2500)) { 837 phylink_set(mac_supported, 2500baseT_Full); 838 phylink_set(mac_supported, 2500baseX_Full); 839 } 840 if (!max_speed || (max_speed >= 5000)) { 841 phylink_set(mac_supported, 5000baseT_Full); 842 } 843 if (!max_speed || (max_speed >= 10000)) { 844 phylink_set(mac_supported, 10000baseSR_Full); 845 phylink_set(mac_supported, 10000baseLR_Full); 846 phylink_set(mac_supported, 10000baseER_Full); 847 phylink_set(mac_supported, 10000baseLRM_Full); 848 phylink_set(mac_supported, 10000baseT_Full); 849 phylink_set(mac_supported, 10000baseKX4_Full); 850 phylink_set(mac_supported, 10000baseKR_Full); 851 } 852 } 853 854 /* Half-Duplex can only work with single queue */ 855 if (tx_cnt > 1) { 856 phylink_set(mask, 10baseT_Half); 857 phylink_set(mask, 100baseT_Half); 858 phylink_set(mask, 1000baseT_Half); 859 } 860 861 bitmap_and(supported, supported, mac_supported, 862 __ETHTOOL_LINK_MODE_MASK_NBITS); 863 bitmap_andnot(supported, supported, mask, 864 __ETHTOOL_LINK_MODE_MASK_NBITS); 865 bitmap_and(state->advertising, state->advertising, mac_supported, 866 __ETHTOOL_LINK_MODE_MASK_NBITS); 867 bitmap_andnot(state->advertising, state->advertising, mask, 868 __ETHTOOL_LINK_MODE_MASK_NBITS); 869 } 870 871 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 872 struct phylink_link_state *state) 873 { 874 state->link = 0; 875 } 876 877 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 878 const struct phylink_link_state *state) 879 { 880 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 881 u32 ctrl; 882 883 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 884 ctrl &= ~priv->hw->link.speed_mask; 885 886 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 887 switch (state->speed) { 888 case SPEED_10000: 889 ctrl |= priv->hw->link.xgmii.speed10000; 890 break; 891 case SPEED_5000: 892 ctrl |= priv->hw->link.xgmii.speed5000; 893 break; 894 case SPEED_2500: 895 ctrl |= priv->hw->link.xgmii.speed2500; 896 break; 897 default: 898 return; 899 } 900 } else { 901 switch (state->speed) { 902 case SPEED_2500: 903 ctrl |= priv->hw->link.speed2500; 904 break; 905 case SPEED_1000: 906 ctrl |= priv->hw->link.speed1000; 907 break; 908 case SPEED_100: 909 ctrl |= priv->hw->link.speed100; 910 break; 911 case SPEED_10: 912 ctrl |= priv->hw->link.speed10; 913 break; 914 default: 915 return; 916 } 917 } 918 919 priv->speed = state->speed; 920 921 if (priv->plat->fix_mac_speed) 922 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); 923 924 if (!state->duplex) 925 ctrl &= ~priv->hw->link.duplex; 926 else 927 ctrl |= priv->hw->link.duplex; 928 929 /* Flow Control operation */ 930 if (state->pause) 931 stmmac_mac_flow_ctrl(priv, state->duplex); 932 933 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 934 } 935 936 static void stmmac_mac_an_restart(struct phylink_config *config) 937 { 938 /* Not Supported */ 939 } 940 941 static void stmmac_mac_link_down(struct phylink_config *config, 942 unsigned int mode, phy_interface_t interface) 943 { 944 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 945 946 stmmac_mac_set(priv, priv->ioaddr, false); 947 priv->eee_active = false; 948 stmmac_eee_init(priv); 949 stmmac_set_eee_pls(priv, priv->hw, false); 950 } 951 952 static void stmmac_mac_link_up(struct phylink_config *config, 953 struct phy_device *phy, 954 unsigned int mode, phy_interface_t interface, 955 int speed, int duplex, 956 bool tx_pause, bool rx_pause) 957 { 958 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 959 960 stmmac_mac_set(priv, priv->ioaddr, true); 961 if (phy && priv->dma_cap.eee) { 962 priv->eee_active = phy_init_eee(phy, 1) >= 0; 963 priv->eee_enabled = stmmac_eee_init(priv); 964 stmmac_set_eee_pls(priv, priv->hw, true); 965 } 966 } 967 968 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 969 .validate = stmmac_validate, 970 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 971 .mac_config = stmmac_mac_config, 972 .mac_an_restart = stmmac_mac_an_restart, 973 .mac_link_down = stmmac_mac_link_down, 974 .mac_link_up = stmmac_mac_link_up, 975 }; 976 977 /** 978 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 979 * @priv: driver private structure 980 * Description: this is to verify if the HW supports the PCS. 981 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 982 * configured for the TBI, RTBI, or SGMII PHY interface. 983 */ 984 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 985 { 986 int interface = priv->plat->interface; 987 988 if (priv->dma_cap.pcs) { 989 if ((interface == PHY_INTERFACE_MODE_RGMII) || 990 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 991 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 992 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 993 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 994 priv->hw->pcs = STMMAC_PCS_RGMII; 995 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 996 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 997 priv->hw->pcs = STMMAC_PCS_SGMII; 998 } 999 } 1000 } 1001 1002 /** 1003 * stmmac_init_phy - PHY initialization 1004 * @dev: net device structure 1005 * Description: it initializes the driver's PHY state, and attaches the PHY 1006 * to the mac driver. 1007 * Return value: 1008 * 0 on success 1009 */ 1010 static int stmmac_init_phy(struct net_device *dev) 1011 { 1012 struct stmmac_priv *priv = netdev_priv(dev); 1013 struct device_node *node; 1014 int ret; 1015 1016 node = priv->plat->phylink_node; 1017 1018 if (node) 1019 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1020 1021 /* Some DT bindings do not set-up the PHY handle. Let's try to 1022 * manually parse it 1023 */ 1024 if (!node || ret) { 1025 int addr = priv->plat->phy_addr; 1026 struct phy_device *phydev; 1027 1028 phydev = mdiobus_get_phy(priv->mii, addr); 1029 if (!phydev) { 1030 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1031 return -ENODEV; 1032 } 1033 1034 ret = phylink_connect_phy(priv->phylink, phydev); 1035 } 1036 1037 return ret; 1038 } 1039 1040 static int stmmac_phy_setup(struct stmmac_priv *priv) 1041 { 1042 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1043 int mode = priv->plat->phy_interface; 1044 struct phylink *phylink; 1045 1046 priv->phylink_config.dev = &priv->dev->dev; 1047 priv->phylink_config.type = PHYLINK_NETDEV; 1048 1049 phylink = phylink_create(&priv->phylink_config, fwnode, 1050 mode, &stmmac_phylink_mac_ops); 1051 if (IS_ERR(phylink)) 1052 return PTR_ERR(phylink); 1053 1054 priv->phylink = phylink; 1055 return 0; 1056 } 1057 1058 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1059 { 1060 u32 rx_cnt = priv->plat->rx_queues_to_use; 1061 void *head_rx; 1062 u32 queue; 1063 1064 /* Display RX rings */ 1065 for (queue = 0; queue < rx_cnt; queue++) { 1066 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1067 1068 pr_info("\tRX Queue %u rings\n", queue); 1069 1070 if (priv->extend_desc) 1071 head_rx = (void *)rx_q->dma_erx; 1072 else 1073 head_rx = (void *)rx_q->dma_rx; 1074 1075 /* Display RX ring */ 1076 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1077 } 1078 } 1079 1080 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1081 { 1082 u32 tx_cnt = priv->plat->tx_queues_to_use; 1083 void *head_tx; 1084 u32 queue; 1085 1086 /* Display TX rings */ 1087 for (queue = 0; queue < tx_cnt; queue++) { 1088 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1089 1090 pr_info("\tTX Queue %d rings\n", queue); 1091 1092 if (priv->extend_desc) 1093 head_tx = (void *)tx_q->dma_etx; 1094 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1095 head_tx = (void *)tx_q->dma_entx; 1096 else 1097 head_tx = (void *)tx_q->dma_tx; 1098 1099 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1100 } 1101 } 1102 1103 static void stmmac_display_rings(struct stmmac_priv *priv) 1104 { 1105 /* Display RX ring */ 1106 stmmac_display_rx_rings(priv); 1107 1108 /* Display TX ring */ 1109 stmmac_display_tx_rings(priv); 1110 } 1111 1112 static int stmmac_set_bfsize(int mtu, int bufsize) 1113 { 1114 int ret = bufsize; 1115 1116 if (mtu >= BUF_SIZE_8KiB) 1117 ret = BUF_SIZE_16KiB; 1118 else if (mtu >= BUF_SIZE_4KiB) 1119 ret = BUF_SIZE_8KiB; 1120 else if (mtu >= BUF_SIZE_2KiB) 1121 ret = BUF_SIZE_4KiB; 1122 else if (mtu > DEFAULT_BUFSIZE) 1123 ret = BUF_SIZE_2KiB; 1124 else 1125 ret = DEFAULT_BUFSIZE; 1126 1127 return ret; 1128 } 1129 1130 /** 1131 * stmmac_clear_rx_descriptors - clear RX descriptors 1132 * @priv: driver private structure 1133 * @queue: RX queue index 1134 * Description: this function is called to clear the RX descriptors 1135 * in case of both basic and extended descriptors are used. 1136 */ 1137 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1138 { 1139 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1140 int i; 1141 1142 /* Clear the RX descriptors */ 1143 for (i = 0; i < DMA_RX_SIZE; i++) 1144 if (priv->extend_desc) 1145 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1146 priv->use_riwt, priv->mode, 1147 (i == DMA_RX_SIZE - 1), 1148 priv->dma_buf_sz); 1149 else 1150 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1151 priv->use_riwt, priv->mode, 1152 (i == DMA_RX_SIZE - 1), 1153 priv->dma_buf_sz); 1154 } 1155 1156 /** 1157 * stmmac_clear_tx_descriptors - clear tx descriptors 1158 * @priv: driver private structure 1159 * @queue: TX queue index. 1160 * Description: this function is called to clear the TX descriptors 1161 * in case of both basic and extended descriptors are used. 1162 */ 1163 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1164 { 1165 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1166 int i; 1167 1168 /* Clear the TX descriptors */ 1169 for (i = 0; i < DMA_TX_SIZE; i++) { 1170 int last = (i == (DMA_TX_SIZE - 1)); 1171 struct dma_desc *p; 1172 1173 if (priv->extend_desc) 1174 p = &tx_q->dma_etx[i].basic; 1175 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1176 p = &tx_q->dma_entx[i].basic; 1177 else 1178 p = &tx_q->dma_tx[i]; 1179 1180 stmmac_init_tx_desc(priv, p, priv->mode, last); 1181 } 1182 } 1183 1184 /** 1185 * stmmac_clear_descriptors - clear descriptors 1186 * @priv: driver private structure 1187 * Description: this function is called to clear the TX and RX descriptors 1188 * in case of both basic and extended descriptors are used. 1189 */ 1190 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1191 { 1192 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1193 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1194 u32 queue; 1195 1196 /* Clear the RX descriptors */ 1197 for (queue = 0; queue < rx_queue_cnt; queue++) 1198 stmmac_clear_rx_descriptors(priv, queue); 1199 1200 /* Clear the TX descriptors */ 1201 for (queue = 0; queue < tx_queue_cnt; queue++) 1202 stmmac_clear_tx_descriptors(priv, queue); 1203 } 1204 1205 /** 1206 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1207 * @priv: driver private structure 1208 * @p: descriptor pointer 1209 * @i: descriptor index 1210 * @flags: gfp flag 1211 * @queue: RX queue index 1212 * Description: this function is called to allocate a receive buffer, perform 1213 * the DMA mapping and init the descriptor. 1214 */ 1215 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1216 int i, gfp_t flags, u32 queue) 1217 { 1218 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1219 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1220 1221 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1222 if (!buf->page) 1223 return -ENOMEM; 1224 1225 if (priv->sph) { 1226 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1227 if (!buf->sec_page) 1228 return -ENOMEM; 1229 1230 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1231 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1232 } else { 1233 buf->sec_page = NULL; 1234 } 1235 1236 buf->addr = page_pool_get_dma_addr(buf->page); 1237 stmmac_set_desc_addr(priv, p, buf->addr); 1238 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1239 stmmac_init_desc3(priv, p); 1240 1241 return 0; 1242 } 1243 1244 /** 1245 * stmmac_free_rx_buffer - free RX dma buffers 1246 * @priv: private structure 1247 * @queue: RX queue index 1248 * @i: buffer index. 1249 */ 1250 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1251 { 1252 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1253 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1254 1255 if (buf->page) 1256 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1257 buf->page = NULL; 1258 1259 if (buf->sec_page) 1260 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1261 buf->sec_page = NULL; 1262 } 1263 1264 /** 1265 * stmmac_free_tx_buffer - free RX dma buffers 1266 * @priv: private structure 1267 * @queue: RX queue index 1268 * @i: buffer index. 1269 */ 1270 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1271 { 1272 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1273 1274 if (tx_q->tx_skbuff_dma[i].buf) { 1275 if (tx_q->tx_skbuff_dma[i].map_as_page) 1276 dma_unmap_page(priv->device, 1277 tx_q->tx_skbuff_dma[i].buf, 1278 tx_q->tx_skbuff_dma[i].len, 1279 DMA_TO_DEVICE); 1280 else 1281 dma_unmap_single(priv->device, 1282 tx_q->tx_skbuff_dma[i].buf, 1283 tx_q->tx_skbuff_dma[i].len, 1284 DMA_TO_DEVICE); 1285 } 1286 1287 if (tx_q->tx_skbuff[i]) { 1288 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1289 tx_q->tx_skbuff[i] = NULL; 1290 tx_q->tx_skbuff_dma[i].buf = 0; 1291 tx_q->tx_skbuff_dma[i].map_as_page = false; 1292 } 1293 } 1294 1295 /** 1296 * init_dma_rx_desc_rings - init the RX descriptor rings 1297 * @dev: net device structure 1298 * @flags: gfp flag. 1299 * Description: this function initializes the DMA RX descriptors 1300 * and allocates the socket buffers. It supports the chained and ring 1301 * modes. 1302 */ 1303 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1304 { 1305 struct stmmac_priv *priv = netdev_priv(dev); 1306 u32 rx_count = priv->plat->rx_queues_to_use; 1307 int ret = -ENOMEM; 1308 int queue; 1309 int i; 1310 1311 /* RX INITIALIZATION */ 1312 netif_dbg(priv, probe, priv->dev, 1313 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1314 1315 for (queue = 0; queue < rx_count; queue++) { 1316 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1317 1318 netif_dbg(priv, probe, priv->dev, 1319 "(%s) dma_rx_phy=0x%08x\n", __func__, 1320 (u32)rx_q->dma_rx_phy); 1321 1322 stmmac_clear_rx_descriptors(priv, queue); 1323 1324 for (i = 0; i < DMA_RX_SIZE; i++) { 1325 struct dma_desc *p; 1326 1327 if (priv->extend_desc) 1328 p = &((rx_q->dma_erx + i)->basic); 1329 else 1330 p = rx_q->dma_rx + i; 1331 1332 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1333 queue); 1334 if (ret) 1335 goto err_init_rx_buffers; 1336 } 1337 1338 rx_q->cur_rx = 0; 1339 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1340 1341 /* Setup the chained descriptor addresses */ 1342 if (priv->mode == STMMAC_CHAIN_MODE) { 1343 if (priv->extend_desc) 1344 stmmac_mode_init(priv, rx_q->dma_erx, 1345 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1346 else 1347 stmmac_mode_init(priv, rx_q->dma_rx, 1348 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1349 } 1350 } 1351 1352 return 0; 1353 1354 err_init_rx_buffers: 1355 while (queue >= 0) { 1356 while (--i >= 0) 1357 stmmac_free_rx_buffer(priv, queue, i); 1358 1359 if (queue == 0) 1360 break; 1361 1362 i = DMA_RX_SIZE; 1363 queue--; 1364 } 1365 1366 return ret; 1367 } 1368 1369 /** 1370 * init_dma_tx_desc_rings - init the TX descriptor rings 1371 * @dev: net device structure. 1372 * Description: this function initializes the DMA TX descriptors 1373 * and allocates the socket buffers. It supports the chained and ring 1374 * modes. 1375 */ 1376 static int init_dma_tx_desc_rings(struct net_device *dev) 1377 { 1378 struct stmmac_priv *priv = netdev_priv(dev); 1379 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1380 u32 queue; 1381 int i; 1382 1383 for (queue = 0; queue < tx_queue_cnt; queue++) { 1384 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1385 1386 netif_dbg(priv, probe, priv->dev, 1387 "(%s) dma_tx_phy=0x%08x\n", __func__, 1388 (u32)tx_q->dma_tx_phy); 1389 1390 /* Setup the chained descriptor addresses */ 1391 if (priv->mode == STMMAC_CHAIN_MODE) { 1392 if (priv->extend_desc) 1393 stmmac_mode_init(priv, tx_q->dma_etx, 1394 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1395 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1396 stmmac_mode_init(priv, tx_q->dma_tx, 1397 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1398 } 1399 1400 for (i = 0; i < DMA_TX_SIZE; i++) { 1401 struct dma_desc *p; 1402 if (priv->extend_desc) 1403 p = &((tx_q->dma_etx + i)->basic); 1404 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1405 p = &((tx_q->dma_entx + i)->basic); 1406 else 1407 p = tx_q->dma_tx + i; 1408 1409 stmmac_clear_desc(priv, p); 1410 1411 tx_q->tx_skbuff_dma[i].buf = 0; 1412 tx_q->tx_skbuff_dma[i].map_as_page = false; 1413 tx_q->tx_skbuff_dma[i].len = 0; 1414 tx_q->tx_skbuff_dma[i].last_segment = false; 1415 tx_q->tx_skbuff[i] = NULL; 1416 } 1417 1418 tx_q->dirty_tx = 0; 1419 tx_q->cur_tx = 0; 1420 tx_q->mss = 0; 1421 1422 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1423 } 1424 1425 return 0; 1426 } 1427 1428 /** 1429 * init_dma_desc_rings - init the RX/TX descriptor rings 1430 * @dev: net device structure 1431 * @flags: gfp flag. 1432 * Description: this function initializes the DMA RX/TX descriptors 1433 * and allocates the socket buffers. It supports the chained and ring 1434 * modes. 1435 */ 1436 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1437 { 1438 struct stmmac_priv *priv = netdev_priv(dev); 1439 int ret; 1440 1441 ret = init_dma_rx_desc_rings(dev, flags); 1442 if (ret) 1443 return ret; 1444 1445 ret = init_dma_tx_desc_rings(dev); 1446 1447 stmmac_clear_descriptors(priv); 1448 1449 if (netif_msg_hw(priv)) 1450 stmmac_display_rings(priv); 1451 1452 return ret; 1453 } 1454 1455 /** 1456 * dma_free_rx_skbufs - free RX dma buffers 1457 * @priv: private structure 1458 * @queue: RX queue index 1459 */ 1460 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1461 { 1462 int i; 1463 1464 for (i = 0; i < DMA_RX_SIZE; i++) 1465 stmmac_free_rx_buffer(priv, queue, i); 1466 } 1467 1468 /** 1469 * dma_free_tx_skbufs - free TX dma buffers 1470 * @priv: private structure 1471 * @queue: TX queue index 1472 */ 1473 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1474 { 1475 int i; 1476 1477 for (i = 0; i < DMA_TX_SIZE; i++) 1478 stmmac_free_tx_buffer(priv, queue, i); 1479 } 1480 1481 /** 1482 * free_dma_rx_desc_resources - free RX dma desc resources 1483 * @priv: private structure 1484 */ 1485 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1486 { 1487 u32 rx_count = priv->plat->rx_queues_to_use; 1488 u32 queue; 1489 1490 /* Free RX queue resources */ 1491 for (queue = 0; queue < rx_count; queue++) { 1492 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1493 1494 /* Release the DMA RX socket buffers */ 1495 dma_free_rx_skbufs(priv, queue); 1496 1497 /* Free DMA regions of consistent memory previously allocated */ 1498 if (!priv->extend_desc) 1499 dma_free_coherent(priv->device, 1500 DMA_RX_SIZE * sizeof(struct dma_desc), 1501 rx_q->dma_rx, rx_q->dma_rx_phy); 1502 else 1503 dma_free_coherent(priv->device, DMA_RX_SIZE * 1504 sizeof(struct dma_extended_desc), 1505 rx_q->dma_erx, rx_q->dma_rx_phy); 1506 1507 kfree(rx_q->buf_pool); 1508 if (rx_q->page_pool) 1509 page_pool_destroy(rx_q->page_pool); 1510 } 1511 } 1512 1513 /** 1514 * free_dma_tx_desc_resources - free TX dma desc resources 1515 * @priv: private structure 1516 */ 1517 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1518 { 1519 u32 tx_count = priv->plat->tx_queues_to_use; 1520 u32 queue; 1521 1522 /* Free TX queue resources */ 1523 for (queue = 0; queue < tx_count; queue++) { 1524 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1525 size_t size; 1526 void *addr; 1527 1528 /* Release the DMA TX socket buffers */ 1529 dma_free_tx_skbufs(priv, queue); 1530 1531 if (priv->extend_desc) { 1532 size = sizeof(struct dma_extended_desc); 1533 addr = tx_q->dma_etx; 1534 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1535 size = sizeof(struct dma_edesc); 1536 addr = tx_q->dma_entx; 1537 } else { 1538 size = sizeof(struct dma_desc); 1539 addr = tx_q->dma_tx; 1540 } 1541 1542 size *= DMA_TX_SIZE; 1543 1544 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1545 1546 kfree(tx_q->tx_skbuff_dma); 1547 kfree(tx_q->tx_skbuff); 1548 } 1549 } 1550 1551 /** 1552 * alloc_dma_rx_desc_resources - alloc RX resources. 1553 * @priv: private structure 1554 * Description: according to which descriptor can be used (extend or basic) 1555 * this function allocates the resources for TX and RX paths. In case of 1556 * reception, for example, it pre-allocated the RX socket buffer in order to 1557 * allow zero-copy mechanism. 1558 */ 1559 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1560 { 1561 u32 rx_count = priv->plat->rx_queues_to_use; 1562 int ret = -ENOMEM; 1563 u32 queue; 1564 1565 /* RX queues buffers and DMA */ 1566 for (queue = 0; queue < rx_count; queue++) { 1567 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1568 struct page_pool_params pp_params = { 0 }; 1569 unsigned int num_pages; 1570 1571 rx_q->queue_index = queue; 1572 rx_q->priv_data = priv; 1573 1574 pp_params.flags = PP_FLAG_DMA_MAP; 1575 pp_params.pool_size = DMA_RX_SIZE; 1576 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1577 pp_params.order = ilog2(num_pages); 1578 pp_params.nid = dev_to_node(priv->device); 1579 pp_params.dev = priv->device; 1580 pp_params.dma_dir = DMA_FROM_DEVICE; 1581 1582 rx_q->page_pool = page_pool_create(&pp_params); 1583 if (IS_ERR(rx_q->page_pool)) { 1584 ret = PTR_ERR(rx_q->page_pool); 1585 rx_q->page_pool = NULL; 1586 goto err_dma; 1587 } 1588 1589 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1590 GFP_KERNEL); 1591 if (!rx_q->buf_pool) 1592 goto err_dma; 1593 1594 if (priv->extend_desc) { 1595 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1596 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1597 &rx_q->dma_rx_phy, 1598 GFP_KERNEL); 1599 if (!rx_q->dma_erx) 1600 goto err_dma; 1601 1602 } else { 1603 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1604 DMA_RX_SIZE * sizeof(struct dma_desc), 1605 &rx_q->dma_rx_phy, 1606 GFP_KERNEL); 1607 if (!rx_q->dma_rx) 1608 goto err_dma; 1609 } 1610 } 1611 1612 return 0; 1613 1614 err_dma: 1615 free_dma_rx_desc_resources(priv); 1616 1617 return ret; 1618 } 1619 1620 /** 1621 * alloc_dma_tx_desc_resources - alloc TX resources. 1622 * @priv: private structure 1623 * Description: according to which descriptor can be used (extend or basic) 1624 * this function allocates the resources for TX and RX paths. In case of 1625 * reception, for example, it pre-allocated the RX socket buffer in order to 1626 * allow zero-copy mechanism. 1627 */ 1628 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1629 { 1630 u32 tx_count = priv->plat->tx_queues_to_use; 1631 int ret = -ENOMEM; 1632 u32 queue; 1633 1634 /* TX queues buffers and DMA */ 1635 for (queue = 0; queue < tx_count; queue++) { 1636 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1637 size_t size; 1638 void *addr; 1639 1640 tx_q->queue_index = queue; 1641 tx_q->priv_data = priv; 1642 1643 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1644 sizeof(*tx_q->tx_skbuff_dma), 1645 GFP_KERNEL); 1646 if (!tx_q->tx_skbuff_dma) 1647 goto err_dma; 1648 1649 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1650 sizeof(struct sk_buff *), 1651 GFP_KERNEL); 1652 if (!tx_q->tx_skbuff) 1653 goto err_dma; 1654 1655 if (priv->extend_desc) 1656 size = sizeof(struct dma_extended_desc); 1657 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1658 size = sizeof(struct dma_edesc); 1659 else 1660 size = sizeof(struct dma_desc); 1661 1662 size *= DMA_TX_SIZE; 1663 1664 addr = dma_alloc_coherent(priv->device, size, 1665 &tx_q->dma_tx_phy, GFP_KERNEL); 1666 if (!addr) 1667 goto err_dma; 1668 1669 if (priv->extend_desc) 1670 tx_q->dma_etx = addr; 1671 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1672 tx_q->dma_entx = addr; 1673 else 1674 tx_q->dma_tx = addr; 1675 } 1676 1677 return 0; 1678 1679 err_dma: 1680 free_dma_tx_desc_resources(priv); 1681 return ret; 1682 } 1683 1684 /** 1685 * alloc_dma_desc_resources - alloc TX/RX resources. 1686 * @priv: private structure 1687 * Description: according to which descriptor can be used (extend or basic) 1688 * this function allocates the resources for TX and RX paths. In case of 1689 * reception, for example, it pre-allocated the RX socket buffer in order to 1690 * allow zero-copy mechanism. 1691 */ 1692 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1693 { 1694 /* RX Allocation */ 1695 int ret = alloc_dma_rx_desc_resources(priv); 1696 1697 if (ret) 1698 return ret; 1699 1700 ret = alloc_dma_tx_desc_resources(priv); 1701 1702 return ret; 1703 } 1704 1705 /** 1706 * free_dma_desc_resources - free dma desc resources 1707 * @priv: private structure 1708 */ 1709 static void free_dma_desc_resources(struct stmmac_priv *priv) 1710 { 1711 /* Release the DMA RX socket buffers */ 1712 free_dma_rx_desc_resources(priv); 1713 1714 /* Release the DMA TX socket buffers */ 1715 free_dma_tx_desc_resources(priv); 1716 } 1717 1718 /** 1719 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1720 * @priv: driver private structure 1721 * Description: It is used for enabling the rx queues in the MAC 1722 */ 1723 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1724 { 1725 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1726 int queue; 1727 u8 mode; 1728 1729 for (queue = 0; queue < rx_queues_count; queue++) { 1730 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1731 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1732 } 1733 } 1734 1735 /** 1736 * stmmac_start_rx_dma - start RX DMA channel 1737 * @priv: driver private structure 1738 * @chan: RX channel index 1739 * Description: 1740 * This starts a RX DMA channel 1741 */ 1742 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1743 { 1744 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1745 stmmac_start_rx(priv, priv->ioaddr, chan); 1746 } 1747 1748 /** 1749 * stmmac_start_tx_dma - start TX DMA channel 1750 * @priv: driver private structure 1751 * @chan: TX channel index 1752 * Description: 1753 * This starts a TX DMA channel 1754 */ 1755 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1756 { 1757 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1758 stmmac_start_tx(priv, priv->ioaddr, chan); 1759 } 1760 1761 /** 1762 * stmmac_stop_rx_dma - stop RX DMA channel 1763 * @priv: driver private structure 1764 * @chan: RX channel index 1765 * Description: 1766 * This stops a RX DMA channel 1767 */ 1768 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1769 { 1770 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1771 stmmac_stop_rx(priv, priv->ioaddr, chan); 1772 } 1773 1774 /** 1775 * stmmac_stop_tx_dma - stop TX DMA channel 1776 * @priv: driver private structure 1777 * @chan: TX channel index 1778 * Description: 1779 * This stops a TX DMA channel 1780 */ 1781 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1782 { 1783 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1784 stmmac_stop_tx(priv, priv->ioaddr, chan); 1785 } 1786 1787 /** 1788 * stmmac_start_all_dma - start all RX and TX DMA channels 1789 * @priv: driver private structure 1790 * Description: 1791 * This starts all the RX and TX DMA channels 1792 */ 1793 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1794 { 1795 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1796 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1797 u32 chan = 0; 1798 1799 for (chan = 0; chan < rx_channels_count; chan++) 1800 stmmac_start_rx_dma(priv, chan); 1801 1802 for (chan = 0; chan < tx_channels_count; chan++) 1803 stmmac_start_tx_dma(priv, chan); 1804 } 1805 1806 /** 1807 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1808 * @priv: driver private structure 1809 * Description: 1810 * This stops the RX and TX DMA channels 1811 */ 1812 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1813 { 1814 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1815 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1816 u32 chan = 0; 1817 1818 for (chan = 0; chan < rx_channels_count; chan++) 1819 stmmac_stop_rx_dma(priv, chan); 1820 1821 for (chan = 0; chan < tx_channels_count; chan++) 1822 stmmac_stop_tx_dma(priv, chan); 1823 } 1824 1825 /** 1826 * stmmac_dma_operation_mode - HW DMA operation mode 1827 * @priv: driver private structure 1828 * Description: it is used for configuring the DMA operation mode register in 1829 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1830 */ 1831 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1832 { 1833 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1834 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1835 int rxfifosz = priv->plat->rx_fifo_size; 1836 int txfifosz = priv->plat->tx_fifo_size; 1837 u32 txmode = 0; 1838 u32 rxmode = 0; 1839 u32 chan = 0; 1840 u8 qmode = 0; 1841 1842 if (rxfifosz == 0) 1843 rxfifosz = priv->dma_cap.rx_fifo_size; 1844 if (txfifosz == 0) 1845 txfifosz = priv->dma_cap.tx_fifo_size; 1846 1847 /* Adjust for real per queue fifo size */ 1848 rxfifosz /= rx_channels_count; 1849 txfifosz /= tx_channels_count; 1850 1851 if (priv->plat->force_thresh_dma_mode) { 1852 txmode = tc; 1853 rxmode = tc; 1854 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1855 /* 1856 * In case of GMAC, SF mode can be enabled 1857 * to perform the TX COE in HW. This depends on: 1858 * 1) TX COE if actually supported 1859 * 2) There is no bugged Jumbo frame support 1860 * that needs to not insert csum in the TDES. 1861 */ 1862 txmode = SF_DMA_MODE; 1863 rxmode = SF_DMA_MODE; 1864 priv->xstats.threshold = SF_DMA_MODE; 1865 } else { 1866 txmode = tc; 1867 rxmode = SF_DMA_MODE; 1868 } 1869 1870 /* configure all channels */ 1871 for (chan = 0; chan < rx_channels_count; chan++) { 1872 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1873 1874 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1875 rxfifosz, qmode); 1876 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1877 chan); 1878 } 1879 1880 for (chan = 0; chan < tx_channels_count; chan++) { 1881 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1882 1883 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1884 txfifosz, qmode); 1885 } 1886 } 1887 1888 /** 1889 * stmmac_tx_clean - to manage the transmission completion 1890 * @priv: driver private structure 1891 * @queue: TX queue index 1892 * Description: it reclaims the transmit resources after transmission completes. 1893 */ 1894 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1895 { 1896 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1897 unsigned int bytes_compl = 0, pkts_compl = 0; 1898 unsigned int entry, count = 0; 1899 1900 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1901 1902 priv->xstats.tx_clean++; 1903 1904 entry = tx_q->dirty_tx; 1905 while ((entry != tx_q->cur_tx) && (count < budget)) { 1906 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1907 struct dma_desc *p; 1908 int status; 1909 1910 if (priv->extend_desc) 1911 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1912 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1913 p = &tx_q->dma_entx[entry].basic; 1914 else 1915 p = tx_q->dma_tx + entry; 1916 1917 status = stmmac_tx_status(priv, &priv->dev->stats, 1918 &priv->xstats, p, priv->ioaddr); 1919 /* Check if the descriptor is owned by the DMA */ 1920 if (unlikely(status & tx_dma_own)) 1921 break; 1922 1923 count++; 1924 1925 /* Make sure descriptor fields are read after reading 1926 * the own bit. 1927 */ 1928 dma_rmb(); 1929 1930 /* Just consider the last segment and ...*/ 1931 if (likely(!(status & tx_not_ls))) { 1932 /* ... verify the status error condition */ 1933 if (unlikely(status & tx_err)) { 1934 priv->dev->stats.tx_errors++; 1935 } else { 1936 priv->dev->stats.tx_packets++; 1937 priv->xstats.tx_pkt_n++; 1938 } 1939 stmmac_get_tx_hwtstamp(priv, p, skb); 1940 } 1941 1942 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1943 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1944 dma_unmap_page(priv->device, 1945 tx_q->tx_skbuff_dma[entry].buf, 1946 tx_q->tx_skbuff_dma[entry].len, 1947 DMA_TO_DEVICE); 1948 else 1949 dma_unmap_single(priv->device, 1950 tx_q->tx_skbuff_dma[entry].buf, 1951 tx_q->tx_skbuff_dma[entry].len, 1952 DMA_TO_DEVICE); 1953 tx_q->tx_skbuff_dma[entry].buf = 0; 1954 tx_q->tx_skbuff_dma[entry].len = 0; 1955 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1956 } 1957 1958 stmmac_clean_desc3(priv, tx_q, p); 1959 1960 tx_q->tx_skbuff_dma[entry].last_segment = false; 1961 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1962 1963 if (likely(skb != NULL)) { 1964 pkts_compl++; 1965 bytes_compl += skb->len; 1966 dev_consume_skb_any(skb); 1967 tx_q->tx_skbuff[entry] = NULL; 1968 } 1969 1970 stmmac_release_tx_desc(priv, p, priv->mode); 1971 1972 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1973 } 1974 tx_q->dirty_tx = entry; 1975 1976 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1977 pkts_compl, bytes_compl); 1978 1979 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1980 queue))) && 1981 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1982 1983 netif_dbg(priv, tx_done, priv->dev, 1984 "%s: restart transmit\n", __func__); 1985 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1986 } 1987 1988 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1989 stmmac_enable_eee_mode(priv); 1990 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1991 } 1992 1993 /* We still have pending packets, let's call for a new scheduling */ 1994 if (tx_q->dirty_tx != tx_q->cur_tx) 1995 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1996 1997 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 1998 1999 return count; 2000 } 2001 2002 /** 2003 * stmmac_tx_err - to manage the tx error 2004 * @priv: driver private structure 2005 * @chan: channel index 2006 * Description: it cleans the descriptors and restarts the transmission 2007 * in case of transmission errors. 2008 */ 2009 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2010 { 2011 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2012 2013 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2014 2015 stmmac_stop_tx_dma(priv, chan); 2016 dma_free_tx_skbufs(priv, chan); 2017 stmmac_clear_tx_descriptors(priv, chan); 2018 tx_q->dirty_tx = 0; 2019 tx_q->cur_tx = 0; 2020 tx_q->mss = 0; 2021 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2022 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2023 tx_q->dma_tx_phy, chan); 2024 stmmac_start_tx_dma(priv, chan); 2025 2026 priv->dev->stats.tx_errors++; 2027 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2028 } 2029 2030 /** 2031 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2032 * @priv: driver private structure 2033 * @txmode: TX operating mode 2034 * @rxmode: RX operating mode 2035 * @chan: channel index 2036 * Description: it is used for configuring of the DMA operation mode in 2037 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2038 * mode. 2039 */ 2040 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2041 u32 rxmode, u32 chan) 2042 { 2043 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2044 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2045 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2046 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2047 int rxfifosz = priv->plat->rx_fifo_size; 2048 int txfifosz = priv->plat->tx_fifo_size; 2049 2050 if (rxfifosz == 0) 2051 rxfifosz = priv->dma_cap.rx_fifo_size; 2052 if (txfifosz == 0) 2053 txfifosz = priv->dma_cap.tx_fifo_size; 2054 2055 /* Adjust for real per queue fifo size */ 2056 rxfifosz /= rx_channels_count; 2057 txfifosz /= tx_channels_count; 2058 2059 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2060 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2061 } 2062 2063 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2064 { 2065 int ret; 2066 2067 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2068 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2069 if (ret && (ret != -EINVAL)) { 2070 stmmac_global_err(priv); 2071 return true; 2072 } 2073 2074 return false; 2075 } 2076 2077 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2078 { 2079 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2080 &priv->xstats, chan); 2081 struct stmmac_channel *ch = &priv->channel[chan]; 2082 unsigned long flags; 2083 2084 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2085 if (napi_schedule_prep(&ch->rx_napi)) { 2086 spin_lock_irqsave(&ch->lock, flags); 2087 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2088 spin_unlock_irqrestore(&ch->lock, flags); 2089 __napi_schedule_irqoff(&ch->rx_napi); 2090 } 2091 } 2092 2093 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2094 if (napi_schedule_prep(&ch->tx_napi)) { 2095 spin_lock_irqsave(&ch->lock, flags); 2096 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2097 spin_unlock_irqrestore(&ch->lock, flags); 2098 __napi_schedule_irqoff(&ch->tx_napi); 2099 } 2100 } 2101 2102 return status; 2103 } 2104 2105 /** 2106 * stmmac_dma_interrupt - DMA ISR 2107 * @priv: driver private structure 2108 * Description: this is the DMA ISR. It is called by the main ISR. 2109 * It calls the dwmac dma routine and schedule poll method in case of some 2110 * work can be done. 2111 */ 2112 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2113 { 2114 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2115 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2116 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2117 tx_channel_count : rx_channel_count; 2118 u32 chan; 2119 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2120 2121 /* Make sure we never check beyond our status buffer. */ 2122 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2123 channels_to_check = ARRAY_SIZE(status); 2124 2125 for (chan = 0; chan < channels_to_check; chan++) 2126 status[chan] = stmmac_napi_check(priv, chan); 2127 2128 for (chan = 0; chan < tx_channel_count; chan++) { 2129 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2130 /* Try to bump up the dma threshold on this failure */ 2131 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2132 (tc <= 256)) { 2133 tc += 64; 2134 if (priv->plat->force_thresh_dma_mode) 2135 stmmac_set_dma_operation_mode(priv, 2136 tc, 2137 tc, 2138 chan); 2139 else 2140 stmmac_set_dma_operation_mode(priv, 2141 tc, 2142 SF_DMA_MODE, 2143 chan); 2144 priv->xstats.threshold = tc; 2145 } 2146 } else if (unlikely(status[chan] == tx_hard_error)) { 2147 stmmac_tx_err(priv, chan); 2148 } 2149 } 2150 } 2151 2152 /** 2153 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2154 * @priv: driver private structure 2155 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2156 */ 2157 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2158 { 2159 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2160 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2161 2162 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2163 2164 if (priv->dma_cap.rmon) { 2165 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2166 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2167 } else 2168 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2169 } 2170 2171 /** 2172 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2173 * @priv: driver private structure 2174 * Description: 2175 * new GMAC chip generations have a new register to indicate the 2176 * presence of the optional feature/functions. 2177 * This can be also used to override the value passed through the 2178 * platform and necessary for old MAC10/100 and GMAC chips. 2179 */ 2180 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2181 { 2182 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2183 } 2184 2185 /** 2186 * stmmac_check_ether_addr - check if the MAC addr is valid 2187 * @priv: driver private structure 2188 * Description: 2189 * it is to verify if the MAC address is valid, in case of failures it 2190 * generates a random MAC address 2191 */ 2192 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2193 { 2194 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2195 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2196 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2197 eth_hw_addr_random(priv->dev); 2198 dev_info(priv->device, "device MAC address %pM\n", 2199 priv->dev->dev_addr); 2200 } 2201 } 2202 2203 /** 2204 * stmmac_init_dma_engine - DMA init. 2205 * @priv: driver private structure 2206 * Description: 2207 * It inits the DMA invoking the specific MAC/GMAC callback. 2208 * Some DMA parameters can be passed from the platform; 2209 * in case of these are not passed a default is kept for the MAC or GMAC. 2210 */ 2211 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2212 { 2213 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2214 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2215 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2216 struct stmmac_rx_queue *rx_q; 2217 struct stmmac_tx_queue *tx_q; 2218 u32 chan = 0; 2219 int atds = 0; 2220 int ret = 0; 2221 2222 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2223 dev_err(priv->device, "Invalid DMA configuration\n"); 2224 return -EINVAL; 2225 } 2226 2227 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2228 atds = 1; 2229 2230 ret = stmmac_reset(priv, priv->ioaddr); 2231 if (ret) { 2232 dev_err(priv->device, "Failed to reset the dma\n"); 2233 return ret; 2234 } 2235 2236 /* DMA Configuration */ 2237 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2238 2239 if (priv->plat->axi) 2240 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2241 2242 /* DMA CSR Channel configuration */ 2243 for (chan = 0; chan < dma_csr_ch; chan++) 2244 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2245 2246 /* DMA RX Channel Configuration */ 2247 for (chan = 0; chan < rx_channels_count; chan++) { 2248 rx_q = &priv->rx_queue[chan]; 2249 2250 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2251 rx_q->dma_rx_phy, chan); 2252 2253 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2254 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2255 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2256 rx_q->rx_tail_addr, chan); 2257 } 2258 2259 /* DMA TX Channel Configuration */ 2260 for (chan = 0; chan < tx_channels_count; chan++) { 2261 tx_q = &priv->tx_queue[chan]; 2262 2263 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2264 tx_q->dma_tx_phy, chan); 2265 2266 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2267 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2268 tx_q->tx_tail_addr, chan); 2269 } 2270 2271 return ret; 2272 } 2273 2274 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2275 { 2276 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2277 2278 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2279 } 2280 2281 /** 2282 * stmmac_tx_timer - mitigation sw timer for tx. 2283 * @data: data pointer 2284 * Description: 2285 * This is the timer handler to directly invoke the stmmac_tx_clean. 2286 */ 2287 static void stmmac_tx_timer(struct timer_list *t) 2288 { 2289 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2290 struct stmmac_priv *priv = tx_q->priv_data; 2291 struct stmmac_channel *ch; 2292 2293 ch = &priv->channel[tx_q->queue_index]; 2294 2295 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2296 unsigned long flags; 2297 2298 spin_lock_irqsave(&ch->lock, flags); 2299 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2300 spin_unlock_irqrestore(&ch->lock, flags); 2301 __napi_schedule(&ch->tx_napi); 2302 } 2303 } 2304 2305 /** 2306 * stmmac_init_coalesce - init mitigation options. 2307 * @priv: driver private structure 2308 * Description: 2309 * This inits the coalesce parameters: i.e. timer rate, 2310 * timer handler and default threshold used for enabling the 2311 * interrupt on completion bit. 2312 */ 2313 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2314 { 2315 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2316 u32 chan; 2317 2318 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2319 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2320 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2321 2322 for (chan = 0; chan < tx_channel_count; chan++) { 2323 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2324 2325 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2326 } 2327 } 2328 2329 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2330 { 2331 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2332 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2333 u32 chan; 2334 2335 /* set TX ring length */ 2336 for (chan = 0; chan < tx_channels_count; chan++) 2337 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2338 (DMA_TX_SIZE - 1), chan); 2339 2340 /* set RX ring length */ 2341 for (chan = 0; chan < rx_channels_count; chan++) 2342 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2343 (DMA_RX_SIZE - 1), chan); 2344 } 2345 2346 /** 2347 * stmmac_set_tx_queue_weight - Set TX queue weight 2348 * @priv: driver private structure 2349 * Description: It is used for setting TX queues weight 2350 */ 2351 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2352 { 2353 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2354 u32 weight; 2355 u32 queue; 2356 2357 for (queue = 0; queue < tx_queues_count; queue++) { 2358 weight = priv->plat->tx_queues_cfg[queue].weight; 2359 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2360 } 2361 } 2362 2363 /** 2364 * stmmac_configure_cbs - Configure CBS in TX queue 2365 * @priv: driver private structure 2366 * Description: It is used for configuring CBS in AVB TX queues 2367 */ 2368 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2369 { 2370 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2371 u32 mode_to_use; 2372 u32 queue; 2373 2374 /* queue 0 is reserved for legacy traffic */ 2375 for (queue = 1; queue < tx_queues_count; queue++) { 2376 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2377 if (mode_to_use == MTL_QUEUE_DCB) 2378 continue; 2379 2380 stmmac_config_cbs(priv, priv->hw, 2381 priv->plat->tx_queues_cfg[queue].send_slope, 2382 priv->plat->tx_queues_cfg[queue].idle_slope, 2383 priv->plat->tx_queues_cfg[queue].high_credit, 2384 priv->plat->tx_queues_cfg[queue].low_credit, 2385 queue); 2386 } 2387 } 2388 2389 /** 2390 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2391 * @priv: driver private structure 2392 * Description: It is used for mapping RX queues to RX dma channels 2393 */ 2394 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2395 { 2396 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2397 u32 queue; 2398 u32 chan; 2399 2400 for (queue = 0; queue < rx_queues_count; queue++) { 2401 chan = priv->plat->rx_queues_cfg[queue].chan; 2402 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2403 } 2404 } 2405 2406 /** 2407 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2408 * @priv: driver private structure 2409 * Description: It is used for configuring the RX Queue Priority 2410 */ 2411 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2412 { 2413 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2414 u32 queue; 2415 u32 prio; 2416 2417 for (queue = 0; queue < rx_queues_count; queue++) { 2418 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2419 continue; 2420 2421 prio = priv->plat->rx_queues_cfg[queue].prio; 2422 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2423 } 2424 } 2425 2426 /** 2427 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2428 * @priv: driver private structure 2429 * Description: It is used for configuring the TX Queue Priority 2430 */ 2431 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2432 { 2433 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2434 u32 queue; 2435 u32 prio; 2436 2437 for (queue = 0; queue < tx_queues_count; queue++) { 2438 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2439 continue; 2440 2441 prio = priv->plat->tx_queues_cfg[queue].prio; 2442 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2443 } 2444 } 2445 2446 /** 2447 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2448 * @priv: driver private structure 2449 * Description: It is used for configuring the RX queue routing 2450 */ 2451 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2452 { 2453 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2454 u32 queue; 2455 u8 packet; 2456 2457 for (queue = 0; queue < rx_queues_count; queue++) { 2458 /* no specific packet type routing specified for the queue */ 2459 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2460 continue; 2461 2462 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2463 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2464 } 2465 } 2466 2467 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2468 { 2469 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2470 priv->rss.enable = false; 2471 return; 2472 } 2473 2474 if (priv->dev->features & NETIF_F_RXHASH) 2475 priv->rss.enable = true; 2476 else 2477 priv->rss.enable = false; 2478 2479 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2480 priv->plat->rx_queues_to_use); 2481 } 2482 2483 /** 2484 * stmmac_mtl_configuration - Configure MTL 2485 * @priv: driver private structure 2486 * Description: It is used for configurring MTL 2487 */ 2488 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2489 { 2490 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2491 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2492 2493 if (tx_queues_count > 1) 2494 stmmac_set_tx_queue_weight(priv); 2495 2496 /* Configure MTL RX algorithms */ 2497 if (rx_queues_count > 1) 2498 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2499 priv->plat->rx_sched_algorithm); 2500 2501 /* Configure MTL TX algorithms */ 2502 if (tx_queues_count > 1) 2503 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2504 priv->plat->tx_sched_algorithm); 2505 2506 /* Configure CBS in AVB TX queues */ 2507 if (tx_queues_count > 1) 2508 stmmac_configure_cbs(priv); 2509 2510 /* Map RX MTL to DMA channels */ 2511 stmmac_rx_queue_dma_chan_map(priv); 2512 2513 /* Enable MAC RX Queues */ 2514 stmmac_mac_enable_rx_queues(priv); 2515 2516 /* Set RX priorities */ 2517 if (rx_queues_count > 1) 2518 stmmac_mac_config_rx_queues_prio(priv); 2519 2520 /* Set TX priorities */ 2521 if (tx_queues_count > 1) 2522 stmmac_mac_config_tx_queues_prio(priv); 2523 2524 /* Set RX routing */ 2525 if (rx_queues_count > 1) 2526 stmmac_mac_config_rx_queues_routing(priv); 2527 2528 /* Receive Side Scaling */ 2529 if (rx_queues_count > 1) 2530 stmmac_mac_config_rss(priv); 2531 } 2532 2533 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2534 { 2535 if (priv->dma_cap.asp) { 2536 netdev_info(priv->dev, "Enabling Safety Features\n"); 2537 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2538 } else { 2539 netdev_info(priv->dev, "No Safety Features support found\n"); 2540 } 2541 } 2542 2543 /** 2544 * stmmac_hw_setup - setup mac in a usable state. 2545 * @dev : pointer to the device structure. 2546 * Description: 2547 * this is the main function to setup the HW in a usable state because the 2548 * dma engine is reset, the core registers are configured (e.g. AXI, 2549 * Checksum features, timers). The DMA is ready to start receiving and 2550 * transmitting. 2551 * Return value: 2552 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2553 * file on failure. 2554 */ 2555 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2556 { 2557 struct stmmac_priv *priv = netdev_priv(dev); 2558 u32 rx_cnt = priv->plat->rx_queues_to_use; 2559 u32 tx_cnt = priv->plat->tx_queues_to_use; 2560 u32 chan; 2561 int ret; 2562 2563 /* DMA initialization and SW reset */ 2564 ret = stmmac_init_dma_engine(priv); 2565 if (ret < 0) { 2566 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2567 __func__); 2568 return ret; 2569 } 2570 2571 /* Copy the MAC addr into the HW */ 2572 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2573 2574 /* PS and related bits will be programmed according to the speed */ 2575 if (priv->hw->pcs) { 2576 int speed = priv->plat->mac_port_sel_speed; 2577 2578 if ((speed == SPEED_10) || (speed == SPEED_100) || 2579 (speed == SPEED_1000)) { 2580 priv->hw->ps = speed; 2581 } else { 2582 dev_warn(priv->device, "invalid port speed\n"); 2583 priv->hw->ps = 0; 2584 } 2585 } 2586 2587 /* Initialize the MAC Core */ 2588 stmmac_core_init(priv, priv->hw, dev); 2589 2590 /* Initialize MTL*/ 2591 stmmac_mtl_configuration(priv); 2592 2593 /* Initialize Safety Features */ 2594 stmmac_safety_feat_configuration(priv); 2595 2596 ret = stmmac_rx_ipc(priv, priv->hw); 2597 if (!ret) { 2598 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2599 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2600 priv->hw->rx_csum = 0; 2601 } 2602 2603 /* Enable the MAC Rx/Tx */ 2604 stmmac_mac_set(priv, priv->ioaddr, true); 2605 2606 /* Set the HW DMA mode and the COE */ 2607 stmmac_dma_operation_mode(priv); 2608 2609 stmmac_mmc_setup(priv); 2610 2611 if (init_ptp) { 2612 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2613 if (ret < 0) 2614 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2615 2616 ret = stmmac_init_ptp(priv); 2617 if (ret == -EOPNOTSUPP) 2618 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2619 else if (ret) 2620 netdev_warn(priv->dev, "PTP init failed\n"); 2621 } 2622 2623 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2624 2625 if (priv->use_riwt) { 2626 if (!priv->rx_riwt) 2627 priv->rx_riwt = DEF_DMA_RIWT; 2628 2629 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2630 } 2631 2632 if (priv->hw->pcs) 2633 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2634 2635 /* set TX and RX rings length */ 2636 stmmac_set_rings_length(priv); 2637 2638 /* Enable TSO */ 2639 if (priv->tso) { 2640 for (chan = 0; chan < tx_cnt; chan++) 2641 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2642 } 2643 2644 /* Enable Split Header */ 2645 if (priv->sph && priv->hw->rx_csum) { 2646 for (chan = 0; chan < rx_cnt; chan++) 2647 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2648 } 2649 2650 /* VLAN Tag Insertion */ 2651 if (priv->dma_cap.vlins) 2652 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2653 2654 /* TBS */ 2655 for (chan = 0; chan < tx_cnt; chan++) { 2656 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2657 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2658 2659 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2660 } 2661 2662 /* Start the ball rolling... */ 2663 stmmac_start_all_dma(priv); 2664 2665 return 0; 2666 } 2667 2668 static void stmmac_hw_teardown(struct net_device *dev) 2669 { 2670 struct stmmac_priv *priv = netdev_priv(dev); 2671 2672 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2673 } 2674 2675 /** 2676 * stmmac_open - open entry point of the driver 2677 * @dev : pointer to the device structure. 2678 * Description: 2679 * This function is the open entry point of the driver. 2680 * Return value: 2681 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2682 * file on failure. 2683 */ 2684 static int stmmac_open(struct net_device *dev) 2685 { 2686 struct stmmac_priv *priv = netdev_priv(dev); 2687 int bfsize = 0; 2688 u32 chan; 2689 int ret; 2690 2691 if (priv->hw->pcs != STMMAC_PCS_TBI && 2692 priv->hw->pcs != STMMAC_PCS_RTBI) { 2693 ret = stmmac_init_phy(dev); 2694 if (ret) { 2695 netdev_err(priv->dev, 2696 "%s: Cannot attach to PHY (error: %d)\n", 2697 __func__, ret); 2698 return ret; 2699 } 2700 } 2701 2702 /* Extra statistics */ 2703 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2704 priv->xstats.threshold = tc; 2705 2706 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2707 if (bfsize < 0) 2708 bfsize = 0; 2709 2710 if (bfsize < BUF_SIZE_16KiB) 2711 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2712 2713 priv->dma_buf_sz = bfsize; 2714 buf_sz = bfsize; 2715 2716 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2717 2718 /* Earlier check for TBS */ 2719 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2720 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2721 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2722 2723 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2724 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2725 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2726 } 2727 2728 ret = alloc_dma_desc_resources(priv); 2729 if (ret < 0) { 2730 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2731 __func__); 2732 goto dma_desc_error; 2733 } 2734 2735 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2736 if (ret < 0) { 2737 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2738 __func__); 2739 goto init_error; 2740 } 2741 2742 ret = stmmac_hw_setup(dev, true); 2743 if (ret < 0) { 2744 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2745 goto init_error; 2746 } 2747 2748 stmmac_init_coalesce(priv); 2749 2750 phylink_start(priv->phylink); 2751 2752 /* Request the IRQ lines */ 2753 ret = request_irq(dev->irq, stmmac_interrupt, 2754 IRQF_SHARED, dev->name, dev); 2755 if (unlikely(ret < 0)) { 2756 netdev_err(priv->dev, 2757 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2758 __func__, dev->irq, ret); 2759 goto irq_error; 2760 } 2761 2762 /* Request the Wake IRQ in case of another line is used for WoL */ 2763 if (priv->wol_irq != dev->irq) { 2764 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2765 IRQF_SHARED, dev->name, dev); 2766 if (unlikely(ret < 0)) { 2767 netdev_err(priv->dev, 2768 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2769 __func__, priv->wol_irq, ret); 2770 goto wolirq_error; 2771 } 2772 } 2773 2774 /* Request the IRQ lines */ 2775 if (priv->lpi_irq > 0) { 2776 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2777 dev->name, dev); 2778 if (unlikely(ret < 0)) { 2779 netdev_err(priv->dev, 2780 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2781 __func__, priv->lpi_irq, ret); 2782 goto lpiirq_error; 2783 } 2784 } 2785 2786 stmmac_enable_all_queues(priv); 2787 stmmac_start_all_queues(priv); 2788 2789 return 0; 2790 2791 lpiirq_error: 2792 if (priv->wol_irq != dev->irq) 2793 free_irq(priv->wol_irq, dev); 2794 wolirq_error: 2795 free_irq(dev->irq, dev); 2796 irq_error: 2797 phylink_stop(priv->phylink); 2798 2799 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2800 del_timer_sync(&priv->tx_queue[chan].txtimer); 2801 2802 stmmac_hw_teardown(dev); 2803 init_error: 2804 free_dma_desc_resources(priv); 2805 dma_desc_error: 2806 phylink_disconnect_phy(priv->phylink); 2807 return ret; 2808 } 2809 2810 /** 2811 * stmmac_release - close entry point of the driver 2812 * @dev : device pointer. 2813 * Description: 2814 * This is the stop entry point of the driver. 2815 */ 2816 static int stmmac_release(struct net_device *dev) 2817 { 2818 struct stmmac_priv *priv = netdev_priv(dev); 2819 u32 chan; 2820 2821 if (priv->eee_enabled) 2822 del_timer_sync(&priv->eee_ctrl_timer); 2823 2824 /* Stop and disconnect the PHY */ 2825 phylink_stop(priv->phylink); 2826 phylink_disconnect_phy(priv->phylink); 2827 2828 stmmac_stop_all_queues(priv); 2829 2830 stmmac_disable_all_queues(priv); 2831 2832 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2833 del_timer_sync(&priv->tx_queue[chan].txtimer); 2834 2835 /* Free the IRQ lines */ 2836 free_irq(dev->irq, dev); 2837 if (priv->wol_irq != dev->irq) 2838 free_irq(priv->wol_irq, dev); 2839 if (priv->lpi_irq > 0) 2840 free_irq(priv->lpi_irq, dev); 2841 2842 /* Stop TX/RX DMA and clear the descriptors */ 2843 stmmac_stop_all_dma(priv); 2844 2845 /* Release and free the Rx/Tx resources */ 2846 free_dma_desc_resources(priv); 2847 2848 /* Disable the MAC Rx/Tx */ 2849 stmmac_mac_set(priv, priv->ioaddr, false); 2850 2851 netif_carrier_off(dev); 2852 2853 stmmac_release_ptp(priv); 2854 2855 return 0; 2856 } 2857 2858 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2859 struct stmmac_tx_queue *tx_q) 2860 { 2861 u16 tag = 0x0, inner_tag = 0x0; 2862 u32 inner_type = 0x0; 2863 struct dma_desc *p; 2864 2865 if (!priv->dma_cap.vlins) 2866 return false; 2867 if (!skb_vlan_tag_present(skb)) 2868 return false; 2869 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2870 inner_tag = skb_vlan_tag_get(skb); 2871 inner_type = STMMAC_VLAN_INSERT; 2872 } 2873 2874 tag = skb_vlan_tag_get(skb); 2875 2876 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2877 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2878 else 2879 p = &tx_q->dma_tx[tx_q->cur_tx]; 2880 2881 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2882 return false; 2883 2884 stmmac_set_tx_owner(priv, p); 2885 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2886 return true; 2887 } 2888 2889 /** 2890 * stmmac_tso_allocator - close entry point of the driver 2891 * @priv: driver private structure 2892 * @des: buffer start address 2893 * @total_len: total length to fill in descriptors 2894 * @last_segmant: condition for the last descriptor 2895 * @queue: TX queue index 2896 * Description: 2897 * This function fills descriptor and request new descriptors according to 2898 * buffer length to fill 2899 */ 2900 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2901 int total_len, bool last_segment, u32 queue) 2902 { 2903 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2904 struct dma_desc *desc; 2905 u32 buff_size; 2906 int tmp_len; 2907 2908 tmp_len = total_len; 2909 2910 while (tmp_len > 0) { 2911 dma_addr_t curr_addr; 2912 2913 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2914 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2915 2916 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2917 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 2918 else 2919 desc = &tx_q->dma_tx[tx_q->cur_tx]; 2920 2921 curr_addr = des + (total_len - tmp_len); 2922 if (priv->dma_cap.addr64 <= 32) 2923 desc->des0 = cpu_to_le32(curr_addr); 2924 else 2925 stmmac_set_desc_addr(priv, desc, curr_addr); 2926 2927 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2928 TSO_MAX_BUFF_SIZE : tmp_len; 2929 2930 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2931 0, 1, 2932 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2933 0, 0); 2934 2935 tmp_len -= TSO_MAX_BUFF_SIZE; 2936 } 2937 } 2938 2939 /** 2940 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2941 * @skb : the socket buffer 2942 * @dev : device pointer 2943 * Description: this is the transmit function that is called on TSO frames 2944 * (support available on GMAC4 and newer chips). 2945 * Diagram below show the ring programming in case of TSO frames: 2946 * 2947 * First Descriptor 2948 * -------- 2949 * | DES0 |---> buffer1 = L2/L3/L4 header 2950 * | DES1 |---> TCP Payload (can continue on next descr...) 2951 * | DES2 |---> buffer 1 and 2 len 2952 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2953 * -------- 2954 * | 2955 * ... 2956 * | 2957 * -------- 2958 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2959 * | DES1 | --| 2960 * | DES2 | --> buffer 1 and 2 len 2961 * | DES3 | 2962 * -------- 2963 * 2964 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2965 */ 2966 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2967 { 2968 struct dma_desc *desc, *first, *mss_desc = NULL; 2969 struct stmmac_priv *priv = netdev_priv(dev); 2970 int desc_size, tmp_pay_len = 0, first_tx; 2971 int nfrags = skb_shinfo(skb)->nr_frags; 2972 u32 queue = skb_get_queue_mapping(skb); 2973 unsigned int first_entry, tx_packets; 2974 struct stmmac_tx_queue *tx_q; 2975 bool has_vlan, set_ic; 2976 u8 proto_hdr_len, hdr; 2977 u32 pay_len, mss; 2978 dma_addr_t des; 2979 int i; 2980 2981 tx_q = &priv->tx_queue[queue]; 2982 first_tx = tx_q->cur_tx; 2983 2984 /* Compute header lengths */ 2985 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 2986 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 2987 hdr = sizeof(struct udphdr); 2988 } else { 2989 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2990 hdr = tcp_hdrlen(skb); 2991 } 2992 2993 /* Desc availability based on threshold should be enough safe */ 2994 if (unlikely(stmmac_tx_avail(priv, queue) < 2995 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2996 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 2997 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 2998 queue)); 2999 /* This is a hard error, log it. */ 3000 netdev_err(priv->dev, 3001 "%s: Tx Ring full when queue awake\n", 3002 __func__); 3003 } 3004 return NETDEV_TX_BUSY; 3005 } 3006 3007 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3008 3009 mss = skb_shinfo(skb)->gso_size; 3010 3011 /* set new MSS value if needed */ 3012 if (mss != tx_q->mss) { 3013 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3014 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3015 else 3016 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3017 3018 stmmac_set_mss(priv, mss_desc, mss); 3019 tx_q->mss = mss; 3020 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3021 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3022 } 3023 3024 if (netif_msg_tx_queued(priv)) { 3025 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3026 __func__, hdr, proto_hdr_len, pay_len, mss); 3027 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3028 skb->data_len); 3029 } 3030 3031 /* Check if VLAN can be inserted by HW */ 3032 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3033 3034 first_entry = tx_q->cur_tx; 3035 WARN_ON(tx_q->tx_skbuff[first_entry]); 3036 3037 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3038 desc = &tx_q->dma_entx[first_entry].basic; 3039 else 3040 desc = &tx_q->dma_tx[first_entry]; 3041 first = desc; 3042 3043 if (has_vlan) 3044 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3045 3046 /* first descriptor: fill Headers on Buf1 */ 3047 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3048 DMA_TO_DEVICE); 3049 if (dma_mapping_error(priv->device, des)) 3050 goto dma_map_err; 3051 3052 tx_q->tx_skbuff_dma[first_entry].buf = des; 3053 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3054 3055 if (priv->dma_cap.addr64 <= 32) { 3056 first->des0 = cpu_to_le32(des); 3057 3058 /* Fill start of payload in buff2 of first descriptor */ 3059 if (pay_len) 3060 first->des1 = cpu_to_le32(des + proto_hdr_len); 3061 3062 /* If needed take extra descriptors to fill the remaining payload */ 3063 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3064 } else { 3065 stmmac_set_desc_addr(priv, first, des); 3066 tmp_pay_len = pay_len; 3067 des += proto_hdr_len; 3068 pay_len = 0; 3069 } 3070 3071 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3072 3073 /* Prepare fragments */ 3074 for (i = 0; i < nfrags; i++) { 3075 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3076 3077 des = skb_frag_dma_map(priv->device, frag, 0, 3078 skb_frag_size(frag), 3079 DMA_TO_DEVICE); 3080 if (dma_mapping_error(priv->device, des)) 3081 goto dma_map_err; 3082 3083 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3084 (i == nfrags - 1), queue); 3085 3086 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3087 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3088 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3089 } 3090 3091 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3092 3093 /* Only the last descriptor gets to point to the skb. */ 3094 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3095 3096 /* Manage tx mitigation */ 3097 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3098 tx_q->tx_count_frames += tx_packets; 3099 3100 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3101 set_ic = true; 3102 else if (!priv->tx_coal_frames) 3103 set_ic = false; 3104 else if (tx_packets > priv->tx_coal_frames) 3105 set_ic = true; 3106 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3107 set_ic = true; 3108 else 3109 set_ic = false; 3110 3111 if (set_ic) { 3112 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3113 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3114 else 3115 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3116 3117 tx_q->tx_count_frames = 0; 3118 stmmac_set_tx_ic(priv, desc); 3119 priv->xstats.tx_set_ic_bit++; 3120 } 3121 3122 /* We've used all descriptors we need for this skb, however, 3123 * advance cur_tx so that it references a fresh descriptor. 3124 * ndo_start_xmit will fill this descriptor the next time it's 3125 * called and stmmac_tx_clean may clean up to this descriptor. 3126 */ 3127 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3128 3129 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3130 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3131 __func__); 3132 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3133 } 3134 3135 dev->stats.tx_bytes += skb->len; 3136 priv->xstats.tx_tso_frames++; 3137 priv->xstats.tx_tso_nfrags += nfrags; 3138 3139 if (priv->sarc_type) 3140 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3141 3142 skb_tx_timestamp(skb); 3143 3144 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3145 priv->hwts_tx_en)) { 3146 /* declare that device is doing timestamping */ 3147 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3148 stmmac_enable_tx_timestamp(priv, first); 3149 } 3150 3151 /* Complete the first descriptor before granting the DMA */ 3152 stmmac_prepare_tso_tx_desc(priv, first, 1, 3153 proto_hdr_len, 3154 pay_len, 3155 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3156 hdr / 4, (skb->len - proto_hdr_len)); 3157 3158 /* If context desc is used to change MSS */ 3159 if (mss_desc) { 3160 /* Make sure that first descriptor has been completely 3161 * written, including its own bit. This is because MSS is 3162 * actually before first descriptor, so we need to make 3163 * sure that MSS's own bit is the last thing written. 3164 */ 3165 dma_wmb(); 3166 stmmac_set_tx_owner(priv, mss_desc); 3167 } 3168 3169 /* The own bit must be the latest setting done when prepare the 3170 * descriptor and then barrier is needed to make sure that 3171 * all is coherent before granting the DMA engine. 3172 */ 3173 wmb(); 3174 3175 if (netif_msg_pktdata(priv)) { 3176 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3177 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3178 tx_q->cur_tx, first, nfrags); 3179 pr_info(">>> frame to be transmitted: "); 3180 print_pkt(skb->data, skb_headlen(skb)); 3181 } 3182 3183 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3184 3185 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3186 desc_size = sizeof(struct dma_edesc); 3187 else 3188 desc_size = sizeof(struct dma_desc); 3189 3190 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3191 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3192 stmmac_tx_timer_arm(priv, queue); 3193 3194 return NETDEV_TX_OK; 3195 3196 dma_map_err: 3197 dev_err(priv->device, "Tx dma map failed\n"); 3198 dev_kfree_skb(skb); 3199 priv->dev->stats.tx_dropped++; 3200 return NETDEV_TX_OK; 3201 } 3202 3203 /** 3204 * stmmac_xmit - Tx entry point of the driver 3205 * @skb : the socket buffer 3206 * @dev : device pointer 3207 * Description : this is the tx entry point of the driver. 3208 * It programs the chain or the ring and supports oversized frames 3209 * and SG feature. 3210 */ 3211 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3212 { 3213 unsigned int first_entry, tx_packets, enh_desc; 3214 struct stmmac_priv *priv = netdev_priv(dev); 3215 unsigned int nopaged_len = skb_headlen(skb); 3216 int i, csum_insertion = 0, is_jumbo = 0; 3217 u32 queue = skb_get_queue_mapping(skb); 3218 int nfrags = skb_shinfo(skb)->nr_frags; 3219 int gso = skb_shinfo(skb)->gso_type; 3220 struct dma_edesc *tbs_desc = NULL; 3221 int entry, desc_size, first_tx; 3222 struct dma_desc *desc, *first; 3223 struct stmmac_tx_queue *tx_q; 3224 bool has_vlan, set_ic; 3225 dma_addr_t des; 3226 3227 tx_q = &priv->tx_queue[queue]; 3228 first_tx = tx_q->cur_tx; 3229 3230 if (priv->tx_path_in_lpi_mode) 3231 stmmac_disable_eee_mode(priv); 3232 3233 /* Manage oversized TCP frames for GMAC4 device */ 3234 if (skb_is_gso(skb) && priv->tso) { 3235 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3236 return stmmac_tso_xmit(skb, dev); 3237 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3238 return stmmac_tso_xmit(skb, dev); 3239 } 3240 3241 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3242 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3243 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3244 queue)); 3245 /* This is a hard error, log it. */ 3246 netdev_err(priv->dev, 3247 "%s: Tx Ring full when queue awake\n", 3248 __func__); 3249 } 3250 return NETDEV_TX_BUSY; 3251 } 3252 3253 /* Check if VLAN can be inserted by HW */ 3254 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3255 3256 entry = tx_q->cur_tx; 3257 first_entry = entry; 3258 WARN_ON(tx_q->tx_skbuff[first_entry]); 3259 3260 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3261 3262 if (likely(priv->extend_desc)) 3263 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3264 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3265 desc = &tx_q->dma_entx[entry].basic; 3266 else 3267 desc = tx_q->dma_tx + entry; 3268 3269 first = desc; 3270 3271 if (has_vlan) 3272 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3273 3274 enh_desc = priv->plat->enh_desc; 3275 /* To program the descriptors according to the size of the frame */ 3276 if (enh_desc) 3277 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3278 3279 if (unlikely(is_jumbo)) { 3280 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3281 if (unlikely(entry < 0) && (entry != -EINVAL)) 3282 goto dma_map_err; 3283 } 3284 3285 for (i = 0; i < nfrags; i++) { 3286 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3287 int len = skb_frag_size(frag); 3288 bool last_segment = (i == (nfrags - 1)); 3289 3290 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3291 WARN_ON(tx_q->tx_skbuff[entry]); 3292 3293 if (likely(priv->extend_desc)) 3294 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3295 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3296 desc = &tx_q->dma_entx[entry].basic; 3297 else 3298 desc = tx_q->dma_tx + entry; 3299 3300 des = skb_frag_dma_map(priv->device, frag, 0, len, 3301 DMA_TO_DEVICE); 3302 if (dma_mapping_error(priv->device, des)) 3303 goto dma_map_err; /* should reuse desc w/o issues */ 3304 3305 tx_q->tx_skbuff_dma[entry].buf = des; 3306 3307 stmmac_set_desc_addr(priv, desc, des); 3308 3309 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3310 tx_q->tx_skbuff_dma[entry].len = len; 3311 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3312 3313 /* Prepare the descriptor and set the own bit too */ 3314 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3315 priv->mode, 1, last_segment, skb->len); 3316 } 3317 3318 /* Only the last descriptor gets to point to the skb. */ 3319 tx_q->tx_skbuff[entry] = skb; 3320 3321 /* According to the coalesce parameter the IC bit for the latest 3322 * segment is reset and the timer re-started to clean the tx status. 3323 * This approach takes care about the fragments: desc is the first 3324 * element in case of no SG. 3325 */ 3326 tx_packets = (entry + 1) - first_tx; 3327 tx_q->tx_count_frames += tx_packets; 3328 3329 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3330 set_ic = true; 3331 else if (!priv->tx_coal_frames) 3332 set_ic = false; 3333 else if (tx_packets > priv->tx_coal_frames) 3334 set_ic = true; 3335 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3336 set_ic = true; 3337 else 3338 set_ic = false; 3339 3340 if (set_ic) { 3341 if (likely(priv->extend_desc)) 3342 desc = &tx_q->dma_etx[entry].basic; 3343 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3344 desc = &tx_q->dma_entx[entry].basic; 3345 else 3346 desc = &tx_q->dma_tx[entry]; 3347 3348 tx_q->tx_count_frames = 0; 3349 stmmac_set_tx_ic(priv, desc); 3350 priv->xstats.tx_set_ic_bit++; 3351 } 3352 3353 /* We've used all descriptors we need for this skb, however, 3354 * advance cur_tx so that it references a fresh descriptor. 3355 * ndo_start_xmit will fill this descriptor the next time it's 3356 * called and stmmac_tx_clean may clean up to this descriptor. 3357 */ 3358 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3359 tx_q->cur_tx = entry; 3360 3361 if (netif_msg_pktdata(priv)) { 3362 netdev_dbg(priv->dev, 3363 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3364 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3365 entry, first, nfrags); 3366 3367 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3368 print_pkt(skb->data, skb->len); 3369 } 3370 3371 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3372 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3373 __func__); 3374 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3375 } 3376 3377 dev->stats.tx_bytes += skb->len; 3378 3379 if (priv->sarc_type) 3380 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3381 3382 skb_tx_timestamp(skb); 3383 3384 /* Ready to fill the first descriptor and set the OWN bit w/o any 3385 * problems because all the descriptors are actually ready to be 3386 * passed to the DMA engine. 3387 */ 3388 if (likely(!is_jumbo)) { 3389 bool last_segment = (nfrags == 0); 3390 3391 des = dma_map_single(priv->device, skb->data, 3392 nopaged_len, DMA_TO_DEVICE); 3393 if (dma_mapping_error(priv->device, des)) 3394 goto dma_map_err; 3395 3396 tx_q->tx_skbuff_dma[first_entry].buf = des; 3397 3398 stmmac_set_desc_addr(priv, first, des); 3399 3400 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3401 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3402 3403 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3404 priv->hwts_tx_en)) { 3405 /* declare that device is doing timestamping */ 3406 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3407 stmmac_enable_tx_timestamp(priv, first); 3408 } 3409 3410 /* Prepare the first descriptor setting the OWN bit too */ 3411 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3412 csum_insertion, priv->mode, 0, last_segment, 3413 skb->len); 3414 } 3415 3416 if (tx_q->tbs & STMMAC_TBS_EN) { 3417 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3418 3419 tbs_desc = &tx_q->dma_entx[first_entry]; 3420 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3421 } 3422 3423 stmmac_set_tx_owner(priv, first); 3424 3425 /* The own bit must be the latest setting done when prepare the 3426 * descriptor and then barrier is needed to make sure that 3427 * all is coherent before granting the DMA engine. 3428 */ 3429 wmb(); 3430 3431 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3432 3433 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3434 3435 if (likely(priv->extend_desc)) 3436 desc_size = sizeof(struct dma_extended_desc); 3437 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3438 desc_size = sizeof(struct dma_edesc); 3439 else 3440 desc_size = sizeof(struct dma_desc); 3441 3442 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3443 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3444 stmmac_tx_timer_arm(priv, queue); 3445 3446 return NETDEV_TX_OK; 3447 3448 dma_map_err: 3449 netdev_err(priv->dev, "Tx DMA map failed\n"); 3450 dev_kfree_skb(skb); 3451 priv->dev->stats.tx_dropped++; 3452 return NETDEV_TX_OK; 3453 } 3454 3455 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3456 { 3457 struct vlan_ethhdr *veth; 3458 __be16 vlan_proto; 3459 u16 vlanid; 3460 3461 veth = (struct vlan_ethhdr *)skb->data; 3462 vlan_proto = veth->h_vlan_proto; 3463 3464 if ((vlan_proto == htons(ETH_P_8021Q) && 3465 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3466 (vlan_proto == htons(ETH_P_8021AD) && 3467 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3468 /* pop the vlan tag */ 3469 vlanid = ntohs(veth->h_vlan_TCI); 3470 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3471 skb_pull(skb, VLAN_HLEN); 3472 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3473 } 3474 } 3475 3476 3477 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3478 { 3479 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3480 return 0; 3481 3482 return 1; 3483 } 3484 3485 /** 3486 * stmmac_rx_refill - refill used skb preallocated buffers 3487 * @priv: driver private structure 3488 * @queue: RX queue index 3489 * Description : this is to reallocate the skb for the reception process 3490 * that is based on zero-copy. 3491 */ 3492 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3493 { 3494 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3495 int len, dirty = stmmac_rx_dirty(priv, queue); 3496 unsigned int entry = rx_q->dirty_rx; 3497 3498 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3499 3500 while (dirty-- > 0) { 3501 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3502 struct dma_desc *p; 3503 bool use_rx_wd; 3504 3505 if (priv->extend_desc) 3506 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3507 else 3508 p = rx_q->dma_rx + entry; 3509 3510 if (!buf->page) { 3511 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3512 if (!buf->page) 3513 break; 3514 } 3515 3516 if (priv->sph && !buf->sec_page) { 3517 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3518 if (!buf->sec_page) 3519 break; 3520 3521 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3522 3523 dma_sync_single_for_device(priv->device, buf->sec_addr, 3524 len, DMA_FROM_DEVICE); 3525 } 3526 3527 buf->addr = page_pool_get_dma_addr(buf->page); 3528 3529 /* Sync whole allocation to device. This will invalidate old 3530 * data. 3531 */ 3532 dma_sync_single_for_device(priv->device, buf->addr, len, 3533 DMA_FROM_DEVICE); 3534 3535 stmmac_set_desc_addr(priv, p, buf->addr); 3536 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3537 stmmac_refill_desc3(priv, rx_q, p); 3538 3539 rx_q->rx_count_frames++; 3540 rx_q->rx_count_frames += priv->rx_coal_frames; 3541 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3542 rx_q->rx_count_frames = 0; 3543 3544 use_rx_wd = !priv->rx_coal_frames; 3545 use_rx_wd |= rx_q->rx_count_frames > 0; 3546 if (!priv->use_riwt) 3547 use_rx_wd = false; 3548 3549 dma_wmb(); 3550 stmmac_set_rx_owner(priv, p, use_rx_wd); 3551 3552 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3553 } 3554 rx_q->dirty_rx = entry; 3555 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3556 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3557 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3558 } 3559 3560 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3561 struct dma_desc *p, 3562 int status, unsigned int len) 3563 { 3564 int ret, coe = priv->hw->rx_csum; 3565 unsigned int plen = 0, hlen = 0; 3566 3567 /* Not first descriptor, buffer is always zero */ 3568 if (priv->sph && len) 3569 return 0; 3570 3571 /* First descriptor, get split header length */ 3572 ret = stmmac_get_rx_header_len(priv, p, &hlen); 3573 if (priv->sph && hlen) { 3574 priv->xstats.rx_split_hdr_pkt_n++; 3575 return hlen; 3576 } 3577 3578 /* First descriptor, not last descriptor and not split header */ 3579 if (status & rx_not_ls) 3580 return priv->dma_buf_sz; 3581 3582 plen = stmmac_get_rx_frame_len(priv, p, coe); 3583 3584 /* First descriptor and last descriptor and not split header */ 3585 return min_t(unsigned int, priv->dma_buf_sz, plen); 3586 } 3587 3588 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3589 struct dma_desc *p, 3590 int status, unsigned int len) 3591 { 3592 int coe = priv->hw->rx_csum; 3593 unsigned int plen = 0; 3594 3595 /* Not split header, buffer is not available */ 3596 if (!priv->sph) 3597 return 0; 3598 3599 /* Not last descriptor */ 3600 if (status & rx_not_ls) 3601 return priv->dma_buf_sz; 3602 3603 plen = stmmac_get_rx_frame_len(priv, p, coe); 3604 3605 /* Last descriptor */ 3606 return plen - len; 3607 } 3608 3609 /** 3610 * stmmac_rx - manage the receive process 3611 * @priv: driver private structure 3612 * @limit: napi bugget 3613 * @queue: RX queue index. 3614 * Description : this the function called by the napi poll method. 3615 * It gets all the frames inside the ring. 3616 */ 3617 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3618 { 3619 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3620 struct stmmac_channel *ch = &priv->channel[queue]; 3621 unsigned int count = 0, error = 0, len = 0; 3622 int status = 0, coe = priv->hw->rx_csum; 3623 unsigned int next_entry = rx_q->cur_rx; 3624 struct sk_buff *skb = NULL; 3625 3626 if (netif_msg_rx_status(priv)) { 3627 void *rx_head; 3628 3629 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3630 if (priv->extend_desc) 3631 rx_head = (void *)rx_q->dma_erx; 3632 else 3633 rx_head = (void *)rx_q->dma_rx; 3634 3635 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3636 } 3637 while (count < limit) { 3638 unsigned int buf1_len = 0, buf2_len = 0; 3639 enum pkt_hash_types hash_type; 3640 struct stmmac_rx_buffer *buf; 3641 struct dma_desc *np, *p; 3642 int entry; 3643 u32 hash; 3644 3645 if (!count && rx_q->state_saved) { 3646 skb = rx_q->state.skb; 3647 error = rx_q->state.error; 3648 len = rx_q->state.len; 3649 } else { 3650 rx_q->state_saved = false; 3651 skb = NULL; 3652 error = 0; 3653 len = 0; 3654 } 3655 3656 if (count >= limit) 3657 break; 3658 3659 read_again: 3660 buf1_len = 0; 3661 buf2_len = 0; 3662 entry = next_entry; 3663 buf = &rx_q->buf_pool[entry]; 3664 3665 if (priv->extend_desc) 3666 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3667 else 3668 p = rx_q->dma_rx + entry; 3669 3670 /* read the status of the incoming frame */ 3671 status = stmmac_rx_status(priv, &priv->dev->stats, 3672 &priv->xstats, p); 3673 /* check if managed by the DMA otherwise go ahead */ 3674 if (unlikely(status & dma_own)) 3675 break; 3676 3677 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3678 next_entry = rx_q->cur_rx; 3679 3680 if (priv->extend_desc) 3681 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3682 else 3683 np = rx_q->dma_rx + next_entry; 3684 3685 prefetch(np); 3686 3687 if (priv->extend_desc) 3688 stmmac_rx_extended_status(priv, &priv->dev->stats, 3689 &priv->xstats, rx_q->dma_erx + entry); 3690 if (unlikely(status == discard_frame)) { 3691 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3692 buf->page = NULL; 3693 error = 1; 3694 if (!priv->hwts_rx_en) 3695 priv->dev->stats.rx_errors++; 3696 } 3697 3698 if (unlikely(error && (status & rx_not_ls))) 3699 goto read_again; 3700 if (unlikely(error)) { 3701 dev_kfree_skb(skb); 3702 skb = NULL; 3703 count++; 3704 continue; 3705 } 3706 3707 /* Buffer is good. Go on. */ 3708 3709 prefetch(page_address(buf->page)); 3710 if (buf->sec_page) 3711 prefetch(page_address(buf->sec_page)); 3712 3713 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3714 len += buf1_len; 3715 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3716 len += buf2_len; 3717 3718 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3719 * Type frames (LLC/LLC-SNAP) 3720 * 3721 * llc_snap is never checked in GMAC >= 4, so this ACS 3722 * feature is always disabled and packets need to be 3723 * stripped manually. 3724 */ 3725 if (likely(!(status & rx_not_ls)) && 3726 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3727 unlikely(status != llc_snap))) { 3728 if (buf2_len) 3729 buf2_len -= ETH_FCS_LEN; 3730 else 3731 buf1_len -= ETH_FCS_LEN; 3732 3733 len -= ETH_FCS_LEN; 3734 } 3735 3736 if (!skb) { 3737 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3738 if (!skb) { 3739 priv->dev->stats.rx_dropped++; 3740 count++; 3741 goto drain_data; 3742 } 3743 3744 dma_sync_single_for_cpu(priv->device, buf->addr, 3745 buf1_len, DMA_FROM_DEVICE); 3746 skb_copy_to_linear_data(skb, page_address(buf->page), 3747 buf1_len); 3748 skb_put(skb, buf1_len); 3749 3750 /* Data payload copied into SKB, page ready for recycle */ 3751 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3752 buf->page = NULL; 3753 } else if (buf1_len) { 3754 dma_sync_single_for_cpu(priv->device, buf->addr, 3755 buf1_len, DMA_FROM_DEVICE); 3756 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3757 buf->page, 0, buf1_len, 3758 priv->dma_buf_sz); 3759 3760 /* Data payload appended into SKB */ 3761 page_pool_release_page(rx_q->page_pool, buf->page); 3762 buf->page = NULL; 3763 } 3764 3765 if (buf2_len) { 3766 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3767 buf2_len, DMA_FROM_DEVICE); 3768 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3769 buf->sec_page, 0, buf2_len, 3770 priv->dma_buf_sz); 3771 3772 /* Data payload appended into SKB */ 3773 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3774 buf->sec_page = NULL; 3775 } 3776 3777 drain_data: 3778 if (likely(status & rx_not_ls)) 3779 goto read_again; 3780 if (!skb) 3781 continue; 3782 3783 /* Got entire packet into SKB. Finish it. */ 3784 3785 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3786 stmmac_rx_vlan(priv->dev, skb); 3787 skb->protocol = eth_type_trans(skb, priv->dev); 3788 3789 if (unlikely(!coe)) 3790 skb_checksum_none_assert(skb); 3791 else 3792 skb->ip_summed = CHECKSUM_UNNECESSARY; 3793 3794 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3795 skb_set_hash(skb, hash, hash_type); 3796 3797 skb_record_rx_queue(skb, queue); 3798 napi_gro_receive(&ch->rx_napi, skb); 3799 skb = NULL; 3800 3801 priv->dev->stats.rx_packets++; 3802 priv->dev->stats.rx_bytes += len; 3803 count++; 3804 } 3805 3806 if (status & rx_not_ls || skb) { 3807 rx_q->state_saved = true; 3808 rx_q->state.skb = skb; 3809 rx_q->state.error = error; 3810 rx_q->state.len = len; 3811 } 3812 3813 stmmac_rx_refill(priv, queue); 3814 3815 priv->xstats.rx_pkt_n += count; 3816 3817 return count; 3818 } 3819 3820 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3821 { 3822 struct stmmac_channel *ch = 3823 container_of(napi, struct stmmac_channel, rx_napi); 3824 struct stmmac_priv *priv = ch->priv_data; 3825 u32 chan = ch->index; 3826 int work_done; 3827 3828 priv->xstats.napi_poll++; 3829 3830 work_done = stmmac_rx(priv, budget, chan); 3831 if (work_done < budget && napi_complete_done(napi, work_done)) { 3832 unsigned long flags; 3833 3834 spin_lock_irqsave(&ch->lock, flags); 3835 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3836 spin_unlock_irqrestore(&ch->lock, flags); 3837 } 3838 3839 return work_done; 3840 } 3841 3842 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3843 { 3844 struct stmmac_channel *ch = 3845 container_of(napi, struct stmmac_channel, tx_napi); 3846 struct stmmac_priv *priv = ch->priv_data; 3847 u32 chan = ch->index; 3848 int work_done; 3849 3850 priv->xstats.napi_poll++; 3851 3852 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3853 work_done = min(work_done, budget); 3854 3855 if (work_done < budget && napi_complete_done(napi, work_done)) { 3856 unsigned long flags; 3857 3858 spin_lock_irqsave(&ch->lock, flags); 3859 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3860 spin_unlock_irqrestore(&ch->lock, flags); 3861 } 3862 3863 return work_done; 3864 } 3865 3866 /** 3867 * stmmac_tx_timeout 3868 * @dev : Pointer to net device structure 3869 * Description: this function is called when a packet transmission fails to 3870 * complete within a reasonable time. The driver will mark the error in the 3871 * netdev structure and arrange for the device to be reset to a sane state 3872 * in order to transmit a new packet. 3873 */ 3874 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3875 { 3876 struct stmmac_priv *priv = netdev_priv(dev); 3877 3878 stmmac_global_err(priv); 3879 } 3880 3881 /** 3882 * stmmac_set_rx_mode - entry point for multicast addressing 3883 * @dev : pointer to the device structure 3884 * Description: 3885 * This function is a driver entry point which gets called by the kernel 3886 * whenever multicast addresses must be enabled/disabled. 3887 * Return value: 3888 * void. 3889 */ 3890 static void stmmac_set_rx_mode(struct net_device *dev) 3891 { 3892 struct stmmac_priv *priv = netdev_priv(dev); 3893 3894 stmmac_set_filter(priv, priv->hw, dev); 3895 } 3896 3897 /** 3898 * stmmac_change_mtu - entry point to change MTU size for the device. 3899 * @dev : device pointer. 3900 * @new_mtu : the new MTU size for the device. 3901 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3902 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3903 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3904 * Return value: 3905 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3906 * file on failure. 3907 */ 3908 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3909 { 3910 struct stmmac_priv *priv = netdev_priv(dev); 3911 int txfifosz = priv->plat->tx_fifo_size; 3912 3913 if (txfifosz == 0) 3914 txfifosz = priv->dma_cap.tx_fifo_size; 3915 3916 txfifosz /= priv->plat->tx_queues_to_use; 3917 3918 if (netif_running(dev)) { 3919 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3920 return -EBUSY; 3921 } 3922 3923 new_mtu = STMMAC_ALIGN(new_mtu); 3924 3925 /* If condition true, FIFO is too small or MTU too large */ 3926 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 3927 return -EINVAL; 3928 3929 dev->mtu = new_mtu; 3930 3931 netdev_update_features(dev); 3932 3933 return 0; 3934 } 3935 3936 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3937 netdev_features_t features) 3938 { 3939 struct stmmac_priv *priv = netdev_priv(dev); 3940 3941 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3942 features &= ~NETIF_F_RXCSUM; 3943 3944 if (!priv->plat->tx_coe) 3945 features &= ~NETIF_F_CSUM_MASK; 3946 3947 /* Some GMAC devices have a bugged Jumbo frame support that 3948 * needs to have the Tx COE disabled for oversized frames 3949 * (due to limited buffer sizes). In this case we disable 3950 * the TX csum insertion in the TDES and not use SF. 3951 */ 3952 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3953 features &= ~NETIF_F_CSUM_MASK; 3954 3955 /* Disable tso if asked by ethtool */ 3956 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3957 if (features & NETIF_F_TSO) 3958 priv->tso = true; 3959 else 3960 priv->tso = false; 3961 } 3962 3963 return features; 3964 } 3965 3966 static int stmmac_set_features(struct net_device *netdev, 3967 netdev_features_t features) 3968 { 3969 struct stmmac_priv *priv = netdev_priv(netdev); 3970 bool sph_en; 3971 u32 chan; 3972 3973 /* Keep the COE Type in case of csum is supporting */ 3974 if (features & NETIF_F_RXCSUM) 3975 priv->hw->rx_csum = priv->plat->rx_coe; 3976 else 3977 priv->hw->rx_csum = 0; 3978 /* No check needed because rx_coe has been set before and it will be 3979 * fixed in case of issue. 3980 */ 3981 stmmac_rx_ipc(priv, priv->hw); 3982 3983 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3984 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 3985 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3986 3987 return 0; 3988 } 3989 3990 /** 3991 * stmmac_interrupt - main ISR 3992 * @irq: interrupt number. 3993 * @dev_id: to pass the net device pointer. 3994 * Description: this is the main driver interrupt service routine. 3995 * It can call: 3996 * o DMA service routine (to manage incoming frame reception and transmission 3997 * status) 3998 * o Core interrupts to manage: remote wake-up, management counter, LPI 3999 * interrupts. 4000 */ 4001 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4002 { 4003 struct net_device *dev = (struct net_device *)dev_id; 4004 struct stmmac_priv *priv = netdev_priv(dev); 4005 u32 rx_cnt = priv->plat->rx_queues_to_use; 4006 u32 tx_cnt = priv->plat->tx_queues_to_use; 4007 u32 queues_count; 4008 u32 queue; 4009 bool xmac; 4010 4011 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4012 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4013 4014 if (priv->irq_wake) 4015 pm_wakeup_event(priv->device, 0); 4016 4017 if (unlikely(!dev)) { 4018 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 4019 return IRQ_NONE; 4020 } 4021 4022 /* Check if adapter is up */ 4023 if (test_bit(STMMAC_DOWN, &priv->state)) 4024 return IRQ_HANDLED; 4025 /* Check if a fatal error happened */ 4026 if (stmmac_safety_feat_interrupt(priv)) 4027 return IRQ_HANDLED; 4028 4029 /* To handle GMAC own interrupts */ 4030 if ((priv->plat->has_gmac) || xmac) { 4031 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4032 int mtl_status; 4033 4034 if (unlikely(status)) { 4035 /* For LPI we need to save the tx status */ 4036 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4037 priv->tx_path_in_lpi_mode = true; 4038 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4039 priv->tx_path_in_lpi_mode = false; 4040 } 4041 4042 for (queue = 0; queue < queues_count; queue++) { 4043 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4044 4045 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4046 queue); 4047 if (mtl_status != -EINVAL) 4048 status |= mtl_status; 4049 4050 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4051 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4052 rx_q->rx_tail_addr, 4053 queue); 4054 } 4055 4056 /* PCS link status */ 4057 if (priv->hw->pcs) { 4058 if (priv->xstats.pcs_link) 4059 netif_carrier_on(dev); 4060 else 4061 netif_carrier_off(dev); 4062 } 4063 } 4064 4065 /* To handle DMA interrupts */ 4066 stmmac_dma_interrupt(priv); 4067 4068 return IRQ_HANDLED; 4069 } 4070 4071 #ifdef CONFIG_NET_POLL_CONTROLLER 4072 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4073 * to allow network I/O with interrupts disabled. 4074 */ 4075 static void stmmac_poll_controller(struct net_device *dev) 4076 { 4077 disable_irq(dev->irq); 4078 stmmac_interrupt(dev->irq, dev); 4079 enable_irq(dev->irq); 4080 } 4081 #endif 4082 4083 /** 4084 * stmmac_ioctl - Entry point for the Ioctl 4085 * @dev: Device pointer. 4086 * @rq: An IOCTL specefic structure, that can contain a pointer to 4087 * a proprietary structure used to pass information to the driver. 4088 * @cmd: IOCTL command 4089 * Description: 4090 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4091 */ 4092 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4093 { 4094 struct stmmac_priv *priv = netdev_priv (dev); 4095 int ret = -EOPNOTSUPP; 4096 4097 if (!netif_running(dev)) 4098 return -EINVAL; 4099 4100 switch (cmd) { 4101 case SIOCGMIIPHY: 4102 case SIOCGMIIREG: 4103 case SIOCSMIIREG: 4104 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4105 break; 4106 case SIOCSHWTSTAMP: 4107 ret = stmmac_hwtstamp_set(dev, rq); 4108 break; 4109 case SIOCGHWTSTAMP: 4110 ret = stmmac_hwtstamp_get(dev, rq); 4111 break; 4112 default: 4113 break; 4114 } 4115 4116 return ret; 4117 } 4118 4119 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4120 void *cb_priv) 4121 { 4122 struct stmmac_priv *priv = cb_priv; 4123 int ret = -EOPNOTSUPP; 4124 4125 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4126 return ret; 4127 4128 stmmac_disable_all_queues(priv); 4129 4130 switch (type) { 4131 case TC_SETUP_CLSU32: 4132 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4133 break; 4134 case TC_SETUP_CLSFLOWER: 4135 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4136 break; 4137 default: 4138 break; 4139 } 4140 4141 stmmac_enable_all_queues(priv); 4142 return ret; 4143 } 4144 4145 static LIST_HEAD(stmmac_block_cb_list); 4146 4147 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4148 void *type_data) 4149 { 4150 struct stmmac_priv *priv = netdev_priv(ndev); 4151 4152 switch (type) { 4153 case TC_SETUP_BLOCK: 4154 return flow_block_cb_setup_simple(type_data, 4155 &stmmac_block_cb_list, 4156 stmmac_setup_tc_block_cb, 4157 priv, priv, true); 4158 case TC_SETUP_QDISC_CBS: 4159 return stmmac_tc_setup_cbs(priv, priv, type_data); 4160 case TC_SETUP_QDISC_TAPRIO: 4161 return stmmac_tc_setup_taprio(priv, priv, type_data); 4162 case TC_SETUP_QDISC_ETF: 4163 return stmmac_tc_setup_etf(priv, priv, type_data); 4164 default: 4165 return -EOPNOTSUPP; 4166 } 4167 } 4168 4169 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4170 struct net_device *sb_dev) 4171 { 4172 int gso = skb_shinfo(skb)->gso_type; 4173 4174 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4175 /* 4176 * There is no way to determine the number of TSO/USO 4177 * capable Queues. Let's use always the Queue 0 4178 * because if TSO/USO is supported then at least this 4179 * one will be capable. 4180 */ 4181 return 0; 4182 } 4183 4184 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4185 } 4186 4187 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4188 { 4189 struct stmmac_priv *priv = netdev_priv(ndev); 4190 int ret = 0; 4191 4192 ret = eth_mac_addr(ndev, addr); 4193 if (ret) 4194 return ret; 4195 4196 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4197 4198 return ret; 4199 } 4200 4201 #ifdef CONFIG_DEBUG_FS 4202 static struct dentry *stmmac_fs_dir; 4203 4204 static void sysfs_display_ring(void *head, int size, int extend_desc, 4205 struct seq_file *seq) 4206 { 4207 int i; 4208 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4209 struct dma_desc *p = (struct dma_desc *)head; 4210 4211 for (i = 0; i < size; i++) { 4212 if (extend_desc) { 4213 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4214 i, (unsigned int)virt_to_phys(ep), 4215 le32_to_cpu(ep->basic.des0), 4216 le32_to_cpu(ep->basic.des1), 4217 le32_to_cpu(ep->basic.des2), 4218 le32_to_cpu(ep->basic.des3)); 4219 ep++; 4220 } else { 4221 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4222 i, (unsigned int)virt_to_phys(p), 4223 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4224 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4225 p++; 4226 } 4227 seq_printf(seq, "\n"); 4228 } 4229 } 4230 4231 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4232 { 4233 struct net_device *dev = seq->private; 4234 struct stmmac_priv *priv = netdev_priv(dev); 4235 u32 rx_count = priv->plat->rx_queues_to_use; 4236 u32 tx_count = priv->plat->tx_queues_to_use; 4237 u32 queue; 4238 4239 if ((dev->flags & IFF_UP) == 0) 4240 return 0; 4241 4242 for (queue = 0; queue < rx_count; queue++) { 4243 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4244 4245 seq_printf(seq, "RX Queue %d:\n", queue); 4246 4247 if (priv->extend_desc) { 4248 seq_printf(seq, "Extended descriptor ring:\n"); 4249 sysfs_display_ring((void *)rx_q->dma_erx, 4250 DMA_RX_SIZE, 1, seq); 4251 } else { 4252 seq_printf(seq, "Descriptor ring:\n"); 4253 sysfs_display_ring((void *)rx_q->dma_rx, 4254 DMA_RX_SIZE, 0, seq); 4255 } 4256 } 4257 4258 for (queue = 0; queue < tx_count; queue++) { 4259 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4260 4261 seq_printf(seq, "TX Queue %d:\n", queue); 4262 4263 if (priv->extend_desc) { 4264 seq_printf(seq, "Extended descriptor ring:\n"); 4265 sysfs_display_ring((void *)tx_q->dma_etx, 4266 DMA_TX_SIZE, 1, seq); 4267 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4268 seq_printf(seq, "Descriptor ring:\n"); 4269 sysfs_display_ring((void *)tx_q->dma_tx, 4270 DMA_TX_SIZE, 0, seq); 4271 } 4272 } 4273 4274 return 0; 4275 } 4276 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4277 4278 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4279 { 4280 struct net_device *dev = seq->private; 4281 struct stmmac_priv *priv = netdev_priv(dev); 4282 4283 if (!priv->hw_cap_support) { 4284 seq_printf(seq, "DMA HW features not supported\n"); 4285 return 0; 4286 } 4287 4288 seq_printf(seq, "==============================\n"); 4289 seq_printf(seq, "\tDMA HW features\n"); 4290 seq_printf(seq, "==============================\n"); 4291 4292 seq_printf(seq, "\t10/100 Mbps: %s\n", 4293 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4294 seq_printf(seq, "\t1000 Mbps: %s\n", 4295 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4296 seq_printf(seq, "\tHalf duplex: %s\n", 4297 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4298 seq_printf(seq, "\tHash Filter: %s\n", 4299 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4300 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4301 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4302 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4303 (priv->dma_cap.pcs) ? "Y" : "N"); 4304 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4305 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4306 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4307 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4308 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4309 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4310 seq_printf(seq, "\tRMON module: %s\n", 4311 (priv->dma_cap.rmon) ? "Y" : "N"); 4312 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4313 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4314 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4315 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4316 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4317 (priv->dma_cap.eee) ? "Y" : "N"); 4318 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4319 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4320 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4321 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4322 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4323 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4324 } else { 4325 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4326 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4327 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4328 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4329 } 4330 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4331 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4332 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4333 priv->dma_cap.number_rx_channel); 4334 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4335 priv->dma_cap.number_tx_channel); 4336 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4337 priv->dma_cap.number_rx_queues); 4338 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4339 priv->dma_cap.number_tx_queues); 4340 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4341 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4342 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4343 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4344 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4345 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4346 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4347 priv->dma_cap.pps_out_num); 4348 seq_printf(seq, "\tSafety Features: %s\n", 4349 priv->dma_cap.asp ? "Y" : "N"); 4350 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4351 priv->dma_cap.frpsel ? "Y" : "N"); 4352 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4353 priv->dma_cap.addr64); 4354 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4355 priv->dma_cap.rssen ? "Y" : "N"); 4356 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4357 priv->dma_cap.vlhash ? "Y" : "N"); 4358 seq_printf(seq, "\tSplit Header: %s\n", 4359 priv->dma_cap.sphen ? "Y" : "N"); 4360 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4361 priv->dma_cap.vlins ? "Y" : "N"); 4362 seq_printf(seq, "\tDouble VLAN: %s\n", 4363 priv->dma_cap.dvlan ? "Y" : "N"); 4364 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4365 priv->dma_cap.l3l4fnum); 4366 seq_printf(seq, "\tARP Offloading: %s\n", 4367 priv->dma_cap.arpoffsel ? "Y" : "N"); 4368 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4369 priv->dma_cap.estsel ? "Y" : "N"); 4370 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4371 priv->dma_cap.fpesel ? "Y" : "N"); 4372 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4373 priv->dma_cap.tbssel ? "Y" : "N"); 4374 return 0; 4375 } 4376 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4377 4378 /* Use network device events to rename debugfs file entries. 4379 */ 4380 static int stmmac_device_event(struct notifier_block *unused, 4381 unsigned long event, void *ptr) 4382 { 4383 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4384 struct stmmac_priv *priv = netdev_priv(dev); 4385 4386 if (dev->netdev_ops != &stmmac_netdev_ops) 4387 goto done; 4388 4389 switch (event) { 4390 case NETDEV_CHANGENAME: 4391 if (priv->dbgfs_dir) 4392 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4393 priv->dbgfs_dir, 4394 stmmac_fs_dir, 4395 dev->name); 4396 break; 4397 } 4398 done: 4399 return NOTIFY_DONE; 4400 } 4401 4402 static struct notifier_block stmmac_notifier = { 4403 .notifier_call = stmmac_device_event, 4404 }; 4405 4406 static void stmmac_init_fs(struct net_device *dev) 4407 { 4408 struct stmmac_priv *priv = netdev_priv(dev); 4409 4410 rtnl_lock(); 4411 4412 /* Create per netdev entries */ 4413 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4414 4415 /* Entry to report DMA RX/TX rings */ 4416 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4417 &stmmac_rings_status_fops); 4418 4419 /* Entry to report the DMA HW features */ 4420 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4421 &stmmac_dma_cap_fops); 4422 4423 rtnl_unlock(); 4424 } 4425 4426 static void stmmac_exit_fs(struct net_device *dev) 4427 { 4428 struct stmmac_priv *priv = netdev_priv(dev); 4429 4430 debugfs_remove_recursive(priv->dbgfs_dir); 4431 } 4432 #endif /* CONFIG_DEBUG_FS */ 4433 4434 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4435 { 4436 unsigned char *data = (unsigned char *)&vid_le; 4437 unsigned char data_byte = 0; 4438 u32 crc = ~0x0; 4439 u32 temp = 0; 4440 int i, bits; 4441 4442 bits = get_bitmask_order(VLAN_VID_MASK); 4443 for (i = 0; i < bits; i++) { 4444 if ((i % 8) == 0) 4445 data_byte = data[i / 8]; 4446 4447 temp = ((crc & 1) ^ data_byte) & 1; 4448 crc >>= 1; 4449 data_byte >>= 1; 4450 4451 if (temp) 4452 crc ^= 0xedb88320; 4453 } 4454 4455 return crc; 4456 } 4457 4458 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4459 { 4460 u32 crc, hash = 0; 4461 __le16 pmatch = 0; 4462 int count = 0; 4463 u16 vid = 0; 4464 4465 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4466 __le16 vid_le = cpu_to_le16(vid); 4467 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4468 hash |= (1 << crc); 4469 count++; 4470 } 4471 4472 if (!priv->dma_cap.vlhash) { 4473 if (count > 2) /* VID = 0 always passes filter */ 4474 return -EOPNOTSUPP; 4475 4476 pmatch = cpu_to_le16(vid); 4477 hash = 0; 4478 } 4479 4480 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4481 } 4482 4483 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4484 { 4485 struct stmmac_priv *priv = netdev_priv(ndev); 4486 bool is_double = false; 4487 int ret; 4488 4489 if (be16_to_cpu(proto) == ETH_P_8021AD) 4490 is_double = true; 4491 4492 set_bit(vid, priv->active_vlans); 4493 ret = stmmac_vlan_update(priv, is_double); 4494 if (ret) { 4495 clear_bit(vid, priv->active_vlans); 4496 return ret; 4497 } 4498 4499 return ret; 4500 } 4501 4502 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4503 { 4504 struct stmmac_priv *priv = netdev_priv(ndev); 4505 bool is_double = false; 4506 4507 if (be16_to_cpu(proto) == ETH_P_8021AD) 4508 is_double = true; 4509 4510 clear_bit(vid, priv->active_vlans); 4511 return stmmac_vlan_update(priv, is_double); 4512 } 4513 4514 static const struct net_device_ops stmmac_netdev_ops = { 4515 .ndo_open = stmmac_open, 4516 .ndo_start_xmit = stmmac_xmit, 4517 .ndo_stop = stmmac_release, 4518 .ndo_change_mtu = stmmac_change_mtu, 4519 .ndo_fix_features = stmmac_fix_features, 4520 .ndo_set_features = stmmac_set_features, 4521 .ndo_set_rx_mode = stmmac_set_rx_mode, 4522 .ndo_tx_timeout = stmmac_tx_timeout, 4523 .ndo_do_ioctl = stmmac_ioctl, 4524 .ndo_setup_tc = stmmac_setup_tc, 4525 .ndo_select_queue = stmmac_select_queue, 4526 #ifdef CONFIG_NET_POLL_CONTROLLER 4527 .ndo_poll_controller = stmmac_poll_controller, 4528 #endif 4529 .ndo_set_mac_address = stmmac_set_mac_address, 4530 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4531 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4532 }; 4533 4534 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4535 { 4536 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4537 return; 4538 if (test_bit(STMMAC_DOWN, &priv->state)) 4539 return; 4540 4541 netdev_err(priv->dev, "Reset adapter.\n"); 4542 4543 rtnl_lock(); 4544 netif_trans_update(priv->dev); 4545 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4546 usleep_range(1000, 2000); 4547 4548 set_bit(STMMAC_DOWN, &priv->state); 4549 dev_close(priv->dev); 4550 dev_open(priv->dev, NULL); 4551 clear_bit(STMMAC_DOWN, &priv->state); 4552 clear_bit(STMMAC_RESETING, &priv->state); 4553 rtnl_unlock(); 4554 } 4555 4556 static void stmmac_service_task(struct work_struct *work) 4557 { 4558 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4559 service_task); 4560 4561 stmmac_reset_subtask(priv); 4562 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4563 } 4564 4565 /** 4566 * stmmac_hw_init - Init the MAC device 4567 * @priv: driver private structure 4568 * Description: this function is to configure the MAC device according to 4569 * some platform parameters or the HW capability register. It prepares the 4570 * driver to use either ring or chain modes and to setup either enhanced or 4571 * normal descriptors. 4572 */ 4573 static int stmmac_hw_init(struct stmmac_priv *priv) 4574 { 4575 int ret; 4576 4577 /* dwmac-sun8i only work in chain mode */ 4578 if (priv->plat->has_sun8i) 4579 chain_mode = 1; 4580 priv->chain_mode = chain_mode; 4581 4582 /* Initialize HW Interface */ 4583 ret = stmmac_hwif_init(priv); 4584 if (ret) 4585 return ret; 4586 4587 /* Get the HW capability (new GMAC newer than 3.50a) */ 4588 priv->hw_cap_support = stmmac_get_hw_features(priv); 4589 if (priv->hw_cap_support) { 4590 dev_info(priv->device, "DMA HW capability register supported\n"); 4591 4592 /* We can override some gmac/dma configuration fields: e.g. 4593 * enh_desc, tx_coe (e.g. that are passed through the 4594 * platform) with the values from the HW capability 4595 * register (if supported). 4596 */ 4597 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4598 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4599 priv->hw->pmt = priv->plat->pmt; 4600 if (priv->dma_cap.hash_tb_sz) { 4601 priv->hw->multicast_filter_bins = 4602 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4603 priv->hw->mcast_bits_log2 = 4604 ilog2(priv->hw->multicast_filter_bins); 4605 } 4606 4607 /* TXCOE doesn't work in thresh DMA mode */ 4608 if (priv->plat->force_thresh_dma_mode) 4609 priv->plat->tx_coe = 0; 4610 else 4611 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4612 4613 /* In case of GMAC4 rx_coe is from HW cap register. */ 4614 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4615 4616 if (priv->dma_cap.rx_coe_type2) 4617 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4618 else if (priv->dma_cap.rx_coe_type1) 4619 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4620 4621 } else { 4622 dev_info(priv->device, "No HW DMA feature register supported\n"); 4623 } 4624 4625 if (priv->plat->rx_coe) { 4626 priv->hw->rx_csum = priv->plat->rx_coe; 4627 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4628 if (priv->synopsys_id < DWMAC_CORE_4_00) 4629 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4630 } 4631 if (priv->plat->tx_coe) 4632 dev_info(priv->device, "TX Checksum insertion supported\n"); 4633 4634 if (priv->plat->pmt) { 4635 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4636 device_set_wakeup_capable(priv->device, 1); 4637 } 4638 4639 if (priv->dma_cap.tsoen) 4640 dev_info(priv->device, "TSO supported\n"); 4641 4642 /* Run HW quirks, if any */ 4643 if (priv->hwif_quirks) { 4644 ret = priv->hwif_quirks(priv); 4645 if (ret) 4646 return ret; 4647 } 4648 4649 /* Rx Watchdog is available in the COREs newer than the 3.40. 4650 * In some case, for example on bugged HW this feature 4651 * has to be disable and this can be done by passing the 4652 * riwt_off field from the platform. 4653 */ 4654 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4655 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4656 priv->use_riwt = 1; 4657 dev_info(priv->device, 4658 "Enable RX Mitigation via HW Watchdog Timer\n"); 4659 } 4660 4661 return 0; 4662 } 4663 4664 /** 4665 * stmmac_dvr_probe 4666 * @device: device pointer 4667 * @plat_dat: platform data pointer 4668 * @res: stmmac resource pointer 4669 * Description: this is the main probe function used to 4670 * call the alloc_etherdev, allocate the priv structure. 4671 * Return: 4672 * returns 0 on success, otherwise errno. 4673 */ 4674 int stmmac_dvr_probe(struct device *device, 4675 struct plat_stmmacenet_data *plat_dat, 4676 struct stmmac_resources *res) 4677 { 4678 struct net_device *ndev = NULL; 4679 struct stmmac_priv *priv; 4680 u32 queue, rxq, maxq; 4681 int i, ret = 0; 4682 4683 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4684 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4685 if (!ndev) 4686 return -ENOMEM; 4687 4688 SET_NETDEV_DEV(ndev, device); 4689 4690 priv = netdev_priv(ndev); 4691 priv->device = device; 4692 priv->dev = ndev; 4693 4694 stmmac_set_ethtool_ops(ndev); 4695 priv->pause = pause; 4696 priv->plat = plat_dat; 4697 priv->ioaddr = res->addr; 4698 priv->dev->base_addr = (unsigned long)res->addr; 4699 4700 priv->dev->irq = res->irq; 4701 priv->wol_irq = res->wol_irq; 4702 priv->lpi_irq = res->lpi_irq; 4703 4704 if (!IS_ERR_OR_NULL(res->mac)) 4705 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4706 4707 dev_set_drvdata(device, priv->dev); 4708 4709 /* Verify driver arguments */ 4710 stmmac_verify_args(); 4711 4712 /* Allocate workqueue */ 4713 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4714 if (!priv->wq) { 4715 dev_err(priv->device, "failed to create workqueue\n"); 4716 return -ENOMEM; 4717 } 4718 4719 INIT_WORK(&priv->service_task, stmmac_service_task); 4720 4721 /* Override with kernel parameters if supplied XXX CRS XXX 4722 * this needs to have multiple instances 4723 */ 4724 if ((phyaddr >= 0) && (phyaddr <= 31)) 4725 priv->plat->phy_addr = phyaddr; 4726 4727 if (priv->plat->stmmac_rst) { 4728 ret = reset_control_assert(priv->plat->stmmac_rst); 4729 reset_control_deassert(priv->plat->stmmac_rst); 4730 /* Some reset controllers have only reset callback instead of 4731 * assert + deassert callbacks pair. 4732 */ 4733 if (ret == -ENOTSUPP) 4734 reset_control_reset(priv->plat->stmmac_rst); 4735 } 4736 4737 /* Init MAC and get the capabilities */ 4738 ret = stmmac_hw_init(priv); 4739 if (ret) 4740 goto error_hw_init; 4741 4742 stmmac_check_ether_addr(priv); 4743 4744 /* Configure real RX and TX queues */ 4745 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4746 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4747 4748 ndev->netdev_ops = &stmmac_netdev_ops; 4749 4750 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4751 NETIF_F_RXCSUM; 4752 4753 ret = stmmac_tc_init(priv, priv); 4754 if (!ret) { 4755 ndev->hw_features |= NETIF_F_HW_TC; 4756 } 4757 4758 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4759 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4760 if (priv->plat->has_gmac4) 4761 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4762 priv->tso = true; 4763 dev_info(priv->device, "TSO feature enabled\n"); 4764 } 4765 4766 if (priv->dma_cap.sphen) { 4767 ndev->hw_features |= NETIF_F_GRO; 4768 priv->sph = true; 4769 dev_info(priv->device, "SPH feature enabled\n"); 4770 } 4771 4772 if (priv->dma_cap.addr64) { 4773 ret = dma_set_mask_and_coherent(device, 4774 DMA_BIT_MASK(priv->dma_cap.addr64)); 4775 if (!ret) { 4776 dev_info(priv->device, "Using %d bits DMA width\n", 4777 priv->dma_cap.addr64); 4778 4779 /* 4780 * If more than 32 bits can be addressed, make sure to 4781 * enable enhanced addressing mode. 4782 */ 4783 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4784 priv->plat->dma_cfg->eame = true; 4785 } else { 4786 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4787 if (ret) { 4788 dev_err(priv->device, "Failed to set DMA Mask\n"); 4789 goto error_hw_init; 4790 } 4791 4792 priv->dma_cap.addr64 = 32; 4793 } 4794 } 4795 4796 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4797 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4798 #ifdef STMMAC_VLAN_TAG_USED 4799 /* Both mac100 and gmac support receive VLAN tag detection */ 4800 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4801 if (priv->dma_cap.vlhash) { 4802 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4803 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4804 } 4805 if (priv->dma_cap.vlins) { 4806 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4807 if (priv->dma_cap.dvlan) 4808 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4809 } 4810 #endif 4811 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4812 4813 /* Initialize RSS */ 4814 rxq = priv->plat->rx_queues_to_use; 4815 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4816 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4817 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4818 4819 if (priv->dma_cap.rssen && priv->plat->rss_en) 4820 ndev->features |= NETIF_F_RXHASH; 4821 4822 /* MTU range: 46 - hw-specific max */ 4823 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4824 if (priv->plat->has_xgmac) 4825 ndev->max_mtu = XGMAC_JUMBO_LEN; 4826 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4827 ndev->max_mtu = JUMBO_LEN; 4828 else 4829 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4830 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4831 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4832 */ 4833 if ((priv->plat->maxmtu < ndev->max_mtu) && 4834 (priv->plat->maxmtu >= ndev->min_mtu)) 4835 ndev->max_mtu = priv->plat->maxmtu; 4836 else if (priv->plat->maxmtu < ndev->min_mtu) 4837 dev_warn(priv->device, 4838 "%s: warning: maxmtu having invalid value (%d)\n", 4839 __func__, priv->plat->maxmtu); 4840 4841 if (flow_ctrl) 4842 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4843 4844 /* Setup channels NAPI */ 4845 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4846 4847 for (queue = 0; queue < maxq; queue++) { 4848 struct stmmac_channel *ch = &priv->channel[queue]; 4849 4850 spin_lock_init(&ch->lock); 4851 ch->priv_data = priv; 4852 ch->index = queue; 4853 4854 if (queue < priv->plat->rx_queues_to_use) { 4855 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4856 NAPI_POLL_WEIGHT); 4857 } 4858 if (queue < priv->plat->tx_queues_to_use) { 4859 netif_tx_napi_add(ndev, &ch->tx_napi, 4860 stmmac_napi_poll_tx, 4861 NAPI_POLL_WEIGHT); 4862 } 4863 } 4864 4865 mutex_init(&priv->lock); 4866 4867 /* If a specific clk_csr value is passed from the platform 4868 * this means that the CSR Clock Range selection cannot be 4869 * changed at run-time and it is fixed. Viceversa the driver'll try to 4870 * set the MDC clock dynamically according to the csr actual 4871 * clock input. 4872 */ 4873 if (priv->plat->clk_csr >= 0) 4874 priv->clk_csr = priv->plat->clk_csr; 4875 else 4876 stmmac_clk_csr_set(priv); 4877 4878 stmmac_check_pcs_mode(priv); 4879 4880 if (priv->hw->pcs != STMMAC_PCS_TBI && 4881 priv->hw->pcs != STMMAC_PCS_RTBI) { 4882 /* MDIO bus Registration */ 4883 ret = stmmac_mdio_register(ndev); 4884 if (ret < 0) { 4885 dev_err(priv->device, 4886 "%s: MDIO bus (id: %d) registration failed", 4887 __func__, priv->plat->bus_id); 4888 goto error_mdio_register; 4889 } 4890 } 4891 4892 ret = stmmac_phy_setup(priv); 4893 if (ret) { 4894 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4895 goto error_phy_setup; 4896 } 4897 4898 ret = register_netdev(ndev); 4899 if (ret) { 4900 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4901 __func__, ret); 4902 goto error_netdev_register; 4903 } 4904 4905 #ifdef CONFIG_DEBUG_FS 4906 stmmac_init_fs(ndev); 4907 #endif 4908 4909 return ret; 4910 4911 error_netdev_register: 4912 phylink_destroy(priv->phylink); 4913 error_phy_setup: 4914 if (priv->hw->pcs != STMMAC_PCS_TBI && 4915 priv->hw->pcs != STMMAC_PCS_RTBI) 4916 stmmac_mdio_unregister(ndev); 4917 error_mdio_register: 4918 for (queue = 0; queue < maxq; queue++) { 4919 struct stmmac_channel *ch = &priv->channel[queue]; 4920 4921 if (queue < priv->plat->rx_queues_to_use) 4922 netif_napi_del(&ch->rx_napi); 4923 if (queue < priv->plat->tx_queues_to_use) 4924 netif_napi_del(&ch->tx_napi); 4925 } 4926 error_hw_init: 4927 destroy_workqueue(priv->wq); 4928 4929 return ret; 4930 } 4931 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4932 4933 /** 4934 * stmmac_dvr_remove 4935 * @dev: device pointer 4936 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4937 * changes the link status, releases the DMA descriptor rings. 4938 */ 4939 int stmmac_dvr_remove(struct device *dev) 4940 { 4941 struct net_device *ndev = dev_get_drvdata(dev); 4942 struct stmmac_priv *priv = netdev_priv(ndev); 4943 4944 netdev_info(priv->dev, "%s: removing driver", __func__); 4945 4946 stmmac_stop_all_dma(priv); 4947 4948 stmmac_mac_set(priv, priv->ioaddr, false); 4949 netif_carrier_off(ndev); 4950 unregister_netdev(ndev); 4951 #ifdef CONFIG_DEBUG_FS 4952 stmmac_exit_fs(ndev); 4953 #endif 4954 phylink_destroy(priv->phylink); 4955 if (priv->plat->stmmac_rst) 4956 reset_control_assert(priv->plat->stmmac_rst); 4957 clk_disable_unprepare(priv->plat->pclk); 4958 clk_disable_unprepare(priv->plat->stmmac_clk); 4959 if (priv->hw->pcs != STMMAC_PCS_TBI && 4960 priv->hw->pcs != STMMAC_PCS_RTBI) 4961 stmmac_mdio_unregister(ndev); 4962 destroy_workqueue(priv->wq); 4963 mutex_destroy(&priv->lock); 4964 4965 return 0; 4966 } 4967 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4968 4969 /** 4970 * stmmac_suspend - suspend callback 4971 * @dev: device pointer 4972 * Description: this is the function to suspend the device and it is called 4973 * by the platform driver to stop the network queue, release the resources, 4974 * program the PMT register (for WoL), clean and release driver resources. 4975 */ 4976 int stmmac_suspend(struct device *dev) 4977 { 4978 struct net_device *ndev = dev_get_drvdata(dev); 4979 struct stmmac_priv *priv = netdev_priv(ndev); 4980 u32 chan; 4981 4982 if (!ndev || !netif_running(ndev)) 4983 return 0; 4984 4985 phylink_mac_change(priv->phylink, false); 4986 4987 mutex_lock(&priv->lock); 4988 4989 netif_device_detach(ndev); 4990 stmmac_stop_all_queues(priv); 4991 4992 stmmac_disable_all_queues(priv); 4993 4994 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 4995 del_timer_sync(&priv->tx_queue[chan].txtimer); 4996 4997 /* Stop TX/RX DMA */ 4998 stmmac_stop_all_dma(priv); 4999 5000 /* Enable Power down mode by programming the PMT regs */ 5001 if (device_may_wakeup(priv->device)) { 5002 stmmac_pmt(priv, priv->hw, priv->wolopts); 5003 priv->irq_wake = 1; 5004 } else { 5005 mutex_unlock(&priv->lock); 5006 rtnl_lock(); 5007 phylink_stop(priv->phylink); 5008 rtnl_unlock(); 5009 mutex_lock(&priv->lock); 5010 5011 stmmac_mac_set(priv, priv->ioaddr, false); 5012 pinctrl_pm_select_sleep_state(priv->device); 5013 /* Disable clock in case of PWM is off */ 5014 if (priv->plat->clk_ptp_ref) 5015 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5016 clk_disable_unprepare(priv->plat->pclk); 5017 clk_disable_unprepare(priv->plat->stmmac_clk); 5018 } 5019 mutex_unlock(&priv->lock); 5020 5021 priv->speed = SPEED_UNKNOWN; 5022 return 0; 5023 } 5024 EXPORT_SYMBOL_GPL(stmmac_suspend); 5025 5026 /** 5027 * stmmac_reset_queues_param - reset queue parameters 5028 * @dev: device pointer 5029 */ 5030 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5031 { 5032 u32 rx_cnt = priv->plat->rx_queues_to_use; 5033 u32 tx_cnt = priv->plat->tx_queues_to_use; 5034 u32 queue; 5035 5036 for (queue = 0; queue < rx_cnt; queue++) { 5037 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5038 5039 rx_q->cur_rx = 0; 5040 rx_q->dirty_rx = 0; 5041 } 5042 5043 for (queue = 0; queue < tx_cnt; queue++) { 5044 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5045 5046 tx_q->cur_tx = 0; 5047 tx_q->dirty_tx = 0; 5048 tx_q->mss = 0; 5049 } 5050 } 5051 5052 /** 5053 * stmmac_resume - resume callback 5054 * @dev: device pointer 5055 * Description: when resume this function is invoked to setup the DMA and CORE 5056 * in a usable state. 5057 */ 5058 int stmmac_resume(struct device *dev) 5059 { 5060 struct net_device *ndev = dev_get_drvdata(dev); 5061 struct stmmac_priv *priv = netdev_priv(ndev); 5062 5063 if (!netif_running(ndev)) 5064 return 0; 5065 5066 /* Power Down bit, into the PM register, is cleared 5067 * automatically as soon as a magic packet or a Wake-up frame 5068 * is received. Anyway, it's better to manually clear 5069 * this bit because it can generate problems while resuming 5070 * from another devices (e.g. serial console). 5071 */ 5072 if (device_may_wakeup(priv->device)) { 5073 mutex_lock(&priv->lock); 5074 stmmac_pmt(priv, priv->hw, 0); 5075 mutex_unlock(&priv->lock); 5076 priv->irq_wake = 0; 5077 } else { 5078 pinctrl_pm_select_default_state(priv->device); 5079 /* enable the clk previously disabled */ 5080 clk_prepare_enable(priv->plat->stmmac_clk); 5081 clk_prepare_enable(priv->plat->pclk); 5082 if (priv->plat->clk_ptp_ref) 5083 clk_prepare_enable(priv->plat->clk_ptp_ref); 5084 /* reset the phy so that it's ready */ 5085 if (priv->mii) 5086 stmmac_mdio_reset(priv->mii); 5087 } 5088 5089 netif_device_attach(ndev); 5090 5091 mutex_lock(&priv->lock); 5092 5093 stmmac_reset_queues_param(priv); 5094 5095 stmmac_clear_descriptors(priv); 5096 5097 stmmac_hw_setup(ndev, false); 5098 stmmac_init_coalesce(priv); 5099 stmmac_set_rx_mode(ndev); 5100 5101 stmmac_enable_all_queues(priv); 5102 5103 stmmac_start_all_queues(priv); 5104 5105 mutex_unlock(&priv->lock); 5106 5107 if (!device_may_wakeup(priv->device)) { 5108 rtnl_lock(); 5109 phylink_start(priv->phylink); 5110 rtnl_unlock(); 5111 } 5112 5113 phylink_mac_change(priv->phylink, true); 5114 5115 return 0; 5116 } 5117 EXPORT_SYMBOL_GPL(stmmac_resume); 5118 5119 #ifndef MODULE 5120 static int __init stmmac_cmdline_opt(char *str) 5121 { 5122 char *opt; 5123 5124 if (!str || !*str) 5125 return -EINVAL; 5126 while ((opt = strsep(&str, ",")) != NULL) { 5127 if (!strncmp(opt, "debug:", 6)) { 5128 if (kstrtoint(opt + 6, 0, &debug)) 5129 goto err; 5130 } else if (!strncmp(opt, "phyaddr:", 8)) { 5131 if (kstrtoint(opt + 8, 0, &phyaddr)) 5132 goto err; 5133 } else if (!strncmp(opt, "buf_sz:", 7)) { 5134 if (kstrtoint(opt + 7, 0, &buf_sz)) 5135 goto err; 5136 } else if (!strncmp(opt, "tc:", 3)) { 5137 if (kstrtoint(opt + 3, 0, &tc)) 5138 goto err; 5139 } else if (!strncmp(opt, "watchdog:", 9)) { 5140 if (kstrtoint(opt + 9, 0, &watchdog)) 5141 goto err; 5142 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5143 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5144 goto err; 5145 } else if (!strncmp(opt, "pause:", 6)) { 5146 if (kstrtoint(opt + 6, 0, &pause)) 5147 goto err; 5148 } else if (!strncmp(opt, "eee_timer:", 10)) { 5149 if (kstrtoint(opt + 10, 0, &eee_timer)) 5150 goto err; 5151 } else if (!strncmp(opt, "chain_mode:", 11)) { 5152 if (kstrtoint(opt + 11, 0, &chain_mode)) 5153 goto err; 5154 } 5155 } 5156 return 0; 5157 5158 err: 5159 pr_err("%s: ERROR broken module parameter conversion", __func__); 5160 return -EINVAL; 5161 } 5162 5163 __setup("stmmaceth=", stmmac_cmdline_opt); 5164 #endif /* MODULE */ 5165 5166 static int __init stmmac_init(void) 5167 { 5168 #ifdef CONFIG_DEBUG_FS 5169 /* Create debugfs main directory if it doesn't exist yet */ 5170 if (!stmmac_fs_dir) 5171 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5172 register_netdevice_notifier(&stmmac_notifier); 5173 #endif 5174 5175 return 0; 5176 } 5177 5178 static void __exit stmmac_exit(void) 5179 { 5180 #ifdef CONFIG_DEBUG_FS 5181 unregister_netdevice_notifier(&stmmac_notifier); 5182 debugfs_remove_recursive(stmmac_fs_dir); 5183 #endif 5184 } 5185 5186 module_init(stmmac_init) 5187 module_exit(stmmac_exit) 5188 5189 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5190 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5191 MODULE_LICENSE("GPL"); 5192