1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_STMMAC_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_STMMAC_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 57 58 /* Module parameters */ 59 #define TX_TIMEO 5000 60 static int watchdog = TX_TIMEO; 61 module_param(watchdog, int, S_IRUGO | S_IWUSR); 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 63 64 static int debug = -1; 65 module_param(debug, int, S_IRUGO | S_IWUSR); 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 67 68 static int phyaddr = -1; 69 module_param(phyaddr, int, S_IRUGO); 70 MODULE_PARM_DESC(phyaddr, "Physical device address"); 71 72 #define DMA_TX_SIZE 256 73 static int dma_txsize = DMA_TX_SIZE; 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 76 77 #define DMA_RX_SIZE 256 78 static int dma_rxsize = DMA_RX_SIZE; 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 81 82 static int flow_ctrl = FLOW_OFF; 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 85 86 static int pause = PAUSE_TIME; 87 module_param(pause, int, S_IRUGO | S_IWUSR); 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 89 90 #define TC_DEFAULT 64 91 static int tc = TC_DEFAULT; 92 module_param(tc, int, S_IRUGO | S_IWUSR); 93 MODULE_PARM_DESC(tc, "DMA threshold control value"); 94 95 #define DEFAULT_BUFSIZE 1536 96 static int buf_sz = DEFAULT_BUFSIZE; 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 99 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 101 NETIF_MSG_LINK | NETIF_MSG_IFUP | 102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 103 104 #define STMMAC_DEFAULT_LPI_TIMER 1000 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 109 110 /* By default the driver will use the ring mode to manage tx and rx descriptors 111 * but passing this value so user can force to use the chain instead of the ring 112 */ 113 static unsigned int chain_mode; 114 module_param(chain_mode, int, S_IRUGO); 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 116 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 118 119 #ifdef CONFIG_STMMAC_DEBUG_FS 120 static int stmmac_init_fs(struct net_device *dev); 121 static void stmmac_exit_fs(void); 122 #endif 123 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 125 126 /** 127 * stmmac_verify_args - verify the driver parameters. 128 * Description: it verifies if some wrong parameter is passed to the driver. 129 * Note that wrong parameters are replaced with the default values. 130 */ 131 static void stmmac_verify_args(void) 132 { 133 if (unlikely(watchdog < 0)) 134 watchdog = TX_TIMEO; 135 if (unlikely(dma_rxsize < 0)) 136 dma_rxsize = DMA_RX_SIZE; 137 if (unlikely(dma_txsize < 0)) 138 dma_txsize = DMA_TX_SIZE; 139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 140 buf_sz = DEFAULT_BUFSIZE; 141 if (unlikely(flow_ctrl > 1)) 142 flow_ctrl = FLOW_AUTO; 143 else if (likely(flow_ctrl < 0)) 144 flow_ctrl = FLOW_OFF; 145 if (unlikely((pause < 0) || (pause > 0xffff))) 146 pause = PAUSE_TIME; 147 if (eee_timer < 0) 148 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 149 } 150 151 /** 152 * stmmac_clk_csr_set - dynamically set the MDC clock 153 * @priv: driver private structure 154 * Description: this is to dynamically set the MDC clock according to the csr 155 * clock input. 156 * Note: 157 * If a specific clk_csr value is passed from the platform 158 * this means that the CSR Clock Range selection cannot be 159 * changed at run-time and it is fixed (as reported in the driver 160 * documentation). Viceversa the driver will try to set the MDC 161 * clock dynamically according to the actual clock input. 162 */ 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 164 { 165 u32 clk_rate; 166 167 clk_rate = clk_get_rate(priv->stmmac_clk); 168 169 /* Platform provided default clk_csr would be assumed valid 170 * for all other cases except for the below mentioned ones. 171 * For values higher than the IEEE 802.3 specified frequency 172 * we can not estimate the proper divider as it is not known 173 * the frequency of clk_csr_i. So we do not change the default 174 * divider. 175 */ 176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 177 if (clk_rate < CSR_F_35M) 178 priv->clk_csr = STMMAC_CSR_20_35M; 179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 180 priv->clk_csr = STMMAC_CSR_35_60M; 181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 182 priv->clk_csr = STMMAC_CSR_60_100M; 183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 184 priv->clk_csr = STMMAC_CSR_100_150M; 185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 186 priv->clk_csr = STMMAC_CSR_150_250M; 187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 188 priv->clk_csr = STMMAC_CSR_250_300M; 189 } 190 } 191 192 static void print_pkt(unsigned char *buf, int len) 193 { 194 int j; 195 pr_debug("len = %d byte, buf addr: 0x%p", len, buf); 196 for (j = 0; j < len; j++) { 197 if ((j % 16) == 0) 198 pr_debug("\n %03x:", j); 199 pr_debug(" %02x", buf[j]); 200 } 201 pr_debug("\n"); 202 } 203 204 /* minimum number of free TX descriptors required to wake up TX process */ 205 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 206 207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 208 { 209 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 210 } 211 212 /** 213 * stmmac_hw_fix_mac_speed: callback for speed selection 214 * @priv: driver private structure 215 * Description: on some platforms (e.g. ST), some HW system configuraton 216 * registers have to be set according to the link speed negotiated. 217 */ 218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 219 { 220 struct phy_device *phydev = priv->phydev; 221 222 if (likely(priv->plat->fix_mac_speed)) 223 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 224 } 225 226 /** 227 * stmmac_enable_eee_mode: Check and enter in LPI mode 228 * @priv: driver private structure 229 * Description: this function is to verify and enter in LPI mode for EEE. 230 */ 231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 232 { 233 /* Check and enter in LPI mode */ 234 if ((priv->dirty_tx == priv->cur_tx) && 235 (priv->tx_path_in_lpi_mode == false)) 236 priv->hw->mac->set_eee_mode(priv->hw); 237 } 238 239 /** 240 * stmmac_disable_eee_mode: disable/exit from EEE 241 * @priv: driver private structure 242 * Description: this function is to exit and disable EEE in case of 243 * LPI state is true. This is called by the xmit. 244 */ 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 246 { 247 priv->hw->mac->reset_eee_mode(priv->hw); 248 del_timer_sync(&priv->eee_ctrl_timer); 249 priv->tx_path_in_lpi_mode = false; 250 } 251 252 /** 253 * stmmac_eee_ctrl_timer: EEE TX SW timer. 254 * @arg : data hook 255 * Description: 256 * if there is no data transfer and if we are not in LPI state, 257 * then MAC Transmitter can be moved to LPI state. 258 */ 259 static void stmmac_eee_ctrl_timer(unsigned long arg) 260 { 261 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 262 263 stmmac_enable_eee_mode(priv); 264 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 265 } 266 267 /** 268 * stmmac_eee_init: init EEE 269 * @priv: driver private structure 270 * Description: 271 * If the EEE support has been enabled while configuring the driver, 272 * if the GMAC actually supports the EEE (from the HW cap reg) and the 273 * phy can also manage EEE, so enable the LPI state and start the timer 274 * to verify if the tx path can enter in LPI state. 275 */ 276 bool stmmac_eee_init(struct stmmac_priv *priv) 277 { 278 char *phy_bus_name = priv->plat->phy_bus_name; 279 bool ret = false; 280 281 /* Using PCS we cannot dial with the phy registers at this stage 282 * so we do not support extra feature like EEE. 283 */ 284 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 285 (priv->pcs == STMMAC_PCS_RTBI)) 286 goto out; 287 288 /* Never init EEE in case of a switch is attached */ 289 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) 290 goto out; 291 292 /* MAC core supports the EEE feature. */ 293 if (priv->dma_cap.eee) { 294 int tx_lpi_timer = priv->tx_lpi_timer; 295 296 /* Check if the PHY supports EEE */ 297 if (phy_init_eee(priv->phydev, 1)) { 298 /* To manage at run-time if the EEE cannot be supported 299 * anymore (for example because the lp caps have been 300 * changed). 301 * In that case the driver disable own timers. 302 */ 303 if (priv->eee_active) { 304 pr_debug("stmmac: disable EEE\n"); 305 del_timer_sync(&priv->eee_ctrl_timer); 306 priv->hw->mac->set_eee_timer(priv->hw, 0, 307 tx_lpi_timer); 308 } 309 priv->eee_active = 0; 310 goto out; 311 } 312 /* Activate the EEE and start timers */ 313 if (!priv->eee_active) { 314 priv->eee_active = 1; 315 init_timer(&priv->eee_ctrl_timer); 316 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 317 priv->eee_ctrl_timer.data = (unsigned long)priv; 318 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 319 add_timer(&priv->eee_ctrl_timer); 320 321 priv->hw->mac->set_eee_timer(priv->hw, 322 STMMAC_DEFAULT_LIT_LS, 323 tx_lpi_timer); 324 } 325 /* Set HW EEE according to the speed */ 326 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); 327 328 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 329 330 ret = true; 331 } 332 out: 333 return ret; 334 } 335 336 /* stmmac_get_tx_hwtstamp: get HW TX timestamps 337 * @priv: driver private structure 338 * @entry : descriptor index to be used. 339 * @skb : the socket buffer 340 * Description : 341 * This function will read timestamp from the descriptor & pass it to stack. 342 * and also perform some sanity checks. 343 */ 344 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 345 unsigned int entry, struct sk_buff *skb) 346 { 347 struct skb_shared_hwtstamps shhwtstamp; 348 u64 ns; 349 void *desc = NULL; 350 351 if (!priv->hwts_tx_en) 352 return; 353 354 /* exit if skb doesn't support hw tstamp */ 355 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 356 return; 357 358 if (priv->adv_ts) 359 desc = (priv->dma_etx + entry); 360 else 361 desc = (priv->dma_tx + entry); 362 363 /* check tx tstamp status */ 364 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 365 return; 366 367 /* get the valid tstamp */ 368 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 369 370 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 371 shhwtstamp.hwtstamp = ns_to_ktime(ns); 372 /* pass tstamp to stack */ 373 skb_tstamp_tx(skb, &shhwtstamp); 374 375 return; 376 } 377 378 /* stmmac_get_rx_hwtstamp: get HW RX timestamps 379 * @priv: driver private structure 380 * @entry : descriptor index to be used. 381 * @skb : the socket buffer 382 * Description : 383 * This function will read received packet's timestamp from the descriptor 384 * and pass it to stack. It also perform some sanity checks. 385 */ 386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 387 unsigned int entry, struct sk_buff *skb) 388 { 389 struct skb_shared_hwtstamps *shhwtstamp = NULL; 390 u64 ns; 391 void *desc = NULL; 392 393 if (!priv->hwts_rx_en) 394 return; 395 396 if (priv->adv_ts) 397 desc = (priv->dma_erx + entry); 398 else 399 desc = (priv->dma_rx + entry); 400 401 /* exit if rx tstamp is not valid */ 402 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 403 return; 404 405 /* get valid tstamp */ 406 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 407 shhwtstamp = skb_hwtstamps(skb); 408 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 409 shhwtstamp->hwtstamp = ns_to_ktime(ns); 410 } 411 412 /** 413 * stmmac_hwtstamp_ioctl - control hardware timestamping. 414 * @dev: device pointer. 415 * @ifr: An IOCTL specefic structure, that can contain a pointer to 416 * a proprietary structure used to pass information to the driver. 417 * Description: 418 * This function configures the MAC to enable/disable both outgoing(TX) 419 * and incoming(RX) packets time stamping based on user input. 420 * Return Value: 421 * 0 on success and an appropriate -ve integer on failure. 422 */ 423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 424 { 425 struct stmmac_priv *priv = netdev_priv(dev); 426 struct hwtstamp_config config; 427 struct timespec now; 428 u64 temp = 0; 429 u32 ptp_v2 = 0; 430 u32 tstamp_all = 0; 431 u32 ptp_over_ipv4_udp = 0; 432 u32 ptp_over_ipv6_udp = 0; 433 u32 ptp_over_ethernet = 0; 434 u32 snap_type_sel = 0; 435 u32 ts_master_en = 0; 436 u32 ts_event_en = 0; 437 u32 value = 0; 438 439 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 440 netdev_alert(priv->dev, "No support for HW time stamping\n"); 441 priv->hwts_tx_en = 0; 442 priv->hwts_rx_en = 0; 443 444 return -EOPNOTSUPP; 445 } 446 447 if (copy_from_user(&config, ifr->ifr_data, 448 sizeof(struct hwtstamp_config))) 449 return -EFAULT; 450 451 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 452 __func__, config.flags, config.tx_type, config.rx_filter); 453 454 /* reserved for future extensions */ 455 if (config.flags) 456 return -EINVAL; 457 458 if (config.tx_type != HWTSTAMP_TX_OFF && 459 config.tx_type != HWTSTAMP_TX_ON) 460 return -ERANGE; 461 462 if (priv->adv_ts) { 463 switch (config.rx_filter) { 464 case HWTSTAMP_FILTER_NONE: 465 /* time stamp no incoming packet at all */ 466 config.rx_filter = HWTSTAMP_FILTER_NONE; 467 break; 468 469 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 470 /* PTP v1, UDP, any kind of event packet */ 471 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 472 /* take time stamp for all event messages */ 473 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 474 475 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 476 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 477 break; 478 479 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 480 /* PTP v1, UDP, Sync packet */ 481 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 482 /* take time stamp for SYNC messages only */ 483 ts_event_en = PTP_TCR_TSEVNTENA; 484 485 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 486 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 487 break; 488 489 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 490 /* PTP v1, UDP, Delay_req packet */ 491 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 492 /* take time stamp for Delay_Req messages only */ 493 ts_master_en = PTP_TCR_TSMSTRENA; 494 ts_event_en = PTP_TCR_TSEVNTENA; 495 496 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 497 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 498 break; 499 500 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 501 /* PTP v2, UDP, any kind of event packet */ 502 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 503 ptp_v2 = PTP_TCR_TSVER2ENA; 504 /* take time stamp for all event messages */ 505 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 506 507 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 508 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 509 break; 510 511 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 512 /* PTP v2, UDP, Sync packet */ 513 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 514 ptp_v2 = PTP_TCR_TSVER2ENA; 515 /* take time stamp for SYNC messages only */ 516 ts_event_en = PTP_TCR_TSEVNTENA; 517 518 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 519 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 520 break; 521 522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 523 /* PTP v2, UDP, Delay_req packet */ 524 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 525 ptp_v2 = PTP_TCR_TSVER2ENA; 526 /* take time stamp for Delay_Req messages only */ 527 ts_master_en = PTP_TCR_TSMSTRENA; 528 ts_event_en = PTP_TCR_TSEVNTENA; 529 530 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 531 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 532 break; 533 534 case HWTSTAMP_FILTER_PTP_V2_EVENT: 535 /* PTP v2/802.AS1 any layer, any kind of event packet */ 536 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 537 ptp_v2 = PTP_TCR_TSVER2ENA; 538 /* take time stamp for all event messages */ 539 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 540 541 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 542 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 543 ptp_over_ethernet = PTP_TCR_TSIPENA; 544 break; 545 546 case HWTSTAMP_FILTER_PTP_V2_SYNC: 547 /* PTP v2/802.AS1, any layer, Sync packet */ 548 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 549 ptp_v2 = PTP_TCR_TSVER2ENA; 550 /* take time stamp for SYNC messages only */ 551 ts_event_en = PTP_TCR_TSEVNTENA; 552 553 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 554 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 555 ptp_over_ethernet = PTP_TCR_TSIPENA; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 559 /* PTP v2/802.AS1, any layer, Delay_req packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 561 ptp_v2 = PTP_TCR_TSVER2ENA; 562 /* take time stamp for Delay_Req messages only */ 563 ts_master_en = PTP_TCR_TSMSTRENA; 564 ts_event_en = PTP_TCR_TSEVNTENA; 565 566 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 567 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 568 ptp_over_ethernet = PTP_TCR_TSIPENA; 569 break; 570 571 case HWTSTAMP_FILTER_ALL: 572 /* time stamp any incoming packet */ 573 config.rx_filter = HWTSTAMP_FILTER_ALL; 574 tstamp_all = PTP_TCR_TSENALL; 575 break; 576 577 default: 578 return -ERANGE; 579 } 580 } else { 581 switch (config.rx_filter) { 582 case HWTSTAMP_FILTER_NONE: 583 config.rx_filter = HWTSTAMP_FILTER_NONE; 584 break; 585 default: 586 /* PTP v1, UDP, any kind of event packet */ 587 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 588 break; 589 } 590 } 591 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 592 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 593 594 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 595 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 596 else { 597 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 598 tstamp_all | ptp_v2 | ptp_over_ethernet | 599 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 600 ts_master_en | snap_type_sel); 601 602 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 603 604 /* program Sub Second Increment reg */ 605 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 606 607 /* calculate default added value: 608 * formula is : 609 * addend = (2^32)/freq_div_ratio; 610 * where, freq_div_ratio = clk_ptp_ref_i/50MHz 611 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i; 612 * NOTE: clk_ptp_ref_i should be >= 50MHz to 613 * achive 20ns accuracy. 614 * 615 * 2^x * y == (y << x), hence 616 * 2^32 * 50000000 ==> (50000000 << 32) 617 */ 618 temp = (u64) (50000000ULL << 32); 619 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 620 priv->hw->ptp->config_addend(priv->ioaddr, 621 priv->default_addend); 622 623 /* initialize system time */ 624 getnstimeofday(&now); 625 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 626 now.tv_nsec); 627 } 628 629 return copy_to_user(ifr->ifr_data, &config, 630 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 631 } 632 633 /** 634 * stmmac_init_ptp: init PTP 635 * @priv: driver private structure 636 * Description: this is to verify if the HW supports the PTPv1 or v2. 637 * This is done by looking at the HW cap. register. 638 * Also it registers the ptp driver. 639 */ 640 static int stmmac_init_ptp(struct stmmac_priv *priv) 641 { 642 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 643 return -EOPNOTSUPP; 644 645 /* Fall-back to main clock in case of no PTP ref is passed */ 646 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 647 if (IS_ERR(priv->clk_ptp_ref)) { 648 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 649 priv->clk_ptp_ref = NULL; 650 } else { 651 clk_prepare_enable(priv->clk_ptp_ref); 652 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 653 } 654 655 priv->adv_ts = 0; 656 if (priv->dma_cap.atime_stamp && priv->extend_desc) 657 priv->adv_ts = 1; 658 659 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) 660 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 661 662 if (netif_msg_hw(priv) && priv->adv_ts) 663 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); 664 665 priv->hw->ptp = &stmmac_ptp; 666 priv->hwts_tx_en = 0; 667 priv->hwts_rx_en = 0; 668 669 return stmmac_ptp_register(priv); 670 } 671 672 static void stmmac_release_ptp(struct stmmac_priv *priv) 673 { 674 if (priv->clk_ptp_ref) 675 clk_disable_unprepare(priv->clk_ptp_ref); 676 stmmac_ptp_unregister(priv); 677 } 678 679 /** 680 * stmmac_adjust_link 681 * @dev: net device structure 682 * Description: it adjusts the link parameters. 683 */ 684 static void stmmac_adjust_link(struct net_device *dev) 685 { 686 struct stmmac_priv *priv = netdev_priv(dev); 687 struct phy_device *phydev = priv->phydev; 688 unsigned long flags; 689 int new_state = 0; 690 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 691 692 if (phydev == NULL) 693 return; 694 695 spin_lock_irqsave(&priv->lock, flags); 696 697 if (phydev->link) { 698 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 699 700 /* Now we make sure that we can be in full duplex mode. 701 * If not, we operate in half-duplex mode. */ 702 if (phydev->duplex != priv->oldduplex) { 703 new_state = 1; 704 if (!(phydev->duplex)) 705 ctrl &= ~priv->hw->link.duplex; 706 else 707 ctrl |= priv->hw->link.duplex; 708 priv->oldduplex = phydev->duplex; 709 } 710 /* Flow Control operation */ 711 if (phydev->pause) 712 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 713 fc, pause_time); 714 715 if (phydev->speed != priv->speed) { 716 new_state = 1; 717 switch (phydev->speed) { 718 case 1000: 719 if (likely(priv->plat->has_gmac)) 720 ctrl &= ~priv->hw->link.port; 721 stmmac_hw_fix_mac_speed(priv); 722 break; 723 case 100: 724 case 10: 725 if (priv->plat->has_gmac) { 726 ctrl |= priv->hw->link.port; 727 if (phydev->speed == SPEED_100) { 728 ctrl |= priv->hw->link.speed; 729 } else { 730 ctrl &= ~(priv->hw->link.speed); 731 } 732 } else { 733 ctrl &= ~priv->hw->link.port; 734 } 735 stmmac_hw_fix_mac_speed(priv); 736 break; 737 default: 738 if (netif_msg_link(priv)) 739 pr_warn("%s: Speed (%d) not 10/100\n", 740 dev->name, phydev->speed); 741 break; 742 } 743 744 priv->speed = phydev->speed; 745 } 746 747 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 748 749 if (!priv->oldlink) { 750 new_state = 1; 751 priv->oldlink = 1; 752 } 753 } else if (priv->oldlink) { 754 new_state = 1; 755 priv->oldlink = 0; 756 priv->speed = 0; 757 priv->oldduplex = -1; 758 } 759 760 if (new_state && netif_msg_link(priv)) 761 phy_print_status(phydev); 762 763 /* At this stage, it could be needed to setup the EEE or adjust some 764 * MAC related HW registers. 765 */ 766 priv->eee_enabled = stmmac_eee_init(priv); 767 768 spin_unlock_irqrestore(&priv->lock, flags); 769 } 770 771 /** 772 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported 773 * @priv: driver private structure 774 * Description: this is to verify if the HW supports the PCS. 775 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 776 * configured for the TBI, RTBI, or SGMII PHY interface. 777 */ 778 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 779 { 780 int interface = priv->plat->interface; 781 782 if (priv->dma_cap.pcs) { 783 if ((interface == PHY_INTERFACE_MODE_RGMII) || 784 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 785 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 786 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 787 pr_debug("STMMAC: PCS RGMII support enable\n"); 788 priv->pcs = STMMAC_PCS_RGMII; 789 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 790 pr_debug("STMMAC: PCS SGMII support enable\n"); 791 priv->pcs = STMMAC_PCS_SGMII; 792 } 793 } 794 } 795 796 /** 797 * stmmac_init_phy - PHY initialization 798 * @dev: net device structure 799 * Description: it initializes the driver's PHY state, and attaches the PHY 800 * to the mac driver. 801 * Return value: 802 * 0 on success 803 */ 804 static int stmmac_init_phy(struct net_device *dev) 805 { 806 struct stmmac_priv *priv = netdev_priv(dev); 807 struct phy_device *phydev; 808 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 809 char bus_id[MII_BUS_ID_SIZE]; 810 int interface = priv->plat->interface; 811 int max_speed = priv->plat->max_speed; 812 priv->oldlink = 0; 813 priv->speed = 0; 814 priv->oldduplex = -1; 815 816 if (priv->plat->phy_bus_name) 817 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 818 priv->plat->phy_bus_name, priv->plat->bus_id); 819 else 820 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 821 priv->plat->bus_id); 822 823 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 824 priv->plat->phy_addr); 825 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 826 827 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 828 829 if (IS_ERR(phydev)) { 830 pr_err("%s: Could not attach to PHY\n", dev->name); 831 return PTR_ERR(phydev); 832 } 833 834 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 835 if ((interface == PHY_INTERFACE_MODE_MII) || 836 (interface == PHY_INTERFACE_MODE_RMII) || 837 (max_speed < 1000 && max_speed > 0)) 838 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 839 SUPPORTED_1000baseT_Full); 840 841 /* 842 * Broken HW is sometimes missing the pull-up resistor on the 843 * MDIO line, which results in reads to non-existent devices returning 844 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 845 * device as well. 846 * Note: phydev->phy_id is the result of reading the UID PHY registers. 847 */ 848 if (phydev->phy_id == 0) { 849 phy_disconnect(phydev); 850 return -ENODEV; 851 } 852 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 853 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 854 855 priv->phydev = phydev; 856 857 return 0; 858 } 859 860 /** 861 * stmmac_display_ring: display ring 862 * @head: pointer to the head of the ring passed. 863 * @size: size of the ring. 864 * @extend_desc: to verify if extended descriptors are used. 865 * Description: display the control/status and buffer descriptors. 866 */ 867 static void stmmac_display_ring(void *head, int size, int extend_desc) 868 { 869 int i; 870 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 871 struct dma_desc *p = (struct dma_desc *)head; 872 873 for (i = 0; i < size; i++) { 874 u64 x; 875 if (extend_desc) { 876 x = *(u64 *) ep; 877 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 878 i, (unsigned int)virt_to_phys(ep), 879 (unsigned int)x, (unsigned int)(x >> 32), 880 ep->basic.des2, ep->basic.des3); 881 ep++; 882 } else { 883 x = *(u64 *) p; 884 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 885 i, (unsigned int)virt_to_phys(p), 886 (unsigned int)x, (unsigned int)(x >> 32), 887 p->des2, p->des3); 888 p++; 889 } 890 pr_info("\n"); 891 } 892 } 893 894 static void stmmac_display_rings(struct stmmac_priv *priv) 895 { 896 unsigned int txsize = priv->dma_tx_size; 897 unsigned int rxsize = priv->dma_rx_size; 898 899 if (priv->extend_desc) { 900 pr_info("Extended RX descriptor ring:\n"); 901 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 902 pr_info("Extended TX descriptor ring:\n"); 903 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 904 } else { 905 pr_info("RX descriptor ring:\n"); 906 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 907 pr_info("TX descriptor ring:\n"); 908 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 909 } 910 } 911 912 static int stmmac_set_bfsize(int mtu, int bufsize) 913 { 914 int ret = bufsize; 915 916 if (mtu >= BUF_SIZE_4KiB) 917 ret = BUF_SIZE_8KiB; 918 else if (mtu >= BUF_SIZE_2KiB) 919 ret = BUF_SIZE_4KiB; 920 else if (mtu > DEFAULT_BUFSIZE) 921 ret = BUF_SIZE_2KiB; 922 else 923 ret = DEFAULT_BUFSIZE; 924 925 return ret; 926 } 927 928 /** 929 * stmmac_clear_descriptors: clear descriptors 930 * @priv: driver private structure 931 * Description: this function is called to clear the tx and rx descriptors 932 * in case of both basic and extended descriptors are used. 933 */ 934 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 935 { 936 int i; 937 unsigned int txsize = priv->dma_tx_size; 938 unsigned int rxsize = priv->dma_rx_size; 939 940 /* Clear the Rx/Tx descriptors */ 941 for (i = 0; i < rxsize; i++) 942 if (priv->extend_desc) 943 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 944 priv->use_riwt, priv->mode, 945 (i == rxsize - 1)); 946 else 947 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 948 priv->use_riwt, priv->mode, 949 (i == rxsize - 1)); 950 for (i = 0; i < txsize; i++) 951 if (priv->extend_desc) 952 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 953 priv->mode, 954 (i == txsize - 1)); 955 else 956 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 957 priv->mode, 958 (i == txsize - 1)); 959 } 960 961 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 962 int i) 963 { 964 struct sk_buff *skb; 965 966 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 967 GFP_KERNEL); 968 if (!skb) { 969 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 970 return -ENOMEM; 971 } 972 skb_reserve(skb, NET_IP_ALIGN); 973 priv->rx_skbuff[i] = skb; 974 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 975 priv->dma_buf_sz, 976 DMA_FROM_DEVICE); 977 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 978 pr_err("%s: DMA mapping error\n", __func__); 979 dev_kfree_skb_any(skb); 980 return -EINVAL; 981 } 982 983 p->des2 = priv->rx_skbuff_dma[i]; 984 985 if ((priv->hw->mode->init_desc3) && 986 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 987 priv->hw->mode->init_desc3(p); 988 989 return 0; 990 } 991 992 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 993 { 994 if (priv->rx_skbuff[i]) { 995 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 996 priv->dma_buf_sz, DMA_FROM_DEVICE); 997 dev_kfree_skb_any(priv->rx_skbuff[i]); 998 } 999 priv->rx_skbuff[i] = NULL; 1000 } 1001 1002 /** 1003 * init_dma_desc_rings - init the RX/TX descriptor rings 1004 * @dev: net device structure 1005 * Description: this function initializes the DMA RX/TX descriptors 1006 * and allocates the socket buffers. It suppors the chained and ring 1007 * modes. 1008 */ 1009 static int init_dma_desc_rings(struct net_device *dev) 1010 { 1011 int i; 1012 struct stmmac_priv *priv = netdev_priv(dev); 1013 unsigned int txsize = priv->dma_tx_size; 1014 unsigned int rxsize = priv->dma_rx_size; 1015 unsigned int bfsize = 0; 1016 int ret = -ENOMEM; 1017 1018 if (priv->hw->mode->set_16kib_bfsize) 1019 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1020 1021 if (bfsize < BUF_SIZE_16KiB) 1022 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1023 1024 priv->dma_buf_sz = bfsize; 1025 1026 if (netif_msg_probe(priv)) 1027 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1028 txsize, rxsize, bfsize); 1029 1030 if (netif_msg_probe(priv)) { 1031 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1032 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1033 1034 /* RX INITIALIZATION */ 1035 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1036 } 1037 for (i = 0; i < rxsize; i++) { 1038 struct dma_desc *p; 1039 if (priv->extend_desc) 1040 p = &((priv->dma_erx + i)->basic); 1041 else 1042 p = priv->dma_rx + i; 1043 1044 ret = stmmac_init_rx_buffers(priv, p, i); 1045 if (ret) 1046 goto err_init_rx_buffers; 1047 1048 if (netif_msg_probe(priv)) 1049 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1050 priv->rx_skbuff[i]->data, 1051 (unsigned int)priv->rx_skbuff_dma[i]); 1052 } 1053 priv->cur_rx = 0; 1054 priv->dirty_rx = (unsigned int)(i - rxsize); 1055 buf_sz = bfsize; 1056 1057 /* Setup the chained descriptor addresses */ 1058 if (priv->mode == STMMAC_CHAIN_MODE) { 1059 if (priv->extend_desc) { 1060 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1061 rxsize, 1); 1062 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1063 txsize, 1); 1064 } else { 1065 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1066 rxsize, 0); 1067 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1068 txsize, 0); 1069 } 1070 } 1071 1072 /* TX INITIALIZATION */ 1073 for (i = 0; i < txsize; i++) { 1074 struct dma_desc *p; 1075 if (priv->extend_desc) 1076 p = &((priv->dma_etx + i)->basic); 1077 else 1078 p = priv->dma_tx + i; 1079 p->des2 = 0; 1080 priv->tx_skbuff_dma[i].buf = 0; 1081 priv->tx_skbuff_dma[i].map_as_page = false; 1082 priv->tx_skbuff[i] = NULL; 1083 } 1084 1085 priv->dirty_tx = 0; 1086 priv->cur_tx = 0; 1087 1088 stmmac_clear_descriptors(priv); 1089 1090 if (netif_msg_hw(priv)) 1091 stmmac_display_rings(priv); 1092 1093 return 0; 1094 err_init_rx_buffers: 1095 while (--i >= 0) 1096 stmmac_free_rx_buffers(priv, i); 1097 return ret; 1098 } 1099 1100 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1101 { 1102 int i; 1103 1104 for (i = 0; i < priv->dma_rx_size; i++) 1105 stmmac_free_rx_buffers(priv, i); 1106 } 1107 1108 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1109 { 1110 int i; 1111 1112 for (i = 0; i < priv->dma_tx_size; i++) { 1113 struct dma_desc *p; 1114 1115 if (priv->extend_desc) 1116 p = &((priv->dma_etx + i)->basic); 1117 else 1118 p = priv->dma_tx + i; 1119 1120 if (priv->tx_skbuff_dma[i].buf) { 1121 if (priv->tx_skbuff_dma[i].map_as_page) 1122 dma_unmap_page(priv->device, 1123 priv->tx_skbuff_dma[i].buf, 1124 priv->hw->desc->get_tx_len(p), 1125 DMA_TO_DEVICE); 1126 else 1127 dma_unmap_single(priv->device, 1128 priv->tx_skbuff_dma[i].buf, 1129 priv->hw->desc->get_tx_len(p), 1130 DMA_TO_DEVICE); 1131 } 1132 1133 if (priv->tx_skbuff[i] != NULL) { 1134 dev_kfree_skb_any(priv->tx_skbuff[i]); 1135 priv->tx_skbuff[i] = NULL; 1136 priv->tx_skbuff_dma[i].buf = 0; 1137 priv->tx_skbuff_dma[i].map_as_page = false; 1138 } 1139 } 1140 } 1141 1142 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1143 { 1144 unsigned int txsize = priv->dma_tx_size; 1145 unsigned int rxsize = priv->dma_rx_size; 1146 int ret = -ENOMEM; 1147 1148 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1149 GFP_KERNEL); 1150 if (!priv->rx_skbuff_dma) 1151 return -ENOMEM; 1152 1153 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1154 GFP_KERNEL); 1155 if (!priv->rx_skbuff) 1156 goto err_rx_skbuff; 1157 1158 priv->tx_skbuff_dma = kmalloc_array(txsize, 1159 sizeof(*priv->tx_skbuff_dma), 1160 GFP_KERNEL); 1161 if (!priv->tx_skbuff_dma) 1162 goto err_tx_skbuff_dma; 1163 1164 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1165 GFP_KERNEL); 1166 if (!priv->tx_skbuff) 1167 goto err_tx_skbuff; 1168 1169 if (priv->extend_desc) { 1170 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 1171 sizeof(struct 1172 dma_extended_desc), 1173 &priv->dma_rx_phy, 1174 GFP_KERNEL); 1175 if (!priv->dma_erx) 1176 goto err_dma; 1177 1178 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 1179 sizeof(struct 1180 dma_extended_desc), 1181 &priv->dma_tx_phy, 1182 GFP_KERNEL); 1183 if (!priv->dma_etx) { 1184 dma_free_coherent(priv->device, priv->dma_rx_size * 1185 sizeof(struct dma_extended_desc), 1186 priv->dma_erx, priv->dma_rx_phy); 1187 goto err_dma; 1188 } 1189 } else { 1190 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1191 sizeof(struct dma_desc), 1192 &priv->dma_rx_phy, 1193 GFP_KERNEL); 1194 if (!priv->dma_rx) 1195 goto err_dma; 1196 1197 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1198 sizeof(struct dma_desc), 1199 &priv->dma_tx_phy, 1200 GFP_KERNEL); 1201 if (!priv->dma_tx) { 1202 dma_free_coherent(priv->device, priv->dma_rx_size * 1203 sizeof(struct dma_desc), 1204 priv->dma_rx, priv->dma_rx_phy); 1205 goto err_dma; 1206 } 1207 } 1208 1209 return 0; 1210 1211 err_dma: 1212 kfree(priv->tx_skbuff); 1213 err_tx_skbuff: 1214 kfree(priv->tx_skbuff_dma); 1215 err_tx_skbuff_dma: 1216 kfree(priv->rx_skbuff); 1217 err_rx_skbuff: 1218 kfree(priv->rx_skbuff_dma); 1219 return ret; 1220 } 1221 1222 static void free_dma_desc_resources(struct stmmac_priv *priv) 1223 { 1224 /* Release the DMA TX/RX socket buffers */ 1225 dma_free_rx_skbufs(priv); 1226 dma_free_tx_skbufs(priv); 1227 1228 /* Free DMA regions of consistent memory previously allocated */ 1229 if (!priv->extend_desc) { 1230 dma_free_coherent(priv->device, 1231 priv->dma_tx_size * sizeof(struct dma_desc), 1232 priv->dma_tx, priv->dma_tx_phy); 1233 dma_free_coherent(priv->device, 1234 priv->dma_rx_size * sizeof(struct dma_desc), 1235 priv->dma_rx, priv->dma_rx_phy); 1236 } else { 1237 dma_free_coherent(priv->device, priv->dma_tx_size * 1238 sizeof(struct dma_extended_desc), 1239 priv->dma_etx, priv->dma_tx_phy); 1240 dma_free_coherent(priv->device, priv->dma_rx_size * 1241 sizeof(struct dma_extended_desc), 1242 priv->dma_erx, priv->dma_rx_phy); 1243 } 1244 kfree(priv->rx_skbuff_dma); 1245 kfree(priv->rx_skbuff); 1246 kfree(priv->tx_skbuff_dma); 1247 kfree(priv->tx_skbuff); 1248 } 1249 1250 /** 1251 * stmmac_dma_operation_mode - HW DMA operation mode 1252 * @priv: driver private structure 1253 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 1254 * or Store-And-Forward capability. 1255 */ 1256 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1257 { 1258 if (priv->plat->force_thresh_dma_mode) 1259 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1260 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1261 /* 1262 * In case of GMAC, SF mode can be enabled 1263 * to perform the TX COE in HW. This depends on: 1264 * 1) TX COE if actually supported 1265 * 2) There is no bugged Jumbo frame support 1266 * that needs to not insert csum in the TDES. 1267 */ 1268 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1269 tc = SF_DMA_MODE; 1270 } else 1271 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1272 } 1273 1274 /** 1275 * stmmac_tx_clean: 1276 * @priv: driver private structure 1277 * Description: it reclaims resources after transmission completes. 1278 */ 1279 static void stmmac_tx_clean(struct stmmac_priv *priv) 1280 { 1281 unsigned int txsize = priv->dma_tx_size; 1282 1283 spin_lock(&priv->tx_lock); 1284 1285 priv->xstats.tx_clean++; 1286 1287 while (priv->dirty_tx != priv->cur_tx) { 1288 int last; 1289 unsigned int entry = priv->dirty_tx % txsize; 1290 struct sk_buff *skb = priv->tx_skbuff[entry]; 1291 struct dma_desc *p; 1292 1293 if (priv->extend_desc) 1294 p = (struct dma_desc *)(priv->dma_etx + entry); 1295 else 1296 p = priv->dma_tx + entry; 1297 1298 /* Check if the descriptor is owned by the DMA. */ 1299 if (priv->hw->desc->get_tx_owner(p)) 1300 break; 1301 1302 /* Verify tx error by looking at the last segment. */ 1303 last = priv->hw->desc->get_tx_ls(p); 1304 if (likely(last)) { 1305 int tx_error = 1306 priv->hw->desc->tx_status(&priv->dev->stats, 1307 &priv->xstats, p, 1308 priv->ioaddr); 1309 if (likely(tx_error == 0)) { 1310 priv->dev->stats.tx_packets++; 1311 priv->xstats.tx_pkt_n++; 1312 } else 1313 priv->dev->stats.tx_errors++; 1314 1315 stmmac_get_tx_hwtstamp(priv, entry, skb); 1316 } 1317 if (netif_msg_tx_done(priv)) 1318 pr_debug("%s: curr %d, dirty %d\n", __func__, 1319 priv->cur_tx, priv->dirty_tx); 1320 1321 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1322 if (priv->tx_skbuff_dma[entry].map_as_page) 1323 dma_unmap_page(priv->device, 1324 priv->tx_skbuff_dma[entry].buf, 1325 priv->hw->desc->get_tx_len(p), 1326 DMA_TO_DEVICE); 1327 else 1328 dma_unmap_single(priv->device, 1329 priv->tx_skbuff_dma[entry].buf, 1330 priv->hw->desc->get_tx_len(p), 1331 DMA_TO_DEVICE); 1332 priv->tx_skbuff_dma[entry].buf = 0; 1333 priv->tx_skbuff_dma[entry].map_as_page = false; 1334 } 1335 priv->hw->mode->clean_desc3(priv, p); 1336 1337 if (likely(skb != NULL)) { 1338 dev_consume_skb_any(skb); 1339 priv->tx_skbuff[entry] = NULL; 1340 } 1341 1342 priv->hw->desc->release_tx_desc(p, priv->mode); 1343 1344 priv->dirty_tx++; 1345 } 1346 if (unlikely(netif_queue_stopped(priv->dev) && 1347 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1348 netif_tx_lock(priv->dev); 1349 if (netif_queue_stopped(priv->dev) && 1350 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1351 if (netif_msg_tx_done(priv)) 1352 pr_debug("%s: restart transmit\n", __func__); 1353 netif_wake_queue(priv->dev); 1354 } 1355 netif_tx_unlock(priv->dev); 1356 } 1357 1358 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1359 stmmac_enable_eee_mode(priv); 1360 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1361 } 1362 spin_unlock(&priv->tx_lock); 1363 } 1364 1365 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1366 { 1367 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1368 } 1369 1370 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1371 { 1372 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1373 } 1374 1375 /** 1376 * stmmac_tx_err: irq tx error mng function 1377 * @priv: driver private structure 1378 * Description: it cleans the descriptors and restarts the transmission 1379 * in case of errors. 1380 */ 1381 static void stmmac_tx_err(struct stmmac_priv *priv) 1382 { 1383 int i; 1384 int txsize = priv->dma_tx_size; 1385 netif_stop_queue(priv->dev); 1386 1387 priv->hw->dma->stop_tx(priv->ioaddr); 1388 dma_free_tx_skbufs(priv); 1389 for (i = 0; i < txsize; i++) 1390 if (priv->extend_desc) 1391 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1392 priv->mode, 1393 (i == txsize - 1)); 1394 else 1395 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1396 priv->mode, 1397 (i == txsize - 1)); 1398 priv->dirty_tx = 0; 1399 priv->cur_tx = 0; 1400 priv->hw->dma->start_tx(priv->ioaddr); 1401 1402 priv->dev->stats.tx_errors++; 1403 netif_wake_queue(priv->dev); 1404 } 1405 1406 /** 1407 * stmmac_dma_interrupt: DMA ISR 1408 * @priv: driver private structure 1409 * Description: this is the DMA ISR. It is called by the main ISR. 1410 * It calls the dwmac dma routine to understand which type of interrupt 1411 * happened. In case of there is a Normal interrupt and either TX or RX 1412 * interrupt happened so the NAPI is scheduled. 1413 */ 1414 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1415 { 1416 int status; 1417 1418 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1419 if (likely((status & handle_rx)) || (status & handle_tx)) { 1420 if (likely(napi_schedule_prep(&priv->napi))) { 1421 stmmac_disable_dma_irq(priv); 1422 __napi_schedule(&priv->napi); 1423 } 1424 } 1425 if (unlikely(status & tx_hard_error_bump_tc)) { 1426 /* Try to bump up the dma threshold on this failure */ 1427 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 1428 tc += 64; 1429 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1430 priv->xstats.threshold = tc; 1431 } 1432 } else if (unlikely(status == tx_hard_error)) 1433 stmmac_tx_err(priv); 1434 } 1435 1436 /** 1437 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1438 * @priv: driver private structure 1439 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1440 */ 1441 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1442 { 1443 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1444 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1445 1446 dwmac_mmc_intr_all_mask(priv->ioaddr); 1447 1448 if (priv->dma_cap.rmon) { 1449 dwmac_mmc_ctrl(priv->ioaddr, mode); 1450 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1451 } else 1452 pr_info(" No MAC Management Counters available\n"); 1453 } 1454 1455 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1456 { 1457 u32 hwid = priv->hw->synopsys_uid; 1458 1459 /* Check Synopsys Id (not available on old chips) */ 1460 if (likely(hwid)) { 1461 u32 uid = ((hwid & 0x0000ff00) >> 8); 1462 u32 synid = (hwid & 0x000000ff); 1463 1464 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1465 uid, synid); 1466 1467 return synid; 1468 } 1469 return 0; 1470 } 1471 1472 /** 1473 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors 1474 * @priv: driver private structure 1475 * Description: select the Enhanced/Alternate or Normal descriptors. 1476 * In case of Enhanced/Alternate, it looks at the extended descriptors are 1477 * supported by the HW cap. register. 1478 */ 1479 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1480 { 1481 if (priv->plat->enh_desc) { 1482 pr_info(" Enhanced/Alternate descriptors\n"); 1483 1484 /* GMAC older than 3.50 has no extended descriptors */ 1485 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1486 pr_info("\tEnabled extended descriptors\n"); 1487 priv->extend_desc = 1; 1488 } else 1489 pr_warn("Extended descriptors not supported\n"); 1490 1491 priv->hw->desc = &enh_desc_ops; 1492 } else { 1493 pr_info(" Normal descriptors\n"); 1494 priv->hw->desc = &ndesc_ops; 1495 } 1496 } 1497 1498 /** 1499 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register. 1500 * @priv: driver private structure 1501 * Description: 1502 * new GMAC chip generations have a new register to indicate the 1503 * presence of the optional feature/functions. 1504 * This can be also used to override the value passed through the 1505 * platform and necessary for old MAC10/100 and GMAC chips. 1506 */ 1507 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1508 { 1509 u32 hw_cap = 0; 1510 1511 if (priv->hw->dma->get_hw_feature) { 1512 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1513 1514 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1515 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1516 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1517 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1518 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1519 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1520 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1521 priv->dma_cap.pmt_remote_wake_up = 1522 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1523 priv->dma_cap.pmt_magic_frame = 1524 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1525 /* MMC */ 1526 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1527 /* IEEE 1588-2002 */ 1528 priv->dma_cap.time_stamp = 1529 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1530 /* IEEE 1588-2008 */ 1531 priv->dma_cap.atime_stamp = 1532 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1533 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1534 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1535 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1536 /* TX and RX csum */ 1537 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1538 priv->dma_cap.rx_coe_type1 = 1539 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1540 priv->dma_cap.rx_coe_type2 = 1541 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1542 priv->dma_cap.rxfifo_over_2048 = 1543 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1544 /* TX and RX number of channels */ 1545 priv->dma_cap.number_rx_channel = 1546 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1547 priv->dma_cap.number_tx_channel = 1548 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1549 /* Alternate (enhanced) DESC mode */ 1550 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1551 } 1552 1553 return hw_cap; 1554 } 1555 1556 /** 1557 * stmmac_check_ether_addr: check if the MAC addr is valid 1558 * @priv: driver private structure 1559 * Description: 1560 * it is to verify if the MAC address is valid, in case of failures it 1561 * generates a random MAC address 1562 */ 1563 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1564 { 1565 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1566 priv->hw->mac->get_umac_addr(priv->hw, 1567 priv->dev->dev_addr, 0); 1568 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1569 eth_hw_addr_random(priv->dev); 1570 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1571 priv->dev->dev_addr); 1572 } 1573 } 1574 1575 /** 1576 * stmmac_init_dma_engine: DMA init. 1577 * @priv: driver private structure 1578 * Description: 1579 * It inits the DMA invoking the specific MAC/GMAC callback. 1580 * Some DMA parameters can be passed from the platform; 1581 * in case of these are not passed a default is kept for the MAC or GMAC. 1582 */ 1583 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1584 { 1585 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1586 int mixed_burst = 0; 1587 int atds = 0; 1588 1589 if (priv->plat->dma_cfg) { 1590 pbl = priv->plat->dma_cfg->pbl; 1591 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1592 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1593 burst_len = priv->plat->dma_cfg->burst_len; 1594 } 1595 1596 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1597 atds = 1; 1598 1599 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1600 burst_len, priv->dma_tx_phy, 1601 priv->dma_rx_phy, atds); 1602 } 1603 1604 /** 1605 * stmmac_tx_timer: mitigation sw timer for tx. 1606 * @data: data pointer 1607 * Description: 1608 * This is the timer handler to directly invoke the stmmac_tx_clean. 1609 */ 1610 static void stmmac_tx_timer(unsigned long data) 1611 { 1612 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1613 1614 stmmac_tx_clean(priv); 1615 } 1616 1617 /** 1618 * stmmac_init_tx_coalesce: init tx mitigation options. 1619 * @priv: driver private structure 1620 * Description: 1621 * This inits the transmit coalesce parameters: i.e. timer rate, 1622 * timer handler and default threshold used for enabling the 1623 * interrupt on completion bit. 1624 */ 1625 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1626 { 1627 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1628 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1629 init_timer(&priv->txtimer); 1630 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1631 priv->txtimer.data = (unsigned long)priv; 1632 priv->txtimer.function = stmmac_tx_timer; 1633 add_timer(&priv->txtimer); 1634 } 1635 1636 /** 1637 * stmmac_hw_setup: setup mac in a usable state. 1638 * @dev : pointer to the device structure. 1639 * Description: 1640 * This function sets up the ip in a usable state. 1641 * Return value: 1642 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1643 * file on failure. 1644 */ 1645 static int stmmac_hw_setup(struct net_device *dev) 1646 { 1647 struct stmmac_priv *priv = netdev_priv(dev); 1648 int ret; 1649 1650 ret = init_dma_desc_rings(dev); 1651 if (ret < 0) { 1652 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1653 return ret; 1654 } 1655 /* DMA initialization and SW reset */ 1656 ret = stmmac_init_dma_engine(priv); 1657 if (ret < 0) { 1658 pr_err("%s: DMA engine initialization failed\n", __func__); 1659 return ret; 1660 } 1661 1662 /* Copy the MAC addr into the HW */ 1663 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1664 1665 /* If required, perform hw setup of the bus. */ 1666 if (priv->plat->bus_setup) 1667 priv->plat->bus_setup(priv->ioaddr); 1668 1669 /* Initialize the MAC Core */ 1670 priv->hw->mac->core_init(priv->hw, dev->mtu); 1671 1672 ret = priv->hw->mac->rx_ipc(priv->hw); 1673 if (!ret) { 1674 pr_warn(" RX IPC Checksum Offload disabled\n"); 1675 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1676 priv->hw->rx_csum = 0; 1677 } 1678 1679 /* Enable the MAC Rx/Tx */ 1680 stmmac_set_mac(priv->ioaddr, true); 1681 1682 /* Set the HW DMA mode and the COE */ 1683 stmmac_dma_operation_mode(priv); 1684 1685 stmmac_mmc_setup(priv); 1686 1687 ret = stmmac_init_ptp(priv); 1688 if (ret && ret != -EOPNOTSUPP) 1689 pr_warn("%s: failed PTP initialisation\n", __func__); 1690 1691 #ifdef CONFIG_STMMAC_DEBUG_FS 1692 ret = stmmac_init_fs(dev); 1693 if (ret < 0) 1694 pr_warn("%s: failed debugFS registration\n", __func__); 1695 #endif 1696 /* Start the ball rolling... */ 1697 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1698 priv->hw->dma->start_tx(priv->ioaddr); 1699 priv->hw->dma->start_rx(priv->ioaddr); 1700 1701 /* Dump DMA/MAC registers */ 1702 if (netif_msg_hw(priv)) { 1703 priv->hw->mac->dump_regs(priv->hw); 1704 priv->hw->dma->dump_regs(priv->ioaddr); 1705 } 1706 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1707 1708 priv->eee_enabled = stmmac_eee_init(priv); 1709 1710 stmmac_init_tx_coalesce(priv); 1711 1712 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1713 priv->rx_riwt = MAX_DMA_RIWT; 1714 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1715 } 1716 1717 if (priv->pcs && priv->hw->mac->ctrl_ane) 1718 priv->hw->mac->ctrl_ane(priv->hw, 0); 1719 1720 return 0; 1721 } 1722 1723 /** 1724 * stmmac_open - open entry point of the driver 1725 * @dev : pointer to the device structure. 1726 * Description: 1727 * This function is the open entry point of the driver. 1728 * Return value: 1729 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1730 * file on failure. 1731 */ 1732 static int stmmac_open(struct net_device *dev) 1733 { 1734 struct stmmac_priv *priv = netdev_priv(dev); 1735 int ret; 1736 1737 stmmac_check_ether_addr(priv); 1738 1739 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1740 priv->pcs != STMMAC_PCS_RTBI) { 1741 ret = stmmac_init_phy(dev); 1742 if (ret) { 1743 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1744 __func__, ret); 1745 return ret; 1746 } 1747 } 1748 1749 /* Extra statistics */ 1750 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1751 priv->xstats.threshold = tc; 1752 1753 /* Create and initialize the TX/RX descriptors chains. */ 1754 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1755 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1756 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1757 1758 ret = alloc_dma_desc_resources(priv); 1759 if (ret < 0) { 1760 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1761 goto dma_desc_error; 1762 } 1763 1764 ret = stmmac_hw_setup(dev); 1765 if (ret < 0) { 1766 pr_err("%s: Hw setup failed\n", __func__); 1767 goto init_error; 1768 } 1769 1770 if (priv->phydev) 1771 phy_start(priv->phydev); 1772 1773 /* Request the IRQ lines */ 1774 ret = request_irq(dev->irq, stmmac_interrupt, 1775 IRQF_SHARED, dev->name, dev); 1776 if (unlikely(ret < 0)) { 1777 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1778 __func__, dev->irq, ret); 1779 goto init_error; 1780 } 1781 1782 /* Request the Wake IRQ in case of another line is used for WoL */ 1783 if (priv->wol_irq != dev->irq) { 1784 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1785 IRQF_SHARED, dev->name, dev); 1786 if (unlikely(ret < 0)) { 1787 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1788 __func__, priv->wol_irq, ret); 1789 goto wolirq_error; 1790 } 1791 } 1792 1793 /* Request the IRQ lines */ 1794 if (priv->lpi_irq > 0) { 1795 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1796 dev->name, dev); 1797 if (unlikely(ret < 0)) { 1798 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1799 __func__, priv->lpi_irq, ret); 1800 goto lpiirq_error; 1801 } 1802 } 1803 1804 napi_enable(&priv->napi); 1805 netif_start_queue(dev); 1806 1807 return 0; 1808 1809 lpiirq_error: 1810 if (priv->wol_irq != dev->irq) 1811 free_irq(priv->wol_irq, dev); 1812 wolirq_error: 1813 free_irq(dev->irq, dev); 1814 1815 init_error: 1816 free_dma_desc_resources(priv); 1817 dma_desc_error: 1818 if (priv->phydev) 1819 phy_disconnect(priv->phydev); 1820 1821 return ret; 1822 } 1823 1824 /** 1825 * stmmac_release - close entry point of the driver 1826 * @dev : device pointer. 1827 * Description: 1828 * This is the stop entry point of the driver. 1829 */ 1830 static int stmmac_release(struct net_device *dev) 1831 { 1832 struct stmmac_priv *priv = netdev_priv(dev); 1833 1834 if (priv->eee_enabled) 1835 del_timer_sync(&priv->eee_ctrl_timer); 1836 1837 /* Stop and disconnect the PHY */ 1838 if (priv->phydev) { 1839 phy_stop(priv->phydev); 1840 phy_disconnect(priv->phydev); 1841 priv->phydev = NULL; 1842 } 1843 1844 netif_stop_queue(dev); 1845 1846 napi_disable(&priv->napi); 1847 1848 del_timer_sync(&priv->txtimer); 1849 1850 /* Free the IRQ lines */ 1851 free_irq(dev->irq, dev); 1852 if (priv->wol_irq != dev->irq) 1853 free_irq(priv->wol_irq, dev); 1854 if (priv->lpi_irq > 0) 1855 free_irq(priv->lpi_irq, dev); 1856 1857 /* Stop TX/RX DMA and clear the descriptors */ 1858 priv->hw->dma->stop_tx(priv->ioaddr); 1859 priv->hw->dma->stop_rx(priv->ioaddr); 1860 1861 /* Release and free the Rx/Tx resources */ 1862 free_dma_desc_resources(priv); 1863 1864 /* Disable the MAC Rx/Tx */ 1865 stmmac_set_mac(priv->ioaddr, false); 1866 1867 netif_carrier_off(dev); 1868 1869 #ifdef CONFIG_STMMAC_DEBUG_FS 1870 stmmac_exit_fs(); 1871 #endif 1872 1873 stmmac_release_ptp(priv); 1874 1875 return 0; 1876 } 1877 1878 /** 1879 * stmmac_xmit: Tx entry point of the driver 1880 * @skb : the socket buffer 1881 * @dev : device pointer 1882 * Description : this is the tx entry point of the driver. 1883 * It programs the chain or the ring and supports oversized frames 1884 * and SG feature. 1885 */ 1886 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1887 { 1888 struct stmmac_priv *priv = netdev_priv(dev); 1889 unsigned int txsize = priv->dma_tx_size; 1890 unsigned int entry; 1891 int i, csum_insertion = 0, is_jumbo = 0; 1892 int nfrags = skb_shinfo(skb)->nr_frags; 1893 struct dma_desc *desc, *first; 1894 unsigned int nopaged_len = skb_headlen(skb); 1895 unsigned int enh_desc = priv->plat->enh_desc; 1896 1897 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1898 if (!netif_queue_stopped(dev)) { 1899 netif_stop_queue(dev); 1900 /* This is a hard error, log it. */ 1901 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1902 } 1903 return NETDEV_TX_BUSY; 1904 } 1905 1906 spin_lock(&priv->tx_lock); 1907 1908 if (priv->tx_path_in_lpi_mode) 1909 stmmac_disable_eee_mode(priv); 1910 1911 entry = priv->cur_tx % txsize; 1912 1913 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1914 1915 if (priv->extend_desc) 1916 desc = (struct dma_desc *)(priv->dma_etx + entry); 1917 else 1918 desc = priv->dma_tx + entry; 1919 1920 first = desc; 1921 1922 /* To program the descriptors according to the size of the frame */ 1923 if (enh_desc) 1924 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 1925 1926 if (likely(!is_jumbo)) { 1927 desc->des2 = dma_map_single(priv->device, skb->data, 1928 nopaged_len, DMA_TO_DEVICE); 1929 if (dma_mapping_error(priv->device, desc->des2)) 1930 goto dma_map_err; 1931 priv->tx_skbuff_dma[entry].buf = desc->des2; 1932 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1933 csum_insertion, priv->mode); 1934 } else { 1935 desc = first; 1936 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 1937 if (unlikely(entry < 0)) 1938 goto dma_map_err; 1939 } 1940 1941 for (i = 0; i < nfrags; i++) { 1942 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1943 int len = skb_frag_size(frag); 1944 1945 priv->tx_skbuff[entry] = NULL; 1946 entry = (++priv->cur_tx) % txsize; 1947 if (priv->extend_desc) 1948 desc = (struct dma_desc *)(priv->dma_etx + entry); 1949 else 1950 desc = priv->dma_tx + entry; 1951 1952 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1953 DMA_TO_DEVICE); 1954 if (dma_mapping_error(priv->device, desc->des2)) 1955 goto dma_map_err; /* should reuse desc w/o issues */ 1956 1957 priv->tx_skbuff_dma[entry].buf = desc->des2; 1958 priv->tx_skbuff_dma[entry].map_as_page = true; 1959 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 1960 priv->mode); 1961 wmb(); 1962 priv->hw->desc->set_tx_owner(desc); 1963 wmb(); 1964 } 1965 1966 priv->tx_skbuff[entry] = skb; 1967 1968 /* Finalize the latest segment. */ 1969 priv->hw->desc->close_tx_desc(desc); 1970 1971 wmb(); 1972 /* According to the coalesce parameter the IC bit for the latest 1973 * segment could be reset and the timer re-started to invoke the 1974 * stmmac_tx function. This approach takes care about the fragments. 1975 */ 1976 priv->tx_count_frames += nfrags + 1; 1977 if (priv->tx_coal_frames > priv->tx_count_frames) { 1978 priv->hw->desc->clear_tx_ic(desc); 1979 priv->xstats.tx_reset_ic_bit++; 1980 mod_timer(&priv->txtimer, 1981 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1982 } else 1983 priv->tx_count_frames = 0; 1984 1985 /* To avoid raise condition */ 1986 priv->hw->desc->set_tx_owner(first); 1987 wmb(); 1988 1989 priv->cur_tx++; 1990 1991 if (netif_msg_pktdata(priv)) { 1992 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 1993 __func__, (priv->cur_tx % txsize), 1994 (priv->dirty_tx % txsize), entry, first, nfrags); 1995 1996 if (priv->extend_desc) 1997 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 1998 else 1999 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 2000 2001 pr_debug(">>> frame to be transmitted: "); 2002 print_pkt(skb->data, skb->len); 2003 } 2004 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2005 if (netif_msg_hw(priv)) 2006 pr_debug("%s: stop transmitted packets\n", __func__); 2007 netif_stop_queue(dev); 2008 } 2009 2010 dev->stats.tx_bytes += skb->len; 2011 2012 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2013 priv->hwts_tx_en)) { 2014 /* declare that device is doing timestamping */ 2015 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2016 priv->hw->desc->enable_tx_timestamp(first); 2017 } 2018 2019 if (!priv->hwts_tx_en) 2020 skb_tx_timestamp(skb); 2021 2022 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2023 2024 spin_unlock(&priv->tx_lock); 2025 return NETDEV_TX_OK; 2026 2027 dma_map_err: 2028 dev_err(priv->device, "Tx dma map failed\n"); 2029 dev_kfree_skb(skb); 2030 priv->dev->stats.tx_dropped++; 2031 return NETDEV_TX_OK; 2032 } 2033 2034 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2035 { 2036 struct ethhdr *ehdr; 2037 u16 vlanid; 2038 2039 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2040 NETIF_F_HW_VLAN_CTAG_RX && 2041 !__vlan_get_tag(skb, &vlanid)) { 2042 /* pop the vlan tag */ 2043 ehdr = (struct ethhdr *)skb->data; 2044 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2045 skb_pull(skb, VLAN_HLEN); 2046 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2047 } 2048 } 2049 2050 2051 /** 2052 * stmmac_rx_refill: refill used skb preallocated buffers 2053 * @priv: driver private structure 2054 * Description : this is to reallocate the skb for the reception process 2055 * that is based on zero-copy. 2056 */ 2057 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2058 { 2059 unsigned int rxsize = priv->dma_rx_size; 2060 int bfsize = priv->dma_buf_sz; 2061 2062 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 2063 unsigned int entry = priv->dirty_rx % rxsize; 2064 struct dma_desc *p; 2065 2066 if (priv->extend_desc) 2067 p = (struct dma_desc *)(priv->dma_erx + entry); 2068 else 2069 p = priv->dma_rx + entry; 2070 2071 if (likely(priv->rx_skbuff[entry] == NULL)) { 2072 struct sk_buff *skb; 2073 2074 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2075 2076 if (unlikely(skb == NULL)) 2077 break; 2078 2079 priv->rx_skbuff[entry] = skb; 2080 priv->rx_skbuff_dma[entry] = 2081 dma_map_single(priv->device, skb->data, bfsize, 2082 DMA_FROM_DEVICE); 2083 if (dma_mapping_error(priv->device, 2084 priv->rx_skbuff_dma[entry])) { 2085 dev_err(priv->device, "Rx dma map failed\n"); 2086 dev_kfree_skb(skb); 2087 break; 2088 } 2089 p->des2 = priv->rx_skbuff_dma[entry]; 2090 2091 priv->hw->mode->refill_desc3(priv, p); 2092 2093 if (netif_msg_rx_status(priv)) 2094 pr_debug("\trefill entry #%d\n", entry); 2095 } 2096 wmb(); 2097 priv->hw->desc->set_rx_owner(p); 2098 wmb(); 2099 } 2100 } 2101 2102 /** 2103 * stmmac_rx_refill: refill used skb preallocated buffers 2104 * @priv: driver private structure 2105 * @limit: napi bugget. 2106 * Description : this the function called by the napi poll method. 2107 * It gets all the frames inside the ring. 2108 */ 2109 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2110 { 2111 unsigned int rxsize = priv->dma_rx_size; 2112 unsigned int entry = priv->cur_rx % rxsize; 2113 unsigned int next_entry; 2114 unsigned int count = 0; 2115 int coe = priv->hw->rx_csum; 2116 2117 if (netif_msg_rx_status(priv)) { 2118 pr_debug("%s: descriptor ring:\n", __func__); 2119 if (priv->extend_desc) 2120 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2121 else 2122 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2123 } 2124 while (count < limit) { 2125 int status; 2126 struct dma_desc *p; 2127 2128 if (priv->extend_desc) 2129 p = (struct dma_desc *)(priv->dma_erx + entry); 2130 else 2131 p = priv->dma_rx + entry; 2132 2133 if (priv->hw->desc->get_rx_owner(p)) 2134 break; 2135 2136 count++; 2137 2138 next_entry = (++priv->cur_rx) % rxsize; 2139 if (priv->extend_desc) 2140 prefetch(priv->dma_erx + next_entry); 2141 else 2142 prefetch(priv->dma_rx + next_entry); 2143 2144 /* read the status of the incoming frame */ 2145 status = priv->hw->desc->rx_status(&priv->dev->stats, 2146 &priv->xstats, p); 2147 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2148 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2149 &priv->xstats, 2150 priv->dma_erx + 2151 entry); 2152 if (unlikely(status == discard_frame)) { 2153 priv->dev->stats.rx_errors++; 2154 if (priv->hwts_rx_en && !priv->extend_desc) { 2155 /* DESC2 & DESC3 will be overwitten by device 2156 * with timestamp value, hence reinitialize 2157 * them in stmmac_rx_refill() function so that 2158 * device can reuse it. 2159 */ 2160 priv->rx_skbuff[entry] = NULL; 2161 dma_unmap_single(priv->device, 2162 priv->rx_skbuff_dma[entry], 2163 priv->dma_buf_sz, 2164 DMA_FROM_DEVICE); 2165 } 2166 } else { 2167 struct sk_buff *skb; 2168 int frame_len; 2169 2170 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2171 2172 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2173 * Type frames (LLC/LLC-SNAP) 2174 */ 2175 if (unlikely(status != llc_snap)) 2176 frame_len -= ETH_FCS_LEN; 2177 2178 if (netif_msg_rx_status(priv)) { 2179 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2180 p, entry, p->des2); 2181 if (frame_len > ETH_FRAME_LEN) 2182 pr_debug("\tframe size %d, COE: %d\n", 2183 frame_len, status); 2184 } 2185 skb = priv->rx_skbuff[entry]; 2186 if (unlikely(!skb)) { 2187 pr_err("%s: Inconsistent Rx descriptor chain\n", 2188 priv->dev->name); 2189 priv->dev->stats.rx_dropped++; 2190 break; 2191 } 2192 prefetch(skb->data - NET_IP_ALIGN); 2193 priv->rx_skbuff[entry] = NULL; 2194 2195 stmmac_get_rx_hwtstamp(priv, entry, skb); 2196 2197 skb_put(skb, frame_len); 2198 dma_unmap_single(priv->device, 2199 priv->rx_skbuff_dma[entry], 2200 priv->dma_buf_sz, DMA_FROM_DEVICE); 2201 2202 if (netif_msg_pktdata(priv)) { 2203 pr_debug("frame received (%dbytes)", frame_len); 2204 print_pkt(skb->data, frame_len); 2205 } 2206 2207 stmmac_rx_vlan(priv->dev, skb); 2208 2209 skb->protocol = eth_type_trans(skb, priv->dev); 2210 2211 if (unlikely(!coe)) 2212 skb_checksum_none_assert(skb); 2213 else 2214 skb->ip_summed = CHECKSUM_UNNECESSARY; 2215 2216 napi_gro_receive(&priv->napi, skb); 2217 2218 priv->dev->stats.rx_packets++; 2219 priv->dev->stats.rx_bytes += frame_len; 2220 } 2221 entry = next_entry; 2222 } 2223 2224 stmmac_rx_refill(priv); 2225 2226 priv->xstats.rx_pkt_n += count; 2227 2228 return count; 2229 } 2230 2231 /** 2232 * stmmac_poll - stmmac poll method (NAPI) 2233 * @napi : pointer to the napi structure. 2234 * @budget : maximum number of packets that the current CPU can receive from 2235 * all interfaces. 2236 * Description : 2237 * To look at the incoming frames and clear the tx resources. 2238 */ 2239 static int stmmac_poll(struct napi_struct *napi, int budget) 2240 { 2241 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2242 int work_done = 0; 2243 2244 priv->xstats.napi_poll++; 2245 stmmac_tx_clean(priv); 2246 2247 work_done = stmmac_rx(priv, budget); 2248 if (work_done < budget) { 2249 napi_complete(napi); 2250 stmmac_enable_dma_irq(priv); 2251 } 2252 return work_done; 2253 } 2254 2255 /** 2256 * stmmac_tx_timeout 2257 * @dev : Pointer to net device structure 2258 * Description: this function is called when a packet transmission fails to 2259 * complete within a reasonable time. The driver will mark the error in the 2260 * netdev structure and arrange for the device to be reset to a sane state 2261 * in order to transmit a new packet. 2262 */ 2263 static void stmmac_tx_timeout(struct net_device *dev) 2264 { 2265 struct stmmac_priv *priv = netdev_priv(dev); 2266 2267 /* Clear Tx resources and restart transmitting again */ 2268 stmmac_tx_err(priv); 2269 } 2270 2271 /** 2272 * stmmac_set_rx_mode - entry point for multicast addressing 2273 * @dev : pointer to the device structure 2274 * Description: 2275 * This function is a driver entry point which gets called by the kernel 2276 * whenever multicast addresses must be enabled/disabled. 2277 * Return value: 2278 * void. 2279 */ 2280 static void stmmac_set_rx_mode(struct net_device *dev) 2281 { 2282 struct stmmac_priv *priv = netdev_priv(dev); 2283 2284 spin_lock(&priv->lock); 2285 priv->hw->mac->set_filter(priv->hw, dev); 2286 spin_unlock(&priv->lock); 2287 } 2288 2289 /** 2290 * stmmac_change_mtu - entry point to change MTU size for the device. 2291 * @dev : device pointer. 2292 * @new_mtu : the new MTU size for the device. 2293 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2294 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2295 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2296 * Return value: 2297 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2298 * file on failure. 2299 */ 2300 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2301 { 2302 struct stmmac_priv *priv = netdev_priv(dev); 2303 int max_mtu; 2304 2305 if (netif_running(dev)) { 2306 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2307 return -EBUSY; 2308 } 2309 2310 if (priv->plat->enh_desc) 2311 max_mtu = JUMBO_LEN; 2312 else 2313 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2314 2315 if (priv->plat->maxmtu < max_mtu) 2316 max_mtu = priv->plat->maxmtu; 2317 2318 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2319 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2320 return -EINVAL; 2321 } 2322 2323 dev->mtu = new_mtu; 2324 netdev_update_features(dev); 2325 2326 return 0; 2327 } 2328 2329 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2330 netdev_features_t features) 2331 { 2332 struct stmmac_priv *priv = netdev_priv(dev); 2333 2334 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2335 features &= ~NETIF_F_RXCSUM; 2336 2337 if (!priv->plat->tx_coe) 2338 features &= ~NETIF_F_ALL_CSUM; 2339 2340 /* Some GMAC devices have a bugged Jumbo frame support that 2341 * needs to have the Tx COE disabled for oversized frames 2342 * (due to limited buffer sizes). In this case we disable 2343 * the TX csum insertionin the TDES and not use SF. 2344 */ 2345 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2346 features &= ~NETIF_F_ALL_CSUM; 2347 2348 return features; 2349 } 2350 2351 static int stmmac_set_features(struct net_device *netdev, 2352 netdev_features_t features) 2353 { 2354 struct stmmac_priv *priv = netdev_priv(netdev); 2355 2356 /* Keep the COE Type in case of csum is supporting */ 2357 if (features & NETIF_F_RXCSUM) 2358 priv->hw->rx_csum = priv->plat->rx_coe; 2359 else 2360 priv->hw->rx_csum = 0; 2361 /* No check needed because rx_coe has been set before and it will be 2362 * fixed in case of issue. 2363 */ 2364 priv->hw->mac->rx_ipc(priv->hw); 2365 2366 return 0; 2367 } 2368 2369 /** 2370 * stmmac_interrupt - main ISR 2371 * @irq: interrupt number. 2372 * @dev_id: to pass the net device pointer. 2373 * Description: this is the main driver interrupt service routine. 2374 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI 2375 * interrupts. 2376 */ 2377 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2378 { 2379 struct net_device *dev = (struct net_device *)dev_id; 2380 struct stmmac_priv *priv = netdev_priv(dev); 2381 2382 if (priv->irq_wake) 2383 pm_wakeup_event(priv->device, 0); 2384 2385 if (unlikely(!dev)) { 2386 pr_err("%s: invalid dev pointer\n", __func__); 2387 return IRQ_NONE; 2388 } 2389 2390 /* To handle GMAC own interrupts */ 2391 if (priv->plat->has_gmac) { 2392 int status = priv->hw->mac->host_irq_status(priv->hw, 2393 &priv->xstats); 2394 if (unlikely(status)) { 2395 /* For LPI we need to save the tx status */ 2396 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2397 priv->tx_path_in_lpi_mode = true; 2398 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2399 priv->tx_path_in_lpi_mode = false; 2400 } 2401 } 2402 2403 /* To handle DMA interrupts */ 2404 stmmac_dma_interrupt(priv); 2405 2406 return IRQ_HANDLED; 2407 } 2408 2409 #ifdef CONFIG_NET_POLL_CONTROLLER 2410 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2411 * to allow network I/O with interrupts disabled. 2412 */ 2413 static void stmmac_poll_controller(struct net_device *dev) 2414 { 2415 disable_irq(dev->irq); 2416 stmmac_interrupt(dev->irq, dev); 2417 enable_irq(dev->irq); 2418 } 2419 #endif 2420 2421 /** 2422 * stmmac_ioctl - Entry point for the Ioctl 2423 * @dev: Device pointer. 2424 * @rq: An IOCTL specefic structure, that can contain a pointer to 2425 * a proprietary structure used to pass information to the driver. 2426 * @cmd: IOCTL command 2427 * Description: 2428 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2429 */ 2430 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2431 { 2432 struct stmmac_priv *priv = netdev_priv(dev); 2433 int ret = -EOPNOTSUPP; 2434 2435 if (!netif_running(dev)) 2436 return -EINVAL; 2437 2438 switch (cmd) { 2439 case SIOCGMIIPHY: 2440 case SIOCGMIIREG: 2441 case SIOCSMIIREG: 2442 if (!priv->phydev) 2443 return -EINVAL; 2444 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2445 break; 2446 case SIOCSHWTSTAMP: 2447 ret = stmmac_hwtstamp_ioctl(dev, rq); 2448 break; 2449 default: 2450 break; 2451 } 2452 2453 return ret; 2454 } 2455 2456 #ifdef CONFIG_STMMAC_DEBUG_FS 2457 static struct dentry *stmmac_fs_dir; 2458 static struct dentry *stmmac_rings_status; 2459 static struct dentry *stmmac_dma_cap; 2460 2461 static void sysfs_display_ring(void *head, int size, int extend_desc, 2462 struct seq_file *seq) 2463 { 2464 int i; 2465 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2466 struct dma_desc *p = (struct dma_desc *)head; 2467 2468 for (i = 0; i < size; i++) { 2469 u64 x; 2470 if (extend_desc) { 2471 x = *(u64 *) ep; 2472 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2473 i, (unsigned int)virt_to_phys(ep), 2474 (unsigned int)x, (unsigned int)(x >> 32), 2475 ep->basic.des2, ep->basic.des3); 2476 ep++; 2477 } else { 2478 x = *(u64 *) p; 2479 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2480 i, (unsigned int)virt_to_phys(ep), 2481 (unsigned int)x, (unsigned int)(x >> 32), 2482 p->des2, p->des3); 2483 p++; 2484 } 2485 seq_printf(seq, "\n"); 2486 } 2487 } 2488 2489 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2490 { 2491 struct net_device *dev = seq->private; 2492 struct stmmac_priv *priv = netdev_priv(dev); 2493 unsigned int txsize = priv->dma_tx_size; 2494 unsigned int rxsize = priv->dma_rx_size; 2495 2496 if (priv->extend_desc) { 2497 seq_printf(seq, "Extended RX descriptor ring:\n"); 2498 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2499 seq_printf(seq, "Extended TX descriptor ring:\n"); 2500 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2501 } else { 2502 seq_printf(seq, "RX descriptor ring:\n"); 2503 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2504 seq_printf(seq, "TX descriptor ring:\n"); 2505 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2506 } 2507 2508 return 0; 2509 } 2510 2511 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2512 { 2513 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2514 } 2515 2516 static const struct file_operations stmmac_rings_status_fops = { 2517 .owner = THIS_MODULE, 2518 .open = stmmac_sysfs_ring_open, 2519 .read = seq_read, 2520 .llseek = seq_lseek, 2521 .release = single_release, 2522 }; 2523 2524 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2525 { 2526 struct net_device *dev = seq->private; 2527 struct stmmac_priv *priv = netdev_priv(dev); 2528 2529 if (!priv->hw_cap_support) { 2530 seq_printf(seq, "DMA HW features not supported\n"); 2531 return 0; 2532 } 2533 2534 seq_printf(seq, "==============================\n"); 2535 seq_printf(seq, "\tDMA HW features\n"); 2536 seq_printf(seq, "==============================\n"); 2537 2538 seq_printf(seq, "\t10/100 Mbps %s\n", 2539 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2540 seq_printf(seq, "\t1000 Mbps %s\n", 2541 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2542 seq_printf(seq, "\tHalf duple %s\n", 2543 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2544 seq_printf(seq, "\tHash Filter: %s\n", 2545 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2546 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2547 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2548 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2549 (priv->dma_cap.pcs) ? "Y" : "N"); 2550 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2551 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2552 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2553 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2554 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2555 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2556 seq_printf(seq, "\tRMON module: %s\n", 2557 (priv->dma_cap.rmon) ? "Y" : "N"); 2558 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2559 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2560 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2561 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2562 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2563 (priv->dma_cap.eee) ? "Y" : "N"); 2564 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2565 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2566 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2567 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2568 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2569 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2570 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2571 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2572 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2573 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2574 priv->dma_cap.number_rx_channel); 2575 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2576 priv->dma_cap.number_tx_channel); 2577 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2578 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2579 2580 return 0; 2581 } 2582 2583 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2584 { 2585 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2586 } 2587 2588 static const struct file_operations stmmac_dma_cap_fops = { 2589 .owner = THIS_MODULE, 2590 .open = stmmac_sysfs_dma_cap_open, 2591 .read = seq_read, 2592 .llseek = seq_lseek, 2593 .release = single_release, 2594 }; 2595 2596 static int stmmac_init_fs(struct net_device *dev) 2597 { 2598 /* Create debugfs entries */ 2599 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2600 2601 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2602 pr_err("ERROR %s, debugfs create directory failed\n", 2603 STMMAC_RESOURCE_NAME); 2604 2605 return -ENOMEM; 2606 } 2607 2608 /* Entry to report DMA RX/TX rings */ 2609 stmmac_rings_status = debugfs_create_file("descriptors_status", 2610 S_IRUGO, stmmac_fs_dir, dev, 2611 &stmmac_rings_status_fops); 2612 2613 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2614 pr_info("ERROR creating stmmac ring debugfs file\n"); 2615 debugfs_remove(stmmac_fs_dir); 2616 2617 return -ENOMEM; 2618 } 2619 2620 /* Entry to report the DMA HW features */ 2621 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2622 dev, &stmmac_dma_cap_fops); 2623 2624 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2625 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2626 debugfs_remove(stmmac_rings_status); 2627 debugfs_remove(stmmac_fs_dir); 2628 2629 return -ENOMEM; 2630 } 2631 2632 return 0; 2633 } 2634 2635 static void stmmac_exit_fs(void) 2636 { 2637 debugfs_remove(stmmac_rings_status); 2638 debugfs_remove(stmmac_dma_cap); 2639 debugfs_remove(stmmac_fs_dir); 2640 } 2641 #endif /* CONFIG_STMMAC_DEBUG_FS */ 2642 2643 static const struct net_device_ops stmmac_netdev_ops = { 2644 .ndo_open = stmmac_open, 2645 .ndo_start_xmit = stmmac_xmit, 2646 .ndo_stop = stmmac_release, 2647 .ndo_change_mtu = stmmac_change_mtu, 2648 .ndo_fix_features = stmmac_fix_features, 2649 .ndo_set_features = stmmac_set_features, 2650 .ndo_set_rx_mode = stmmac_set_rx_mode, 2651 .ndo_tx_timeout = stmmac_tx_timeout, 2652 .ndo_do_ioctl = stmmac_ioctl, 2653 #ifdef CONFIG_NET_POLL_CONTROLLER 2654 .ndo_poll_controller = stmmac_poll_controller, 2655 #endif 2656 .ndo_set_mac_address = eth_mac_addr, 2657 }; 2658 2659 /** 2660 * stmmac_hw_init - Init the MAC device 2661 * @priv: driver private structure 2662 * Description: this function detects which MAC device 2663 * (GMAC/MAC10-100) has to attached, checks the HW capability 2664 * (if supported) and sets the driver's features (for example 2665 * to use the ring or chaine mode or support the normal/enh 2666 * descriptor structure). 2667 */ 2668 static int stmmac_hw_init(struct stmmac_priv *priv) 2669 { 2670 struct mac_device_info *mac; 2671 2672 /* Identify the MAC HW device */ 2673 if (priv->plat->has_gmac) { 2674 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2675 mac = dwmac1000_setup(priv->ioaddr, 2676 priv->plat->multicast_filter_bins, 2677 priv->plat->unicast_filter_entries); 2678 } else { 2679 mac = dwmac100_setup(priv->ioaddr); 2680 } 2681 if (!mac) 2682 return -ENOMEM; 2683 2684 priv->hw = mac; 2685 2686 /* Get and dump the chip ID */ 2687 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2688 2689 /* To use the chained or ring mode */ 2690 if (chain_mode) { 2691 priv->hw->mode = &chain_mode_ops; 2692 pr_info(" Chain mode enabled\n"); 2693 priv->mode = STMMAC_CHAIN_MODE; 2694 } else { 2695 priv->hw->mode = &ring_mode_ops; 2696 pr_info(" Ring mode enabled\n"); 2697 priv->mode = STMMAC_RING_MODE; 2698 } 2699 2700 /* Get the HW capability (new GMAC newer than 3.50a) */ 2701 priv->hw_cap_support = stmmac_get_hw_features(priv); 2702 if (priv->hw_cap_support) { 2703 pr_info(" DMA HW capability register supported"); 2704 2705 /* We can override some gmac/dma configuration fields: e.g. 2706 * enh_desc, tx_coe (e.g. that are passed through the 2707 * platform) with the values from the HW capability 2708 * register (if supported). 2709 */ 2710 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2711 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2712 2713 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2714 2715 if (priv->dma_cap.rx_coe_type2) 2716 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2717 else if (priv->dma_cap.rx_coe_type1) 2718 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2719 2720 } else 2721 pr_info(" No HW DMA feature register supported"); 2722 2723 /* To use alternate (extended) or normal descriptor structures */ 2724 stmmac_selec_desc_mode(priv); 2725 2726 if (priv->plat->rx_coe) { 2727 priv->hw->rx_csum = priv->plat->rx_coe; 2728 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2729 priv->plat->rx_coe); 2730 } 2731 if (priv->plat->tx_coe) 2732 pr_info(" TX Checksum insertion supported\n"); 2733 2734 if (priv->plat->pmt) { 2735 pr_info(" Wake-Up On Lan supported\n"); 2736 device_set_wakeup_capable(priv->device, 1); 2737 } 2738 2739 return 0; 2740 } 2741 2742 /** 2743 * stmmac_dvr_probe 2744 * @device: device pointer 2745 * @plat_dat: platform data pointer 2746 * @addr: iobase memory address 2747 * Description: this is the main probe function used to 2748 * call the alloc_etherdev, allocate the priv structure. 2749 */ 2750 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2751 struct plat_stmmacenet_data *plat_dat, 2752 void __iomem *addr) 2753 { 2754 int ret = 0; 2755 struct net_device *ndev = NULL; 2756 struct stmmac_priv *priv; 2757 2758 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2759 if (!ndev) 2760 return NULL; 2761 2762 SET_NETDEV_DEV(ndev, device); 2763 2764 priv = netdev_priv(ndev); 2765 priv->device = device; 2766 priv->dev = ndev; 2767 2768 ether_setup(ndev); 2769 2770 stmmac_set_ethtool_ops(ndev); 2771 priv->pause = pause; 2772 priv->plat = plat_dat; 2773 priv->ioaddr = addr; 2774 priv->dev->base_addr = (unsigned long)addr; 2775 2776 /* Verify driver arguments */ 2777 stmmac_verify_args(); 2778 2779 /* Override with kernel parameters if supplied XXX CRS XXX 2780 * this needs to have multiple instances 2781 */ 2782 if ((phyaddr >= 0) && (phyaddr <= 31)) 2783 priv->plat->phy_addr = phyaddr; 2784 2785 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 2786 if (IS_ERR(priv->stmmac_clk)) { 2787 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 2788 __func__); 2789 /* If failed to obtain stmmac_clk and specific clk_csr value 2790 * is NOT passed from the platform, probe fail. 2791 */ 2792 if (!priv->plat->clk_csr) { 2793 ret = PTR_ERR(priv->stmmac_clk); 2794 goto error_clk_get; 2795 } else { 2796 priv->stmmac_clk = NULL; 2797 } 2798 } 2799 clk_prepare_enable(priv->stmmac_clk); 2800 2801 priv->stmmac_rst = devm_reset_control_get(priv->device, 2802 STMMAC_RESOURCE_NAME); 2803 if (IS_ERR(priv->stmmac_rst)) { 2804 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 2805 ret = -EPROBE_DEFER; 2806 goto error_hw_init; 2807 } 2808 dev_info(priv->device, "no reset control found\n"); 2809 priv->stmmac_rst = NULL; 2810 } 2811 if (priv->stmmac_rst) 2812 reset_control_deassert(priv->stmmac_rst); 2813 2814 /* Init MAC and get the capabilities */ 2815 ret = stmmac_hw_init(priv); 2816 if (ret) 2817 goto error_hw_init; 2818 2819 ndev->netdev_ops = &stmmac_netdev_ops; 2820 2821 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2822 NETIF_F_RXCSUM; 2823 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2824 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2825 #ifdef STMMAC_VLAN_TAG_USED 2826 /* Both mac100 and gmac support receive VLAN tag detection */ 2827 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2828 #endif 2829 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2830 2831 if (flow_ctrl) 2832 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2833 2834 /* Rx Watchdog is available in the COREs newer than the 3.40. 2835 * In some case, for example on bugged HW this feature 2836 * has to be disable and this can be done by passing the 2837 * riwt_off field from the platform. 2838 */ 2839 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2840 priv->use_riwt = 1; 2841 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2842 } 2843 2844 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2845 2846 spin_lock_init(&priv->lock); 2847 spin_lock_init(&priv->tx_lock); 2848 2849 ret = register_netdev(ndev); 2850 if (ret) { 2851 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2852 goto error_netdev_register; 2853 } 2854 2855 /* If a specific clk_csr value is passed from the platform 2856 * this means that the CSR Clock Range selection cannot be 2857 * changed at run-time and it is fixed. Viceversa the driver'll try to 2858 * set the MDC clock dynamically according to the csr actual 2859 * clock input. 2860 */ 2861 if (!priv->plat->clk_csr) 2862 stmmac_clk_csr_set(priv); 2863 else 2864 priv->clk_csr = priv->plat->clk_csr; 2865 2866 stmmac_check_pcs_mode(priv); 2867 2868 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2869 priv->pcs != STMMAC_PCS_RTBI) { 2870 /* MDIO bus Registration */ 2871 ret = stmmac_mdio_register(ndev); 2872 if (ret < 0) { 2873 pr_debug("%s: MDIO bus (id: %d) registration failed", 2874 __func__, priv->plat->bus_id); 2875 goto error_mdio_register; 2876 } 2877 } 2878 2879 return priv; 2880 2881 error_mdio_register: 2882 unregister_netdev(ndev); 2883 error_netdev_register: 2884 netif_napi_del(&priv->napi); 2885 error_hw_init: 2886 clk_disable_unprepare(priv->stmmac_clk); 2887 error_clk_get: 2888 free_netdev(ndev); 2889 2890 return ERR_PTR(ret); 2891 } 2892 2893 /** 2894 * stmmac_dvr_remove 2895 * @ndev: net device pointer 2896 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2897 * changes the link status, releases the DMA descriptor rings. 2898 */ 2899 int stmmac_dvr_remove(struct net_device *ndev) 2900 { 2901 struct stmmac_priv *priv = netdev_priv(ndev); 2902 2903 pr_info("%s:\n\tremoving driver", __func__); 2904 2905 priv->hw->dma->stop_rx(priv->ioaddr); 2906 priv->hw->dma->stop_tx(priv->ioaddr); 2907 2908 stmmac_set_mac(priv->ioaddr, false); 2909 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2910 priv->pcs != STMMAC_PCS_RTBI) 2911 stmmac_mdio_unregister(ndev); 2912 netif_carrier_off(ndev); 2913 unregister_netdev(ndev); 2914 if (priv->stmmac_rst) 2915 reset_control_assert(priv->stmmac_rst); 2916 clk_disable_unprepare(priv->stmmac_clk); 2917 free_netdev(ndev); 2918 2919 return 0; 2920 } 2921 2922 #ifdef CONFIG_PM 2923 int stmmac_suspend(struct net_device *ndev) 2924 { 2925 struct stmmac_priv *priv = netdev_priv(ndev); 2926 unsigned long flags; 2927 2928 if (!ndev || !netif_running(ndev)) 2929 return 0; 2930 2931 if (priv->phydev) 2932 phy_stop(priv->phydev); 2933 2934 spin_lock_irqsave(&priv->lock, flags); 2935 2936 netif_device_detach(ndev); 2937 netif_stop_queue(ndev); 2938 2939 napi_disable(&priv->napi); 2940 2941 /* Stop TX/RX DMA */ 2942 priv->hw->dma->stop_tx(priv->ioaddr); 2943 priv->hw->dma->stop_rx(priv->ioaddr); 2944 2945 stmmac_clear_descriptors(priv); 2946 2947 /* Enable Power down mode by programming the PMT regs */ 2948 if (device_may_wakeup(priv->device)) { 2949 priv->hw->mac->pmt(priv->hw, priv->wolopts); 2950 priv->irq_wake = 1; 2951 } else { 2952 stmmac_set_mac(priv->ioaddr, false); 2953 pinctrl_pm_select_sleep_state(priv->device); 2954 /* Disable clock in case of PWM is off */ 2955 clk_disable_unprepare(priv->stmmac_clk); 2956 } 2957 spin_unlock_irqrestore(&priv->lock, flags); 2958 2959 priv->oldlink = 0; 2960 priv->speed = 0; 2961 priv->oldduplex = -1; 2962 return 0; 2963 } 2964 2965 int stmmac_resume(struct net_device *ndev) 2966 { 2967 struct stmmac_priv *priv = netdev_priv(ndev); 2968 unsigned long flags; 2969 2970 if (!netif_running(ndev)) 2971 return 0; 2972 2973 spin_lock_irqsave(&priv->lock, flags); 2974 2975 /* Power Down bit, into the PM register, is cleared 2976 * automatically as soon as a magic packet or a Wake-up frame 2977 * is received. Anyway, it's better to manually clear 2978 * this bit because it can generate problems while resuming 2979 * from another devices (e.g. serial console). 2980 */ 2981 if (device_may_wakeup(priv->device)) { 2982 priv->hw->mac->pmt(priv->hw, 0); 2983 priv->irq_wake = 0; 2984 } else { 2985 pinctrl_pm_select_default_state(priv->device); 2986 /* enable the clk prevously disabled */ 2987 clk_prepare_enable(priv->stmmac_clk); 2988 /* reset the phy so that it's ready */ 2989 if (priv->mii) 2990 stmmac_mdio_reset(priv->mii); 2991 } 2992 2993 netif_device_attach(ndev); 2994 2995 stmmac_hw_setup(ndev); 2996 2997 napi_enable(&priv->napi); 2998 2999 netif_start_queue(ndev); 3000 3001 spin_unlock_irqrestore(&priv->lock, flags); 3002 3003 if (priv->phydev) 3004 phy_start(priv->phydev); 3005 3006 return 0; 3007 } 3008 #endif /* CONFIG_PM */ 3009 3010 /* Driver can be configured w/ and w/ both PCI and Platf drivers 3011 * depending on the configuration selected. 3012 */ 3013 static int __init stmmac_init(void) 3014 { 3015 int ret; 3016 3017 ret = stmmac_register_platform(); 3018 if (ret) 3019 goto err; 3020 ret = stmmac_register_pci(); 3021 if (ret) 3022 goto err_pci; 3023 return 0; 3024 err_pci: 3025 stmmac_unregister_platform(); 3026 err: 3027 pr_err("stmmac: driver registration failed\n"); 3028 return ret; 3029 } 3030 3031 static void __exit stmmac_exit(void) 3032 { 3033 stmmac_unregister_platform(); 3034 stmmac_unregister_pci(); 3035 } 3036 3037 module_init(stmmac_init); 3038 module_exit(stmmac_exit); 3039 3040 #ifndef MODULE 3041 static int __init stmmac_cmdline_opt(char *str) 3042 { 3043 char *opt; 3044 3045 if (!str || !*str) 3046 return -EINVAL; 3047 while ((opt = strsep(&str, ",")) != NULL) { 3048 if (!strncmp(opt, "debug:", 6)) { 3049 if (kstrtoint(opt + 6, 0, &debug)) 3050 goto err; 3051 } else if (!strncmp(opt, "phyaddr:", 8)) { 3052 if (kstrtoint(opt + 8, 0, &phyaddr)) 3053 goto err; 3054 } else if (!strncmp(opt, "dma_txsize:", 11)) { 3055 if (kstrtoint(opt + 11, 0, &dma_txsize)) 3056 goto err; 3057 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 3058 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 3059 goto err; 3060 } else if (!strncmp(opt, "buf_sz:", 7)) { 3061 if (kstrtoint(opt + 7, 0, &buf_sz)) 3062 goto err; 3063 } else if (!strncmp(opt, "tc:", 3)) { 3064 if (kstrtoint(opt + 3, 0, &tc)) 3065 goto err; 3066 } else if (!strncmp(opt, "watchdog:", 9)) { 3067 if (kstrtoint(opt + 9, 0, &watchdog)) 3068 goto err; 3069 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3070 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3071 goto err; 3072 } else if (!strncmp(opt, "pause:", 6)) { 3073 if (kstrtoint(opt + 6, 0, &pause)) 3074 goto err; 3075 } else if (!strncmp(opt, "eee_timer:", 10)) { 3076 if (kstrtoint(opt + 10, 0, &eee_timer)) 3077 goto err; 3078 } else if (!strncmp(opt, "chain_mode:", 11)) { 3079 if (kstrtoint(opt + 11, 0, &chain_mode)) 3080 goto err; 3081 } 3082 } 3083 return 0; 3084 3085 err: 3086 pr_err("%s: ERROR broken module parameter conversion", __func__); 3087 return -EINVAL; 3088 } 3089 3090 __setup("stmmaceth=", stmmac_cmdline_opt); 3091 #endif /* MODULE */ 3092 3093 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3094 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3095 MODULE_LICENSE("GPL"); 3096