1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 135 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 136 u32 rxmode, u32 chan); 137 138 #ifdef CONFIG_DEBUG_FS 139 static const struct net_device_ops stmmac_netdev_ops; 140 static void stmmac_init_fs(struct net_device *dev); 141 static void stmmac_exit_fs(struct net_device *dev); 142 #endif 143 144 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 145 146 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 147 { 148 int ret = 0; 149 150 if (enabled) { 151 ret = clk_prepare_enable(priv->plat->stmmac_clk); 152 if (ret) 153 return ret; 154 ret = clk_prepare_enable(priv->plat->pclk); 155 if (ret) { 156 clk_disable_unprepare(priv->plat->stmmac_clk); 157 return ret; 158 } 159 if (priv->plat->clks_config) { 160 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 161 if (ret) { 162 clk_disable_unprepare(priv->plat->stmmac_clk); 163 clk_disable_unprepare(priv->plat->pclk); 164 return ret; 165 } 166 } 167 } else { 168 clk_disable_unprepare(priv->plat->stmmac_clk); 169 clk_disable_unprepare(priv->plat->pclk); 170 if (priv->plat->clks_config) 171 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 172 } 173 174 return ret; 175 } 176 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 177 178 /** 179 * stmmac_verify_args - verify the driver parameters. 180 * Description: it checks the driver parameters and set a default in case of 181 * errors. 182 */ 183 static void stmmac_verify_args(void) 184 { 185 if (unlikely(watchdog < 0)) 186 watchdog = TX_TIMEO; 187 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 188 buf_sz = DEFAULT_BUFSIZE; 189 if (unlikely(flow_ctrl > 1)) 190 flow_ctrl = FLOW_AUTO; 191 else if (likely(flow_ctrl < 0)) 192 flow_ctrl = FLOW_OFF; 193 if (unlikely((pause < 0) || (pause > 0xffff))) 194 pause = PAUSE_TIME; 195 if (eee_timer < 0) 196 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 197 } 198 199 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 200 { 201 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 202 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 203 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 204 u32 queue; 205 206 for (queue = 0; queue < maxq; queue++) { 207 struct stmmac_channel *ch = &priv->channel[queue]; 208 209 if (stmmac_xdp_is_enabled(priv) && 210 test_bit(queue, priv->af_xdp_zc_qps)) { 211 napi_disable(&ch->rxtx_napi); 212 continue; 213 } 214 215 if (queue < rx_queues_cnt) 216 napi_disable(&ch->rx_napi); 217 if (queue < tx_queues_cnt) 218 napi_disable(&ch->tx_napi); 219 } 220 } 221 222 /** 223 * stmmac_disable_all_queues - Disable all queues 224 * @priv: driver private structure 225 */ 226 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 227 { 228 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 229 struct stmmac_rx_queue *rx_q; 230 u32 queue; 231 232 /* synchronize_rcu() needed for pending XDP buffers to drain */ 233 for (queue = 0; queue < rx_queues_cnt; queue++) { 234 rx_q = &priv->rx_queue[queue]; 235 if (rx_q->xsk_pool) { 236 synchronize_rcu(); 237 break; 238 } 239 } 240 241 __stmmac_disable_all_queues(priv); 242 } 243 244 /** 245 * stmmac_enable_all_queues - Enable all queues 246 * @priv: driver private structure 247 */ 248 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 249 { 250 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 251 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 252 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 253 u32 queue; 254 255 for (queue = 0; queue < maxq; queue++) { 256 struct stmmac_channel *ch = &priv->channel[queue]; 257 258 if (stmmac_xdp_is_enabled(priv) && 259 test_bit(queue, priv->af_xdp_zc_qps)) { 260 napi_enable(&ch->rxtx_napi); 261 continue; 262 } 263 264 if (queue < rx_queues_cnt) 265 napi_enable(&ch->rx_napi); 266 if (queue < tx_queues_cnt) 267 napi_enable(&ch->tx_napi); 268 } 269 } 270 271 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 272 { 273 if (!test_bit(STMMAC_DOWN, &priv->state) && 274 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 275 queue_work(priv->wq, &priv->service_task); 276 } 277 278 static void stmmac_global_err(struct stmmac_priv *priv) 279 { 280 netif_carrier_off(priv->dev); 281 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 282 stmmac_service_event_schedule(priv); 283 } 284 285 /** 286 * stmmac_clk_csr_set - dynamically set the MDC clock 287 * @priv: driver private structure 288 * Description: this is to dynamically set the MDC clock according to the csr 289 * clock input. 290 * Note: 291 * If a specific clk_csr value is passed from the platform 292 * this means that the CSR Clock Range selection cannot be 293 * changed at run-time and it is fixed (as reported in the driver 294 * documentation). Viceversa the driver will try to set the MDC 295 * clock dynamically according to the actual clock input. 296 */ 297 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 298 { 299 u32 clk_rate; 300 301 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 302 303 /* Platform provided default clk_csr would be assumed valid 304 * for all other cases except for the below mentioned ones. 305 * For values higher than the IEEE 802.3 specified frequency 306 * we can not estimate the proper divider as it is not known 307 * the frequency of clk_csr_i. So we do not change the default 308 * divider. 309 */ 310 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 311 if (clk_rate < CSR_F_35M) 312 priv->clk_csr = STMMAC_CSR_20_35M; 313 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 314 priv->clk_csr = STMMAC_CSR_35_60M; 315 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 316 priv->clk_csr = STMMAC_CSR_60_100M; 317 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 318 priv->clk_csr = STMMAC_CSR_100_150M; 319 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 320 priv->clk_csr = STMMAC_CSR_150_250M; 321 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 322 priv->clk_csr = STMMAC_CSR_250_300M; 323 } 324 325 if (priv->plat->has_sun8i) { 326 if (clk_rate > 160000000) 327 priv->clk_csr = 0x03; 328 else if (clk_rate > 80000000) 329 priv->clk_csr = 0x02; 330 else if (clk_rate > 40000000) 331 priv->clk_csr = 0x01; 332 else 333 priv->clk_csr = 0; 334 } 335 336 if (priv->plat->has_xgmac) { 337 if (clk_rate > 400000000) 338 priv->clk_csr = 0x5; 339 else if (clk_rate > 350000000) 340 priv->clk_csr = 0x4; 341 else if (clk_rate > 300000000) 342 priv->clk_csr = 0x3; 343 else if (clk_rate > 250000000) 344 priv->clk_csr = 0x2; 345 else if (clk_rate > 150000000) 346 priv->clk_csr = 0x1; 347 else 348 priv->clk_csr = 0x0; 349 } 350 } 351 352 static void print_pkt(unsigned char *buf, int len) 353 { 354 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 355 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 356 } 357 358 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 359 { 360 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 361 u32 avail; 362 363 if (tx_q->dirty_tx > tx_q->cur_tx) 364 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 365 else 366 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 367 368 return avail; 369 } 370 371 /** 372 * stmmac_rx_dirty - Get RX queue dirty 373 * @priv: driver private structure 374 * @queue: RX queue index 375 */ 376 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 377 { 378 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 379 u32 dirty; 380 381 if (rx_q->dirty_rx <= rx_q->cur_rx) 382 dirty = rx_q->cur_rx - rx_q->dirty_rx; 383 else 384 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 385 386 return dirty; 387 } 388 389 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 390 { 391 int tx_lpi_timer; 392 393 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 394 priv->eee_sw_timer_en = en ? 0 : 1; 395 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 396 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 397 } 398 399 /** 400 * stmmac_enable_eee_mode - check and enter in LPI mode 401 * @priv: driver private structure 402 * Description: this function is to verify and enter in LPI mode in case of 403 * EEE. 404 */ 405 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 406 { 407 u32 tx_cnt = priv->plat->tx_queues_to_use; 408 u32 queue; 409 410 /* check if all TX queues have the work finished */ 411 for (queue = 0; queue < tx_cnt; queue++) { 412 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 413 414 if (tx_q->dirty_tx != tx_q->cur_tx) 415 return -EBUSY; /* still unfinished work */ 416 } 417 418 /* Check and enter in LPI mode */ 419 if (!priv->tx_path_in_lpi_mode) 420 stmmac_set_eee_mode(priv, priv->hw, 421 priv->plat->en_tx_lpi_clockgating); 422 return 0; 423 } 424 425 /** 426 * stmmac_disable_eee_mode - disable and exit from LPI mode 427 * @priv: driver private structure 428 * Description: this function is to exit and disable EEE in case of 429 * LPI state is true. This is called by the xmit. 430 */ 431 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 432 { 433 if (!priv->eee_sw_timer_en) { 434 stmmac_lpi_entry_timer_config(priv, 0); 435 return; 436 } 437 438 stmmac_reset_eee_mode(priv, priv->hw); 439 del_timer_sync(&priv->eee_ctrl_timer); 440 priv->tx_path_in_lpi_mode = false; 441 } 442 443 /** 444 * stmmac_eee_ctrl_timer - EEE TX SW timer. 445 * @t: timer_list struct containing private info 446 * Description: 447 * if there is no data transfer and if we are not in LPI state, 448 * then MAC Transmitter can be moved to LPI state. 449 */ 450 static void stmmac_eee_ctrl_timer(struct timer_list *t) 451 { 452 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 453 454 if (stmmac_enable_eee_mode(priv)) 455 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 456 } 457 458 /** 459 * stmmac_eee_init - init EEE 460 * @priv: driver private structure 461 * Description: 462 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 463 * can also manage EEE, this function enable the LPI state and start related 464 * timer. 465 */ 466 bool stmmac_eee_init(struct stmmac_priv *priv) 467 { 468 int eee_tw_timer = priv->eee_tw_timer; 469 470 /* Using PCS we cannot dial with the phy registers at this stage 471 * so we do not support extra feature like EEE. 472 */ 473 if (priv->hw->pcs == STMMAC_PCS_TBI || 474 priv->hw->pcs == STMMAC_PCS_RTBI) 475 return false; 476 477 /* Check if MAC core supports the EEE feature. */ 478 if (!priv->dma_cap.eee) 479 return false; 480 481 mutex_lock(&priv->lock); 482 483 /* Check if it needs to be deactivated */ 484 if (!priv->eee_active) { 485 if (priv->eee_enabled) { 486 netdev_dbg(priv->dev, "disable EEE\n"); 487 stmmac_lpi_entry_timer_config(priv, 0); 488 del_timer_sync(&priv->eee_ctrl_timer); 489 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 490 if (priv->hw->xpcs) 491 xpcs_config_eee(priv->hw->xpcs, 492 priv->plat->mult_fact_100ns, 493 false); 494 } 495 mutex_unlock(&priv->lock); 496 return false; 497 } 498 499 if (priv->eee_active && !priv->eee_enabled) { 500 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 501 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 502 eee_tw_timer); 503 if (priv->hw->xpcs) 504 xpcs_config_eee(priv->hw->xpcs, 505 priv->plat->mult_fact_100ns, 506 true); 507 } 508 509 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 510 del_timer_sync(&priv->eee_ctrl_timer); 511 priv->tx_path_in_lpi_mode = false; 512 stmmac_lpi_entry_timer_config(priv, 1); 513 } else { 514 stmmac_lpi_entry_timer_config(priv, 0); 515 mod_timer(&priv->eee_ctrl_timer, 516 STMMAC_LPI_T(priv->tx_lpi_timer)); 517 } 518 519 mutex_unlock(&priv->lock); 520 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 521 return true; 522 } 523 524 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 525 * @priv: driver private structure 526 * @p : descriptor pointer 527 * @skb : the socket buffer 528 * Description : 529 * This function will read timestamp from the descriptor & pass it to stack. 530 * and also perform some sanity checks. 531 */ 532 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 533 struct dma_desc *p, struct sk_buff *skb) 534 { 535 struct skb_shared_hwtstamps shhwtstamp; 536 bool found = false; 537 u64 ns = 0; 538 539 if (!priv->hwts_tx_en) 540 return; 541 542 /* exit if skb doesn't support hw tstamp */ 543 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 544 return; 545 546 /* check tx tstamp status */ 547 if (stmmac_get_tx_timestamp_status(priv, p)) { 548 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 549 found = true; 550 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 551 found = true; 552 } 553 554 if (found) { 555 ns -= priv->plat->cdc_error_adj; 556 557 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 558 shhwtstamp.hwtstamp = ns_to_ktime(ns); 559 560 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 561 /* pass tstamp to stack */ 562 skb_tstamp_tx(skb, &shhwtstamp); 563 } 564 } 565 566 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 567 * @priv: driver private structure 568 * @p : descriptor pointer 569 * @np : next descriptor pointer 570 * @skb : the socket buffer 571 * Description : 572 * This function will read received packet's timestamp from the descriptor 573 * and pass it to stack. It also perform some sanity checks. 574 */ 575 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 576 struct dma_desc *np, struct sk_buff *skb) 577 { 578 struct skb_shared_hwtstamps *shhwtstamp = NULL; 579 struct dma_desc *desc = p; 580 u64 ns = 0; 581 582 if (!priv->hwts_rx_en) 583 return; 584 /* For GMAC4, the valid timestamp is from CTX next desc. */ 585 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 586 desc = np; 587 588 /* Check if timestamp is available */ 589 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 590 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 591 592 ns -= priv->plat->cdc_error_adj; 593 594 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 595 shhwtstamp = skb_hwtstamps(skb); 596 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 597 shhwtstamp->hwtstamp = ns_to_ktime(ns); 598 } else { 599 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 600 } 601 } 602 603 /** 604 * stmmac_hwtstamp_set - control hardware timestamping. 605 * @dev: device pointer. 606 * @ifr: An IOCTL specific structure, that can contain a pointer to 607 * a proprietary structure used to pass information to the driver. 608 * Description: 609 * This function configures the MAC to enable/disable both outgoing(TX) 610 * and incoming(RX) packets time stamping based on user input. 611 * Return Value: 612 * 0 on success and an appropriate -ve integer on failure. 613 */ 614 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 615 { 616 struct stmmac_priv *priv = netdev_priv(dev); 617 struct hwtstamp_config config; 618 u32 ptp_v2 = 0; 619 u32 tstamp_all = 0; 620 u32 ptp_over_ipv4_udp = 0; 621 u32 ptp_over_ipv6_udp = 0; 622 u32 ptp_over_ethernet = 0; 623 u32 snap_type_sel = 0; 624 u32 ts_master_en = 0; 625 u32 ts_event_en = 0; 626 627 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 628 netdev_alert(priv->dev, "No support for HW time stamping\n"); 629 priv->hwts_tx_en = 0; 630 priv->hwts_rx_en = 0; 631 632 return -EOPNOTSUPP; 633 } 634 635 if (copy_from_user(&config, ifr->ifr_data, 636 sizeof(config))) 637 return -EFAULT; 638 639 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 640 __func__, config.flags, config.tx_type, config.rx_filter); 641 642 if (config.tx_type != HWTSTAMP_TX_OFF && 643 config.tx_type != HWTSTAMP_TX_ON) 644 return -ERANGE; 645 646 if (priv->adv_ts) { 647 switch (config.rx_filter) { 648 case HWTSTAMP_FILTER_NONE: 649 /* time stamp no incoming packet at all */ 650 config.rx_filter = HWTSTAMP_FILTER_NONE; 651 break; 652 653 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 654 /* PTP v1, UDP, any kind of event packet */ 655 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 656 /* 'xmac' hardware can support Sync, Pdelay_Req and 657 * Pdelay_resp by setting bit14 and bits17/16 to 01 658 * This leaves Delay_Req timestamps out. 659 * Enable all events *and* general purpose message 660 * timestamping 661 */ 662 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 663 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 664 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 665 break; 666 667 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 668 /* PTP v1, UDP, Sync packet */ 669 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 670 /* take time stamp for SYNC messages only */ 671 ts_event_en = PTP_TCR_TSEVNTENA; 672 673 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 674 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 675 break; 676 677 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 678 /* PTP v1, UDP, Delay_req packet */ 679 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 680 /* take time stamp for Delay_Req messages only */ 681 ts_master_en = PTP_TCR_TSMSTRENA; 682 ts_event_en = PTP_TCR_TSEVNTENA; 683 684 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 685 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 686 break; 687 688 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 689 /* PTP v2, UDP, any kind of event packet */ 690 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 691 ptp_v2 = PTP_TCR_TSVER2ENA; 692 /* take time stamp for all event messages */ 693 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 694 695 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 696 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 697 break; 698 699 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 700 /* PTP v2, UDP, Sync packet */ 701 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 702 ptp_v2 = PTP_TCR_TSVER2ENA; 703 /* take time stamp for SYNC messages only */ 704 ts_event_en = PTP_TCR_TSEVNTENA; 705 706 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 707 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 708 break; 709 710 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 711 /* PTP v2, UDP, Delay_req packet */ 712 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 713 ptp_v2 = PTP_TCR_TSVER2ENA; 714 /* take time stamp for Delay_Req messages only */ 715 ts_master_en = PTP_TCR_TSMSTRENA; 716 ts_event_en = PTP_TCR_TSEVNTENA; 717 718 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 719 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 720 break; 721 722 case HWTSTAMP_FILTER_PTP_V2_EVENT: 723 /* PTP v2/802.AS1 any layer, any kind of event packet */ 724 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 725 ptp_v2 = PTP_TCR_TSVER2ENA; 726 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 727 if (priv->synopsys_id < DWMAC_CORE_4_10) 728 ts_event_en = PTP_TCR_TSEVNTENA; 729 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 730 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 731 ptp_over_ethernet = PTP_TCR_TSIPENA; 732 break; 733 734 case HWTSTAMP_FILTER_PTP_V2_SYNC: 735 /* PTP v2/802.AS1, any layer, Sync packet */ 736 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 737 ptp_v2 = PTP_TCR_TSVER2ENA; 738 /* take time stamp for SYNC messages only */ 739 ts_event_en = PTP_TCR_TSEVNTENA; 740 741 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 742 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 743 ptp_over_ethernet = PTP_TCR_TSIPENA; 744 break; 745 746 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 747 /* PTP v2/802.AS1, any layer, Delay_req packet */ 748 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 749 ptp_v2 = PTP_TCR_TSVER2ENA; 750 /* take time stamp for Delay_Req messages only */ 751 ts_master_en = PTP_TCR_TSMSTRENA; 752 ts_event_en = PTP_TCR_TSEVNTENA; 753 754 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 755 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 756 ptp_over_ethernet = PTP_TCR_TSIPENA; 757 break; 758 759 case HWTSTAMP_FILTER_NTP_ALL: 760 case HWTSTAMP_FILTER_ALL: 761 /* time stamp any incoming packet */ 762 config.rx_filter = HWTSTAMP_FILTER_ALL; 763 tstamp_all = PTP_TCR_TSENALL; 764 break; 765 766 default: 767 return -ERANGE; 768 } 769 } else { 770 switch (config.rx_filter) { 771 case HWTSTAMP_FILTER_NONE: 772 config.rx_filter = HWTSTAMP_FILTER_NONE; 773 break; 774 default: 775 /* PTP v1, UDP, any kind of event packet */ 776 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 777 break; 778 } 779 } 780 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 781 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 782 783 priv->systime_flags = STMMAC_HWTS_ACTIVE; 784 785 if (priv->hwts_tx_en || priv->hwts_rx_en) { 786 priv->systime_flags |= tstamp_all | ptp_v2 | 787 ptp_over_ethernet | ptp_over_ipv6_udp | 788 ptp_over_ipv4_udp | ts_event_en | 789 ts_master_en | snap_type_sel; 790 } 791 792 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 793 794 memcpy(&priv->tstamp_config, &config, sizeof(config)); 795 796 return copy_to_user(ifr->ifr_data, &config, 797 sizeof(config)) ? -EFAULT : 0; 798 } 799 800 /** 801 * stmmac_hwtstamp_get - read hardware timestamping. 802 * @dev: device pointer. 803 * @ifr: An IOCTL specific structure, that can contain a pointer to 804 * a proprietary structure used to pass information to the driver. 805 * Description: 806 * This function obtain the current hardware timestamping settings 807 * as requested. 808 */ 809 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 810 { 811 struct stmmac_priv *priv = netdev_priv(dev); 812 struct hwtstamp_config *config = &priv->tstamp_config; 813 814 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 815 return -EOPNOTSUPP; 816 817 return copy_to_user(ifr->ifr_data, config, 818 sizeof(*config)) ? -EFAULT : 0; 819 } 820 821 /** 822 * stmmac_init_tstamp_counter - init hardware timestamping counter 823 * @priv: driver private structure 824 * @systime_flags: timestamping flags 825 * Description: 826 * Initialize hardware counter for packet timestamping. 827 * This is valid as long as the interface is open and not suspended. 828 * Will be rerun after resuming from suspend, case in which the timestamping 829 * flags updated by stmmac_hwtstamp_set() also need to be restored. 830 */ 831 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 832 { 833 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 834 struct timespec64 now; 835 u32 sec_inc = 0; 836 u64 temp = 0; 837 int ret; 838 839 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 840 return -EOPNOTSUPP; 841 842 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 843 if (ret < 0) { 844 netdev_warn(priv->dev, 845 "failed to enable PTP reference clock: %pe\n", 846 ERR_PTR(ret)); 847 return ret; 848 } 849 850 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 851 priv->systime_flags = systime_flags; 852 853 /* program Sub Second Increment reg */ 854 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 855 priv->plat->clk_ptp_rate, 856 xmac, &sec_inc); 857 temp = div_u64(1000000000ULL, sec_inc); 858 859 /* Store sub second increment for later use */ 860 priv->sub_second_inc = sec_inc; 861 862 /* calculate default added value: 863 * formula is : 864 * addend = (2^32)/freq_div_ratio; 865 * where, freq_div_ratio = 1e9ns/sec_inc 866 */ 867 temp = (u64)(temp << 32); 868 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 869 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 870 871 /* initialize system time */ 872 ktime_get_real_ts64(&now); 873 874 /* lower 32 bits of tv_sec are safe until y2106 */ 875 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 876 877 return 0; 878 } 879 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 880 881 /** 882 * stmmac_init_ptp - init PTP 883 * @priv: driver private structure 884 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 885 * This is done by looking at the HW cap. register. 886 * This function also registers the ptp driver. 887 */ 888 static int stmmac_init_ptp(struct stmmac_priv *priv) 889 { 890 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 891 int ret; 892 893 if (priv->plat->ptp_clk_freq_config) 894 priv->plat->ptp_clk_freq_config(priv); 895 896 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 897 if (ret) 898 return ret; 899 900 priv->adv_ts = 0; 901 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 902 if (xmac && priv->dma_cap.atime_stamp) 903 priv->adv_ts = 1; 904 /* Dwmac 3.x core with extend_desc can support adv_ts */ 905 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 906 priv->adv_ts = 1; 907 908 if (priv->dma_cap.time_stamp) 909 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 910 911 if (priv->adv_ts) 912 netdev_info(priv->dev, 913 "IEEE 1588-2008 Advanced Timestamp supported\n"); 914 915 priv->hwts_tx_en = 0; 916 priv->hwts_rx_en = 0; 917 918 return 0; 919 } 920 921 static void stmmac_release_ptp(struct stmmac_priv *priv) 922 { 923 clk_disable_unprepare(priv->plat->clk_ptp_ref); 924 stmmac_ptp_unregister(priv); 925 } 926 927 /** 928 * stmmac_mac_flow_ctrl - Configure flow control in all queues 929 * @priv: driver private structure 930 * @duplex: duplex passed to the next function 931 * Description: It is used for configuring the flow control in all queues 932 */ 933 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 934 { 935 u32 tx_cnt = priv->plat->tx_queues_to_use; 936 937 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 938 priv->pause, tx_cnt); 939 } 940 941 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 942 phy_interface_t interface) 943 { 944 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 945 946 if (!priv->hw->xpcs) 947 return NULL; 948 949 return &priv->hw->xpcs->pcs; 950 } 951 952 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 953 const struct phylink_link_state *state) 954 { 955 /* Nothing to do, xpcs_config() handles everything */ 956 } 957 958 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 959 { 960 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 961 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 962 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 963 bool *hs_enable = &fpe_cfg->hs_enable; 964 965 if (is_up && *hs_enable) { 966 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 967 } else { 968 *lo_state = FPE_STATE_OFF; 969 *lp_state = FPE_STATE_OFF; 970 } 971 } 972 973 static void stmmac_mac_link_down(struct phylink_config *config, 974 unsigned int mode, phy_interface_t interface) 975 { 976 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 977 978 stmmac_mac_set(priv, priv->ioaddr, false); 979 priv->eee_active = false; 980 priv->tx_lpi_enabled = false; 981 priv->eee_enabled = stmmac_eee_init(priv); 982 stmmac_set_eee_pls(priv, priv->hw, false); 983 984 if (priv->dma_cap.fpesel) 985 stmmac_fpe_link_state_handle(priv, false); 986 } 987 988 static void stmmac_mac_link_up(struct phylink_config *config, 989 struct phy_device *phy, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 995 u32 ctrl; 996 997 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 998 ctrl &= ~priv->hw->link.speed_mask; 999 1000 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1001 switch (speed) { 1002 case SPEED_10000: 1003 ctrl |= priv->hw->link.xgmii.speed10000; 1004 break; 1005 case SPEED_5000: 1006 ctrl |= priv->hw->link.xgmii.speed5000; 1007 break; 1008 case SPEED_2500: 1009 ctrl |= priv->hw->link.xgmii.speed2500; 1010 break; 1011 default: 1012 return; 1013 } 1014 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1015 switch (speed) { 1016 case SPEED_100000: 1017 ctrl |= priv->hw->link.xlgmii.speed100000; 1018 break; 1019 case SPEED_50000: 1020 ctrl |= priv->hw->link.xlgmii.speed50000; 1021 break; 1022 case SPEED_40000: 1023 ctrl |= priv->hw->link.xlgmii.speed40000; 1024 break; 1025 case SPEED_25000: 1026 ctrl |= priv->hw->link.xlgmii.speed25000; 1027 break; 1028 case SPEED_10000: 1029 ctrl |= priv->hw->link.xgmii.speed10000; 1030 break; 1031 case SPEED_2500: 1032 ctrl |= priv->hw->link.speed2500; 1033 break; 1034 case SPEED_1000: 1035 ctrl |= priv->hw->link.speed1000; 1036 break; 1037 default: 1038 return; 1039 } 1040 } else { 1041 switch (speed) { 1042 case SPEED_2500: 1043 ctrl |= priv->hw->link.speed2500; 1044 break; 1045 case SPEED_1000: 1046 ctrl |= priv->hw->link.speed1000; 1047 break; 1048 case SPEED_100: 1049 ctrl |= priv->hw->link.speed100; 1050 break; 1051 case SPEED_10: 1052 ctrl |= priv->hw->link.speed10; 1053 break; 1054 default: 1055 return; 1056 } 1057 } 1058 1059 priv->speed = speed; 1060 1061 if (priv->plat->fix_mac_speed) 1062 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1063 1064 if (!duplex) 1065 ctrl &= ~priv->hw->link.duplex; 1066 else 1067 ctrl |= priv->hw->link.duplex; 1068 1069 /* Flow Control operation */ 1070 if (tx_pause && rx_pause) 1071 stmmac_mac_flow_ctrl(priv, duplex); 1072 1073 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1074 1075 stmmac_mac_set(priv, priv->ioaddr, true); 1076 if (phy && priv->dma_cap.eee) { 1077 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1078 priv->eee_enabled = stmmac_eee_init(priv); 1079 priv->tx_lpi_enabled = priv->eee_enabled; 1080 stmmac_set_eee_pls(priv, priv->hw, true); 1081 } 1082 1083 if (priv->dma_cap.fpesel) 1084 stmmac_fpe_link_state_handle(priv, true); 1085 } 1086 1087 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1088 .validate = phylink_generic_validate, 1089 .mac_select_pcs = stmmac_mac_select_pcs, 1090 .mac_config = stmmac_mac_config, 1091 .mac_link_down = stmmac_mac_link_down, 1092 .mac_link_up = stmmac_mac_link_up, 1093 }; 1094 1095 /** 1096 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1097 * @priv: driver private structure 1098 * Description: this is to verify if the HW supports the PCS. 1099 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1100 * configured for the TBI, RTBI, or SGMII PHY interface. 1101 */ 1102 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1103 { 1104 int interface = priv->plat->interface; 1105 1106 if (priv->dma_cap.pcs) { 1107 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1108 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1109 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1110 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1111 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1112 priv->hw->pcs = STMMAC_PCS_RGMII; 1113 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1114 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1115 priv->hw->pcs = STMMAC_PCS_SGMII; 1116 } 1117 } 1118 } 1119 1120 /** 1121 * stmmac_init_phy - PHY initialization 1122 * @dev: net device structure 1123 * Description: it initializes the driver's PHY state, and attaches the PHY 1124 * to the mac driver. 1125 * Return value: 1126 * 0 on success 1127 */ 1128 static int stmmac_init_phy(struct net_device *dev) 1129 { 1130 struct stmmac_priv *priv = netdev_priv(dev); 1131 struct device_node *node; 1132 int ret; 1133 1134 node = priv->plat->phylink_node; 1135 1136 if (node) 1137 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1138 1139 /* Some DT bindings do not set-up the PHY handle. Let's try to 1140 * manually parse it 1141 */ 1142 if (!node || ret) { 1143 int addr = priv->plat->phy_addr; 1144 struct phy_device *phydev; 1145 1146 phydev = mdiobus_get_phy(priv->mii, addr); 1147 if (!phydev) { 1148 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1149 return -ENODEV; 1150 } 1151 1152 ret = phylink_connect_phy(priv->phylink, phydev); 1153 } 1154 1155 if (!priv->plat->pmt) { 1156 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1157 1158 phylink_ethtool_get_wol(priv->phylink, &wol); 1159 device_set_wakeup_capable(priv->device, !!wol.supported); 1160 } 1161 1162 return ret; 1163 } 1164 1165 static int stmmac_phy_setup(struct stmmac_priv *priv) 1166 { 1167 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1168 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1169 int max_speed = priv->plat->max_speed; 1170 int mode = priv->plat->phy_interface; 1171 struct phylink *phylink; 1172 1173 priv->phylink_config.dev = &priv->dev->dev; 1174 priv->phylink_config.type = PHYLINK_NETDEV; 1175 if (priv->plat->mdio_bus_data) 1176 priv->phylink_config.ovr_an_inband = 1177 mdio_bus_data->xpcs_an_inband; 1178 1179 if (!fwnode) 1180 fwnode = dev_fwnode(priv->device); 1181 1182 /* Set the platform/firmware specified interface mode */ 1183 __set_bit(mode, priv->phylink_config.supported_interfaces); 1184 1185 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1186 if (priv->hw->xpcs) 1187 xpcs_get_interfaces(priv->hw->xpcs, 1188 priv->phylink_config.supported_interfaces); 1189 1190 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1191 MAC_10 | MAC_100; 1192 1193 if (!max_speed || max_speed >= 1000) 1194 priv->phylink_config.mac_capabilities |= MAC_1000; 1195 1196 if (priv->plat->has_gmac4) { 1197 if (!max_speed || max_speed >= 2500) 1198 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1199 } else if (priv->plat->has_xgmac) { 1200 if (!max_speed || max_speed >= 2500) 1201 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1202 if (!max_speed || max_speed >= 5000) 1203 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1204 if (!max_speed || max_speed >= 10000) 1205 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1206 if (!max_speed || max_speed >= 25000) 1207 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1208 if (!max_speed || max_speed >= 40000) 1209 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1210 if (!max_speed || max_speed >= 50000) 1211 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1212 if (!max_speed || max_speed >= 100000) 1213 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1214 } 1215 1216 /* Half-Duplex can only work with single queue */ 1217 if (priv->plat->tx_queues_to_use > 1) 1218 priv->phylink_config.mac_capabilities &= 1219 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1220 1221 phylink = phylink_create(&priv->phylink_config, fwnode, 1222 mode, &stmmac_phylink_mac_ops); 1223 if (IS_ERR(phylink)) 1224 return PTR_ERR(phylink); 1225 1226 priv->phylink = phylink; 1227 return 0; 1228 } 1229 1230 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1231 { 1232 u32 rx_cnt = priv->plat->rx_queues_to_use; 1233 unsigned int desc_size; 1234 void *head_rx; 1235 u32 queue; 1236 1237 /* Display RX rings */ 1238 for (queue = 0; queue < rx_cnt; queue++) { 1239 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1240 1241 pr_info("\tRX Queue %u rings\n", queue); 1242 1243 if (priv->extend_desc) { 1244 head_rx = (void *)rx_q->dma_erx; 1245 desc_size = sizeof(struct dma_extended_desc); 1246 } else { 1247 head_rx = (void *)rx_q->dma_rx; 1248 desc_size = sizeof(struct dma_desc); 1249 } 1250 1251 /* Display RX ring */ 1252 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, 1253 rx_q->dma_rx_phy, desc_size); 1254 } 1255 } 1256 1257 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1258 { 1259 u32 tx_cnt = priv->plat->tx_queues_to_use; 1260 unsigned int desc_size; 1261 void *head_tx; 1262 u32 queue; 1263 1264 /* Display TX rings */ 1265 for (queue = 0; queue < tx_cnt; queue++) { 1266 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1267 1268 pr_info("\tTX Queue %d rings\n", queue); 1269 1270 if (priv->extend_desc) { 1271 head_tx = (void *)tx_q->dma_etx; 1272 desc_size = sizeof(struct dma_extended_desc); 1273 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1274 head_tx = (void *)tx_q->dma_entx; 1275 desc_size = sizeof(struct dma_edesc); 1276 } else { 1277 head_tx = (void *)tx_q->dma_tx; 1278 desc_size = sizeof(struct dma_desc); 1279 } 1280 1281 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, 1282 tx_q->dma_tx_phy, desc_size); 1283 } 1284 } 1285 1286 static void stmmac_display_rings(struct stmmac_priv *priv) 1287 { 1288 /* Display RX ring */ 1289 stmmac_display_rx_rings(priv); 1290 1291 /* Display TX ring */ 1292 stmmac_display_tx_rings(priv); 1293 } 1294 1295 static int stmmac_set_bfsize(int mtu, int bufsize) 1296 { 1297 int ret = bufsize; 1298 1299 if (mtu >= BUF_SIZE_8KiB) 1300 ret = BUF_SIZE_16KiB; 1301 else if (mtu >= BUF_SIZE_4KiB) 1302 ret = BUF_SIZE_8KiB; 1303 else if (mtu >= BUF_SIZE_2KiB) 1304 ret = BUF_SIZE_4KiB; 1305 else if (mtu > DEFAULT_BUFSIZE) 1306 ret = BUF_SIZE_2KiB; 1307 else 1308 ret = DEFAULT_BUFSIZE; 1309 1310 return ret; 1311 } 1312 1313 /** 1314 * stmmac_clear_rx_descriptors - clear RX descriptors 1315 * @priv: driver private structure 1316 * @queue: RX queue index 1317 * Description: this function is called to clear the RX descriptors 1318 * in case of both basic and extended descriptors are used. 1319 */ 1320 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1321 { 1322 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1323 int i; 1324 1325 /* Clear the RX descriptors */ 1326 for (i = 0; i < priv->dma_rx_size; i++) 1327 if (priv->extend_desc) 1328 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1329 priv->use_riwt, priv->mode, 1330 (i == priv->dma_rx_size - 1), 1331 priv->dma_buf_sz); 1332 else 1333 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1334 priv->use_riwt, priv->mode, 1335 (i == priv->dma_rx_size - 1), 1336 priv->dma_buf_sz); 1337 } 1338 1339 /** 1340 * stmmac_clear_tx_descriptors - clear tx descriptors 1341 * @priv: driver private structure 1342 * @queue: TX queue index. 1343 * Description: this function is called to clear the TX descriptors 1344 * in case of both basic and extended descriptors are used. 1345 */ 1346 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1347 { 1348 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1349 int i; 1350 1351 /* Clear the TX descriptors */ 1352 for (i = 0; i < priv->dma_tx_size; i++) { 1353 int last = (i == (priv->dma_tx_size - 1)); 1354 struct dma_desc *p; 1355 1356 if (priv->extend_desc) 1357 p = &tx_q->dma_etx[i].basic; 1358 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1359 p = &tx_q->dma_entx[i].basic; 1360 else 1361 p = &tx_q->dma_tx[i]; 1362 1363 stmmac_init_tx_desc(priv, p, priv->mode, last); 1364 } 1365 } 1366 1367 /** 1368 * stmmac_clear_descriptors - clear descriptors 1369 * @priv: driver private structure 1370 * Description: this function is called to clear the TX and RX descriptors 1371 * in case of both basic and extended descriptors are used. 1372 */ 1373 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1374 { 1375 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1376 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1377 u32 queue; 1378 1379 /* Clear the RX descriptors */ 1380 for (queue = 0; queue < rx_queue_cnt; queue++) 1381 stmmac_clear_rx_descriptors(priv, queue); 1382 1383 /* Clear the TX descriptors */ 1384 for (queue = 0; queue < tx_queue_cnt; queue++) 1385 stmmac_clear_tx_descriptors(priv, queue); 1386 } 1387 1388 /** 1389 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1390 * @priv: driver private structure 1391 * @p: descriptor pointer 1392 * @i: descriptor index 1393 * @flags: gfp flag 1394 * @queue: RX queue index 1395 * Description: this function is called to allocate a receive buffer, perform 1396 * the DMA mapping and init the descriptor. 1397 */ 1398 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1399 int i, gfp_t flags, u32 queue) 1400 { 1401 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1402 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1403 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1404 1405 if (priv->dma_cap.addr64 <= 32) 1406 gfp |= GFP_DMA32; 1407 1408 if (!buf->page) { 1409 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1410 if (!buf->page) 1411 return -ENOMEM; 1412 buf->page_offset = stmmac_rx_offset(priv); 1413 } 1414 1415 if (priv->sph && !buf->sec_page) { 1416 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1417 if (!buf->sec_page) 1418 return -ENOMEM; 1419 1420 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1421 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1422 } else { 1423 buf->sec_page = NULL; 1424 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1425 } 1426 1427 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1428 1429 stmmac_set_desc_addr(priv, p, buf->addr); 1430 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1431 stmmac_init_desc3(priv, p); 1432 1433 return 0; 1434 } 1435 1436 /** 1437 * stmmac_free_rx_buffer - free RX dma buffers 1438 * @priv: private structure 1439 * @queue: RX queue index 1440 * @i: buffer index. 1441 */ 1442 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1443 { 1444 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1445 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1446 1447 if (buf->page) 1448 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1449 buf->page = NULL; 1450 1451 if (buf->sec_page) 1452 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1453 buf->sec_page = NULL; 1454 } 1455 1456 /** 1457 * stmmac_free_tx_buffer - free RX dma buffers 1458 * @priv: private structure 1459 * @queue: RX queue index 1460 * @i: buffer index. 1461 */ 1462 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1463 { 1464 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1465 1466 if (tx_q->tx_skbuff_dma[i].buf && 1467 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1468 if (tx_q->tx_skbuff_dma[i].map_as_page) 1469 dma_unmap_page(priv->device, 1470 tx_q->tx_skbuff_dma[i].buf, 1471 tx_q->tx_skbuff_dma[i].len, 1472 DMA_TO_DEVICE); 1473 else 1474 dma_unmap_single(priv->device, 1475 tx_q->tx_skbuff_dma[i].buf, 1476 tx_q->tx_skbuff_dma[i].len, 1477 DMA_TO_DEVICE); 1478 } 1479 1480 if (tx_q->xdpf[i] && 1481 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1482 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1483 xdp_return_frame(tx_q->xdpf[i]); 1484 tx_q->xdpf[i] = NULL; 1485 } 1486 1487 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1488 tx_q->xsk_frames_done++; 1489 1490 if (tx_q->tx_skbuff[i] && 1491 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1492 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1493 tx_q->tx_skbuff[i] = NULL; 1494 } 1495 1496 tx_q->tx_skbuff_dma[i].buf = 0; 1497 tx_q->tx_skbuff_dma[i].map_as_page = false; 1498 } 1499 1500 /** 1501 * dma_free_rx_skbufs - free RX dma buffers 1502 * @priv: private structure 1503 * @queue: RX queue index 1504 */ 1505 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1506 { 1507 int i; 1508 1509 for (i = 0; i < priv->dma_rx_size; i++) 1510 stmmac_free_rx_buffer(priv, queue, i); 1511 } 1512 1513 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, 1514 gfp_t flags) 1515 { 1516 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1517 int i; 1518 1519 for (i = 0; i < priv->dma_rx_size; i++) { 1520 struct dma_desc *p; 1521 int ret; 1522 1523 if (priv->extend_desc) 1524 p = &((rx_q->dma_erx + i)->basic); 1525 else 1526 p = rx_q->dma_rx + i; 1527 1528 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1529 queue); 1530 if (ret) 1531 return ret; 1532 1533 rx_q->buf_alloc_num++; 1534 } 1535 1536 return 0; 1537 } 1538 1539 /** 1540 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1541 * @priv: private structure 1542 * @queue: RX queue index 1543 */ 1544 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) 1545 { 1546 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1547 int i; 1548 1549 for (i = 0; i < priv->dma_rx_size; i++) { 1550 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1551 1552 if (!buf->xdp) 1553 continue; 1554 1555 xsk_buff_free(buf->xdp); 1556 buf->xdp = NULL; 1557 } 1558 } 1559 1560 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) 1561 { 1562 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1563 int i; 1564 1565 for (i = 0; i < priv->dma_rx_size; i++) { 1566 struct stmmac_rx_buffer *buf; 1567 dma_addr_t dma_addr; 1568 struct dma_desc *p; 1569 1570 if (priv->extend_desc) 1571 p = (struct dma_desc *)(rx_q->dma_erx + i); 1572 else 1573 p = rx_q->dma_rx + i; 1574 1575 buf = &rx_q->buf_pool[i]; 1576 1577 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1578 if (!buf->xdp) 1579 return -ENOMEM; 1580 1581 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1582 stmmac_set_desc_addr(priv, p, dma_addr); 1583 rx_q->buf_alloc_num++; 1584 } 1585 1586 return 0; 1587 } 1588 1589 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1590 { 1591 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1592 return NULL; 1593 1594 return xsk_get_pool_from_qid(priv->dev, queue); 1595 } 1596 1597 /** 1598 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1599 * @priv: driver private structure 1600 * @queue: RX queue index 1601 * @flags: gfp flag. 1602 * Description: this function initializes the DMA RX descriptors 1603 * and allocates the socket buffers. It supports the chained and ring 1604 * modes. 1605 */ 1606 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) 1607 { 1608 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1609 int ret; 1610 1611 netif_dbg(priv, probe, priv->dev, 1612 "(%s) dma_rx_phy=0x%08x\n", __func__, 1613 (u32)rx_q->dma_rx_phy); 1614 1615 stmmac_clear_rx_descriptors(priv, queue); 1616 1617 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1618 1619 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1620 1621 if (rx_q->xsk_pool) { 1622 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1623 MEM_TYPE_XSK_BUFF_POOL, 1624 NULL)); 1625 netdev_info(priv->dev, 1626 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1627 rx_q->queue_index); 1628 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1629 } else { 1630 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1631 MEM_TYPE_PAGE_POOL, 1632 rx_q->page_pool)); 1633 netdev_info(priv->dev, 1634 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1635 rx_q->queue_index); 1636 } 1637 1638 if (rx_q->xsk_pool) { 1639 /* RX XDP ZC buffer pool may not be populated, e.g. 1640 * xdpsock TX-only. 1641 */ 1642 stmmac_alloc_rx_buffers_zc(priv, queue); 1643 } else { 1644 ret = stmmac_alloc_rx_buffers(priv, queue, flags); 1645 if (ret < 0) 1646 return -ENOMEM; 1647 } 1648 1649 rx_q->cur_rx = 0; 1650 rx_q->dirty_rx = 0; 1651 1652 /* Setup the chained descriptor addresses */ 1653 if (priv->mode == STMMAC_CHAIN_MODE) { 1654 if (priv->extend_desc) 1655 stmmac_mode_init(priv, rx_q->dma_erx, 1656 rx_q->dma_rx_phy, 1657 priv->dma_rx_size, 1); 1658 else 1659 stmmac_mode_init(priv, rx_q->dma_rx, 1660 rx_q->dma_rx_phy, 1661 priv->dma_rx_size, 0); 1662 } 1663 1664 return 0; 1665 } 1666 1667 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1668 { 1669 struct stmmac_priv *priv = netdev_priv(dev); 1670 u32 rx_count = priv->plat->rx_queues_to_use; 1671 u32 queue; 1672 int ret; 1673 1674 /* RX INITIALIZATION */ 1675 netif_dbg(priv, probe, priv->dev, 1676 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1677 1678 for (queue = 0; queue < rx_count; queue++) { 1679 ret = __init_dma_rx_desc_rings(priv, queue, flags); 1680 if (ret) 1681 goto err_init_rx_buffers; 1682 } 1683 1684 return 0; 1685 1686 err_init_rx_buffers: 1687 while (queue >= 0) { 1688 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1689 1690 if (rx_q->xsk_pool) 1691 dma_free_rx_xskbufs(priv, queue); 1692 else 1693 dma_free_rx_skbufs(priv, queue); 1694 1695 rx_q->buf_alloc_num = 0; 1696 rx_q->xsk_pool = NULL; 1697 1698 if (queue == 0) 1699 break; 1700 1701 queue--; 1702 } 1703 1704 return ret; 1705 } 1706 1707 /** 1708 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1709 * @priv: driver private structure 1710 * @queue : TX queue index 1711 * Description: this function initializes the DMA TX descriptors 1712 * and allocates the socket buffers. It supports the chained and ring 1713 * modes. 1714 */ 1715 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) 1716 { 1717 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1718 int i; 1719 1720 netif_dbg(priv, probe, priv->dev, 1721 "(%s) dma_tx_phy=0x%08x\n", __func__, 1722 (u32)tx_q->dma_tx_phy); 1723 1724 /* Setup the chained descriptor addresses */ 1725 if (priv->mode == STMMAC_CHAIN_MODE) { 1726 if (priv->extend_desc) 1727 stmmac_mode_init(priv, tx_q->dma_etx, 1728 tx_q->dma_tx_phy, 1729 priv->dma_tx_size, 1); 1730 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1731 stmmac_mode_init(priv, tx_q->dma_tx, 1732 tx_q->dma_tx_phy, 1733 priv->dma_tx_size, 0); 1734 } 1735 1736 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1737 1738 for (i = 0; i < priv->dma_tx_size; i++) { 1739 struct dma_desc *p; 1740 1741 if (priv->extend_desc) 1742 p = &((tx_q->dma_etx + i)->basic); 1743 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1744 p = &((tx_q->dma_entx + i)->basic); 1745 else 1746 p = tx_q->dma_tx + i; 1747 1748 stmmac_clear_desc(priv, p); 1749 1750 tx_q->tx_skbuff_dma[i].buf = 0; 1751 tx_q->tx_skbuff_dma[i].map_as_page = false; 1752 tx_q->tx_skbuff_dma[i].len = 0; 1753 tx_q->tx_skbuff_dma[i].last_segment = false; 1754 tx_q->tx_skbuff[i] = NULL; 1755 } 1756 1757 tx_q->dirty_tx = 0; 1758 tx_q->cur_tx = 0; 1759 tx_q->mss = 0; 1760 1761 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1762 1763 return 0; 1764 } 1765 1766 static int init_dma_tx_desc_rings(struct net_device *dev) 1767 { 1768 struct stmmac_priv *priv = netdev_priv(dev); 1769 u32 tx_queue_cnt; 1770 u32 queue; 1771 1772 tx_queue_cnt = priv->plat->tx_queues_to_use; 1773 1774 for (queue = 0; queue < tx_queue_cnt; queue++) 1775 __init_dma_tx_desc_rings(priv, queue); 1776 1777 return 0; 1778 } 1779 1780 /** 1781 * init_dma_desc_rings - init the RX/TX descriptor rings 1782 * @dev: net device structure 1783 * @flags: gfp flag. 1784 * Description: this function initializes the DMA RX/TX descriptors 1785 * and allocates the socket buffers. It supports the chained and ring 1786 * modes. 1787 */ 1788 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1789 { 1790 struct stmmac_priv *priv = netdev_priv(dev); 1791 int ret; 1792 1793 ret = init_dma_rx_desc_rings(dev, flags); 1794 if (ret) 1795 return ret; 1796 1797 ret = init_dma_tx_desc_rings(dev); 1798 1799 stmmac_clear_descriptors(priv); 1800 1801 if (netif_msg_hw(priv)) 1802 stmmac_display_rings(priv); 1803 1804 return ret; 1805 } 1806 1807 /** 1808 * dma_free_tx_skbufs - free TX dma buffers 1809 * @priv: private structure 1810 * @queue: TX queue index 1811 */ 1812 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1813 { 1814 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1815 int i; 1816 1817 tx_q->xsk_frames_done = 0; 1818 1819 for (i = 0; i < priv->dma_tx_size; i++) 1820 stmmac_free_tx_buffer(priv, queue, i); 1821 1822 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1823 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1824 tx_q->xsk_frames_done = 0; 1825 tx_q->xsk_pool = NULL; 1826 } 1827 } 1828 1829 /** 1830 * stmmac_free_tx_skbufs - free TX skb buffers 1831 * @priv: private structure 1832 */ 1833 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1834 { 1835 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1836 u32 queue; 1837 1838 for (queue = 0; queue < tx_queue_cnt; queue++) 1839 dma_free_tx_skbufs(priv, queue); 1840 } 1841 1842 /** 1843 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1844 * @priv: private structure 1845 * @queue: RX queue index 1846 */ 1847 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1848 { 1849 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1850 1851 /* Release the DMA RX socket buffers */ 1852 if (rx_q->xsk_pool) 1853 dma_free_rx_xskbufs(priv, queue); 1854 else 1855 dma_free_rx_skbufs(priv, queue); 1856 1857 rx_q->buf_alloc_num = 0; 1858 rx_q->xsk_pool = NULL; 1859 1860 /* Free DMA regions of consistent memory previously allocated */ 1861 if (!priv->extend_desc) 1862 dma_free_coherent(priv->device, priv->dma_rx_size * 1863 sizeof(struct dma_desc), 1864 rx_q->dma_rx, rx_q->dma_rx_phy); 1865 else 1866 dma_free_coherent(priv->device, priv->dma_rx_size * 1867 sizeof(struct dma_extended_desc), 1868 rx_q->dma_erx, rx_q->dma_rx_phy); 1869 1870 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1871 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1872 1873 kfree(rx_q->buf_pool); 1874 if (rx_q->page_pool) 1875 page_pool_destroy(rx_q->page_pool); 1876 } 1877 1878 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1879 { 1880 u32 rx_count = priv->plat->rx_queues_to_use; 1881 u32 queue; 1882 1883 /* Free RX queue resources */ 1884 for (queue = 0; queue < rx_count; queue++) 1885 __free_dma_rx_desc_resources(priv, queue); 1886 } 1887 1888 /** 1889 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1890 * @priv: private structure 1891 * @queue: TX queue index 1892 */ 1893 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 1894 { 1895 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1896 size_t size; 1897 void *addr; 1898 1899 /* Release the DMA TX socket buffers */ 1900 dma_free_tx_skbufs(priv, queue); 1901 1902 if (priv->extend_desc) { 1903 size = sizeof(struct dma_extended_desc); 1904 addr = tx_q->dma_etx; 1905 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1906 size = sizeof(struct dma_edesc); 1907 addr = tx_q->dma_entx; 1908 } else { 1909 size = sizeof(struct dma_desc); 1910 addr = tx_q->dma_tx; 1911 } 1912 1913 size *= priv->dma_tx_size; 1914 1915 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1916 1917 kfree(tx_q->tx_skbuff_dma); 1918 kfree(tx_q->tx_skbuff); 1919 } 1920 1921 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1922 { 1923 u32 tx_count = priv->plat->tx_queues_to_use; 1924 u32 queue; 1925 1926 /* Free TX queue resources */ 1927 for (queue = 0; queue < tx_count; queue++) 1928 __free_dma_tx_desc_resources(priv, queue); 1929 } 1930 1931 /** 1932 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1933 * @priv: private structure 1934 * @queue: RX queue index 1935 * Description: according to which descriptor can be used (extend or basic) 1936 * this function allocates the resources for TX and RX paths. In case of 1937 * reception, for example, it pre-allocated the RX socket buffer in order to 1938 * allow zero-copy mechanism. 1939 */ 1940 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1941 { 1942 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1943 struct stmmac_channel *ch = &priv->channel[queue]; 1944 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1945 struct page_pool_params pp_params = { 0 }; 1946 unsigned int num_pages; 1947 unsigned int napi_id; 1948 int ret; 1949 1950 rx_q->queue_index = queue; 1951 rx_q->priv_data = priv; 1952 1953 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1954 pp_params.pool_size = priv->dma_rx_size; 1955 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1956 pp_params.order = ilog2(num_pages); 1957 pp_params.nid = dev_to_node(priv->device); 1958 pp_params.dev = priv->device; 1959 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1960 pp_params.offset = stmmac_rx_offset(priv); 1961 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 1962 1963 rx_q->page_pool = page_pool_create(&pp_params); 1964 if (IS_ERR(rx_q->page_pool)) { 1965 ret = PTR_ERR(rx_q->page_pool); 1966 rx_q->page_pool = NULL; 1967 return ret; 1968 } 1969 1970 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1971 sizeof(*rx_q->buf_pool), 1972 GFP_KERNEL); 1973 if (!rx_q->buf_pool) 1974 return -ENOMEM; 1975 1976 if (priv->extend_desc) { 1977 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1978 priv->dma_rx_size * 1979 sizeof(struct dma_extended_desc), 1980 &rx_q->dma_rx_phy, 1981 GFP_KERNEL); 1982 if (!rx_q->dma_erx) 1983 return -ENOMEM; 1984 1985 } else { 1986 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1987 priv->dma_rx_size * 1988 sizeof(struct dma_desc), 1989 &rx_q->dma_rx_phy, 1990 GFP_KERNEL); 1991 if (!rx_q->dma_rx) 1992 return -ENOMEM; 1993 } 1994 1995 if (stmmac_xdp_is_enabled(priv) && 1996 test_bit(queue, priv->af_xdp_zc_qps)) 1997 napi_id = ch->rxtx_napi.napi_id; 1998 else 1999 napi_id = ch->rx_napi.napi_id; 2000 2001 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2002 rx_q->queue_index, 2003 napi_id); 2004 if (ret) { 2005 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2006 return -EINVAL; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 2013 { 2014 u32 rx_count = priv->plat->rx_queues_to_use; 2015 u32 queue; 2016 int ret; 2017 2018 /* RX queues buffers and DMA */ 2019 for (queue = 0; queue < rx_count; queue++) { 2020 ret = __alloc_dma_rx_desc_resources(priv, queue); 2021 if (ret) 2022 goto err_dma; 2023 } 2024 2025 return 0; 2026 2027 err_dma: 2028 free_dma_rx_desc_resources(priv); 2029 2030 return ret; 2031 } 2032 2033 /** 2034 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2035 * @priv: private structure 2036 * @queue: TX queue index 2037 * Description: according to which descriptor can be used (extend or basic) 2038 * this function allocates the resources for TX and RX paths. In case of 2039 * reception, for example, it pre-allocated the RX socket buffer in order to 2040 * allow zero-copy mechanism. 2041 */ 2042 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 2043 { 2044 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2045 size_t size; 2046 void *addr; 2047 2048 tx_q->queue_index = queue; 2049 tx_q->priv_data = priv; 2050 2051 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 2052 sizeof(*tx_q->tx_skbuff_dma), 2053 GFP_KERNEL); 2054 if (!tx_q->tx_skbuff_dma) 2055 return -ENOMEM; 2056 2057 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 2058 sizeof(struct sk_buff *), 2059 GFP_KERNEL); 2060 if (!tx_q->tx_skbuff) 2061 return -ENOMEM; 2062 2063 if (priv->extend_desc) 2064 size = sizeof(struct dma_extended_desc); 2065 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2066 size = sizeof(struct dma_edesc); 2067 else 2068 size = sizeof(struct dma_desc); 2069 2070 size *= priv->dma_tx_size; 2071 2072 addr = dma_alloc_coherent(priv->device, size, 2073 &tx_q->dma_tx_phy, GFP_KERNEL); 2074 if (!addr) 2075 return -ENOMEM; 2076 2077 if (priv->extend_desc) 2078 tx_q->dma_etx = addr; 2079 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2080 tx_q->dma_entx = addr; 2081 else 2082 tx_q->dma_tx = addr; 2083 2084 return 0; 2085 } 2086 2087 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 2088 { 2089 u32 tx_count = priv->plat->tx_queues_to_use; 2090 u32 queue; 2091 int ret; 2092 2093 /* TX queues buffers and DMA */ 2094 for (queue = 0; queue < tx_count; queue++) { 2095 ret = __alloc_dma_tx_desc_resources(priv, queue); 2096 if (ret) 2097 goto err_dma; 2098 } 2099 2100 return 0; 2101 2102 err_dma: 2103 free_dma_tx_desc_resources(priv); 2104 return ret; 2105 } 2106 2107 /** 2108 * alloc_dma_desc_resources - alloc TX/RX resources. 2109 * @priv: private structure 2110 * Description: according to which descriptor can be used (extend or basic) 2111 * this function allocates the resources for TX and RX paths. In case of 2112 * reception, for example, it pre-allocated the RX socket buffer in order to 2113 * allow zero-copy mechanism. 2114 */ 2115 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 2116 { 2117 /* RX Allocation */ 2118 int ret = alloc_dma_rx_desc_resources(priv); 2119 2120 if (ret) 2121 return ret; 2122 2123 ret = alloc_dma_tx_desc_resources(priv); 2124 2125 return ret; 2126 } 2127 2128 /** 2129 * free_dma_desc_resources - free dma desc resources 2130 * @priv: private structure 2131 */ 2132 static void free_dma_desc_resources(struct stmmac_priv *priv) 2133 { 2134 /* Release the DMA TX socket buffers */ 2135 free_dma_tx_desc_resources(priv); 2136 2137 /* Release the DMA RX socket buffers later 2138 * to ensure all pending XDP_TX buffers are returned. 2139 */ 2140 free_dma_rx_desc_resources(priv); 2141 } 2142 2143 /** 2144 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2145 * @priv: driver private structure 2146 * Description: It is used for enabling the rx queues in the MAC 2147 */ 2148 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2149 { 2150 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2151 int queue; 2152 u8 mode; 2153 2154 for (queue = 0; queue < rx_queues_count; queue++) { 2155 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2156 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2157 } 2158 } 2159 2160 /** 2161 * stmmac_start_rx_dma - start RX DMA channel 2162 * @priv: driver private structure 2163 * @chan: RX channel index 2164 * Description: 2165 * This starts a RX DMA channel 2166 */ 2167 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2168 { 2169 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2170 stmmac_start_rx(priv, priv->ioaddr, chan); 2171 } 2172 2173 /** 2174 * stmmac_start_tx_dma - start TX DMA channel 2175 * @priv: driver private structure 2176 * @chan: TX channel index 2177 * Description: 2178 * This starts a TX DMA channel 2179 */ 2180 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2181 { 2182 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2183 stmmac_start_tx(priv, priv->ioaddr, chan); 2184 } 2185 2186 /** 2187 * stmmac_stop_rx_dma - stop RX DMA channel 2188 * @priv: driver private structure 2189 * @chan: RX channel index 2190 * Description: 2191 * This stops a RX DMA channel 2192 */ 2193 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2194 { 2195 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2196 stmmac_stop_rx(priv, priv->ioaddr, chan); 2197 } 2198 2199 /** 2200 * stmmac_stop_tx_dma - stop TX DMA channel 2201 * @priv: driver private structure 2202 * @chan: TX channel index 2203 * Description: 2204 * This stops a TX DMA channel 2205 */ 2206 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2207 { 2208 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2209 stmmac_stop_tx(priv, priv->ioaddr, chan); 2210 } 2211 2212 /** 2213 * stmmac_start_all_dma - start all RX and TX DMA channels 2214 * @priv: driver private structure 2215 * Description: 2216 * This starts all the RX and TX DMA channels 2217 */ 2218 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2219 { 2220 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2221 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2222 u32 chan = 0; 2223 2224 for (chan = 0; chan < rx_channels_count; chan++) 2225 stmmac_start_rx_dma(priv, chan); 2226 2227 for (chan = 0; chan < tx_channels_count; chan++) 2228 stmmac_start_tx_dma(priv, chan); 2229 } 2230 2231 /** 2232 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2233 * @priv: driver private structure 2234 * Description: 2235 * This stops the RX and TX DMA channels 2236 */ 2237 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2238 { 2239 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2240 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2241 u32 chan = 0; 2242 2243 for (chan = 0; chan < rx_channels_count; chan++) 2244 stmmac_stop_rx_dma(priv, chan); 2245 2246 for (chan = 0; chan < tx_channels_count; chan++) 2247 stmmac_stop_tx_dma(priv, chan); 2248 } 2249 2250 /** 2251 * stmmac_dma_operation_mode - HW DMA operation mode 2252 * @priv: driver private structure 2253 * Description: it is used for configuring the DMA operation mode register in 2254 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2255 */ 2256 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2257 { 2258 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2259 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2260 int rxfifosz = priv->plat->rx_fifo_size; 2261 int txfifosz = priv->plat->tx_fifo_size; 2262 u32 txmode = 0; 2263 u32 rxmode = 0; 2264 u32 chan = 0; 2265 u8 qmode = 0; 2266 2267 if (rxfifosz == 0) 2268 rxfifosz = priv->dma_cap.rx_fifo_size; 2269 if (txfifosz == 0) 2270 txfifosz = priv->dma_cap.tx_fifo_size; 2271 2272 /* Adjust for real per queue fifo size */ 2273 rxfifosz /= rx_channels_count; 2274 txfifosz /= tx_channels_count; 2275 2276 if (priv->plat->force_thresh_dma_mode) { 2277 txmode = tc; 2278 rxmode = tc; 2279 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2280 /* 2281 * In case of GMAC, SF mode can be enabled 2282 * to perform the TX COE in HW. This depends on: 2283 * 1) TX COE if actually supported 2284 * 2) There is no bugged Jumbo frame support 2285 * that needs to not insert csum in the TDES. 2286 */ 2287 txmode = SF_DMA_MODE; 2288 rxmode = SF_DMA_MODE; 2289 priv->xstats.threshold = SF_DMA_MODE; 2290 } else { 2291 txmode = tc; 2292 rxmode = SF_DMA_MODE; 2293 } 2294 2295 /* configure all channels */ 2296 for (chan = 0; chan < rx_channels_count; chan++) { 2297 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2298 u32 buf_size; 2299 2300 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2301 2302 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2303 rxfifosz, qmode); 2304 2305 if (rx_q->xsk_pool) { 2306 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2307 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2308 buf_size, 2309 chan); 2310 } else { 2311 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2312 priv->dma_buf_sz, 2313 chan); 2314 } 2315 } 2316 2317 for (chan = 0; chan < tx_channels_count; chan++) { 2318 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2319 2320 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2321 txfifosz, qmode); 2322 } 2323 } 2324 2325 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2326 { 2327 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2328 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2329 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2330 unsigned int entry = tx_q->cur_tx; 2331 struct dma_desc *tx_desc = NULL; 2332 struct xdp_desc xdp_desc; 2333 bool work_done = true; 2334 2335 /* Avoids TX time-out as we are sharing with slow path */ 2336 txq_trans_cond_update(nq); 2337 2338 budget = min(budget, stmmac_tx_avail(priv, queue)); 2339 2340 while (budget-- > 0) { 2341 dma_addr_t dma_addr; 2342 bool set_ic; 2343 2344 /* We are sharing with slow path and stop XSK TX desc submission when 2345 * available TX ring is less than threshold. 2346 */ 2347 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2348 !netif_carrier_ok(priv->dev)) { 2349 work_done = false; 2350 break; 2351 } 2352 2353 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2354 break; 2355 2356 if (likely(priv->extend_desc)) 2357 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2358 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2359 tx_desc = &tx_q->dma_entx[entry].basic; 2360 else 2361 tx_desc = tx_q->dma_tx + entry; 2362 2363 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2364 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2365 2366 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2367 2368 /* To return XDP buffer to XSK pool, we simple call 2369 * xsk_tx_completed(), so we don't need to fill up 2370 * 'buf' and 'xdpf'. 2371 */ 2372 tx_q->tx_skbuff_dma[entry].buf = 0; 2373 tx_q->xdpf[entry] = NULL; 2374 2375 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2376 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2377 tx_q->tx_skbuff_dma[entry].last_segment = true; 2378 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2379 2380 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2381 2382 tx_q->tx_count_frames++; 2383 2384 if (!priv->tx_coal_frames[queue]) 2385 set_ic = false; 2386 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2387 set_ic = true; 2388 else 2389 set_ic = false; 2390 2391 if (set_ic) { 2392 tx_q->tx_count_frames = 0; 2393 stmmac_set_tx_ic(priv, tx_desc); 2394 priv->xstats.tx_set_ic_bit++; 2395 } 2396 2397 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2398 true, priv->mode, true, true, 2399 xdp_desc.len); 2400 2401 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2402 2403 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2404 entry = tx_q->cur_tx; 2405 } 2406 2407 if (tx_desc) { 2408 stmmac_flush_tx_descriptors(priv, queue); 2409 xsk_tx_release(pool); 2410 } 2411 2412 /* Return true if all of the 3 conditions are met 2413 * a) TX Budget is still available 2414 * b) work_done = true when XSK TX desc peek is empty (no more 2415 * pending XSK TX for transmission) 2416 */ 2417 return !!budget && work_done; 2418 } 2419 2420 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2421 { 2422 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2423 tc += 64; 2424 2425 if (priv->plat->force_thresh_dma_mode) 2426 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2427 else 2428 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2429 chan); 2430 2431 priv->xstats.threshold = tc; 2432 } 2433 } 2434 2435 /** 2436 * stmmac_tx_clean - to manage the transmission completion 2437 * @priv: driver private structure 2438 * @budget: napi budget limiting this functions packet handling 2439 * @queue: TX queue index 2440 * Description: it reclaims the transmit resources after transmission completes. 2441 */ 2442 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2443 { 2444 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2445 unsigned int bytes_compl = 0, pkts_compl = 0; 2446 unsigned int entry, xmits = 0, count = 0; 2447 2448 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2449 2450 priv->xstats.tx_clean++; 2451 2452 tx_q->xsk_frames_done = 0; 2453 2454 entry = tx_q->dirty_tx; 2455 2456 /* Try to clean all TX complete frame in 1 shot */ 2457 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { 2458 struct xdp_frame *xdpf; 2459 struct sk_buff *skb; 2460 struct dma_desc *p; 2461 int status; 2462 2463 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2464 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2465 xdpf = tx_q->xdpf[entry]; 2466 skb = NULL; 2467 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2468 xdpf = NULL; 2469 skb = tx_q->tx_skbuff[entry]; 2470 } else { 2471 xdpf = NULL; 2472 skb = NULL; 2473 } 2474 2475 if (priv->extend_desc) 2476 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2477 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2478 p = &tx_q->dma_entx[entry].basic; 2479 else 2480 p = tx_q->dma_tx + entry; 2481 2482 status = stmmac_tx_status(priv, &priv->dev->stats, 2483 &priv->xstats, p, priv->ioaddr); 2484 /* Check if the descriptor is owned by the DMA */ 2485 if (unlikely(status & tx_dma_own)) 2486 break; 2487 2488 count++; 2489 2490 /* Make sure descriptor fields are read after reading 2491 * the own bit. 2492 */ 2493 dma_rmb(); 2494 2495 /* Just consider the last segment and ...*/ 2496 if (likely(!(status & tx_not_ls))) { 2497 /* ... verify the status error condition */ 2498 if (unlikely(status & tx_err)) { 2499 priv->dev->stats.tx_errors++; 2500 if (unlikely(status & tx_err_bump_tc)) 2501 stmmac_bump_dma_threshold(priv, queue); 2502 } else { 2503 priv->dev->stats.tx_packets++; 2504 priv->xstats.tx_pkt_n++; 2505 priv->xstats.txq_stats[queue].tx_pkt_n++; 2506 } 2507 if (skb) 2508 stmmac_get_tx_hwtstamp(priv, p, skb); 2509 } 2510 2511 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2512 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2513 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2514 dma_unmap_page(priv->device, 2515 tx_q->tx_skbuff_dma[entry].buf, 2516 tx_q->tx_skbuff_dma[entry].len, 2517 DMA_TO_DEVICE); 2518 else 2519 dma_unmap_single(priv->device, 2520 tx_q->tx_skbuff_dma[entry].buf, 2521 tx_q->tx_skbuff_dma[entry].len, 2522 DMA_TO_DEVICE); 2523 tx_q->tx_skbuff_dma[entry].buf = 0; 2524 tx_q->tx_skbuff_dma[entry].len = 0; 2525 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2526 } 2527 2528 stmmac_clean_desc3(priv, tx_q, p); 2529 2530 tx_q->tx_skbuff_dma[entry].last_segment = false; 2531 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2532 2533 if (xdpf && 2534 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2535 xdp_return_frame_rx_napi(xdpf); 2536 tx_q->xdpf[entry] = NULL; 2537 } 2538 2539 if (xdpf && 2540 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2541 xdp_return_frame(xdpf); 2542 tx_q->xdpf[entry] = NULL; 2543 } 2544 2545 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2546 tx_q->xsk_frames_done++; 2547 2548 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2549 if (likely(skb)) { 2550 pkts_compl++; 2551 bytes_compl += skb->len; 2552 dev_consume_skb_any(skb); 2553 tx_q->tx_skbuff[entry] = NULL; 2554 } 2555 } 2556 2557 stmmac_release_tx_desc(priv, p, priv->mode); 2558 2559 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2560 } 2561 tx_q->dirty_tx = entry; 2562 2563 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2564 pkts_compl, bytes_compl); 2565 2566 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2567 queue))) && 2568 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2569 2570 netif_dbg(priv, tx_done, priv->dev, 2571 "%s: restart transmit\n", __func__); 2572 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2573 } 2574 2575 if (tx_q->xsk_pool) { 2576 bool work_done; 2577 2578 if (tx_q->xsk_frames_done) 2579 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2580 2581 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2582 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2583 2584 /* For XSK TX, we try to send as many as possible. 2585 * If XSK work done (XSK TX desc empty and budget still 2586 * available), return "budget - 1" to reenable TX IRQ. 2587 * Else, return "budget" to make NAPI continue polling. 2588 */ 2589 work_done = stmmac_xdp_xmit_zc(priv, queue, 2590 STMMAC_XSK_TX_BUDGET_MAX); 2591 if (work_done) 2592 xmits = budget - 1; 2593 else 2594 xmits = budget; 2595 } 2596 2597 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2598 priv->eee_sw_timer_en) { 2599 if (stmmac_enable_eee_mode(priv)) 2600 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2601 } 2602 2603 /* We still have pending packets, let's call for a new scheduling */ 2604 if (tx_q->dirty_tx != tx_q->cur_tx) 2605 hrtimer_start(&tx_q->txtimer, 2606 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2607 HRTIMER_MODE_REL); 2608 2609 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2610 2611 /* Combine decisions from TX clean and XSK TX */ 2612 return max(count, xmits); 2613 } 2614 2615 /** 2616 * stmmac_tx_err - to manage the tx error 2617 * @priv: driver private structure 2618 * @chan: channel index 2619 * Description: it cleans the descriptors and restarts the transmission 2620 * in case of transmission errors. 2621 */ 2622 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2623 { 2624 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2625 2626 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2627 2628 stmmac_stop_tx_dma(priv, chan); 2629 dma_free_tx_skbufs(priv, chan); 2630 stmmac_clear_tx_descriptors(priv, chan); 2631 tx_q->dirty_tx = 0; 2632 tx_q->cur_tx = 0; 2633 tx_q->mss = 0; 2634 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2635 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2636 tx_q->dma_tx_phy, chan); 2637 stmmac_start_tx_dma(priv, chan); 2638 2639 priv->dev->stats.tx_errors++; 2640 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2641 } 2642 2643 /** 2644 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2645 * @priv: driver private structure 2646 * @txmode: TX operating mode 2647 * @rxmode: RX operating mode 2648 * @chan: channel index 2649 * Description: it is used for configuring of the DMA operation mode in 2650 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2651 * mode. 2652 */ 2653 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2654 u32 rxmode, u32 chan) 2655 { 2656 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2657 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2658 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2659 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2660 int rxfifosz = priv->plat->rx_fifo_size; 2661 int txfifosz = priv->plat->tx_fifo_size; 2662 2663 if (rxfifosz == 0) 2664 rxfifosz = priv->dma_cap.rx_fifo_size; 2665 if (txfifosz == 0) 2666 txfifosz = priv->dma_cap.tx_fifo_size; 2667 2668 /* Adjust for real per queue fifo size */ 2669 rxfifosz /= rx_channels_count; 2670 txfifosz /= tx_channels_count; 2671 2672 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2673 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2674 } 2675 2676 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2677 { 2678 int ret; 2679 2680 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2681 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2682 if (ret && (ret != -EINVAL)) { 2683 stmmac_global_err(priv); 2684 return true; 2685 } 2686 2687 return false; 2688 } 2689 2690 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2691 { 2692 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2693 &priv->xstats, chan, dir); 2694 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2695 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2696 struct stmmac_channel *ch = &priv->channel[chan]; 2697 struct napi_struct *rx_napi; 2698 struct napi_struct *tx_napi; 2699 unsigned long flags; 2700 2701 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2702 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2703 2704 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2705 if (napi_schedule_prep(rx_napi)) { 2706 spin_lock_irqsave(&ch->lock, flags); 2707 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2708 spin_unlock_irqrestore(&ch->lock, flags); 2709 __napi_schedule(rx_napi); 2710 } 2711 } 2712 2713 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2714 if (napi_schedule_prep(tx_napi)) { 2715 spin_lock_irqsave(&ch->lock, flags); 2716 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2717 spin_unlock_irqrestore(&ch->lock, flags); 2718 __napi_schedule(tx_napi); 2719 } 2720 } 2721 2722 return status; 2723 } 2724 2725 /** 2726 * stmmac_dma_interrupt - DMA ISR 2727 * @priv: driver private structure 2728 * Description: this is the DMA ISR. It is called by the main ISR. 2729 * It calls the dwmac dma routine and schedule poll method in case of some 2730 * work can be done. 2731 */ 2732 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2733 { 2734 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2735 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2736 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2737 tx_channel_count : rx_channel_count; 2738 u32 chan; 2739 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2740 2741 /* Make sure we never check beyond our status buffer. */ 2742 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2743 channels_to_check = ARRAY_SIZE(status); 2744 2745 for (chan = 0; chan < channels_to_check; chan++) 2746 status[chan] = stmmac_napi_check(priv, chan, 2747 DMA_DIR_RXTX); 2748 2749 for (chan = 0; chan < tx_channel_count; chan++) { 2750 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2751 /* Try to bump up the dma threshold on this failure */ 2752 stmmac_bump_dma_threshold(priv, chan); 2753 } else if (unlikely(status[chan] == tx_hard_error)) { 2754 stmmac_tx_err(priv, chan); 2755 } 2756 } 2757 } 2758 2759 /** 2760 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2761 * @priv: driver private structure 2762 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2763 */ 2764 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2765 { 2766 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2767 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2768 2769 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2770 2771 if (priv->dma_cap.rmon) { 2772 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2773 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2774 } else 2775 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2776 } 2777 2778 /** 2779 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2780 * @priv: driver private structure 2781 * Description: 2782 * new GMAC chip generations have a new register to indicate the 2783 * presence of the optional feature/functions. 2784 * This can be also used to override the value passed through the 2785 * platform and necessary for old MAC10/100 and GMAC chips. 2786 */ 2787 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2788 { 2789 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2790 } 2791 2792 /** 2793 * stmmac_check_ether_addr - check if the MAC addr is valid 2794 * @priv: driver private structure 2795 * Description: 2796 * it is to verify if the MAC address is valid, in case of failures it 2797 * generates a random MAC address 2798 */ 2799 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2800 { 2801 u8 addr[ETH_ALEN]; 2802 2803 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2804 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2805 if (is_valid_ether_addr(addr)) 2806 eth_hw_addr_set(priv->dev, addr); 2807 else 2808 eth_hw_addr_random(priv->dev); 2809 dev_info(priv->device, "device MAC address %pM\n", 2810 priv->dev->dev_addr); 2811 } 2812 } 2813 2814 /** 2815 * stmmac_init_dma_engine - DMA init. 2816 * @priv: driver private structure 2817 * Description: 2818 * It inits the DMA invoking the specific MAC/GMAC callback. 2819 * Some DMA parameters can be passed from the platform; 2820 * in case of these are not passed a default is kept for the MAC or GMAC. 2821 */ 2822 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2823 { 2824 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2825 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2826 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2827 struct stmmac_rx_queue *rx_q; 2828 struct stmmac_tx_queue *tx_q; 2829 u32 chan = 0; 2830 int atds = 0; 2831 int ret = 0; 2832 2833 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2834 dev_err(priv->device, "Invalid DMA configuration\n"); 2835 return -EINVAL; 2836 } 2837 2838 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2839 atds = 1; 2840 2841 ret = stmmac_reset(priv, priv->ioaddr); 2842 if (ret) { 2843 dev_err(priv->device, "Failed to reset the dma\n"); 2844 return ret; 2845 } 2846 2847 /* DMA Configuration */ 2848 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2849 2850 if (priv->plat->axi) 2851 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2852 2853 /* DMA CSR Channel configuration */ 2854 for (chan = 0; chan < dma_csr_ch; chan++) 2855 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2856 2857 /* DMA RX Channel Configuration */ 2858 for (chan = 0; chan < rx_channels_count; chan++) { 2859 rx_q = &priv->rx_queue[chan]; 2860 2861 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2862 rx_q->dma_rx_phy, chan); 2863 2864 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2865 (rx_q->buf_alloc_num * 2866 sizeof(struct dma_desc)); 2867 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2868 rx_q->rx_tail_addr, chan); 2869 } 2870 2871 /* DMA TX Channel Configuration */ 2872 for (chan = 0; chan < tx_channels_count; chan++) { 2873 tx_q = &priv->tx_queue[chan]; 2874 2875 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2876 tx_q->dma_tx_phy, chan); 2877 2878 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2879 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2880 tx_q->tx_tail_addr, chan); 2881 } 2882 2883 return ret; 2884 } 2885 2886 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2887 { 2888 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2889 2890 hrtimer_start(&tx_q->txtimer, 2891 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2892 HRTIMER_MODE_REL); 2893 } 2894 2895 /** 2896 * stmmac_tx_timer - mitigation sw timer for tx. 2897 * @t: data pointer 2898 * Description: 2899 * This is the timer handler to directly invoke the stmmac_tx_clean. 2900 */ 2901 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2902 { 2903 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2904 struct stmmac_priv *priv = tx_q->priv_data; 2905 struct stmmac_channel *ch; 2906 struct napi_struct *napi; 2907 2908 ch = &priv->channel[tx_q->queue_index]; 2909 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2910 2911 if (likely(napi_schedule_prep(napi))) { 2912 unsigned long flags; 2913 2914 spin_lock_irqsave(&ch->lock, flags); 2915 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2916 spin_unlock_irqrestore(&ch->lock, flags); 2917 __napi_schedule(napi); 2918 } 2919 2920 return HRTIMER_NORESTART; 2921 } 2922 2923 /** 2924 * stmmac_init_coalesce - init mitigation options. 2925 * @priv: driver private structure 2926 * Description: 2927 * This inits the coalesce parameters: i.e. timer rate, 2928 * timer handler and default threshold used for enabling the 2929 * interrupt on completion bit. 2930 */ 2931 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2932 { 2933 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2934 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2935 u32 chan; 2936 2937 for (chan = 0; chan < tx_channel_count; chan++) { 2938 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2939 2940 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 2941 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 2942 2943 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2944 tx_q->txtimer.function = stmmac_tx_timer; 2945 } 2946 2947 for (chan = 0; chan < rx_channel_count; chan++) 2948 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 2949 } 2950 2951 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2952 { 2953 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2954 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2955 u32 chan; 2956 2957 /* set TX ring length */ 2958 for (chan = 0; chan < tx_channels_count; chan++) 2959 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2960 (priv->dma_tx_size - 1), chan); 2961 2962 /* set RX ring length */ 2963 for (chan = 0; chan < rx_channels_count; chan++) 2964 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2965 (priv->dma_rx_size - 1), chan); 2966 } 2967 2968 /** 2969 * stmmac_set_tx_queue_weight - Set TX queue weight 2970 * @priv: driver private structure 2971 * Description: It is used for setting TX queues weight 2972 */ 2973 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2974 { 2975 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2976 u32 weight; 2977 u32 queue; 2978 2979 for (queue = 0; queue < tx_queues_count; queue++) { 2980 weight = priv->plat->tx_queues_cfg[queue].weight; 2981 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2982 } 2983 } 2984 2985 /** 2986 * stmmac_configure_cbs - Configure CBS in TX queue 2987 * @priv: driver private structure 2988 * Description: It is used for configuring CBS in AVB TX queues 2989 */ 2990 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2991 { 2992 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2993 u32 mode_to_use; 2994 u32 queue; 2995 2996 /* queue 0 is reserved for legacy traffic */ 2997 for (queue = 1; queue < tx_queues_count; queue++) { 2998 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2999 if (mode_to_use == MTL_QUEUE_DCB) 3000 continue; 3001 3002 stmmac_config_cbs(priv, priv->hw, 3003 priv->plat->tx_queues_cfg[queue].send_slope, 3004 priv->plat->tx_queues_cfg[queue].idle_slope, 3005 priv->plat->tx_queues_cfg[queue].high_credit, 3006 priv->plat->tx_queues_cfg[queue].low_credit, 3007 queue); 3008 } 3009 } 3010 3011 /** 3012 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3013 * @priv: driver private structure 3014 * Description: It is used for mapping RX queues to RX dma channels 3015 */ 3016 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3017 { 3018 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3019 u32 queue; 3020 u32 chan; 3021 3022 for (queue = 0; queue < rx_queues_count; queue++) { 3023 chan = priv->plat->rx_queues_cfg[queue].chan; 3024 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3025 } 3026 } 3027 3028 /** 3029 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3030 * @priv: driver private structure 3031 * Description: It is used for configuring the RX Queue Priority 3032 */ 3033 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3034 { 3035 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3036 u32 queue; 3037 u32 prio; 3038 3039 for (queue = 0; queue < rx_queues_count; queue++) { 3040 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3041 continue; 3042 3043 prio = priv->plat->rx_queues_cfg[queue].prio; 3044 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3045 } 3046 } 3047 3048 /** 3049 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3050 * @priv: driver private structure 3051 * Description: It is used for configuring the TX Queue Priority 3052 */ 3053 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3054 { 3055 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3056 u32 queue; 3057 u32 prio; 3058 3059 for (queue = 0; queue < tx_queues_count; queue++) { 3060 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3061 continue; 3062 3063 prio = priv->plat->tx_queues_cfg[queue].prio; 3064 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3065 } 3066 } 3067 3068 /** 3069 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3070 * @priv: driver private structure 3071 * Description: It is used for configuring the RX queue routing 3072 */ 3073 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3074 { 3075 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3076 u32 queue; 3077 u8 packet; 3078 3079 for (queue = 0; queue < rx_queues_count; queue++) { 3080 /* no specific packet type routing specified for the queue */ 3081 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3082 continue; 3083 3084 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3085 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3086 } 3087 } 3088 3089 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3090 { 3091 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3092 priv->rss.enable = false; 3093 return; 3094 } 3095 3096 if (priv->dev->features & NETIF_F_RXHASH) 3097 priv->rss.enable = true; 3098 else 3099 priv->rss.enable = false; 3100 3101 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3102 priv->plat->rx_queues_to_use); 3103 } 3104 3105 /** 3106 * stmmac_mtl_configuration - Configure MTL 3107 * @priv: driver private structure 3108 * Description: It is used for configurring MTL 3109 */ 3110 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3111 { 3112 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3113 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3114 3115 if (tx_queues_count > 1) 3116 stmmac_set_tx_queue_weight(priv); 3117 3118 /* Configure MTL RX algorithms */ 3119 if (rx_queues_count > 1) 3120 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3121 priv->plat->rx_sched_algorithm); 3122 3123 /* Configure MTL TX algorithms */ 3124 if (tx_queues_count > 1) 3125 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3126 priv->plat->tx_sched_algorithm); 3127 3128 /* Configure CBS in AVB TX queues */ 3129 if (tx_queues_count > 1) 3130 stmmac_configure_cbs(priv); 3131 3132 /* Map RX MTL to DMA channels */ 3133 stmmac_rx_queue_dma_chan_map(priv); 3134 3135 /* Enable MAC RX Queues */ 3136 stmmac_mac_enable_rx_queues(priv); 3137 3138 /* Set RX priorities */ 3139 if (rx_queues_count > 1) 3140 stmmac_mac_config_rx_queues_prio(priv); 3141 3142 /* Set TX priorities */ 3143 if (tx_queues_count > 1) 3144 stmmac_mac_config_tx_queues_prio(priv); 3145 3146 /* Set RX routing */ 3147 if (rx_queues_count > 1) 3148 stmmac_mac_config_rx_queues_routing(priv); 3149 3150 /* Receive Side Scaling */ 3151 if (rx_queues_count > 1) 3152 stmmac_mac_config_rss(priv); 3153 } 3154 3155 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3156 { 3157 if (priv->dma_cap.asp) { 3158 netdev_info(priv->dev, "Enabling Safety Features\n"); 3159 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3160 priv->plat->safety_feat_cfg); 3161 } else { 3162 netdev_info(priv->dev, "No Safety Features support found\n"); 3163 } 3164 } 3165 3166 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3167 { 3168 char *name; 3169 3170 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3171 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3172 3173 name = priv->wq_name; 3174 sprintf(name, "%s-fpe", priv->dev->name); 3175 3176 priv->fpe_wq = create_singlethread_workqueue(name); 3177 if (!priv->fpe_wq) { 3178 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3179 3180 return -ENOMEM; 3181 } 3182 netdev_info(priv->dev, "FPE workqueue start"); 3183 3184 return 0; 3185 } 3186 3187 /** 3188 * stmmac_hw_setup - setup mac in a usable state. 3189 * @dev : pointer to the device structure. 3190 * @ptp_register: register PTP if set 3191 * Description: 3192 * this is the main function to setup the HW in a usable state because the 3193 * dma engine is reset, the core registers are configured (e.g. AXI, 3194 * Checksum features, timers). The DMA is ready to start receiving and 3195 * transmitting. 3196 * Return value: 3197 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3198 * file on failure. 3199 */ 3200 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3201 { 3202 struct stmmac_priv *priv = netdev_priv(dev); 3203 u32 rx_cnt = priv->plat->rx_queues_to_use; 3204 u32 tx_cnt = priv->plat->tx_queues_to_use; 3205 bool sph_en; 3206 u32 chan; 3207 int ret; 3208 3209 /* DMA initialization and SW reset */ 3210 ret = stmmac_init_dma_engine(priv); 3211 if (ret < 0) { 3212 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3213 __func__); 3214 return ret; 3215 } 3216 3217 /* Copy the MAC addr into the HW */ 3218 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3219 3220 /* PS and related bits will be programmed according to the speed */ 3221 if (priv->hw->pcs) { 3222 int speed = priv->plat->mac_port_sel_speed; 3223 3224 if ((speed == SPEED_10) || (speed == SPEED_100) || 3225 (speed == SPEED_1000)) { 3226 priv->hw->ps = speed; 3227 } else { 3228 dev_warn(priv->device, "invalid port speed\n"); 3229 priv->hw->ps = 0; 3230 } 3231 } 3232 3233 /* Initialize the MAC Core */ 3234 stmmac_core_init(priv, priv->hw, dev); 3235 3236 /* Initialize MTL*/ 3237 stmmac_mtl_configuration(priv); 3238 3239 /* Initialize Safety Features */ 3240 stmmac_safety_feat_configuration(priv); 3241 3242 ret = stmmac_rx_ipc(priv, priv->hw); 3243 if (!ret) { 3244 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3245 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3246 priv->hw->rx_csum = 0; 3247 } 3248 3249 /* Enable the MAC Rx/Tx */ 3250 stmmac_mac_set(priv, priv->ioaddr, true); 3251 3252 /* Set the HW DMA mode and the COE */ 3253 stmmac_dma_operation_mode(priv); 3254 3255 stmmac_mmc_setup(priv); 3256 3257 ret = stmmac_init_ptp(priv); 3258 if (ret == -EOPNOTSUPP) 3259 netdev_warn(priv->dev, "PTP not supported by HW\n"); 3260 else if (ret) 3261 netdev_warn(priv->dev, "PTP init failed\n"); 3262 else if (ptp_register) 3263 stmmac_ptp_register(priv); 3264 3265 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3266 3267 /* Convert the timer from msec to usec */ 3268 if (!priv->tx_lpi_timer) 3269 priv->tx_lpi_timer = eee_timer * 1000; 3270 3271 if (priv->use_riwt) { 3272 u32 queue; 3273 3274 for (queue = 0; queue < rx_cnt; queue++) { 3275 if (!priv->rx_riwt[queue]) 3276 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3277 3278 stmmac_rx_watchdog(priv, priv->ioaddr, 3279 priv->rx_riwt[queue], queue); 3280 } 3281 } 3282 3283 if (priv->hw->pcs) 3284 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3285 3286 /* set TX and RX rings length */ 3287 stmmac_set_rings_length(priv); 3288 3289 /* Enable TSO */ 3290 if (priv->tso) { 3291 for (chan = 0; chan < tx_cnt; chan++) { 3292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3293 3294 /* TSO and TBS cannot co-exist */ 3295 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3296 continue; 3297 3298 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3299 } 3300 } 3301 3302 /* Enable Split Header */ 3303 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3304 for (chan = 0; chan < rx_cnt; chan++) 3305 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3306 3307 3308 /* VLAN Tag Insertion */ 3309 if (priv->dma_cap.vlins) 3310 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3311 3312 /* TBS */ 3313 for (chan = 0; chan < tx_cnt; chan++) { 3314 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3315 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3316 3317 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3318 } 3319 3320 /* Configure real RX and TX queues */ 3321 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3322 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3323 3324 /* Start the ball rolling... */ 3325 stmmac_start_all_dma(priv); 3326 3327 if (priv->dma_cap.fpesel) { 3328 stmmac_fpe_start_wq(priv); 3329 3330 if (priv->plat->fpe_cfg->enable) 3331 stmmac_fpe_handshake(priv, true); 3332 } 3333 3334 return 0; 3335 } 3336 3337 static void stmmac_hw_teardown(struct net_device *dev) 3338 { 3339 struct stmmac_priv *priv = netdev_priv(dev); 3340 3341 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3342 } 3343 3344 static void stmmac_free_irq(struct net_device *dev, 3345 enum request_irq_err irq_err, int irq_idx) 3346 { 3347 struct stmmac_priv *priv = netdev_priv(dev); 3348 int j; 3349 3350 switch (irq_err) { 3351 case REQ_IRQ_ERR_ALL: 3352 irq_idx = priv->plat->tx_queues_to_use; 3353 fallthrough; 3354 case REQ_IRQ_ERR_TX: 3355 for (j = irq_idx - 1; j >= 0; j--) { 3356 if (priv->tx_irq[j] > 0) { 3357 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3358 free_irq(priv->tx_irq[j], &priv->tx_queue[j]); 3359 } 3360 } 3361 irq_idx = priv->plat->rx_queues_to_use; 3362 fallthrough; 3363 case REQ_IRQ_ERR_RX: 3364 for (j = irq_idx - 1; j >= 0; j--) { 3365 if (priv->rx_irq[j] > 0) { 3366 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3367 free_irq(priv->rx_irq[j], &priv->rx_queue[j]); 3368 } 3369 } 3370 3371 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3372 free_irq(priv->sfty_ue_irq, dev); 3373 fallthrough; 3374 case REQ_IRQ_ERR_SFTY_UE: 3375 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3376 free_irq(priv->sfty_ce_irq, dev); 3377 fallthrough; 3378 case REQ_IRQ_ERR_SFTY_CE: 3379 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3380 free_irq(priv->lpi_irq, dev); 3381 fallthrough; 3382 case REQ_IRQ_ERR_LPI: 3383 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3384 free_irq(priv->wol_irq, dev); 3385 fallthrough; 3386 case REQ_IRQ_ERR_WOL: 3387 free_irq(dev->irq, dev); 3388 fallthrough; 3389 case REQ_IRQ_ERR_MAC: 3390 case REQ_IRQ_ERR_NO: 3391 /* If MAC IRQ request error, no more IRQ to free */ 3392 break; 3393 } 3394 } 3395 3396 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3397 { 3398 struct stmmac_priv *priv = netdev_priv(dev); 3399 enum request_irq_err irq_err; 3400 cpumask_t cpu_mask; 3401 int irq_idx = 0; 3402 char *int_name; 3403 int ret; 3404 int i; 3405 3406 /* For common interrupt */ 3407 int_name = priv->int_name_mac; 3408 sprintf(int_name, "%s:%s", dev->name, "mac"); 3409 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3410 0, int_name, dev); 3411 if (unlikely(ret < 0)) { 3412 netdev_err(priv->dev, 3413 "%s: alloc mac MSI %d (error: %d)\n", 3414 __func__, dev->irq, ret); 3415 irq_err = REQ_IRQ_ERR_MAC; 3416 goto irq_error; 3417 } 3418 3419 /* Request the Wake IRQ in case of another line 3420 * is used for WoL 3421 */ 3422 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3423 int_name = priv->int_name_wol; 3424 sprintf(int_name, "%s:%s", dev->name, "wol"); 3425 ret = request_irq(priv->wol_irq, 3426 stmmac_mac_interrupt, 3427 0, int_name, dev); 3428 if (unlikely(ret < 0)) { 3429 netdev_err(priv->dev, 3430 "%s: alloc wol MSI %d (error: %d)\n", 3431 __func__, priv->wol_irq, ret); 3432 irq_err = REQ_IRQ_ERR_WOL; 3433 goto irq_error; 3434 } 3435 } 3436 3437 /* Request the LPI IRQ in case of another line 3438 * is used for LPI 3439 */ 3440 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3441 int_name = priv->int_name_lpi; 3442 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3443 ret = request_irq(priv->lpi_irq, 3444 stmmac_mac_interrupt, 3445 0, int_name, dev); 3446 if (unlikely(ret < 0)) { 3447 netdev_err(priv->dev, 3448 "%s: alloc lpi MSI %d (error: %d)\n", 3449 __func__, priv->lpi_irq, ret); 3450 irq_err = REQ_IRQ_ERR_LPI; 3451 goto irq_error; 3452 } 3453 } 3454 3455 /* Request the Safety Feature Correctible Error line in 3456 * case of another line is used 3457 */ 3458 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3459 int_name = priv->int_name_sfty_ce; 3460 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3461 ret = request_irq(priv->sfty_ce_irq, 3462 stmmac_safety_interrupt, 3463 0, int_name, dev); 3464 if (unlikely(ret < 0)) { 3465 netdev_err(priv->dev, 3466 "%s: alloc sfty ce MSI %d (error: %d)\n", 3467 __func__, priv->sfty_ce_irq, ret); 3468 irq_err = REQ_IRQ_ERR_SFTY_CE; 3469 goto irq_error; 3470 } 3471 } 3472 3473 /* Request the Safety Feature Uncorrectible Error line in 3474 * case of another line is used 3475 */ 3476 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3477 int_name = priv->int_name_sfty_ue; 3478 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3479 ret = request_irq(priv->sfty_ue_irq, 3480 stmmac_safety_interrupt, 3481 0, int_name, dev); 3482 if (unlikely(ret < 0)) { 3483 netdev_err(priv->dev, 3484 "%s: alloc sfty ue MSI %d (error: %d)\n", 3485 __func__, priv->sfty_ue_irq, ret); 3486 irq_err = REQ_IRQ_ERR_SFTY_UE; 3487 goto irq_error; 3488 } 3489 } 3490 3491 /* Request Rx MSI irq */ 3492 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3493 if (i >= MTL_MAX_RX_QUEUES) 3494 break; 3495 if (priv->rx_irq[i] == 0) 3496 continue; 3497 3498 int_name = priv->int_name_rx_irq[i]; 3499 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3500 ret = request_irq(priv->rx_irq[i], 3501 stmmac_msi_intr_rx, 3502 0, int_name, &priv->rx_queue[i]); 3503 if (unlikely(ret < 0)) { 3504 netdev_err(priv->dev, 3505 "%s: alloc rx-%d MSI %d (error: %d)\n", 3506 __func__, i, priv->rx_irq[i], ret); 3507 irq_err = REQ_IRQ_ERR_RX; 3508 irq_idx = i; 3509 goto irq_error; 3510 } 3511 cpumask_clear(&cpu_mask); 3512 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3513 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3514 } 3515 3516 /* Request Tx MSI irq */ 3517 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3518 if (i >= MTL_MAX_TX_QUEUES) 3519 break; 3520 if (priv->tx_irq[i] == 0) 3521 continue; 3522 3523 int_name = priv->int_name_tx_irq[i]; 3524 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3525 ret = request_irq(priv->tx_irq[i], 3526 stmmac_msi_intr_tx, 3527 0, int_name, &priv->tx_queue[i]); 3528 if (unlikely(ret < 0)) { 3529 netdev_err(priv->dev, 3530 "%s: alloc tx-%d MSI %d (error: %d)\n", 3531 __func__, i, priv->tx_irq[i], ret); 3532 irq_err = REQ_IRQ_ERR_TX; 3533 irq_idx = i; 3534 goto irq_error; 3535 } 3536 cpumask_clear(&cpu_mask); 3537 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3538 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3539 } 3540 3541 return 0; 3542 3543 irq_error: 3544 stmmac_free_irq(dev, irq_err, irq_idx); 3545 return ret; 3546 } 3547 3548 static int stmmac_request_irq_single(struct net_device *dev) 3549 { 3550 struct stmmac_priv *priv = netdev_priv(dev); 3551 enum request_irq_err irq_err; 3552 int ret; 3553 3554 ret = request_irq(dev->irq, stmmac_interrupt, 3555 IRQF_SHARED, dev->name, dev); 3556 if (unlikely(ret < 0)) { 3557 netdev_err(priv->dev, 3558 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3559 __func__, dev->irq, ret); 3560 irq_err = REQ_IRQ_ERR_MAC; 3561 goto irq_error; 3562 } 3563 3564 /* Request the Wake IRQ in case of another line 3565 * is used for WoL 3566 */ 3567 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3568 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3569 IRQF_SHARED, dev->name, dev); 3570 if (unlikely(ret < 0)) { 3571 netdev_err(priv->dev, 3572 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3573 __func__, priv->wol_irq, ret); 3574 irq_err = REQ_IRQ_ERR_WOL; 3575 goto irq_error; 3576 } 3577 } 3578 3579 /* Request the IRQ lines */ 3580 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3581 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3582 IRQF_SHARED, dev->name, dev); 3583 if (unlikely(ret < 0)) { 3584 netdev_err(priv->dev, 3585 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3586 __func__, priv->lpi_irq, ret); 3587 irq_err = REQ_IRQ_ERR_LPI; 3588 goto irq_error; 3589 } 3590 } 3591 3592 return 0; 3593 3594 irq_error: 3595 stmmac_free_irq(dev, irq_err, 0); 3596 return ret; 3597 } 3598 3599 static int stmmac_request_irq(struct net_device *dev) 3600 { 3601 struct stmmac_priv *priv = netdev_priv(dev); 3602 int ret; 3603 3604 /* Request the IRQ lines */ 3605 if (priv->plat->multi_msi_en) 3606 ret = stmmac_request_irq_multi_msi(dev); 3607 else 3608 ret = stmmac_request_irq_single(dev); 3609 3610 return ret; 3611 } 3612 3613 /** 3614 * stmmac_open - open entry point of the driver 3615 * @dev : pointer to the device structure. 3616 * Description: 3617 * This function is the open entry point of the driver. 3618 * Return value: 3619 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3620 * file on failure. 3621 */ 3622 static int stmmac_open(struct net_device *dev) 3623 { 3624 struct stmmac_priv *priv = netdev_priv(dev); 3625 int mode = priv->plat->phy_interface; 3626 int bfsize = 0; 3627 u32 chan; 3628 int ret; 3629 3630 ret = pm_runtime_get_sync(priv->device); 3631 if (ret < 0) { 3632 pm_runtime_put_noidle(priv->device); 3633 return ret; 3634 } 3635 3636 if (priv->hw->pcs != STMMAC_PCS_TBI && 3637 priv->hw->pcs != STMMAC_PCS_RTBI && 3638 (!priv->hw->xpcs || 3639 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3640 ret = stmmac_init_phy(dev); 3641 if (ret) { 3642 netdev_err(priv->dev, 3643 "%s: Cannot attach to PHY (error: %d)\n", 3644 __func__, ret); 3645 goto init_phy_error; 3646 } 3647 } 3648 3649 /* Extra statistics */ 3650 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3651 priv->xstats.threshold = tc; 3652 3653 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 3654 if (bfsize < 0) 3655 bfsize = 0; 3656 3657 if (bfsize < BUF_SIZE_16KiB) 3658 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 3659 3660 priv->dma_buf_sz = bfsize; 3661 buf_sz = bfsize; 3662 3663 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3664 3665 if (!priv->dma_tx_size) 3666 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3667 if (!priv->dma_rx_size) 3668 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3669 3670 /* Earlier check for TBS */ 3671 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3672 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3673 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3674 3675 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3676 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3677 } 3678 3679 ret = alloc_dma_desc_resources(priv); 3680 if (ret < 0) { 3681 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3682 __func__); 3683 goto dma_desc_error; 3684 } 3685 3686 ret = init_dma_desc_rings(dev, GFP_KERNEL); 3687 if (ret < 0) { 3688 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3689 __func__); 3690 goto init_error; 3691 } 3692 3693 ret = stmmac_hw_setup(dev, true); 3694 if (ret < 0) { 3695 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3696 goto init_error; 3697 } 3698 3699 stmmac_init_coalesce(priv); 3700 3701 phylink_start(priv->phylink); 3702 /* We may have called phylink_speed_down before */ 3703 phylink_speed_up(priv->phylink); 3704 3705 ret = stmmac_request_irq(dev); 3706 if (ret) 3707 goto irq_error; 3708 3709 stmmac_enable_all_queues(priv); 3710 netif_tx_start_all_queues(priv->dev); 3711 3712 return 0; 3713 3714 irq_error: 3715 phylink_stop(priv->phylink); 3716 3717 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3718 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3719 3720 stmmac_hw_teardown(dev); 3721 init_error: 3722 free_dma_desc_resources(priv); 3723 dma_desc_error: 3724 phylink_disconnect_phy(priv->phylink); 3725 init_phy_error: 3726 pm_runtime_put(priv->device); 3727 return ret; 3728 } 3729 3730 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3731 { 3732 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3733 3734 if (priv->fpe_wq) 3735 destroy_workqueue(priv->fpe_wq); 3736 3737 netdev_info(priv->dev, "FPE workqueue stop"); 3738 } 3739 3740 /** 3741 * stmmac_release - close entry point of the driver 3742 * @dev : device pointer. 3743 * Description: 3744 * This is the stop entry point of the driver. 3745 */ 3746 static int stmmac_release(struct net_device *dev) 3747 { 3748 struct stmmac_priv *priv = netdev_priv(dev); 3749 u32 chan; 3750 3751 netif_tx_disable(dev); 3752 3753 if (device_may_wakeup(priv->device)) 3754 phylink_speed_down(priv->phylink, false); 3755 /* Stop and disconnect the PHY */ 3756 phylink_stop(priv->phylink); 3757 phylink_disconnect_phy(priv->phylink); 3758 3759 stmmac_disable_all_queues(priv); 3760 3761 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3762 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3763 3764 /* Free the IRQ lines */ 3765 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3766 3767 if (priv->eee_enabled) { 3768 priv->tx_path_in_lpi_mode = false; 3769 del_timer_sync(&priv->eee_ctrl_timer); 3770 } 3771 3772 /* Stop TX/RX DMA and clear the descriptors */ 3773 stmmac_stop_all_dma(priv); 3774 3775 /* Release and free the Rx/Tx resources */ 3776 free_dma_desc_resources(priv); 3777 3778 /* Disable the MAC Rx/Tx */ 3779 stmmac_mac_set(priv, priv->ioaddr, false); 3780 3781 netif_carrier_off(dev); 3782 3783 stmmac_release_ptp(priv); 3784 3785 pm_runtime_put(priv->device); 3786 3787 if (priv->dma_cap.fpesel) 3788 stmmac_fpe_stop_wq(priv); 3789 3790 return 0; 3791 } 3792 3793 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3794 struct stmmac_tx_queue *tx_q) 3795 { 3796 u16 tag = 0x0, inner_tag = 0x0; 3797 u32 inner_type = 0x0; 3798 struct dma_desc *p; 3799 3800 if (!priv->dma_cap.vlins) 3801 return false; 3802 if (!skb_vlan_tag_present(skb)) 3803 return false; 3804 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3805 inner_tag = skb_vlan_tag_get(skb); 3806 inner_type = STMMAC_VLAN_INSERT; 3807 } 3808 3809 tag = skb_vlan_tag_get(skb); 3810 3811 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3812 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3813 else 3814 p = &tx_q->dma_tx[tx_q->cur_tx]; 3815 3816 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3817 return false; 3818 3819 stmmac_set_tx_owner(priv, p); 3820 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3821 return true; 3822 } 3823 3824 /** 3825 * stmmac_tso_allocator - close entry point of the driver 3826 * @priv: driver private structure 3827 * @des: buffer start address 3828 * @total_len: total length to fill in descriptors 3829 * @last_segment: condition for the last descriptor 3830 * @queue: TX queue index 3831 * Description: 3832 * This function fills descriptor and request new descriptors according to 3833 * buffer length to fill 3834 */ 3835 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3836 int total_len, bool last_segment, u32 queue) 3837 { 3838 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3839 struct dma_desc *desc; 3840 u32 buff_size; 3841 int tmp_len; 3842 3843 tmp_len = total_len; 3844 3845 while (tmp_len > 0) { 3846 dma_addr_t curr_addr; 3847 3848 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3849 priv->dma_tx_size); 3850 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3851 3852 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3853 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3854 else 3855 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3856 3857 curr_addr = des + (total_len - tmp_len); 3858 if (priv->dma_cap.addr64 <= 32) 3859 desc->des0 = cpu_to_le32(curr_addr); 3860 else 3861 stmmac_set_desc_addr(priv, desc, curr_addr); 3862 3863 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3864 TSO_MAX_BUFF_SIZE : tmp_len; 3865 3866 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3867 0, 1, 3868 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3869 0, 0); 3870 3871 tmp_len -= TSO_MAX_BUFF_SIZE; 3872 } 3873 } 3874 3875 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 3876 { 3877 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3878 int desc_size; 3879 3880 if (likely(priv->extend_desc)) 3881 desc_size = sizeof(struct dma_extended_desc); 3882 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3883 desc_size = sizeof(struct dma_edesc); 3884 else 3885 desc_size = sizeof(struct dma_desc); 3886 3887 /* The own bit must be the latest setting done when prepare the 3888 * descriptor and then barrier is needed to make sure that 3889 * all is coherent before granting the DMA engine. 3890 */ 3891 wmb(); 3892 3893 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3894 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3895 } 3896 3897 /** 3898 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3899 * @skb : the socket buffer 3900 * @dev : device pointer 3901 * Description: this is the transmit function that is called on TSO frames 3902 * (support available on GMAC4 and newer chips). 3903 * Diagram below show the ring programming in case of TSO frames: 3904 * 3905 * First Descriptor 3906 * -------- 3907 * | DES0 |---> buffer1 = L2/L3/L4 header 3908 * | DES1 |---> TCP Payload (can continue on next descr...) 3909 * | DES2 |---> buffer 1 and 2 len 3910 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3911 * -------- 3912 * | 3913 * ... 3914 * | 3915 * -------- 3916 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3917 * | DES1 | --| 3918 * | DES2 | --> buffer 1 and 2 len 3919 * | DES3 | 3920 * -------- 3921 * 3922 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3923 */ 3924 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3925 { 3926 struct dma_desc *desc, *first, *mss_desc = NULL; 3927 struct stmmac_priv *priv = netdev_priv(dev); 3928 int nfrags = skb_shinfo(skb)->nr_frags; 3929 u32 queue = skb_get_queue_mapping(skb); 3930 unsigned int first_entry, tx_packets; 3931 int tmp_pay_len = 0, first_tx; 3932 struct stmmac_tx_queue *tx_q; 3933 bool has_vlan, set_ic; 3934 u8 proto_hdr_len, hdr; 3935 u32 pay_len, mss; 3936 dma_addr_t des; 3937 int i; 3938 3939 tx_q = &priv->tx_queue[queue]; 3940 first_tx = tx_q->cur_tx; 3941 3942 /* Compute header lengths */ 3943 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3944 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3945 hdr = sizeof(struct udphdr); 3946 } else { 3947 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3948 hdr = tcp_hdrlen(skb); 3949 } 3950 3951 /* Desc availability based on threshold should be enough safe */ 3952 if (unlikely(stmmac_tx_avail(priv, queue) < 3953 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3954 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3955 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3956 queue)); 3957 /* This is a hard error, log it. */ 3958 netdev_err(priv->dev, 3959 "%s: Tx Ring full when queue awake\n", 3960 __func__); 3961 } 3962 return NETDEV_TX_BUSY; 3963 } 3964 3965 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3966 3967 mss = skb_shinfo(skb)->gso_size; 3968 3969 /* set new MSS value if needed */ 3970 if (mss != tx_q->mss) { 3971 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3972 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3973 else 3974 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3975 3976 stmmac_set_mss(priv, mss_desc, mss); 3977 tx_q->mss = mss; 3978 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3979 priv->dma_tx_size); 3980 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3981 } 3982 3983 if (netif_msg_tx_queued(priv)) { 3984 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3985 __func__, hdr, proto_hdr_len, pay_len, mss); 3986 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3987 skb->data_len); 3988 } 3989 3990 /* Check if VLAN can be inserted by HW */ 3991 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3992 3993 first_entry = tx_q->cur_tx; 3994 WARN_ON(tx_q->tx_skbuff[first_entry]); 3995 3996 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3997 desc = &tx_q->dma_entx[first_entry].basic; 3998 else 3999 desc = &tx_q->dma_tx[first_entry]; 4000 first = desc; 4001 4002 if (has_vlan) 4003 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4004 4005 /* first descriptor: fill Headers on Buf1 */ 4006 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4007 DMA_TO_DEVICE); 4008 if (dma_mapping_error(priv->device, des)) 4009 goto dma_map_err; 4010 4011 tx_q->tx_skbuff_dma[first_entry].buf = des; 4012 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4013 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4014 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4015 4016 if (priv->dma_cap.addr64 <= 32) { 4017 first->des0 = cpu_to_le32(des); 4018 4019 /* Fill start of payload in buff2 of first descriptor */ 4020 if (pay_len) 4021 first->des1 = cpu_to_le32(des + proto_hdr_len); 4022 4023 /* If needed take extra descriptors to fill the remaining payload */ 4024 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4025 } else { 4026 stmmac_set_desc_addr(priv, first, des); 4027 tmp_pay_len = pay_len; 4028 des += proto_hdr_len; 4029 pay_len = 0; 4030 } 4031 4032 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4033 4034 /* Prepare fragments */ 4035 for (i = 0; i < nfrags; i++) { 4036 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4037 4038 des = skb_frag_dma_map(priv->device, frag, 0, 4039 skb_frag_size(frag), 4040 DMA_TO_DEVICE); 4041 if (dma_mapping_error(priv->device, des)) 4042 goto dma_map_err; 4043 4044 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4045 (i == nfrags - 1), queue); 4046 4047 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4048 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4049 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4050 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4051 } 4052 4053 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4054 4055 /* Only the last descriptor gets to point to the skb. */ 4056 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4057 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4058 4059 /* Manage tx mitigation */ 4060 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4061 tx_q->tx_count_frames += tx_packets; 4062 4063 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4064 set_ic = true; 4065 else if (!priv->tx_coal_frames[queue]) 4066 set_ic = false; 4067 else if (tx_packets > priv->tx_coal_frames[queue]) 4068 set_ic = true; 4069 else if ((tx_q->tx_count_frames % 4070 priv->tx_coal_frames[queue]) < tx_packets) 4071 set_ic = true; 4072 else 4073 set_ic = false; 4074 4075 if (set_ic) { 4076 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4077 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4078 else 4079 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4080 4081 tx_q->tx_count_frames = 0; 4082 stmmac_set_tx_ic(priv, desc); 4083 priv->xstats.tx_set_ic_bit++; 4084 } 4085 4086 /* We've used all descriptors we need for this skb, however, 4087 * advance cur_tx so that it references a fresh descriptor. 4088 * ndo_start_xmit will fill this descriptor the next time it's 4089 * called and stmmac_tx_clean may clean up to this descriptor. 4090 */ 4091 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 4092 4093 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4094 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4095 __func__); 4096 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4097 } 4098 4099 dev->stats.tx_bytes += skb->len; 4100 priv->xstats.tx_tso_frames++; 4101 priv->xstats.tx_tso_nfrags += nfrags; 4102 4103 if (priv->sarc_type) 4104 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4105 4106 skb_tx_timestamp(skb); 4107 4108 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4109 priv->hwts_tx_en)) { 4110 /* declare that device is doing timestamping */ 4111 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4112 stmmac_enable_tx_timestamp(priv, first); 4113 } 4114 4115 /* Complete the first descriptor before granting the DMA */ 4116 stmmac_prepare_tso_tx_desc(priv, first, 1, 4117 proto_hdr_len, 4118 pay_len, 4119 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4120 hdr / 4, (skb->len - proto_hdr_len)); 4121 4122 /* If context desc is used to change MSS */ 4123 if (mss_desc) { 4124 /* Make sure that first descriptor has been completely 4125 * written, including its own bit. This is because MSS is 4126 * actually before first descriptor, so we need to make 4127 * sure that MSS's own bit is the last thing written. 4128 */ 4129 dma_wmb(); 4130 stmmac_set_tx_owner(priv, mss_desc); 4131 } 4132 4133 if (netif_msg_pktdata(priv)) { 4134 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4135 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4136 tx_q->cur_tx, first, nfrags); 4137 pr_info(">>> frame to be transmitted: "); 4138 print_pkt(skb->data, skb_headlen(skb)); 4139 } 4140 4141 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4142 4143 stmmac_flush_tx_descriptors(priv, queue); 4144 stmmac_tx_timer_arm(priv, queue); 4145 4146 return NETDEV_TX_OK; 4147 4148 dma_map_err: 4149 dev_err(priv->device, "Tx dma map failed\n"); 4150 dev_kfree_skb(skb); 4151 priv->dev->stats.tx_dropped++; 4152 return NETDEV_TX_OK; 4153 } 4154 4155 /** 4156 * stmmac_xmit - Tx entry point of the driver 4157 * @skb : the socket buffer 4158 * @dev : device pointer 4159 * Description : this is the tx entry point of the driver. 4160 * It programs the chain or the ring and supports oversized frames 4161 * and SG feature. 4162 */ 4163 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4164 { 4165 unsigned int first_entry, tx_packets, enh_desc; 4166 struct stmmac_priv *priv = netdev_priv(dev); 4167 unsigned int nopaged_len = skb_headlen(skb); 4168 int i, csum_insertion = 0, is_jumbo = 0; 4169 u32 queue = skb_get_queue_mapping(skb); 4170 int nfrags = skb_shinfo(skb)->nr_frags; 4171 int gso = skb_shinfo(skb)->gso_type; 4172 struct dma_edesc *tbs_desc = NULL; 4173 struct dma_desc *desc, *first; 4174 struct stmmac_tx_queue *tx_q; 4175 bool has_vlan, set_ic; 4176 int entry, first_tx; 4177 dma_addr_t des; 4178 4179 tx_q = &priv->tx_queue[queue]; 4180 first_tx = tx_q->cur_tx; 4181 4182 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4183 stmmac_disable_eee_mode(priv); 4184 4185 /* Manage oversized TCP frames for GMAC4 device */ 4186 if (skb_is_gso(skb) && priv->tso) { 4187 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4188 return stmmac_tso_xmit(skb, dev); 4189 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4190 return stmmac_tso_xmit(skb, dev); 4191 } 4192 4193 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4194 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4195 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4196 queue)); 4197 /* This is a hard error, log it. */ 4198 netdev_err(priv->dev, 4199 "%s: Tx Ring full when queue awake\n", 4200 __func__); 4201 } 4202 return NETDEV_TX_BUSY; 4203 } 4204 4205 /* Check if VLAN can be inserted by HW */ 4206 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4207 4208 entry = tx_q->cur_tx; 4209 first_entry = entry; 4210 WARN_ON(tx_q->tx_skbuff[first_entry]); 4211 4212 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4213 4214 if (likely(priv->extend_desc)) 4215 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4216 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4217 desc = &tx_q->dma_entx[entry].basic; 4218 else 4219 desc = tx_q->dma_tx + entry; 4220 4221 first = desc; 4222 4223 if (has_vlan) 4224 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4225 4226 enh_desc = priv->plat->enh_desc; 4227 /* To program the descriptors according to the size of the frame */ 4228 if (enh_desc) 4229 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4230 4231 if (unlikely(is_jumbo)) { 4232 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4233 if (unlikely(entry < 0) && (entry != -EINVAL)) 4234 goto dma_map_err; 4235 } 4236 4237 for (i = 0; i < nfrags; i++) { 4238 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4239 int len = skb_frag_size(frag); 4240 bool last_segment = (i == (nfrags - 1)); 4241 4242 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4243 WARN_ON(tx_q->tx_skbuff[entry]); 4244 4245 if (likely(priv->extend_desc)) 4246 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4247 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4248 desc = &tx_q->dma_entx[entry].basic; 4249 else 4250 desc = tx_q->dma_tx + entry; 4251 4252 des = skb_frag_dma_map(priv->device, frag, 0, len, 4253 DMA_TO_DEVICE); 4254 if (dma_mapping_error(priv->device, des)) 4255 goto dma_map_err; /* should reuse desc w/o issues */ 4256 4257 tx_q->tx_skbuff_dma[entry].buf = des; 4258 4259 stmmac_set_desc_addr(priv, desc, des); 4260 4261 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4262 tx_q->tx_skbuff_dma[entry].len = len; 4263 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4264 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4265 4266 /* Prepare the descriptor and set the own bit too */ 4267 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4268 priv->mode, 1, last_segment, skb->len); 4269 } 4270 4271 /* Only the last descriptor gets to point to the skb. */ 4272 tx_q->tx_skbuff[entry] = skb; 4273 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4274 4275 /* According to the coalesce parameter the IC bit for the latest 4276 * segment is reset and the timer re-started to clean the tx status. 4277 * This approach takes care about the fragments: desc is the first 4278 * element in case of no SG. 4279 */ 4280 tx_packets = (entry + 1) - first_tx; 4281 tx_q->tx_count_frames += tx_packets; 4282 4283 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4284 set_ic = true; 4285 else if (!priv->tx_coal_frames[queue]) 4286 set_ic = false; 4287 else if (tx_packets > priv->tx_coal_frames[queue]) 4288 set_ic = true; 4289 else if ((tx_q->tx_count_frames % 4290 priv->tx_coal_frames[queue]) < tx_packets) 4291 set_ic = true; 4292 else 4293 set_ic = false; 4294 4295 if (set_ic) { 4296 if (likely(priv->extend_desc)) 4297 desc = &tx_q->dma_etx[entry].basic; 4298 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4299 desc = &tx_q->dma_entx[entry].basic; 4300 else 4301 desc = &tx_q->dma_tx[entry]; 4302 4303 tx_q->tx_count_frames = 0; 4304 stmmac_set_tx_ic(priv, desc); 4305 priv->xstats.tx_set_ic_bit++; 4306 } 4307 4308 /* We've used all descriptors we need for this skb, however, 4309 * advance cur_tx so that it references a fresh descriptor. 4310 * ndo_start_xmit will fill this descriptor the next time it's 4311 * called and stmmac_tx_clean may clean up to this descriptor. 4312 */ 4313 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4314 tx_q->cur_tx = entry; 4315 4316 if (netif_msg_pktdata(priv)) { 4317 netdev_dbg(priv->dev, 4318 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4319 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4320 entry, first, nfrags); 4321 4322 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4323 print_pkt(skb->data, skb->len); 4324 } 4325 4326 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4327 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4328 __func__); 4329 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4330 } 4331 4332 dev->stats.tx_bytes += skb->len; 4333 4334 if (priv->sarc_type) 4335 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4336 4337 skb_tx_timestamp(skb); 4338 4339 /* Ready to fill the first descriptor and set the OWN bit w/o any 4340 * problems because all the descriptors are actually ready to be 4341 * passed to the DMA engine. 4342 */ 4343 if (likely(!is_jumbo)) { 4344 bool last_segment = (nfrags == 0); 4345 4346 des = dma_map_single(priv->device, skb->data, 4347 nopaged_len, DMA_TO_DEVICE); 4348 if (dma_mapping_error(priv->device, des)) 4349 goto dma_map_err; 4350 4351 tx_q->tx_skbuff_dma[first_entry].buf = des; 4352 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4353 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4354 4355 stmmac_set_desc_addr(priv, first, des); 4356 4357 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4358 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4359 4360 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4361 priv->hwts_tx_en)) { 4362 /* declare that device is doing timestamping */ 4363 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4364 stmmac_enable_tx_timestamp(priv, first); 4365 } 4366 4367 /* Prepare the first descriptor setting the OWN bit too */ 4368 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4369 csum_insertion, priv->mode, 0, last_segment, 4370 skb->len); 4371 } 4372 4373 if (tx_q->tbs & STMMAC_TBS_EN) { 4374 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4375 4376 tbs_desc = &tx_q->dma_entx[first_entry]; 4377 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4378 } 4379 4380 stmmac_set_tx_owner(priv, first); 4381 4382 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4383 4384 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4385 4386 stmmac_flush_tx_descriptors(priv, queue); 4387 stmmac_tx_timer_arm(priv, queue); 4388 4389 return NETDEV_TX_OK; 4390 4391 dma_map_err: 4392 netdev_err(priv->dev, "Tx DMA map failed\n"); 4393 dev_kfree_skb(skb); 4394 priv->dev->stats.tx_dropped++; 4395 return NETDEV_TX_OK; 4396 } 4397 4398 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4399 { 4400 struct vlan_ethhdr *veth; 4401 __be16 vlan_proto; 4402 u16 vlanid; 4403 4404 veth = (struct vlan_ethhdr *)skb->data; 4405 vlan_proto = veth->h_vlan_proto; 4406 4407 if ((vlan_proto == htons(ETH_P_8021Q) && 4408 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4409 (vlan_proto == htons(ETH_P_8021AD) && 4410 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4411 /* pop the vlan tag */ 4412 vlanid = ntohs(veth->h_vlan_TCI); 4413 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4414 skb_pull(skb, VLAN_HLEN); 4415 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4416 } 4417 } 4418 4419 /** 4420 * stmmac_rx_refill - refill used skb preallocated buffers 4421 * @priv: driver private structure 4422 * @queue: RX queue index 4423 * Description : this is to reallocate the skb for the reception process 4424 * that is based on zero-copy. 4425 */ 4426 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4427 { 4428 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4429 int dirty = stmmac_rx_dirty(priv, queue); 4430 unsigned int entry = rx_q->dirty_rx; 4431 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4432 4433 if (priv->dma_cap.addr64 <= 32) 4434 gfp |= GFP_DMA32; 4435 4436 while (dirty-- > 0) { 4437 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4438 struct dma_desc *p; 4439 bool use_rx_wd; 4440 4441 if (priv->extend_desc) 4442 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4443 else 4444 p = rx_q->dma_rx + entry; 4445 4446 if (!buf->page) { 4447 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4448 if (!buf->page) 4449 break; 4450 } 4451 4452 if (priv->sph && !buf->sec_page) { 4453 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4454 if (!buf->sec_page) 4455 break; 4456 4457 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4458 } 4459 4460 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4461 4462 stmmac_set_desc_addr(priv, p, buf->addr); 4463 if (priv->sph) 4464 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4465 else 4466 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4467 stmmac_refill_desc3(priv, rx_q, p); 4468 4469 rx_q->rx_count_frames++; 4470 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4471 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4472 rx_q->rx_count_frames = 0; 4473 4474 use_rx_wd = !priv->rx_coal_frames[queue]; 4475 use_rx_wd |= rx_q->rx_count_frames > 0; 4476 if (!priv->use_riwt) 4477 use_rx_wd = false; 4478 4479 dma_wmb(); 4480 stmmac_set_rx_owner(priv, p, use_rx_wd); 4481 4482 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4483 } 4484 rx_q->dirty_rx = entry; 4485 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4486 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4487 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4488 } 4489 4490 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4491 struct dma_desc *p, 4492 int status, unsigned int len) 4493 { 4494 unsigned int plen = 0, hlen = 0; 4495 int coe = priv->hw->rx_csum; 4496 4497 /* Not first descriptor, buffer is always zero */ 4498 if (priv->sph && len) 4499 return 0; 4500 4501 /* First descriptor, get split header length */ 4502 stmmac_get_rx_header_len(priv, p, &hlen); 4503 if (priv->sph && hlen) { 4504 priv->xstats.rx_split_hdr_pkt_n++; 4505 return hlen; 4506 } 4507 4508 /* First descriptor, not last descriptor and not split header */ 4509 if (status & rx_not_ls) 4510 return priv->dma_buf_sz; 4511 4512 plen = stmmac_get_rx_frame_len(priv, p, coe); 4513 4514 /* First descriptor and last descriptor and not split header */ 4515 return min_t(unsigned int, priv->dma_buf_sz, plen); 4516 } 4517 4518 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4519 struct dma_desc *p, 4520 int status, unsigned int len) 4521 { 4522 int coe = priv->hw->rx_csum; 4523 unsigned int plen = 0; 4524 4525 /* Not split header, buffer is not available */ 4526 if (!priv->sph) 4527 return 0; 4528 4529 /* Not last descriptor */ 4530 if (status & rx_not_ls) 4531 return priv->dma_buf_sz; 4532 4533 plen = stmmac_get_rx_frame_len(priv, p, coe); 4534 4535 /* Last descriptor */ 4536 return plen - len; 4537 } 4538 4539 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4540 struct xdp_frame *xdpf, bool dma_map) 4541 { 4542 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4543 unsigned int entry = tx_q->cur_tx; 4544 struct dma_desc *tx_desc; 4545 dma_addr_t dma_addr; 4546 bool set_ic; 4547 4548 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4549 return STMMAC_XDP_CONSUMED; 4550 4551 if (likely(priv->extend_desc)) 4552 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4553 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4554 tx_desc = &tx_q->dma_entx[entry].basic; 4555 else 4556 tx_desc = tx_q->dma_tx + entry; 4557 4558 if (dma_map) { 4559 dma_addr = dma_map_single(priv->device, xdpf->data, 4560 xdpf->len, DMA_TO_DEVICE); 4561 if (dma_mapping_error(priv->device, dma_addr)) 4562 return STMMAC_XDP_CONSUMED; 4563 4564 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4565 } else { 4566 struct page *page = virt_to_page(xdpf->data); 4567 4568 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4569 xdpf->headroom; 4570 dma_sync_single_for_device(priv->device, dma_addr, 4571 xdpf->len, DMA_BIDIRECTIONAL); 4572 4573 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4574 } 4575 4576 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4577 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4578 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4579 tx_q->tx_skbuff_dma[entry].last_segment = true; 4580 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4581 4582 tx_q->xdpf[entry] = xdpf; 4583 4584 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4585 4586 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4587 true, priv->mode, true, true, 4588 xdpf->len); 4589 4590 tx_q->tx_count_frames++; 4591 4592 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4593 set_ic = true; 4594 else 4595 set_ic = false; 4596 4597 if (set_ic) { 4598 tx_q->tx_count_frames = 0; 4599 stmmac_set_tx_ic(priv, tx_desc); 4600 priv->xstats.tx_set_ic_bit++; 4601 } 4602 4603 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4604 4605 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4606 tx_q->cur_tx = entry; 4607 4608 return STMMAC_XDP_TX; 4609 } 4610 4611 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4612 int cpu) 4613 { 4614 int index = cpu; 4615 4616 if (unlikely(index < 0)) 4617 index = 0; 4618 4619 while (index >= priv->plat->tx_queues_to_use) 4620 index -= priv->plat->tx_queues_to_use; 4621 4622 return index; 4623 } 4624 4625 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4626 struct xdp_buff *xdp) 4627 { 4628 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4629 int cpu = smp_processor_id(); 4630 struct netdev_queue *nq; 4631 int queue; 4632 int res; 4633 4634 if (unlikely(!xdpf)) 4635 return STMMAC_XDP_CONSUMED; 4636 4637 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4638 nq = netdev_get_tx_queue(priv->dev, queue); 4639 4640 __netif_tx_lock(nq, cpu); 4641 /* Avoids TX time-out as we are sharing with slow path */ 4642 txq_trans_cond_update(nq); 4643 4644 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4645 if (res == STMMAC_XDP_TX) 4646 stmmac_flush_tx_descriptors(priv, queue); 4647 4648 __netif_tx_unlock(nq); 4649 4650 return res; 4651 } 4652 4653 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4654 struct bpf_prog *prog, 4655 struct xdp_buff *xdp) 4656 { 4657 u32 act; 4658 int res; 4659 4660 act = bpf_prog_run_xdp(prog, xdp); 4661 switch (act) { 4662 case XDP_PASS: 4663 res = STMMAC_XDP_PASS; 4664 break; 4665 case XDP_TX: 4666 res = stmmac_xdp_xmit_back(priv, xdp); 4667 break; 4668 case XDP_REDIRECT: 4669 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4670 res = STMMAC_XDP_CONSUMED; 4671 else 4672 res = STMMAC_XDP_REDIRECT; 4673 break; 4674 default: 4675 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4676 fallthrough; 4677 case XDP_ABORTED: 4678 trace_xdp_exception(priv->dev, prog, act); 4679 fallthrough; 4680 case XDP_DROP: 4681 res = STMMAC_XDP_CONSUMED; 4682 break; 4683 } 4684 4685 return res; 4686 } 4687 4688 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4689 struct xdp_buff *xdp) 4690 { 4691 struct bpf_prog *prog; 4692 int res; 4693 4694 prog = READ_ONCE(priv->xdp_prog); 4695 if (!prog) { 4696 res = STMMAC_XDP_PASS; 4697 goto out; 4698 } 4699 4700 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4701 out: 4702 return ERR_PTR(-res); 4703 } 4704 4705 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4706 int xdp_status) 4707 { 4708 int cpu = smp_processor_id(); 4709 int queue; 4710 4711 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4712 4713 if (xdp_status & STMMAC_XDP_TX) 4714 stmmac_tx_timer_arm(priv, queue); 4715 4716 if (xdp_status & STMMAC_XDP_REDIRECT) 4717 xdp_do_flush(); 4718 } 4719 4720 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4721 struct xdp_buff *xdp) 4722 { 4723 unsigned int metasize = xdp->data - xdp->data_meta; 4724 unsigned int datasize = xdp->data_end - xdp->data; 4725 struct sk_buff *skb; 4726 4727 skb = __napi_alloc_skb(&ch->rxtx_napi, 4728 xdp->data_end - xdp->data_hard_start, 4729 GFP_ATOMIC | __GFP_NOWARN); 4730 if (unlikely(!skb)) 4731 return NULL; 4732 4733 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4734 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4735 if (metasize) 4736 skb_metadata_set(skb, metasize); 4737 4738 return skb; 4739 } 4740 4741 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4742 struct dma_desc *p, struct dma_desc *np, 4743 struct xdp_buff *xdp) 4744 { 4745 struct stmmac_channel *ch = &priv->channel[queue]; 4746 unsigned int len = xdp->data_end - xdp->data; 4747 enum pkt_hash_types hash_type; 4748 int coe = priv->hw->rx_csum; 4749 struct sk_buff *skb; 4750 u32 hash; 4751 4752 skb = stmmac_construct_skb_zc(ch, xdp); 4753 if (!skb) { 4754 priv->dev->stats.rx_dropped++; 4755 return; 4756 } 4757 4758 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4759 stmmac_rx_vlan(priv->dev, skb); 4760 skb->protocol = eth_type_trans(skb, priv->dev); 4761 4762 if (unlikely(!coe)) 4763 skb_checksum_none_assert(skb); 4764 else 4765 skb->ip_summed = CHECKSUM_UNNECESSARY; 4766 4767 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4768 skb_set_hash(skb, hash, hash_type); 4769 4770 skb_record_rx_queue(skb, queue); 4771 napi_gro_receive(&ch->rxtx_napi, skb); 4772 4773 priv->dev->stats.rx_packets++; 4774 priv->dev->stats.rx_bytes += len; 4775 } 4776 4777 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4778 { 4779 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4780 unsigned int entry = rx_q->dirty_rx; 4781 struct dma_desc *rx_desc = NULL; 4782 bool ret = true; 4783 4784 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4785 4786 while (budget-- > 0 && entry != rx_q->cur_rx) { 4787 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4788 dma_addr_t dma_addr; 4789 bool use_rx_wd; 4790 4791 if (!buf->xdp) { 4792 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4793 if (!buf->xdp) { 4794 ret = false; 4795 break; 4796 } 4797 } 4798 4799 if (priv->extend_desc) 4800 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4801 else 4802 rx_desc = rx_q->dma_rx + entry; 4803 4804 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4805 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4806 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4807 stmmac_refill_desc3(priv, rx_q, rx_desc); 4808 4809 rx_q->rx_count_frames++; 4810 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4811 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4812 rx_q->rx_count_frames = 0; 4813 4814 use_rx_wd = !priv->rx_coal_frames[queue]; 4815 use_rx_wd |= rx_q->rx_count_frames > 0; 4816 if (!priv->use_riwt) 4817 use_rx_wd = false; 4818 4819 dma_wmb(); 4820 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4821 4822 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4823 } 4824 4825 if (rx_desc) { 4826 rx_q->dirty_rx = entry; 4827 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4828 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4829 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4830 } 4831 4832 return ret; 4833 } 4834 4835 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4836 { 4837 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4838 unsigned int count = 0, error = 0, len = 0; 4839 int dirty = stmmac_rx_dirty(priv, queue); 4840 unsigned int next_entry = rx_q->cur_rx; 4841 unsigned int desc_size; 4842 struct bpf_prog *prog; 4843 bool failure = false; 4844 int xdp_status = 0; 4845 int status = 0; 4846 4847 if (netif_msg_rx_status(priv)) { 4848 void *rx_head; 4849 4850 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4851 if (priv->extend_desc) { 4852 rx_head = (void *)rx_q->dma_erx; 4853 desc_size = sizeof(struct dma_extended_desc); 4854 } else { 4855 rx_head = (void *)rx_q->dma_rx; 4856 desc_size = sizeof(struct dma_desc); 4857 } 4858 4859 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 4860 rx_q->dma_rx_phy, desc_size); 4861 } 4862 while (count < limit) { 4863 struct stmmac_rx_buffer *buf; 4864 unsigned int buf1_len = 0; 4865 struct dma_desc *np, *p; 4866 int entry; 4867 int res; 4868 4869 if (!count && rx_q->state_saved) { 4870 error = rx_q->state.error; 4871 len = rx_q->state.len; 4872 } else { 4873 rx_q->state_saved = false; 4874 error = 0; 4875 len = 0; 4876 } 4877 4878 if (count >= limit) 4879 break; 4880 4881 read_again: 4882 buf1_len = 0; 4883 entry = next_entry; 4884 buf = &rx_q->buf_pool[entry]; 4885 4886 if (dirty >= STMMAC_RX_FILL_BATCH) { 4887 failure = failure || 4888 !stmmac_rx_refill_zc(priv, queue, dirty); 4889 dirty = 0; 4890 } 4891 4892 if (priv->extend_desc) 4893 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4894 else 4895 p = rx_q->dma_rx + entry; 4896 4897 /* read the status of the incoming frame */ 4898 status = stmmac_rx_status(priv, &priv->dev->stats, 4899 &priv->xstats, p); 4900 /* check if managed by the DMA otherwise go ahead */ 4901 if (unlikely(status & dma_own)) 4902 break; 4903 4904 /* Prefetch the next RX descriptor */ 4905 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 4906 priv->dma_rx_size); 4907 next_entry = rx_q->cur_rx; 4908 4909 if (priv->extend_desc) 4910 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 4911 else 4912 np = rx_q->dma_rx + next_entry; 4913 4914 prefetch(np); 4915 4916 /* Ensure a valid XSK buffer before proceed */ 4917 if (!buf->xdp) 4918 break; 4919 4920 if (priv->extend_desc) 4921 stmmac_rx_extended_status(priv, &priv->dev->stats, 4922 &priv->xstats, 4923 rx_q->dma_erx + entry); 4924 if (unlikely(status == discard_frame)) { 4925 xsk_buff_free(buf->xdp); 4926 buf->xdp = NULL; 4927 dirty++; 4928 error = 1; 4929 if (!priv->hwts_rx_en) 4930 priv->dev->stats.rx_errors++; 4931 } 4932 4933 if (unlikely(error && (status & rx_not_ls))) 4934 goto read_again; 4935 if (unlikely(error)) { 4936 count++; 4937 continue; 4938 } 4939 4940 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 4941 if (likely(status & rx_not_ls)) { 4942 xsk_buff_free(buf->xdp); 4943 buf->xdp = NULL; 4944 dirty++; 4945 count++; 4946 goto read_again; 4947 } 4948 4949 /* XDP ZC Frame only support primary buffers for now */ 4950 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 4951 len += buf1_len; 4952 4953 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 4954 * Type frames (LLC/LLC-SNAP) 4955 * 4956 * llc_snap is never checked in GMAC >= 4, so this ACS 4957 * feature is always disabled and packets need to be 4958 * stripped manually. 4959 */ 4960 if (likely(!(status & rx_not_ls)) && 4961 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 4962 unlikely(status != llc_snap))) { 4963 buf1_len -= ETH_FCS_LEN; 4964 len -= ETH_FCS_LEN; 4965 } 4966 4967 /* RX buffer is good and fit into a XSK pool buffer */ 4968 buf->xdp->data_end = buf->xdp->data + buf1_len; 4969 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 4970 4971 prog = READ_ONCE(priv->xdp_prog); 4972 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 4973 4974 switch (res) { 4975 case STMMAC_XDP_PASS: 4976 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 4977 xsk_buff_free(buf->xdp); 4978 break; 4979 case STMMAC_XDP_CONSUMED: 4980 xsk_buff_free(buf->xdp); 4981 priv->dev->stats.rx_dropped++; 4982 break; 4983 case STMMAC_XDP_TX: 4984 case STMMAC_XDP_REDIRECT: 4985 xdp_status |= res; 4986 break; 4987 } 4988 4989 buf->xdp = NULL; 4990 dirty++; 4991 count++; 4992 } 4993 4994 if (status & rx_not_ls) { 4995 rx_q->state_saved = true; 4996 rx_q->state.error = error; 4997 rx_q->state.len = len; 4998 } 4999 5000 stmmac_finalize_xdp_rx(priv, xdp_status); 5001 5002 priv->xstats.rx_pkt_n += count; 5003 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5004 5005 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5006 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5007 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5008 else 5009 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5010 5011 return (int)count; 5012 } 5013 5014 return failure ? limit : (int)count; 5015 } 5016 5017 /** 5018 * stmmac_rx - manage the receive process 5019 * @priv: driver private structure 5020 * @limit: napi bugget 5021 * @queue: RX queue index. 5022 * Description : this the function called by the napi poll method. 5023 * It gets all the frames inside the ring. 5024 */ 5025 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5026 { 5027 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5028 struct stmmac_channel *ch = &priv->channel[queue]; 5029 unsigned int count = 0, error = 0, len = 0; 5030 int status = 0, coe = priv->hw->rx_csum; 5031 unsigned int next_entry = rx_q->cur_rx; 5032 enum dma_data_direction dma_dir; 5033 unsigned int desc_size; 5034 struct sk_buff *skb = NULL; 5035 struct xdp_buff xdp; 5036 int xdp_status = 0; 5037 int buf_sz; 5038 5039 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5040 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5041 5042 if (netif_msg_rx_status(priv)) { 5043 void *rx_head; 5044 5045 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5046 if (priv->extend_desc) { 5047 rx_head = (void *)rx_q->dma_erx; 5048 desc_size = sizeof(struct dma_extended_desc); 5049 } else { 5050 rx_head = (void *)rx_q->dma_rx; 5051 desc_size = sizeof(struct dma_desc); 5052 } 5053 5054 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 5055 rx_q->dma_rx_phy, desc_size); 5056 } 5057 while (count < limit) { 5058 unsigned int buf1_len = 0, buf2_len = 0; 5059 enum pkt_hash_types hash_type; 5060 struct stmmac_rx_buffer *buf; 5061 struct dma_desc *np, *p; 5062 int entry; 5063 u32 hash; 5064 5065 if (!count && rx_q->state_saved) { 5066 skb = rx_q->state.skb; 5067 error = rx_q->state.error; 5068 len = rx_q->state.len; 5069 } else { 5070 rx_q->state_saved = false; 5071 skb = NULL; 5072 error = 0; 5073 len = 0; 5074 } 5075 5076 if (count >= limit) 5077 break; 5078 5079 read_again: 5080 buf1_len = 0; 5081 buf2_len = 0; 5082 entry = next_entry; 5083 buf = &rx_q->buf_pool[entry]; 5084 5085 if (priv->extend_desc) 5086 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5087 else 5088 p = rx_q->dma_rx + entry; 5089 5090 /* read the status of the incoming frame */ 5091 status = stmmac_rx_status(priv, &priv->dev->stats, 5092 &priv->xstats, p); 5093 /* check if managed by the DMA otherwise go ahead */ 5094 if (unlikely(status & dma_own)) 5095 break; 5096 5097 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5098 priv->dma_rx_size); 5099 next_entry = rx_q->cur_rx; 5100 5101 if (priv->extend_desc) 5102 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5103 else 5104 np = rx_q->dma_rx + next_entry; 5105 5106 prefetch(np); 5107 5108 if (priv->extend_desc) 5109 stmmac_rx_extended_status(priv, &priv->dev->stats, 5110 &priv->xstats, rx_q->dma_erx + entry); 5111 if (unlikely(status == discard_frame)) { 5112 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5113 buf->page = NULL; 5114 error = 1; 5115 if (!priv->hwts_rx_en) 5116 priv->dev->stats.rx_errors++; 5117 } 5118 5119 if (unlikely(error && (status & rx_not_ls))) 5120 goto read_again; 5121 if (unlikely(error)) { 5122 dev_kfree_skb(skb); 5123 skb = NULL; 5124 count++; 5125 continue; 5126 } 5127 5128 /* Buffer is good. Go on. */ 5129 5130 prefetch(page_address(buf->page) + buf->page_offset); 5131 if (buf->sec_page) 5132 prefetch(page_address(buf->sec_page)); 5133 5134 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5135 len += buf1_len; 5136 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5137 len += buf2_len; 5138 5139 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 5140 * Type frames (LLC/LLC-SNAP) 5141 * 5142 * llc_snap is never checked in GMAC >= 4, so this ACS 5143 * feature is always disabled and packets need to be 5144 * stripped manually. 5145 */ 5146 if (likely(!(status & rx_not_ls)) && 5147 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 5148 unlikely(status != llc_snap))) { 5149 if (buf2_len) { 5150 buf2_len -= ETH_FCS_LEN; 5151 len -= ETH_FCS_LEN; 5152 } else if (buf1_len) { 5153 buf1_len -= ETH_FCS_LEN; 5154 len -= ETH_FCS_LEN; 5155 } 5156 } 5157 5158 if (!skb) { 5159 unsigned int pre_len, sync_len; 5160 5161 dma_sync_single_for_cpu(priv->device, buf->addr, 5162 buf1_len, dma_dir); 5163 5164 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5165 xdp_prepare_buff(&xdp, page_address(buf->page), 5166 buf->page_offset, buf1_len, false); 5167 5168 pre_len = xdp.data_end - xdp.data_hard_start - 5169 buf->page_offset; 5170 skb = stmmac_xdp_run_prog(priv, &xdp); 5171 /* Due xdp_adjust_tail: DMA sync for_device 5172 * cover max len CPU touch 5173 */ 5174 sync_len = xdp.data_end - xdp.data_hard_start - 5175 buf->page_offset; 5176 sync_len = max(sync_len, pre_len); 5177 5178 /* For Not XDP_PASS verdict */ 5179 if (IS_ERR(skb)) { 5180 unsigned int xdp_res = -PTR_ERR(skb); 5181 5182 if (xdp_res & STMMAC_XDP_CONSUMED) { 5183 page_pool_put_page(rx_q->page_pool, 5184 virt_to_head_page(xdp.data), 5185 sync_len, true); 5186 buf->page = NULL; 5187 priv->dev->stats.rx_dropped++; 5188 5189 /* Clear skb as it was set as 5190 * status by XDP program. 5191 */ 5192 skb = NULL; 5193 5194 if (unlikely((status & rx_not_ls))) 5195 goto read_again; 5196 5197 count++; 5198 continue; 5199 } else if (xdp_res & (STMMAC_XDP_TX | 5200 STMMAC_XDP_REDIRECT)) { 5201 xdp_status |= xdp_res; 5202 buf->page = NULL; 5203 skb = NULL; 5204 count++; 5205 continue; 5206 } 5207 } 5208 } 5209 5210 if (!skb) { 5211 /* XDP program may expand or reduce tail */ 5212 buf1_len = xdp.data_end - xdp.data; 5213 5214 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5215 if (!skb) { 5216 priv->dev->stats.rx_dropped++; 5217 count++; 5218 goto drain_data; 5219 } 5220 5221 /* XDP program may adjust header */ 5222 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5223 skb_put(skb, buf1_len); 5224 5225 /* Data payload copied into SKB, page ready for recycle */ 5226 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5227 buf->page = NULL; 5228 } else if (buf1_len) { 5229 dma_sync_single_for_cpu(priv->device, buf->addr, 5230 buf1_len, dma_dir); 5231 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5232 buf->page, buf->page_offset, buf1_len, 5233 priv->dma_buf_sz); 5234 5235 /* Data payload appended into SKB */ 5236 page_pool_release_page(rx_q->page_pool, buf->page); 5237 buf->page = NULL; 5238 } 5239 5240 if (buf2_len) { 5241 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5242 buf2_len, dma_dir); 5243 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5244 buf->sec_page, 0, buf2_len, 5245 priv->dma_buf_sz); 5246 5247 /* Data payload appended into SKB */ 5248 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5249 buf->sec_page = NULL; 5250 } 5251 5252 drain_data: 5253 if (likely(status & rx_not_ls)) 5254 goto read_again; 5255 if (!skb) 5256 continue; 5257 5258 /* Got entire packet into SKB. Finish it. */ 5259 5260 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5261 stmmac_rx_vlan(priv->dev, skb); 5262 skb->protocol = eth_type_trans(skb, priv->dev); 5263 5264 if (unlikely(!coe)) 5265 skb_checksum_none_assert(skb); 5266 else 5267 skb->ip_summed = CHECKSUM_UNNECESSARY; 5268 5269 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5270 skb_set_hash(skb, hash, hash_type); 5271 5272 skb_record_rx_queue(skb, queue); 5273 napi_gro_receive(&ch->rx_napi, skb); 5274 skb = NULL; 5275 5276 priv->dev->stats.rx_packets++; 5277 priv->dev->stats.rx_bytes += len; 5278 count++; 5279 } 5280 5281 if (status & rx_not_ls || skb) { 5282 rx_q->state_saved = true; 5283 rx_q->state.skb = skb; 5284 rx_q->state.error = error; 5285 rx_q->state.len = len; 5286 } 5287 5288 stmmac_finalize_xdp_rx(priv, xdp_status); 5289 5290 stmmac_rx_refill(priv, queue); 5291 5292 priv->xstats.rx_pkt_n += count; 5293 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5294 5295 return count; 5296 } 5297 5298 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5299 { 5300 struct stmmac_channel *ch = 5301 container_of(napi, struct stmmac_channel, rx_napi); 5302 struct stmmac_priv *priv = ch->priv_data; 5303 u32 chan = ch->index; 5304 int work_done; 5305 5306 priv->xstats.napi_poll++; 5307 5308 work_done = stmmac_rx(priv, budget, chan); 5309 if (work_done < budget && napi_complete_done(napi, work_done)) { 5310 unsigned long flags; 5311 5312 spin_lock_irqsave(&ch->lock, flags); 5313 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5314 spin_unlock_irqrestore(&ch->lock, flags); 5315 } 5316 5317 return work_done; 5318 } 5319 5320 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5321 { 5322 struct stmmac_channel *ch = 5323 container_of(napi, struct stmmac_channel, tx_napi); 5324 struct stmmac_priv *priv = ch->priv_data; 5325 u32 chan = ch->index; 5326 int work_done; 5327 5328 priv->xstats.napi_poll++; 5329 5330 work_done = stmmac_tx_clean(priv, budget, chan); 5331 work_done = min(work_done, budget); 5332 5333 if (work_done < budget && napi_complete_done(napi, work_done)) { 5334 unsigned long flags; 5335 5336 spin_lock_irqsave(&ch->lock, flags); 5337 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5338 spin_unlock_irqrestore(&ch->lock, flags); 5339 } 5340 5341 return work_done; 5342 } 5343 5344 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5345 { 5346 struct stmmac_channel *ch = 5347 container_of(napi, struct stmmac_channel, rxtx_napi); 5348 struct stmmac_priv *priv = ch->priv_data; 5349 int rx_done, tx_done, rxtx_done; 5350 u32 chan = ch->index; 5351 5352 priv->xstats.napi_poll++; 5353 5354 tx_done = stmmac_tx_clean(priv, budget, chan); 5355 tx_done = min(tx_done, budget); 5356 5357 rx_done = stmmac_rx_zc(priv, budget, chan); 5358 5359 rxtx_done = max(tx_done, rx_done); 5360 5361 /* If either TX or RX work is not complete, return budget 5362 * and keep pooling 5363 */ 5364 if (rxtx_done >= budget) 5365 return budget; 5366 5367 /* all work done, exit the polling mode */ 5368 if (napi_complete_done(napi, rxtx_done)) { 5369 unsigned long flags; 5370 5371 spin_lock_irqsave(&ch->lock, flags); 5372 /* Both RX and TX work done are compelte, 5373 * so enable both RX & TX IRQs. 5374 */ 5375 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5376 spin_unlock_irqrestore(&ch->lock, flags); 5377 } 5378 5379 return min(rxtx_done, budget - 1); 5380 } 5381 5382 /** 5383 * stmmac_tx_timeout 5384 * @dev : Pointer to net device structure 5385 * @txqueue: the index of the hanging transmit queue 5386 * Description: this function is called when a packet transmission fails to 5387 * complete within a reasonable time. The driver will mark the error in the 5388 * netdev structure and arrange for the device to be reset to a sane state 5389 * in order to transmit a new packet. 5390 */ 5391 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5392 { 5393 struct stmmac_priv *priv = netdev_priv(dev); 5394 5395 stmmac_global_err(priv); 5396 } 5397 5398 /** 5399 * stmmac_set_rx_mode - entry point for multicast addressing 5400 * @dev : pointer to the device structure 5401 * Description: 5402 * This function is a driver entry point which gets called by the kernel 5403 * whenever multicast addresses must be enabled/disabled. 5404 * Return value: 5405 * void. 5406 */ 5407 static void stmmac_set_rx_mode(struct net_device *dev) 5408 { 5409 struct stmmac_priv *priv = netdev_priv(dev); 5410 5411 stmmac_set_filter(priv, priv->hw, dev); 5412 } 5413 5414 /** 5415 * stmmac_change_mtu - entry point to change MTU size for the device. 5416 * @dev : device pointer. 5417 * @new_mtu : the new MTU size for the device. 5418 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5419 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5420 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5421 * Return value: 5422 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5423 * file on failure. 5424 */ 5425 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5426 { 5427 struct stmmac_priv *priv = netdev_priv(dev); 5428 int txfifosz = priv->plat->tx_fifo_size; 5429 const int mtu = new_mtu; 5430 5431 if (txfifosz == 0) 5432 txfifosz = priv->dma_cap.tx_fifo_size; 5433 5434 txfifosz /= priv->plat->tx_queues_to_use; 5435 5436 if (netif_running(dev)) { 5437 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 5438 return -EBUSY; 5439 } 5440 5441 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5442 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5443 return -EINVAL; 5444 } 5445 5446 new_mtu = STMMAC_ALIGN(new_mtu); 5447 5448 /* If condition true, FIFO is too small or MTU too large */ 5449 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5450 return -EINVAL; 5451 5452 dev->mtu = mtu; 5453 5454 netdev_update_features(dev); 5455 5456 return 0; 5457 } 5458 5459 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5460 netdev_features_t features) 5461 { 5462 struct stmmac_priv *priv = netdev_priv(dev); 5463 5464 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5465 features &= ~NETIF_F_RXCSUM; 5466 5467 if (!priv->plat->tx_coe) 5468 features &= ~NETIF_F_CSUM_MASK; 5469 5470 /* Some GMAC devices have a bugged Jumbo frame support that 5471 * needs to have the Tx COE disabled for oversized frames 5472 * (due to limited buffer sizes). In this case we disable 5473 * the TX csum insertion in the TDES and not use SF. 5474 */ 5475 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5476 features &= ~NETIF_F_CSUM_MASK; 5477 5478 /* Disable tso if asked by ethtool */ 5479 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5480 if (features & NETIF_F_TSO) 5481 priv->tso = true; 5482 else 5483 priv->tso = false; 5484 } 5485 5486 return features; 5487 } 5488 5489 static int stmmac_set_features(struct net_device *netdev, 5490 netdev_features_t features) 5491 { 5492 struct stmmac_priv *priv = netdev_priv(netdev); 5493 5494 /* Keep the COE Type in case of csum is supporting */ 5495 if (features & NETIF_F_RXCSUM) 5496 priv->hw->rx_csum = priv->plat->rx_coe; 5497 else 5498 priv->hw->rx_csum = 0; 5499 /* No check needed because rx_coe has been set before and it will be 5500 * fixed in case of issue. 5501 */ 5502 stmmac_rx_ipc(priv, priv->hw); 5503 5504 if (priv->sph_cap) { 5505 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5506 u32 chan; 5507 5508 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5509 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5510 } 5511 5512 return 0; 5513 } 5514 5515 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5516 { 5517 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5518 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5519 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5520 bool *hs_enable = &fpe_cfg->hs_enable; 5521 5522 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5523 return; 5524 5525 /* If LP has sent verify mPacket, LP is FPE capable */ 5526 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5527 if (*lp_state < FPE_STATE_CAPABLE) 5528 *lp_state = FPE_STATE_CAPABLE; 5529 5530 /* If user has requested FPE enable, quickly response */ 5531 if (*hs_enable) 5532 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5533 MPACKET_RESPONSE); 5534 } 5535 5536 /* If Local has sent verify mPacket, Local is FPE capable */ 5537 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5538 if (*lo_state < FPE_STATE_CAPABLE) 5539 *lo_state = FPE_STATE_CAPABLE; 5540 } 5541 5542 /* If LP has sent response mPacket, LP is entering FPE ON */ 5543 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5544 *lp_state = FPE_STATE_ENTERING_ON; 5545 5546 /* If Local has sent response mPacket, Local is entering FPE ON */ 5547 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5548 *lo_state = FPE_STATE_ENTERING_ON; 5549 5550 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5551 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5552 priv->fpe_wq) { 5553 queue_work(priv->fpe_wq, &priv->fpe_task); 5554 } 5555 } 5556 5557 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5558 { 5559 u32 rx_cnt = priv->plat->rx_queues_to_use; 5560 u32 tx_cnt = priv->plat->tx_queues_to_use; 5561 u32 queues_count; 5562 u32 queue; 5563 bool xmac; 5564 5565 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5566 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5567 5568 if (priv->irq_wake) 5569 pm_wakeup_event(priv->device, 0); 5570 5571 if (priv->dma_cap.estsel) 5572 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5573 &priv->xstats, tx_cnt); 5574 5575 if (priv->dma_cap.fpesel) { 5576 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5577 priv->dev); 5578 5579 stmmac_fpe_event_status(priv, status); 5580 } 5581 5582 /* To handle GMAC own interrupts */ 5583 if ((priv->plat->has_gmac) || xmac) { 5584 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5585 5586 if (unlikely(status)) { 5587 /* For LPI we need to save the tx status */ 5588 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5589 priv->tx_path_in_lpi_mode = true; 5590 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5591 priv->tx_path_in_lpi_mode = false; 5592 } 5593 5594 for (queue = 0; queue < queues_count; queue++) { 5595 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5596 queue); 5597 } 5598 5599 /* PCS link status */ 5600 if (priv->hw->pcs) { 5601 if (priv->xstats.pcs_link) 5602 netif_carrier_on(priv->dev); 5603 else 5604 netif_carrier_off(priv->dev); 5605 } 5606 5607 stmmac_timestamp_interrupt(priv, priv); 5608 } 5609 } 5610 5611 /** 5612 * stmmac_interrupt - main ISR 5613 * @irq: interrupt number. 5614 * @dev_id: to pass the net device pointer. 5615 * Description: this is the main driver interrupt service routine. 5616 * It can call: 5617 * o DMA service routine (to manage incoming frame reception and transmission 5618 * status) 5619 * o Core interrupts to manage: remote wake-up, management counter, LPI 5620 * interrupts. 5621 */ 5622 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5623 { 5624 struct net_device *dev = (struct net_device *)dev_id; 5625 struct stmmac_priv *priv = netdev_priv(dev); 5626 5627 /* Check if adapter is up */ 5628 if (test_bit(STMMAC_DOWN, &priv->state)) 5629 return IRQ_HANDLED; 5630 5631 /* Check if a fatal error happened */ 5632 if (stmmac_safety_feat_interrupt(priv)) 5633 return IRQ_HANDLED; 5634 5635 /* To handle Common interrupts */ 5636 stmmac_common_interrupt(priv); 5637 5638 /* To handle DMA interrupts */ 5639 stmmac_dma_interrupt(priv); 5640 5641 return IRQ_HANDLED; 5642 } 5643 5644 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5645 { 5646 struct net_device *dev = (struct net_device *)dev_id; 5647 struct stmmac_priv *priv = netdev_priv(dev); 5648 5649 if (unlikely(!dev)) { 5650 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5651 return IRQ_NONE; 5652 } 5653 5654 /* Check if adapter is up */ 5655 if (test_bit(STMMAC_DOWN, &priv->state)) 5656 return IRQ_HANDLED; 5657 5658 /* To handle Common interrupts */ 5659 stmmac_common_interrupt(priv); 5660 5661 return IRQ_HANDLED; 5662 } 5663 5664 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5665 { 5666 struct net_device *dev = (struct net_device *)dev_id; 5667 struct stmmac_priv *priv = netdev_priv(dev); 5668 5669 if (unlikely(!dev)) { 5670 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5671 return IRQ_NONE; 5672 } 5673 5674 /* Check if adapter is up */ 5675 if (test_bit(STMMAC_DOWN, &priv->state)) 5676 return IRQ_HANDLED; 5677 5678 /* Check if a fatal error happened */ 5679 stmmac_safety_feat_interrupt(priv); 5680 5681 return IRQ_HANDLED; 5682 } 5683 5684 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5685 { 5686 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5687 int chan = tx_q->queue_index; 5688 struct stmmac_priv *priv; 5689 int status; 5690 5691 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); 5692 5693 if (unlikely(!data)) { 5694 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5695 return IRQ_NONE; 5696 } 5697 5698 /* Check if adapter is up */ 5699 if (test_bit(STMMAC_DOWN, &priv->state)) 5700 return IRQ_HANDLED; 5701 5702 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5703 5704 if (unlikely(status & tx_hard_error_bump_tc)) { 5705 /* Try to bump up the dma threshold on this failure */ 5706 stmmac_bump_dma_threshold(priv, chan); 5707 } else if (unlikely(status == tx_hard_error)) { 5708 stmmac_tx_err(priv, chan); 5709 } 5710 5711 return IRQ_HANDLED; 5712 } 5713 5714 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5715 { 5716 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5717 int chan = rx_q->queue_index; 5718 struct stmmac_priv *priv; 5719 5720 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); 5721 5722 if (unlikely(!data)) { 5723 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5724 return IRQ_NONE; 5725 } 5726 5727 /* Check if adapter is up */ 5728 if (test_bit(STMMAC_DOWN, &priv->state)) 5729 return IRQ_HANDLED; 5730 5731 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5732 5733 return IRQ_HANDLED; 5734 } 5735 5736 #ifdef CONFIG_NET_POLL_CONTROLLER 5737 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5738 * to allow network I/O with interrupts disabled. 5739 */ 5740 static void stmmac_poll_controller(struct net_device *dev) 5741 { 5742 struct stmmac_priv *priv = netdev_priv(dev); 5743 int i; 5744 5745 /* If adapter is down, do nothing */ 5746 if (test_bit(STMMAC_DOWN, &priv->state)) 5747 return; 5748 5749 if (priv->plat->multi_msi_en) { 5750 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5751 stmmac_msi_intr_rx(0, &priv->rx_queue[i]); 5752 5753 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5754 stmmac_msi_intr_tx(0, &priv->tx_queue[i]); 5755 } else { 5756 disable_irq(dev->irq); 5757 stmmac_interrupt(dev->irq, dev); 5758 enable_irq(dev->irq); 5759 } 5760 } 5761 #endif 5762 5763 /** 5764 * stmmac_ioctl - Entry point for the Ioctl 5765 * @dev: Device pointer. 5766 * @rq: An IOCTL specefic structure, that can contain a pointer to 5767 * a proprietary structure used to pass information to the driver. 5768 * @cmd: IOCTL command 5769 * Description: 5770 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5771 */ 5772 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5773 { 5774 struct stmmac_priv *priv = netdev_priv (dev); 5775 int ret = -EOPNOTSUPP; 5776 5777 if (!netif_running(dev)) 5778 return -EINVAL; 5779 5780 switch (cmd) { 5781 case SIOCGMIIPHY: 5782 case SIOCGMIIREG: 5783 case SIOCSMIIREG: 5784 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5785 break; 5786 case SIOCSHWTSTAMP: 5787 ret = stmmac_hwtstamp_set(dev, rq); 5788 break; 5789 case SIOCGHWTSTAMP: 5790 ret = stmmac_hwtstamp_get(dev, rq); 5791 break; 5792 default: 5793 break; 5794 } 5795 5796 return ret; 5797 } 5798 5799 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5800 void *cb_priv) 5801 { 5802 struct stmmac_priv *priv = cb_priv; 5803 int ret = -EOPNOTSUPP; 5804 5805 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5806 return ret; 5807 5808 __stmmac_disable_all_queues(priv); 5809 5810 switch (type) { 5811 case TC_SETUP_CLSU32: 5812 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5813 break; 5814 case TC_SETUP_CLSFLOWER: 5815 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5816 break; 5817 default: 5818 break; 5819 } 5820 5821 stmmac_enable_all_queues(priv); 5822 return ret; 5823 } 5824 5825 static LIST_HEAD(stmmac_block_cb_list); 5826 5827 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5828 void *type_data) 5829 { 5830 struct stmmac_priv *priv = netdev_priv(ndev); 5831 5832 switch (type) { 5833 case TC_SETUP_BLOCK: 5834 return flow_block_cb_setup_simple(type_data, 5835 &stmmac_block_cb_list, 5836 stmmac_setup_tc_block_cb, 5837 priv, priv, true); 5838 case TC_SETUP_QDISC_CBS: 5839 return stmmac_tc_setup_cbs(priv, priv, type_data); 5840 case TC_SETUP_QDISC_TAPRIO: 5841 return stmmac_tc_setup_taprio(priv, priv, type_data); 5842 case TC_SETUP_QDISC_ETF: 5843 return stmmac_tc_setup_etf(priv, priv, type_data); 5844 default: 5845 return -EOPNOTSUPP; 5846 } 5847 } 5848 5849 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5850 struct net_device *sb_dev) 5851 { 5852 int gso = skb_shinfo(skb)->gso_type; 5853 5854 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 5855 /* 5856 * There is no way to determine the number of TSO/USO 5857 * capable Queues. Let's use always the Queue 0 5858 * because if TSO/USO is supported then at least this 5859 * one will be capable. 5860 */ 5861 return 0; 5862 } 5863 5864 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 5865 } 5866 5867 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 5868 { 5869 struct stmmac_priv *priv = netdev_priv(ndev); 5870 int ret = 0; 5871 5872 ret = pm_runtime_get_sync(priv->device); 5873 if (ret < 0) { 5874 pm_runtime_put_noidle(priv->device); 5875 return ret; 5876 } 5877 5878 ret = eth_mac_addr(ndev, addr); 5879 if (ret) 5880 goto set_mac_error; 5881 5882 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 5883 5884 set_mac_error: 5885 pm_runtime_put(priv->device); 5886 5887 return ret; 5888 } 5889 5890 #ifdef CONFIG_DEBUG_FS 5891 static struct dentry *stmmac_fs_dir; 5892 5893 static void sysfs_display_ring(void *head, int size, int extend_desc, 5894 struct seq_file *seq, dma_addr_t dma_phy_addr) 5895 { 5896 int i; 5897 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 5898 struct dma_desc *p = (struct dma_desc *)head; 5899 dma_addr_t dma_addr; 5900 5901 for (i = 0; i < size; i++) { 5902 if (extend_desc) { 5903 dma_addr = dma_phy_addr + i * sizeof(*ep); 5904 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5905 i, &dma_addr, 5906 le32_to_cpu(ep->basic.des0), 5907 le32_to_cpu(ep->basic.des1), 5908 le32_to_cpu(ep->basic.des2), 5909 le32_to_cpu(ep->basic.des3)); 5910 ep++; 5911 } else { 5912 dma_addr = dma_phy_addr + i * sizeof(*p); 5913 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5914 i, &dma_addr, 5915 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 5916 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 5917 p++; 5918 } 5919 seq_printf(seq, "\n"); 5920 } 5921 } 5922 5923 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 5924 { 5925 struct net_device *dev = seq->private; 5926 struct stmmac_priv *priv = netdev_priv(dev); 5927 u32 rx_count = priv->plat->rx_queues_to_use; 5928 u32 tx_count = priv->plat->tx_queues_to_use; 5929 u32 queue; 5930 5931 if ((dev->flags & IFF_UP) == 0) 5932 return 0; 5933 5934 for (queue = 0; queue < rx_count; queue++) { 5935 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5936 5937 seq_printf(seq, "RX Queue %d:\n", queue); 5938 5939 if (priv->extend_desc) { 5940 seq_printf(seq, "Extended descriptor ring:\n"); 5941 sysfs_display_ring((void *)rx_q->dma_erx, 5942 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); 5943 } else { 5944 seq_printf(seq, "Descriptor ring:\n"); 5945 sysfs_display_ring((void *)rx_q->dma_rx, 5946 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); 5947 } 5948 } 5949 5950 for (queue = 0; queue < tx_count; queue++) { 5951 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5952 5953 seq_printf(seq, "TX Queue %d:\n", queue); 5954 5955 if (priv->extend_desc) { 5956 seq_printf(seq, "Extended descriptor ring:\n"); 5957 sysfs_display_ring((void *)tx_q->dma_etx, 5958 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); 5959 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 5960 seq_printf(seq, "Descriptor ring:\n"); 5961 sysfs_display_ring((void *)tx_q->dma_tx, 5962 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); 5963 } 5964 } 5965 5966 return 0; 5967 } 5968 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 5969 5970 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 5971 { 5972 struct net_device *dev = seq->private; 5973 struct stmmac_priv *priv = netdev_priv(dev); 5974 5975 if (!priv->hw_cap_support) { 5976 seq_printf(seq, "DMA HW features not supported\n"); 5977 return 0; 5978 } 5979 5980 seq_printf(seq, "==============================\n"); 5981 seq_printf(seq, "\tDMA HW features\n"); 5982 seq_printf(seq, "==============================\n"); 5983 5984 seq_printf(seq, "\t10/100 Mbps: %s\n", 5985 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 5986 seq_printf(seq, "\t1000 Mbps: %s\n", 5987 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 5988 seq_printf(seq, "\tHalf duplex: %s\n", 5989 (priv->dma_cap.half_duplex) ? "Y" : "N"); 5990 seq_printf(seq, "\tHash Filter: %s\n", 5991 (priv->dma_cap.hash_filter) ? "Y" : "N"); 5992 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 5993 (priv->dma_cap.multi_addr) ? "Y" : "N"); 5994 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 5995 (priv->dma_cap.pcs) ? "Y" : "N"); 5996 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 5997 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 5998 seq_printf(seq, "\tPMT Remote wake up: %s\n", 5999 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6000 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6001 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6002 seq_printf(seq, "\tRMON module: %s\n", 6003 (priv->dma_cap.rmon) ? "Y" : "N"); 6004 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6005 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6006 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6007 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6008 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6009 (priv->dma_cap.eee) ? "Y" : "N"); 6010 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6011 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6012 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6013 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6014 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6015 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6016 } else { 6017 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6018 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6019 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6020 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6021 } 6022 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6023 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6024 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6025 priv->dma_cap.number_rx_channel); 6026 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6027 priv->dma_cap.number_tx_channel); 6028 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6029 priv->dma_cap.number_rx_queues); 6030 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6031 priv->dma_cap.number_tx_queues); 6032 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6033 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6034 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6035 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6036 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6037 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6038 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6039 priv->dma_cap.pps_out_num); 6040 seq_printf(seq, "\tSafety Features: %s\n", 6041 priv->dma_cap.asp ? "Y" : "N"); 6042 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6043 priv->dma_cap.frpsel ? "Y" : "N"); 6044 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6045 priv->dma_cap.addr64); 6046 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6047 priv->dma_cap.rssen ? "Y" : "N"); 6048 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6049 priv->dma_cap.vlhash ? "Y" : "N"); 6050 seq_printf(seq, "\tSplit Header: %s\n", 6051 priv->dma_cap.sphen ? "Y" : "N"); 6052 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6053 priv->dma_cap.vlins ? "Y" : "N"); 6054 seq_printf(seq, "\tDouble VLAN: %s\n", 6055 priv->dma_cap.dvlan ? "Y" : "N"); 6056 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6057 priv->dma_cap.l3l4fnum); 6058 seq_printf(seq, "\tARP Offloading: %s\n", 6059 priv->dma_cap.arpoffsel ? "Y" : "N"); 6060 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6061 priv->dma_cap.estsel ? "Y" : "N"); 6062 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6063 priv->dma_cap.fpesel ? "Y" : "N"); 6064 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6065 priv->dma_cap.tbssel ? "Y" : "N"); 6066 return 0; 6067 } 6068 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6069 6070 /* Use network device events to rename debugfs file entries. 6071 */ 6072 static int stmmac_device_event(struct notifier_block *unused, 6073 unsigned long event, void *ptr) 6074 { 6075 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6076 struct stmmac_priv *priv = netdev_priv(dev); 6077 6078 if (dev->netdev_ops != &stmmac_netdev_ops) 6079 goto done; 6080 6081 switch (event) { 6082 case NETDEV_CHANGENAME: 6083 if (priv->dbgfs_dir) 6084 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6085 priv->dbgfs_dir, 6086 stmmac_fs_dir, 6087 dev->name); 6088 break; 6089 } 6090 done: 6091 return NOTIFY_DONE; 6092 } 6093 6094 static struct notifier_block stmmac_notifier = { 6095 .notifier_call = stmmac_device_event, 6096 }; 6097 6098 static void stmmac_init_fs(struct net_device *dev) 6099 { 6100 struct stmmac_priv *priv = netdev_priv(dev); 6101 6102 rtnl_lock(); 6103 6104 /* Create per netdev entries */ 6105 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6106 6107 /* Entry to report DMA RX/TX rings */ 6108 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6109 &stmmac_rings_status_fops); 6110 6111 /* Entry to report the DMA HW features */ 6112 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6113 &stmmac_dma_cap_fops); 6114 6115 rtnl_unlock(); 6116 } 6117 6118 static void stmmac_exit_fs(struct net_device *dev) 6119 { 6120 struct stmmac_priv *priv = netdev_priv(dev); 6121 6122 debugfs_remove_recursive(priv->dbgfs_dir); 6123 } 6124 #endif /* CONFIG_DEBUG_FS */ 6125 6126 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6127 { 6128 unsigned char *data = (unsigned char *)&vid_le; 6129 unsigned char data_byte = 0; 6130 u32 crc = ~0x0; 6131 u32 temp = 0; 6132 int i, bits; 6133 6134 bits = get_bitmask_order(VLAN_VID_MASK); 6135 for (i = 0; i < bits; i++) { 6136 if ((i % 8) == 0) 6137 data_byte = data[i / 8]; 6138 6139 temp = ((crc & 1) ^ data_byte) & 1; 6140 crc >>= 1; 6141 data_byte >>= 1; 6142 6143 if (temp) 6144 crc ^= 0xedb88320; 6145 } 6146 6147 return crc; 6148 } 6149 6150 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6151 { 6152 u32 crc, hash = 0; 6153 __le16 pmatch = 0; 6154 int count = 0; 6155 u16 vid = 0; 6156 6157 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6158 __le16 vid_le = cpu_to_le16(vid); 6159 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6160 hash |= (1 << crc); 6161 count++; 6162 } 6163 6164 if (!priv->dma_cap.vlhash) { 6165 if (count > 2) /* VID = 0 always passes filter */ 6166 return -EOPNOTSUPP; 6167 6168 pmatch = cpu_to_le16(vid); 6169 hash = 0; 6170 } 6171 6172 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6173 } 6174 6175 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6176 { 6177 struct stmmac_priv *priv = netdev_priv(ndev); 6178 bool is_double = false; 6179 int ret; 6180 6181 if (be16_to_cpu(proto) == ETH_P_8021AD) 6182 is_double = true; 6183 6184 set_bit(vid, priv->active_vlans); 6185 ret = stmmac_vlan_update(priv, is_double); 6186 if (ret) { 6187 clear_bit(vid, priv->active_vlans); 6188 return ret; 6189 } 6190 6191 if (priv->hw->num_vlan) { 6192 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6193 if (ret) 6194 return ret; 6195 } 6196 6197 return 0; 6198 } 6199 6200 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6201 { 6202 struct stmmac_priv *priv = netdev_priv(ndev); 6203 bool is_double = false; 6204 int ret; 6205 6206 ret = pm_runtime_get_sync(priv->device); 6207 if (ret < 0) { 6208 pm_runtime_put_noidle(priv->device); 6209 return ret; 6210 } 6211 6212 if (be16_to_cpu(proto) == ETH_P_8021AD) 6213 is_double = true; 6214 6215 clear_bit(vid, priv->active_vlans); 6216 6217 if (priv->hw->num_vlan) { 6218 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6219 if (ret) 6220 goto del_vlan_error; 6221 } 6222 6223 ret = stmmac_vlan_update(priv, is_double); 6224 6225 del_vlan_error: 6226 pm_runtime_put(priv->device); 6227 6228 return ret; 6229 } 6230 6231 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6232 { 6233 struct stmmac_priv *priv = netdev_priv(dev); 6234 6235 switch (bpf->command) { 6236 case XDP_SETUP_PROG: 6237 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6238 case XDP_SETUP_XSK_POOL: 6239 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6240 bpf->xsk.queue_id); 6241 default: 6242 return -EOPNOTSUPP; 6243 } 6244 } 6245 6246 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6247 struct xdp_frame **frames, u32 flags) 6248 { 6249 struct stmmac_priv *priv = netdev_priv(dev); 6250 int cpu = smp_processor_id(); 6251 struct netdev_queue *nq; 6252 int i, nxmit = 0; 6253 int queue; 6254 6255 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6256 return -ENETDOWN; 6257 6258 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6259 return -EINVAL; 6260 6261 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6262 nq = netdev_get_tx_queue(priv->dev, queue); 6263 6264 __netif_tx_lock(nq, cpu); 6265 /* Avoids TX time-out as we are sharing with slow path */ 6266 txq_trans_cond_update(nq); 6267 6268 for (i = 0; i < num_frames; i++) { 6269 int res; 6270 6271 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6272 if (res == STMMAC_XDP_CONSUMED) 6273 break; 6274 6275 nxmit++; 6276 } 6277 6278 if (flags & XDP_XMIT_FLUSH) { 6279 stmmac_flush_tx_descriptors(priv, queue); 6280 stmmac_tx_timer_arm(priv, queue); 6281 } 6282 6283 __netif_tx_unlock(nq); 6284 6285 return nxmit; 6286 } 6287 6288 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6289 { 6290 struct stmmac_channel *ch = &priv->channel[queue]; 6291 unsigned long flags; 6292 6293 spin_lock_irqsave(&ch->lock, flags); 6294 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6295 spin_unlock_irqrestore(&ch->lock, flags); 6296 6297 stmmac_stop_rx_dma(priv, queue); 6298 __free_dma_rx_desc_resources(priv, queue); 6299 } 6300 6301 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6302 { 6303 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 6304 struct stmmac_channel *ch = &priv->channel[queue]; 6305 unsigned long flags; 6306 u32 buf_size; 6307 int ret; 6308 6309 ret = __alloc_dma_rx_desc_resources(priv, queue); 6310 if (ret) { 6311 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6312 return; 6313 } 6314 6315 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); 6316 if (ret) { 6317 __free_dma_rx_desc_resources(priv, queue); 6318 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6319 return; 6320 } 6321 6322 stmmac_clear_rx_descriptors(priv, queue); 6323 6324 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6325 rx_q->dma_rx_phy, rx_q->queue_index); 6326 6327 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6328 sizeof(struct dma_desc)); 6329 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6330 rx_q->rx_tail_addr, rx_q->queue_index); 6331 6332 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6333 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6334 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6335 buf_size, 6336 rx_q->queue_index); 6337 } else { 6338 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6339 priv->dma_buf_sz, 6340 rx_q->queue_index); 6341 } 6342 6343 stmmac_start_rx_dma(priv, queue); 6344 6345 spin_lock_irqsave(&ch->lock, flags); 6346 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6347 spin_unlock_irqrestore(&ch->lock, flags); 6348 } 6349 6350 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6351 { 6352 struct stmmac_channel *ch = &priv->channel[queue]; 6353 unsigned long flags; 6354 6355 spin_lock_irqsave(&ch->lock, flags); 6356 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6357 spin_unlock_irqrestore(&ch->lock, flags); 6358 6359 stmmac_stop_tx_dma(priv, queue); 6360 __free_dma_tx_desc_resources(priv, queue); 6361 } 6362 6363 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6364 { 6365 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 6366 struct stmmac_channel *ch = &priv->channel[queue]; 6367 unsigned long flags; 6368 int ret; 6369 6370 ret = __alloc_dma_tx_desc_resources(priv, queue); 6371 if (ret) { 6372 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6373 return; 6374 } 6375 6376 ret = __init_dma_tx_desc_rings(priv, queue); 6377 if (ret) { 6378 __free_dma_tx_desc_resources(priv, queue); 6379 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6380 return; 6381 } 6382 6383 stmmac_clear_tx_descriptors(priv, queue); 6384 6385 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6386 tx_q->dma_tx_phy, tx_q->queue_index); 6387 6388 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6389 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6390 6391 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6392 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6393 tx_q->tx_tail_addr, tx_q->queue_index); 6394 6395 stmmac_start_tx_dma(priv, queue); 6396 6397 spin_lock_irqsave(&ch->lock, flags); 6398 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6399 spin_unlock_irqrestore(&ch->lock, flags); 6400 } 6401 6402 void stmmac_xdp_release(struct net_device *dev) 6403 { 6404 struct stmmac_priv *priv = netdev_priv(dev); 6405 u32 chan; 6406 6407 /* Disable NAPI process */ 6408 stmmac_disable_all_queues(priv); 6409 6410 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6411 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 6412 6413 /* Free the IRQ lines */ 6414 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6415 6416 /* Stop TX/RX DMA channels */ 6417 stmmac_stop_all_dma(priv); 6418 6419 /* Release and free the Rx/Tx resources */ 6420 free_dma_desc_resources(priv); 6421 6422 /* Disable the MAC Rx/Tx */ 6423 stmmac_mac_set(priv, priv->ioaddr, false); 6424 6425 /* set trans_start so we don't get spurious 6426 * watchdogs during reset 6427 */ 6428 netif_trans_update(dev); 6429 netif_carrier_off(dev); 6430 } 6431 6432 int stmmac_xdp_open(struct net_device *dev) 6433 { 6434 struct stmmac_priv *priv = netdev_priv(dev); 6435 u32 rx_cnt = priv->plat->rx_queues_to_use; 6436 u32 tx_cnt = priv->plat->tx_queues_to_use; 6437 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6438 struct stmmac_rx_queue *rx_q; 6439 struct stmmac_tx_queue *tx_q; 6440 u32 buf_size; 6441 bool sph_en; 6442 u32 chan; 6443 int ret; 6444 6445 ret = alloc_dma_desc_resources(priv); 6446 if (ret < 0) { 6447 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6448 __func__); 6449 goto dma_desc_error; 6450 } 6451 6452 ret = init_dma_desc_rings(dev, GFP_KERNEL); 6453 if (ret < 0) { 6454 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6455 __func__); 6456 goto init_error; 6457 } 6458 6459 /* DMA CSR Channel configuration */ 6460 for (chan = 0; chan < dma_csr_ch; chan++) 6461 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6462 6463 /* Adjust Split header */ 6464 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6465 6466 /* DMA RX Channel Configuration */ 6467 for (chan = 0; chan < rx_cnt; chan++) { 6468 rx_q = &priv->rx_queue[chan]; 6469 6470 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6471 rx_q->dma_rx_phy, chan); 6472 6473 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6474 (rx_q->buf_alloc_num * 6475 sizeof(struct dma_desc)); 6476 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6477 rx_q->rx_tail_addr, chan); 6478 6479 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6480 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6481 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6482 buf_size, 6483 rx_q->queue_index); 6484 } else { 6485 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6486 priv->dma_buf_sz, 6487 rx_q->queue_index); 6488 } 6489 6490 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6491 } 6492 6493 /* DMA TX Channel Configuration */ 6494 for (chan = 0; chan < tx_cnt; chan++) { 6495 tx_q = &priv->tx_queue[chan]; 6496 6497 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6498 tx_q->dma_tx_phy, chan); 6499 6500 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6501 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6502 tx_q->tx_tail_addr, chan); 6503 6504 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6505 tx_q->txtimer.function = stmmac_tx_timer; 6506 } 6507 6508 /* Enable the MAC Rx/Tx */ 6509 stmmac_mac_set(priv, priv->ioaddr, true); 6510 6511 /* Start Rx & Tx DMA Channels */ 6512 stmmac_start_all_dma(priv); 6513 6514 ret = stmmac_request_irq(dev); 6515 if (ret) 6516 goto irq_error; 6517 6518 /* Enable NAPI process*/ 6519 stmmac_enable_all_queues(priv); 6520 netif_carrier_on(dev); 6521 netif_tx_start_all_queues(dev); 6522 6523 return 0; 6524 6525 irq_error: 6526 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6527 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 6528 6529 stmmac_hw_teardown(dev); 6530 init_error: 6531 free_dma_desc_resources(priv); 6532 dma_desc_error: 6533 return ret; 6534 } 6535 6536 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6537 { 6538 struct stmmac_priv *priv = netdev_priv(dev); 6539 struct stmmac_rx_queue *rx_q; 6540 struct stmmac_tx_queue *tx_q; 6541 struct stmmac_channel *ch; 6542 6543 if (test_bit(STMMAC_DOWN, &priv->state) || 6544 !netif_carrier_ok(priv->dev)) 6545 return -ENETDOWN; 6546 6547 if (!stmmac_xdp_is_enabled(priv)) 6548 return -ENXIO; 6549 6550 if (queue >= priv->plat->rx_queues_to_use || 6551 queue >= priv->plat->tx_queues_to_use) 6552 return -EINVAL; 6553 6554 rx_q = &priv->rx_queue[queue]; 6555 tx_q = &priv->tx_queue[queue]; 6556 ch = &priv->channel[queue]; 6557 6558 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6559 return -ENXIO; 6560 6561 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6562 /* EQoS does not have per-DMA channel SW interrupt, 6563 * so we schedule RX Napi straight-away. 6564 */ 6565 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6566 __napi_schedule(&ch->rxtx_napi); 6567 } 6568 6569 return 0; 6570 } 6571 6572 static const struct net_device_ops stmmac_netdev_ops = { 6573 .ndo_open = stmmac_open, 6574 .ndo_start_xmit = stmmac_xmit, 6575 .ndo_stop = stmmac_release, 6576 .ndo_change_mtu = stmmac_change_mtu, 6577 .ndo_fix_features = stmmac_fix_features, 6578 .ndo_set_features = stmmac_set_features, 6579 .ndo_set_rx_mode = stmmac_set_rx_mode, 6580 .ndo_tx_timeout = stmmac_tx_timeout, 6581 .ndo_eth_ioctl = stmmac_ioctl, 6582 .ndo_setup_tc = stmmac_setup_tc, 6583 .ndo_select_queue = stmmac_select_queue, 6584 #ifdef CONFIG_NET_POLL_CONTROLLER 6585 .ndo_poll_controller = stmmac_poll_controller, 6586 #endif 6587 .ndo_set_mac_address = stmmac_set_mac_address, 6588 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6589 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6590 .ndo_bpf = stmmac_bpf, 6591 .ndo_xdp_xmit = stmmac_xdp_xmit, 6592 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6593 }; 6594 6595 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6596 { 6597 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6598 return; 6599 if (test_bit(STMMAC_DOWN, &priv->state)) 6600 return; 6601 6602 netdev_err(priv->dev, "Reset adapter.\n"); 6603 6604 rtnl_lock(); 6605 netif_trans_update(priv->dev); 6606 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6607 usleep_range(1000, 2000); 6608 6609 set_bit(STMMAC_DOWN, &priv->state); 6610 dev_close(priv->dev); 6611 dev_open(priv->dev, NULL); 6612 clear_bit(STMMAC_DOWN, &priv->state); 6613 clear_bit(STMMAC_RESETING, &priv->state); 6614 rtnl_unlock(); 6615 } 6616 6617 static void stmmac_service_task(struct work_struct *work) 6618 { 6619 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6620 service_task); 6621 6622 stmmac_reset_subtask(priv); 6623 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6624 } 6625 6626 /** 6627 * stmmac_hw_init - Init the MAC device 6628 * @priv: driver private structure 6629 * Description: this function is to configure the MAC device according to 6630 * some platform parameters or the HW capability register. It prepares the 6631 * driver to use either ring or chain modes and to setup either enhanced or 6632 * normal descriptors. 6633 */ 6634 static int stmmac_hw_init(struct stmmac_priv *priv) 6635 { 6636 int ret; 6637 6638 /* dwmac-sun8i only work in chain mode */ 6639 if (priv->plat->has_sun8i) 6640 chain_mode = 1; 6641 priv->chain_mode = chain_mode; 6642 6643 /* Initialize HW Interface */ 6644 ret = stmmac_hwif_init(priv); 6645 if (ret) 6646 return ret; 6647 6648 /* Get the HW capability (new GMAC newer than 3.50a) */ 6649 priv->hw_cap_support = stmmac_get_hw_features(priv); 6650 if (priv->hw_cap_support) { 6651 dev_info(priv->device, "DMA HW capability register supported\n"); 6652 6653 /* We can override some gmac/dma configuration fields: e.g. 6654 * enh_desc, tx_coe (e.g. that are passed through the 6655 * platform) with the values from the HW capability 6656 * register (if supported). 6657 */ 6658 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6659 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6660 !priv->plat->use_phy_wol; 6661 priv->hw->pmt = priv->plat->pmt; 6662 if (priv->dma_cap.hash_tb_sz) { 6663 priv->hw->multicast_filter_bins = 6664 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6665 priv->hw->mcast_bits_log2 = 6666 ilog2(priv->hw->multicast_filter_bins); 6667 } 6668 6669 /* TXCOE doesn't work in thresh DMA mode */ 6670 if (priv->plat->force_thresh_dma_mode) 6671 priv->plat->tx_coe = 0; 6672 else 6673 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6674 6675 /* In case of GMAC4 rx_coe is from HW cap register. */ 6676 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6677 6678 if (priv->dma_cap.rx_coe_type2) 6679 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6680 else if (priv->dma_cap.rx_coe_type1) 6681 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6682 6683 } else { 6684 dev_info(priv->device, "No HW DMA feature register supported\n"); 6685 } 6686 6687 if (priv->plat->rx_coe) { 6688 priv->hw->rx_csum = priv->plat->rx_coe; 6689 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6690 if (priv->synopsys_id < DWMAC_CORE_4_00) 6691 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6692 } 6693 if (priv->plat->tx_coe) 6694 dev_info(priv->device, "TX Checksum insertion supported\n"); 6695 6696 if (priv->plat->pmt) { 6697 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6698 device_set_wakeup_capable(priv->device, 1); 6699 } 6700 6701 if (priv->dma_cap.tsoen) 6702 dev_info(priv->device, "TSO supported\n"); 6703 6704 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6705 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6706 6707 /* Run HW quirks, if any */ 6708 if (priv->hwif_quirks) { 6709 ret = priv->hwif_quirks(priv); 6710 if (ret) 6711 return ret; 6712 } 6713 6714 /* Rx Watchdog is available in the COREs newer than the 3.40. 6715 * In some case, for example on bugged HW this feature 6716 * has to be disable and this can be done by passing the 6717 * riwt_off field from the platform. 6718 */ 6719 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6720 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6721 priv->use_riwt = 1; 6722 dev_info(priv->device, 6723 "Enable RX Mitigation via HW Watchdog Timer\n"); 6724 } 6725 6726 return 0; 6727 } 6728 6729 static void stmmac_napi_add(struct net_device *dev) 6730 { 6731 struct stmmac_priv *priv = netdev_priv(dev); 6732 u32 queue, maxq; 6733 6734 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6735 6736 for (queue = 0; queue < maxq; queue++) { 6737 struct stmmac_channel *ch = &priv->channel[queue]; 6738 6739 ch->priv_data = priv; 6740 ch->index = queue; 6741 spin_lock_init(&ch->lock); 6742 6743 if (queue < priv->plat->rx_queues_to_use) { 6744 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 6745 NAPI_POLL_WEIGHT); 6746 } 6747 if (queue < priv->plat->tx_queues_to_use) { 6748 netif_tx_napi_add(dev, &ch->tx_napi, 6749 stmmac_napi_poll_tx, 6750 NAPI_POLL_WEIGHT); 6751 } 6752 if (queue < priv->plat->rx_queues_to_use && 6753 queue < priv->plat->tx_queues_to_use) { 6754 netif_napi_add(dev, &ch->rxtx_napi, 6755 stmmac_napi_poll_rxtx, 6756 NAPI_POLL_WEIGHT); 6757 } 6758 } 6759 } 6760 6761 static void stmmac_napi_del(struct net_device *dev) 6762 { 6763 struct stmmac_priv *priv = netdev_priv(dev); 6764 u32 queue, maxq; 6765 6766 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6767 6768 for (queue = 0; queue < maxq; queue++) { 6769 struct stmmac_channel *ch = &priv->channel[queue]; 6770 6771 if (queue < priv->plat->rx_queues_to_use) 6772 netif_napi_del(&ch->rx_napi); 6773 if (queue < priv->plat->tx_queues_to_use) 6774 netif_napi_del(&ch->tx_napi); 6775 if (queue < priv->plat->rx_queues_to_use && 6776 queue < priv->plat->tx_queues_to_use) { 6777 netif_napi_del(&ch->rxtx_napi); 6778 } 6779 } 6780 } 6781 6782 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6783 { 6784 struct stmmac_priv *priv = netdev_priv(dev); 6785 int ret = 0; 6786 6787 if (netif_running(dev)) 6788 stmmac_release(dev); 6789 6790 stmmac_napi_del(dev); 6791 6792 priv->plat->rx_queues_to_use = rx_cnt; 6793 priv->plat->tx_queues_to_use = tx_cnt; 6794 6795 stmmac_napi_add(dev); 6796 6797 if (netif_running(dev)) 6798 ret = stmmac_open(dev); 6799 6800 return ret; 6801 } 6802 6803 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6804 { 6805 struct stmmac_priv *priv = netdev_priv(dev); 6806 int ret = 0; 6807 6808 if (netif_running(dev)) 6809 stmmac_release(dev); 6810 6811 priv->dma_rx_size = rx_size; 6812 priv->dma_tx_size = tx_size; 6813 6814 if (netif_running(dev)) 6815 ret = stmmac_open(dev); 6816 6817 return ret; 6818 } 6819 6820 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6821 static void stmmac_fpe_lp_task(struct work_struct *work) 6822 { 6823 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6824 fpe_task); 6825 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6826 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6827 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6828 bool *hs_enable = &fpe_cfg->hs_enable; 6829 bool *enable = &fpe_cfg->enable; 6830 int retries = 20; 6831 6832 while (retries-- > 0) { 6833 /* Bail out immediately if FPE handshake is OFF */ 6834 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6835 break; 6836 6837 if (*lo_state == FPE_STATE_ENTERING_ON && 6838 *lp_state == FPE_STATE_ENTERING_ON) { 6839 stmmac_fpe_configure(priv, priv->ioaddr, 6840 priv->plat->tx_queues_to_use, 6841 priv->plat->rx_queues_to_use, 6842 *enable); 6843 6844 netdev_info(priv->dev, "configured FPE\n"); 6845 6846 *lo_state = FPE_STATE_ON; 6847 *lp_state = FPE_STATE_ON; 6848 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6849 break; 6850 } 6851 6852 if ((*lo_state == FPE_STATE_CAPABLE || 6853 *lo_state == FPE_STATE_ENTERING_ON) && 6854 *lp_state != FPE_STATE_ON) { 6855 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 6856 *lo_state, *lp_state); 6857 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6858 MPACKET_VERIFY); 6859 } 6860 /* Sleep then retry */ 6861 msleep(500); 6862 } 6863 6864 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 6865 } 6866 6867 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 6868 { 6869 if (priv->plat->fpe_cfg->hs_enable != enable) { 6870 if (enable) { 6871 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6872 MPACKET_VERIFY); 6873 } else { 6874 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 6875 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 6876 } 6877 6878 priv->plat->fpe_cfg->hs_enable = enable; 6879 } 6880 } 6881 6882 /** 6883 * stmmac_dvr_probe 6884 * @device: device pointer 6885 * @plat_dat: platform data pointer 6886 * @res: stmmac resource pointer 6887 * Description: this is the main probe function used to 6888 * call the alloc_etherdev, allocate the priv structure. 6889 * Return: 6890 * returns 0 on success, otherwise errno. 6891 */ 6892 int stmmac_dvr_probe(struct device *device, 6893 struct plat_stmmacenet_data *plat_dat, 6894 struct stmmac_resources *res) 6895 { 6896 struct net_device *ndev = NULL; 6897 struct stmmac_priv *priv; 6898 u32 rxq; 6899 int i, ret = 0; 6900 6901 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 6902 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 6903 if (!ndev) 6904 return -ENOMEM; 6905 6906 SET_NETDEV_DEV(ndev, device); 6907 6908 priv = netdev_priv(ndev); 6909 priv->device = device; 6910 priv->dev = ndev; 6911 6912 stmmac_set_ethtool_ops(ndev); 6913 priv->pause = pause; 6914 priv->plat = plat_dat; 6915 priv->ioaddr = res->addr; 6916 priv->dev->base_addr = (unsigned long)res->addr; 6917 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 6918 6919 priv->dev->irq = res->irq; 6920 priv->wol_irq = res->wol_irq; 6921 priv->lpi_irq = res->lpi_irq; 6922 priv->sfty_ce_irq = res->sfty_ce_irq; 6923 priv->sfty_ue_irq = res->sfty_ue_irq; 6924 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 6925 priv->rx_irq[i] = res->rx_irq[i]; 6926 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 6927 priv->tx_irq[i] = res->tx_irq[i]; 6928 6929 if (!is_zero_ether_addr(res->mac)) 6930 eth_hw_addr_set(priv->dev, res->mac); 6931 6932 dev_set_drvdata(device, priv->dev); 6933 6934 /* Verify driver arguments */ 6935 stmmac_verify_args(); 6936 6937 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 6938 if (!priv->af_xdp_zc_qps) 6939 return -ENOMEM; 6940 6941 /* Allocate workqueue */ 6942 priv->wq = create_singlethread_workqueue("stmmac_wq"); 6943 if (!priv->wq) { 6944 dev_err(priv->device, "failed to create workqueue\n"); 6945 return -ENOMEM; 6946 } 6947 6948 INIT_WORK(&priv->service_task, stmmac_service_task); 6949 6950 /* Initialize Link Partner FPE workqueue */ 6951 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 6952 6953 /* Override with kernel parameters if supplied XXX CRS XXX 6954 * this needs to have multiple instances 6955 */ 6956 if ((phyaddr >= 0) && (phyaddr <= 31)) 6957 priv->plat->phy_addr = phyaddr; 6958 6959 if (priv->plat->stmmac_rst) { 6960 ret = reset_control_assert(priv->plat->stmmac_rst); 6961 reset_control_deassert(priv->plat->stmmac_rst); 6962 /* Some reset controllers have only reset callback instead of 6963 * assert + deassert callbacks pair. 6964 */ 6965 if (ret == -ENOTSUPP) 6966 reset_control_reset(priv->plat->stmmac_rst); 6967 } 6968 6969 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 6970 if (ret == -ENOTSUPP) 6971 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 6972 ERR_PTR(ret)); 6973 6974 /* Init MAC and get the capabilities */ 6975 ret = stmmac_hw_init(priv); 6976 if (ret) 6977 goto error_hw_init; 6978 6979 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 6980 */ 6981 if (priv->synopsys_id < DWMAC_CORE_5_20) 6982 priv->plat->dma_cfg->dche = false; 6983 6984 stmmac_check_ether_addr(priv); 6985 6986 ndev->netdev_ops = &stmmac_netdev_ops; 6987 6988 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6989 NETIF_F_RXCSUM; 6990 6991 ret = stmmac_tc_init(priv, priv); 6992 if (!ret) { 6993 ndev->hw_features |= NETIF_F_HW_TC; 6994 } 6995 6996 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 6997 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 6998 if (priv->plat->has_gmac4) 6999 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7000 priv->tso = true; 7001 dev_info(priv->device, "TSO feature enabled\n"); 7002 } 7003 7004 if (priv->dma_cap.sphen) { 7005 ndev->hw_features |= NETIF_F_GRO; 7006 priv->sph_cap = true; 7007 priv->sph = priv->sph_cap; 7008 dev_info(priv->device, "SPH feature enabled\n"); 7009 } 7010 7011 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7012 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7013 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7014 * So overwrite dma_cap.addr64 according to HW real design. 7015 */ 7016 if (priv->plat->addr64) 7017 priv->dma_cap.addr64 = priv->plat->addr64; 7018 7019 if (priv->dma_cap.addr64) { 7020 ret = dma_set_mask_and_coherent(device, 7021 DMA_BIT_MASK(priv->dma_cap.addr64)); 7022 if (!ret) { 7023 dev_info(priv->device, "Using %d bits DMA width\n", 7024 priv->dma_cap.addr64); 7025 7026 /* 7027 * If more than 32 bits can be addressed, make sure to 7028 * enable enhanced addressing mode. 7029 */ 7030 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7031 priv->plat->dma_cfg->eame = true; 7032 } else { 7033 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7034 if (ret) { 7035 dev_err(priv->device, "Failed to set DMA Mask\n"); 7036 goto error_hw_init; 7037 } 7038 7039 priv->dma_cap.addr64 = 32; 7040 } 7041 } 7042 7043 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7044 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7045 #ifdef STMMAC_VLAN_TAG_USED 7046 /* Both mac100 and gmac support receive VLAN tag detection */ 7047 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7048 if (priv->dma_cap.vlhash) { 7049 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7050 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7051 } 7052 if (priv->dma_cap.vlins) { 7053 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7054 if (priv->dma_cap.dvlan) 7055 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7056 } 7057 #endif 7058 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7059 7060 /* Initialize RSS */ 7061 rxq = priv->plat->rx_queues_to_use; 7062 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7063 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7064 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7065 7066 if (priv->dma_cap.rssen && priv->plat->rss_en) 7067 ndev->features |= NETIF_F_RXHASH; 7068 7069 /* MTU range: 46 - hw-specific max */ 7070 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7071 if (priv->plat->has_xgmac) 7072 ndev->max_mtu = XGMAC_JUMBO_LEN; 7073 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7074 ndev->max_mtu = JUMBO_LEN; 7075 else 7076 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7077 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7078 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7079 */ 7080 if ((priv->plat->maxmtu < ndev->max_mtu) && 7081 (priv->plat->maxmtu >= ndev->min_mtu)) 7082 ndev->max_mtu = priv->plat->maxmtu; 7083 else if (priv->plat->maxmtu < ndev->min_mtu) 7084 dev_warn(priv->device, 7085 "%s: warning: maxmtu having invalid value (%d)\n", 7086 __func__, priv->plat->maxmtu); 7087 7088 if (flow_ctrl) 7089 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7090 7091 /* Setup channels NAPI */ 7092 stmmac_napi_add(ndev); 7093 7094 mutex_init(&priv->lock); 7095 7096 /* If a specific clk_csr value is passed from the platform 7097 * this means that the CSR Clock Range selection cannot be 7098 * changed at run-time and it is fixed. Viceversa the driver'll try to 7099 * set the MDC clock dynamically according to the csr actual 7100 * clock input. 7101 */ 7102 if (priv->plat->clk_csr >= 0) 7103 priv->clk_csr = priv->plat->clk_csr; 7104 else 7105 stmmac_clk_csr_set(priv); 7106 7107 stmmac_check_pcs_mode(priv); 7108 7109 pm_runtime_get_noresume(device); 7110 pm_runtime_set_active(device); 7111 if (!pm_runtime_enabled(device)) 7112 pm_runtime_enable(device); 7113 7114 if (priv->hw->pcs != STMMAC_PCS_TBI && 7115 priv->hw->pcs != STMMAC_PCS_RTBI) { 7116 /* MDIO bus Registration */ 7117 ret = stmmac_mdio_register(ndev); 7118 if (ret < 0) { 7119 dev_err(priv->device, 7120 "%s: MDIO bus (id: %d) registration failed", 7121 __func__, priv->plat->bus_id); 7122 goto error_mdio_register; 7123 } 7124 } 7125 7126 if (priv->plat->speed_mode_2500) 7127 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7128 7129 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7130 ret = stmmac_xpcs_setup(priv->mii); 7131 if (ret) 7132 goto error_xpcs_setup; 7133 } 7134 7135 ret = stmmac_phy_setup(priv); 7136 if (ret) { 7137 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7138 goto error_phy_setup; 7139 } 7140 7141 ret = register_netdev(ndev); 7142 if (ret) { 7143 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7144 __func__, ret); 7145 goto error_netdev_register; 7146 } 7147 7148 if (priv->plat->serdes_powerup) { 7149 ret = priv->plat->serdes_powerup(ndev, 7150 priv->plat->bsp_priv); 7151 7152 if (ret < 0) 7153 goto error_serdes_powerup; 7154 } 7155 7156 #ifdef CONFIG_DEBUG_FS 7157 stmmac_init_fs(ndev); 7158 #endif 7159 7160 if (priv->plat->dump_debug_regs) 7161 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7162 7163 /* Let pm_runtime_put() disable the clocks. 7164 * If CONFIG_PM is not enabled, the clocks will stay powered. 7165 */ 7166 pm_runtime_put(device); 7167 7168 return ret; 7169 7170 error_serdes_powerup: 7171 unregister_netdev(ndev); 7172 error_netdev_register: 7173 phylink_destroy(priv->phylink); 7174 error_xpcs_setup: 7175 error_phy_setup: 7176 if (priv->hw->pcs != STMMAC_PCS_TBI && 7177 priv->hw->pcs != STMMAC_PCS_RTBI) 7178 stmmac_mdio_unregister(ndev); 7179 error_mdio_register: 7180 stmmac_napi_del(ndev); 7181 error_hw_init: 7182 destroy_workqueue(priv->wq); 7183 bitmap_free(priv->af_xdp_zc_qps); 7184 7185 return ret; 7186 } 7187 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7188 7189 /** 7190 * stmmac_dvr_remove 7191 * @dev: device pointer 7192 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7193 * changes the link status, releases the DMA descriptor rings. 7194 */ 7195 int stmmac_dvr_remove(struct device *dev) 7196 { 7197 struct net_device *ndev = dev_get_drvdata(dev); 7198 struct stmmac_priv *priv = netdev_priv(ndev); 7199 7200 netdev_info(priv->dev, "%s: removing driver", __func__); 7201 7202 stmmac_stop_all_dma(priv); 7203 stmmac_mac_set(priv, priv->ioaddr, false); 7204 netif_carrier_off(ndev); 7205 unregister_netdev(ndev); 7206 7207 /* Serdes power down needs to happen after VLAN filter 7208 * is deleted that is triggered by unregister_netdev(). 7209 */ 7210 if (priv->plat->serdes_powerdown) 7211 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7212 7213 #ifdef CONFIG_DEBUG_FS 7214 stmmac_exit_fs(ndev); 7215 #endif 7216 phylink_destroy(priv->phylink); 7217 if (priv->plat->stmmac_rst) 7218 reset_control_assert(priv->plat->stmmac_rst); 7219 reset_control_assert(priv->plat->stmmac_ahb_rst); 7220 pm_runtime_put(dev); 7221 pm_runtime_disable(dev); 7222 if (priv->hw->pcs != STMMAC_PCS_TBI && 7223 priv->hw->pcs != STMMAC_PCS_RTBI) 7224 stmmac_mdio_unregister(ndev); 7225 destroy_workqueue(priv->wq); 7226 mutex_destroy(&priv->lock); 7227 bitmap_free(priv->af_xdp_zc_qps); 7228 7229 return 0; 7230 } 7231 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7232 7233 /** 7234 * stmmac_suspend - suspend callback 7235 * @dev: device pointer 7236 * Description: this is the function to suspend the device and it is called 7237 * by the platform driver to stop the network queue, release the resources, 7238 * program the PMT register (for WoL), clean and release driver resources. 7239 */ 7240 int stmmac_suspend(struct device *dev) 7241 { 7242 struct net_device *ndev = dev_get_drvdata(dev); 7243 struct stmmac_priv *priv = netdev_priv(ndev); 7244 u32 chan; 7245 7246 if (!ndev || !netif_running(ndev)) 7247 return 0; 7248 7249 mutex_lock(&priv->lock); 7250 7251 netif_device_detach(ndev); 7252 7253 stmmac_disable_all_queues(priv); 7254 7255 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7256 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 7257 7258 if (priv->eee_enabled) { 7259 priv->tx_path_in_lpi_mode = false; 7260 del_timer_sync(&priv->eee_ctrl_timer); 7261 } 7262 7263 /* Stop TX/RX DMA */ 7264 stmmac_stop_all_dma(priv); 7265 7266 if (priv->plat->serdes_powerdown) 7267 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7268 7269 /* Enable Power down mode by programming the PMT regs */ 7270 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7271 stmmac_pmt(priv, priv->hw, priv->wolopts); 7272 priv->irq_wake = 1; 7273 } else { 7274 stmmac_mac_set(priv, priv->ioaddr, false); 7275 pinctrl_pm_select_sleep_state(priv->device); 7276 } 7277 7278 mutex_unlock(&priv->lock); 7279 7280 rtnl_lock(); 7281 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7282 phylink_suspend(priv->phylink, true); 7283 } else { 7284 if (device_may_wakeup(priv->device)) 7285 phylink_speed_down(priv->phylink, false); 7286 phylink_suspend(priv->phylink, false); 7287 } 7288 rtnl_unlock(); 7289 7290 if (priv->dma_cap.fpesel) { 7291 /* Disable FPE */ 7292 stmmac_fpe_configure(priv, priv->ioaddr, 7293 priv->plat->tx_queues_to_use, 7294 priv->plat->rx_queues_to_use, false); 7295 7296 stmmac_fpe_handshake(priv, false); 7297 stmmac_fpe_stop_wq(priv); 7298 } 7299 7300 priv->speed = SPEED_UNKNOWN; 7301 return 0; 7302 } 7303 EXPORT_SYMBOL_GPL(stmmac_suspend); 7304 7305 /** 7306 * stmmac_reset_queues_param - reset queue parameters 7307 * @priv: device pointer 7308 */ 7309 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7310 { 7311 u32 rx_cnt = priv->plat->rx_queues_to_use; 7312 u32 tx_cnt = priv->plat->tx_queues_to_use; 7313 u32 queue; 7314 7315 for (queue = 0; queue < rx_cnt; queue++) { 7316 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 7317 7318 rx_q->cur_rx = 0; 7319 rx_q->dirty_rx = 0; 7320 } 7321 7322 for (queue = 0; queue < tx_cnt; queue++) { 7323 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 7324 7325 tx_q->cur_tx = 0; 7326 tx_q->dirty_tx = 0; 7327 tx_q->mss = 0; 7328 7329 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7330 } 7331 } 7332 7333 /** 7334 * stmmac_resume - resume callback 7335 * @dev: device pointer 7336 * Description: when resume this function is invoked to setup the DMA and CORE 7337 * in a usable state. 7338 */ 7339 int stmmac_resume(struct device *dev) 7340 { 7341 struct net_device *ndev = dev_get_drvdata(dev); 7342 struct stmmac_priv *priv = netdev_priv(ndev); 7343 int ret; 7344 7345 if (!netif_running(ndev)) 7346 return 0; 7347 7348 /* Power Down bit, into the PM register, is cleared 7349 * automatically as soon as a magic packet or a Wake-up frame 7350 * is received. Anyway, it's better to manually clear 7351 * this bit because it can generate problems while resuming 7352 * from another devices (e.g. serial console). 7353 */ 7354 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7355 mutex_lock(&priv->lock); 7356 stmmac_pmt(priv, priv->hw, 0); 7357 mutex_unlock(&priv->lock); 7358 priv->irq_wake = 0; 7359 } else { 7360 pinctrl_pm_select_default_state(priv->device); 7361 /* reset the phy so that it's ready */ 7362 if (priv->mii) 7363 stmmac_mdio_reset(priv->mii); 7364 } 7365 7366 if (priv->plat->serdes_powerup) { 7367 ret = priv->plat->serdes_powerup(ndev, 7368 priv->plat->bsp_priv); 7369 7370 if (ret < 0) 7371 return ret; 7372 } 7373 7374 rtnl_lock(); 7375 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7376 phylink_resume(priv->phylink); 7377 } else { 7378 phylink_resume(priv->phylink); 7379 if (device_may_wakeup(priv->device)) 7380 phylink_speed_up(priv->phylink); 7381 } 7382 rtnl_unlock(); 7383 7384 rtnl_lock(); 7385 mutex_lock(&priv->lock); 7386 7387 stmmac_reset_queues_param(priv); 7388 7389 stmmac_free_tx_skbufs(priv); 7390 stmmac_clear_descriptors(priv); 7391 7392 stmmac_hw_setup(ndev, false); 7393 stmmac_init_coalesce(priv); 7394 stmmac_set_rx_mode(ndev); 7395 7396 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7397 7398 stmmac_enable_all_queues(priv); 7399 7400 mutex_unlock(&priv->lock); 7401 rtnl_unlock(); 7402 7403 netif_device_attach(ndev); 7404 7405 return 0; 7406 } 7407 EXPORT_SYMBOL_GPL(stmmac_resume); 7408 7409 #ifndef MODULE 7410 static int __init stmmac_cmdline_opt(char *str) 7411 { 7412 char *opt; 7413 7414 if (!str || !*str) 7415 return -EINVAL; 7416 while ((opt = strsep(&str, ",")) != NULL) { 7417 if (!strncmp(opt, "debug:", 6)) { 7418 if (kstrtoint(opt + 6, 0, &debug)) 7419 goto err; 7420 } else if (!strncmp(opt, "phyaddr:", 8)) { 7421 if (kstrtoint(opt + 8, 0, &phyaddr)) 7422 goto err; 7423 } else if (!strncmp(opt, "buf_sz:", 7)) { 7424 if (kstrtoint(opt + 7, 0, &buf_sz)) 7425 goto err; 7426 } else if (!strncmp(opt, "tc:", 3)) { 7427 if (kstrtoint(opt + 3, 0, &tc)) 7428 goto err; 7429 } else if (!strncmp(opt, "watchdog:", 9)) { 7430 if (kstrtoint(opt + 9, 0, &watchdog)) 7431 goto err; 7432 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7433 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7434 goto err; 7435 } else if (!strncmp(opt, "pause:", 6)) { 7436 if (kstrtoint(opt + 6, 0, &pause)) 7437 goto err; 7438 } else if (!strncmp(opt, "eee_timer:", 10)) { 7439 if (kstrtoint(opt + 10, 0, &eee_timer)) 7440 goto err; 7441 } else if (!strncmp(opt, "chain_mode:", 11)) { 7442 if (kstrtoint(opt + 11, 0, &chain_mode)) 7443 goto err; 7444 } 7445 } 7446 return 0; 7447 7448 err: 7449 pr_err("%s: ERROR broken module parameter conversion", __func__); 7450 return -EINVAL; 7451 } 7452 7453 __setup("stmmaceth=", stmmac_cmdline_opt); 7454 #endif /* MODULE */ 7455 7456 static int __init stmmac_init(void) 7457 { 7458 #ifdef CONFIG_DEBUG_FS 7459 /* Create debugfs main directory if it doesn't exist yet */ 7460 if (!stmmac_fs_dir) 7461 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7462 register_netdevice_notifier(&stmmac_notifier); 7463 #endif 7464 7465 return 0; 7466 } 7467 7468 static void __exit stmmac_exit(void) 7469 { 7470 #ifdef CONFIG_DEBUG_FS 7471 unregister_netdevice_notifier(&stmmac_notifier); 7472 debugfs_remove_recursive(stmmac_fs_dir); 7473 #endif 7474 } 7475 7476 module_init(stmmac_init) 7477 module_exit(stmmac_exit) 7478 7479 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7480 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7481 MODULE_LICENSE("GPL"); 7482