1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <net/pkt_cls.h> 40 #include "stmmac_ptp.h" 41 #include "stmmac.h" 42 #include <linux/reset.h> 43 #include <linux/of_mdio.h> 44 #include "dwmac1000.h" 45 #include "dwxgmac2.h" 46 #include "hwif.h" 47 48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES) 49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 50 51 /* Module parameters */ 52 #define TX_TIMEO 5000 53 static int watchdog = TX_TIMEO; 54 module_param(watchdog, int, 0644); 55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 56 57 static int debug = -1; 58 module_param(debug, int, 0644); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static int phyaddr = -1; 62 module_param(phyaddr, int, 0444); 63 MODULE_PARM_DESC(phyaddr, "Physical device address"); 64 65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 67 68 static int flow_ctrl = FLOW_AUTO; 69 module_param(flow_ctrl, int, 0644); 70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 71 72 static int pause = PAUSE_TIME; 73 module_param(pause, int, 0644); 74 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 75 76 #define TC_DEFAULT 64 77 static int tc = TC_DEFAULT; 78 module_param(tc, int, 0644); 79 MODULE_PARM_DESC(tc, "DMA threshold control value"); 80 81 #define DEFAULT_BUFSIZE 1536 82 static int buf_sz = DEFAULT_BUFSIZE; 83 module_param(buf_sz, int, 0644); 84 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 85 86 #define STMMAC_RX_COPYBREAK 256 87 88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | 90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 91 92 #define STMMAC_DEFAULT_LPI_TIMER 1000 93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 94 module_param(eee_timer, int, 0644); 95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 97 98 /* By default the driver will use the ring mode to manage tx and rx descriptors, 99 * but allow user to force to use the chain instead of the ring 100 */ 101 static unsigned int chain_mode; 102 module_param(chain_mode, int, 0444); 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 104 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 106 107 #ifdef CONFIG_DEBUG_FS 108 static int stmmac_init_fs(struct net_device *dev); 109 static void stmmac_exit_fs(struct net_device *dev); 110 #endif 111 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 113 114 /** 115 * stmmac_verify_args - verify the driver parameters. 116 * Description: it checks the driver parameters and set a default in case of 117 * errors. 118 */ 119 static void stmmac_verify_args(void) 120 { 121 if (unlikely(watchdog < 0)) 122 watchdog = TX_TIMEO; 123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 124 buf_sz = DEFAULT_BUFSIZE; 125 if (unlikely(flow_ctrl > 1)) 126 flow_ctrl = FLOW_AUTO; 127 else if (likely(flow_ctrl < 0)) 128 flow_ctrl = FLOW_OFF; 129 if (unlikely((pause < 0) || (pause > 0xffff))) 130 pause = PAUSE_TIME; 131 if (eee_timer < 0) 132 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 133 } 134 135 /** 136 * stmmac_disable_all_queues - Disable all queues 137 * @priv: driver private structure 138 */ 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 140 { 141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 144 u32 queue; 145 146 for (queue = 0; queue < maxq; queue++) { 147 struct stmmac_channel *ch = &priv->channel[queue]; 148 149 if (queue < rx_queues_cnt) 150 napi_disable(&ch->rx_napi); 151 if (queue < tx_queues_cnt) 152 napi_disable(&ch->tx_napi); 153 } 154 } 155 156 /** 157 * stmmac_enable_all_queues - Enable all queues 158 * @priv: driver private structure 159 */ 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 161 { 162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 165 u32 queue; 166 167 for (queue = 0; queue < maxq; queue++) { 168 struct stmmac_channel *ch = &priv->channel[queue]; 169 170 if (queue < rx_queues_cnt) 171 napi_enable(&ch->rx_napi); 172 if (queue < tx_queues_cnt) 173 napi_enable(&ch->tx_napi); 174 } 175 } 176 177 /** 178 * stmmac_stop_all_queues - Stop all queues 179 * @priv: driver private structure 180 */ 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 182 { 183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 184 u32 queue; 185 186 for (queue = 0; queue < tx_queues_cnt; queue++) 187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 188 } 189 190 /** 191 * stmmac_start_all_queues - Start all queues 192 * @priv: driver private structure 193 */ 194 static void stmmac_start_all_queues(struct stmmac_priv *priv) 195 { 196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 197 u32 queue; 198 199 for (queue = 0; queue < tx_queues_cnt; queue++) 200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 201 } 202 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 204 { 205 if (!test_bit(STMMAC_DOWN, &priv->state) && 206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 207 queue_work(priv->wq, &priv->service_task); 208 } 209 210 static void stmmac_global_err(struct stmmac_priv *priv) 211 { 212 netif_carrier_off(priv->dev); 213 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 214 stmmac_service_event_schedule(priv); 215 } 216 217 /** 218 * stmmac_clk_csr_set - dynamically set the MDC clock 219 * @priv: driver private structure 220 * Description: this is to dynamically set the MDC clock according to the csr 221 * clock input. 222 * Note: 223 * If a specific clk_csr value is passed from the platform 224 * this means that the CSR Clock Range selection cannot be 225 * changed at run-time and it is fixed (as reported in the driver 226 * documentation). Viceversa the driver will try to set the MDC 227 * clock dynamically according to the actual clock input. 228 */ 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 230 { 231 u32 clk_rate; 232 233 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 234 235 /* Platform provided default clk_csr would be assumed valid 236 * for all other cases except for the below mentioned ones. 237 * For values higher than the IEEE 802.3 specified frequency 238 * we can not estimate the proper divider as it is not known 239 * the frequency of clk_csr_i. So we do not change the default 240 * divider. 241 */ 242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 243 if (clk_rate < CSR_F_35M) 244 priv->clk_csr = STMMAC_CSR_20_35M; 245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 246 priv->clk_csr = STMMAC_CSR_35_60M; 247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 248 priv->clk_csr = STMMAC_CSR_60_100M; 249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 250 priv->clk_csr = STMMAC_CSR_100_150M; 251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 252 priv->clk_csr = STMMAC_CSR_150_250M; 253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 254 priv->clk_csr = STMMAC_CSR_250_300M; 255 } 256 257 if (priv->plat->has_sun8i) { 258 if (clk_rate > 160000000) 259 priv->clk_csr = 0x03; 260 else if (clk_rate > 80000000) 261 priv->clk_csr = 0x02; 262 else if (clk_rate > 40000000) 263 priv->clk_csr = 0x01; 264 else 265 priv->clk_csr = 0; 266 } 267 268 if (priv->plat->has_xgmac) { 269 if (clk_rate > 400000000) 270 priv->clk_csr = 0x5; 271 else if (clk_rate > 350000000) 272 priv->clk_csr = 0x4; 273 else if (clk_rate > 300000000) 274 priv->clk_csr = 0x3; 275 else if (clk_rate > 250000000) 276 priv->clk_csr = 0x2; 277 else if (clk_rate > 150000000) 278 priv->clk_csr = 0x1; 279 else 280 priv->clk_csr = 0x0; 281 } 282 } 283 284 static void print_pkt(unsigned char *buf, int len) 285 { 286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 288 } 289 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 291 { 292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 293 u32 avail; 294 295 if (tx_q->dirty_tx > tx_q->cur_tx) 296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 297 else 298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 299 300 return avail; 301 } 302 303 /** 304 * stmmac_rx_dirty - Get RX queue dirty 305 * @priv: driver private structure 306 * @queue: RX queue index 307 */ 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 309 { 310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 311 u32 dirty; 312 313 if (rx_q->dirty_rx <= rx_q->cur_rx) 314 dirty = rx_q->cur_rx - rx_q->dirty_rx; 315 else 316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 317 318 return dirty; 319 } 320 321 /** 322 * stmmac_enable_eee_mode - check and enter in LPI mode 323 * @priv: driver private structure 324 * Description: this function is to verify and enter in LPI mode in case of 325 * EEE. 326 */ 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 328 { 329 u32 tx_cnt = priv->plat->tx_queues_to_use; 330 u32 queue; 331 332 /* check if all TX queues have the work finished */ 333 for (queue = 0; queue < tx_cnt; queue++) { 334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 335 336 if (tx_q->dirty_tx != tx_q->cur_tx) 337 return; /* still unfinished work */ 338 } 339 340 /* Check and enter in LPI mode */ 341 if (!priv->tx_path_in_lpi_mode) 342 stmmac_set_eee_mode(priv, priv->hw, 343 priv->plat->en_tx_lpi_clockgating); 344 } 345 346 /** 347 * stmmac_disable_eee_mode - disable and exit from LPI mode 348 * @priv: driver private structure 349 * Description: this function is to exit and disable EEE in case of 350 * LPI state is true. This is called by the xmit. 351 */ 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 353 { 354 stmmac_reset_eee_mode(priv, priv->hw); 355 del_timer_sync(&priv->eee_ctrl_timer); 356 priv->tx_path_in_lpi_mode = false; 357 } 358 359 /** 360 * stmmac_eee_ctrl_timer - EEE TX SW timer. 361 * @arg : data hook 362 * Description: 363 * if there is no data transfer and if we are not in LPI state, 364 * then MAC Transmitter can be moved to LPI state. 365 */ 366 static void stmmac_eee_ctrl_timer(struct timer_list *t) 367 { 368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 369 370 stmmac_enable_eee_mode(priv); 371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 372 } 373 374 /** 375 * stmmac_eee_init - init EEE 376 * @priv: driver private structure 377 * Description: 378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 379 * can also manage EEE, this function enable the LPI state and start related 380 * timer. 381 */ 382 bool stmmac_eee_init(struct stmmac_priv *priv) 383 { 384 int tx_lpi_timer = priv->tx_lpi_timer; 385 386 /* Using PCS we cannot dial with the phy registers at this stage 387 * so we do not support extra feature like EEE. 388 */ 389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 390 (priv->hw->pcs == STMMAC_PCS_TBI) || 391 (priv->hw->pcs == STMMAC_PCS_RTBI)) 392 return false; 393 394 /* Check if MAC core supports the EEE feature. */ 395 if (!priv->dma_cap.eee) 396 return false; 397 398 mutex_lock(&priv->lock); 399 400 /* Check if it needs to be deactivated */ 401 if (!priv->eee_active && priv->eee_enabled) { 402 netdev_dbg(priv->dev, "disable EEE\n"); 403 del_timer_sync(&priv->eee_ctrl_timer); 404 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 405 return false; 406 } 407 408 if (priv->eee_active && !priv->eee_enabled) { 409 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 410 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 411 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 412 tx_lpi_timer); 413 } 414 415 mutex_unlock(&priv->lock); 416 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 417 return true; 418 } 419 420 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 421 * @priv: driver private structure 422 * @p : descriptor pointer 423 * @skb : the socket buffer 424 * Description : 425 * This function will read timestamp from the descriptor & pass it to stack. 426 * and also perform some sanity checks. 427 */ 428 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 429 struct dma_desc *p, struct sk_buff *skb) 430 { 431 struct skb_shared_hwtstamps shhwtstamp; 432 u64 ns = 0; 433 434 if (!priv->hwts_tx_en) 435 return; 436 437 /* exit if skb doesn't support hw tstamp */ 438 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 439 return; 440 441 /* check tx tstamp status */ 442 if (stmmac_get_tx_timestamp_status(priv, p)) { 443 /* get the valid tstamp */ 444 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 445 446 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 447 shhwtstamp.hwtstamp = ns_to_ktime(ns); 448 449 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 450 /* pass tstamp to stack */ 451 skb_tstamp_tx(skb, &shhwtstamp); 452 } 453 454 return; 455 } 456 457 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 458 * @priv: driver private structure 459 * @p : descriptor pointer 460 * @np : next descriptor pointer 461 * @skb : the socket buffer 462 * Description : 463 * This function will read received packet's timestamp from the descriptor 464 * and pass it to stack. It also perform some sanity checks. 465 */ 466 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 467 struct dma_desc *np, struct sk_buff *skb) 468 { 469 struct skb_shared_hwtstamps *shhwtstamp = NULL; 470 struct dma_desc *desc = p; 471 u64 ns = 0; 472 473 if (!priv->hwts_rx_en) 474 return; 475 /* For GMAC4, the valid timestamp is from CTX next desc. */ 476 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 477 desc = np; 478 479 /* Check if timestamp is available */ 480 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 481 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 482 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 483 shhwtstamp = skb_hwtstamps(skb); 484 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 485 shhwtstamp->hwtstamp = ns_to_ktime(ns); 486 } else { 487 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 488 } 489 } 490 491 /** 492 * stmmac_hwtstamp_set - control hardware timestamping. 493 * @dev: device pointer. 494 * @ifr: An IOCTL specific structure, that can contain a pointer to 495 * a proprietary structure used to pass information to the driver. 496 * Description: 497 * This function configures the MAC to enable/disable both outgoing(TX) 498 * and incoming(RX) packets time stamping based on user input. 499 * Return Value: 500 * 0 on success and an appropriate -ve integer on failure. 501 */ 502 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 503 { 504 struct stmmac_priv *priv = netdev_priv(dev); 505 struct hwtstamp_config config; 506 struct timespec64 now; 507 u64 temp = 0; 508 u32 ptp_v2 = 0; 509 u32 tstamp_all = 0; 510 u32 ptp_over_ipv4_udp = 0; 511 u32 ptp_over_ipv6_udp = 0; 512 u32 ptp_over_ethernet = 0; 513 u32 snap_type_sel = 0; 514 u32 ts_master_en = 0; 515 u32 ts_event_en = 0; 516 u32 sec_inc = 0; 517 u32 value = 0; 518 bool xmac; 519 520 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 521 522 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 523 netdev_alert(priv->dev, "No support for HW time stamping\n"); 524 priv->hwts_tx_en = 0; 525 priv->hwts_rx_en = 0; 526 527 return -EOPNOTSUPP; 528 } 529 530 if (copy_from_user(&config, ifr->ifr_data, 531 sizeof(config))) 532 return -EFAULT; 533 534 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 535 __func__, config.flags, config.tx_type, config.rx_filter); 536 537 /* reserved for future extensions */ 538 if (config.flags) 539 return -EINVAL; 540 541 if (config.tx_type != HWTSTAMP_TX_OFF && 542 config.tx_type != HWTSTAMP_TX_ON) 543 return -ERANGE; 544 545 if (priv->adv_ts) { 546 switch (config.rx_filter) { 547 case HWTSTAMP_FILTER_NONE: 548 /* time stamp no incoming packet at all */ 549 config.rx_filter = HWTSTAMP_FILTER_NONE; 550 break; 551 552 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 553 /* PTP v1, UDP, any kind of event packet */ 554 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 555 /* 'xmac' hardware can support Sync, Pdelay_Req and 556 * Pdelay_resp by setting bit14 and bits17/16 to 01 557 * This leaves Delay_Req timestamps out. 558 * Enable all events *and* general purpose message 559 * timestamping 560 */ 561 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 562 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 563 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 564 break; 565 566 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 567 /* PTP v1, UDP, Sync packet */ 568 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 569 /* take time stamp for SYNC messages only */ 570 ts_event_en = PTP_TCR_TSEVNTENA; 571 572 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 573 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 574 break; 575 576 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 577 /* PTP v1, UDP, Delay_req packet */ 578 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 579 /* take time stamp for Delay_Req messages only */ 580 ts_master_en = PTP_TCR_TSMSTRENA; 581 ts_event_en = PTP_TCR_TSEVNTENA; 582 583 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 584 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 585 break; 586 587 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 588 /* PTP v2, UDP, any kind of event packet */ 589 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 590 ptp_v2 = PTP_TCR_TSVER2ENA; 591 /* take time stamp for all event messages */ 592 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 593 594 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 595 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 596 break; 597 598 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 599 /* PTP v2, UDP, Sync packet */ 600 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 601 ptp_v2 = PTP_TCR_TSVER2ENA; 602 /* take time stamp for SYNC messages only */ 603 ts_event_en = PTP_TCR_TSEVNTENA; 604 605 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 606 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 607 break; 608 609 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 610 /* PTP v2, UDP, Delay_req packet */ 611 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 612 ptp_v2 = PTP_TCR_TSVER2ENA; 613 /* take time stamp for Delay_Req messages only */ 614 ts_master_en = PTP_TCR_TSMSTRENA; 615 ts_event_en = PTP_TCR_TSEVNTENA; 616 617 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 618 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 619 break; 620 621 case HWTSTAMP_FILTER_PTP_V2_EVENT: 622 /* PTP v2/802.AS1 any layer, any kind of event packet */ 623 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 624 ptp_v2 = PTP_TCR_TSVER2ENA; 625 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 626 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 627 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 628 ptp_over_ethernet = PTP_TCR_TSIPENA; 629 break; 630 631 case HWTSTAMP_FILTER_PTP_V2_SYNC: 632 /* PTP v2/802.AS1, any layer, Sync packet */ 633 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 634 ptp_v2 = PTP_TCR_TSVER2ENA; 635 /* take time stamp for SYNC messages only */ 636 ts_event_en = PTP_TCR_TSEVNTENA; 637 638 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 639 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 640 ptp_over_ethernet = PTP_TCR_TSIPENA; 641 break; 642 643 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 644 /* PTP v2/802.AS1, any layer, Delay_req packet */ 645 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 646 ptp_v2 = PTP_TCR_TSVER2ENA; 647 /* take time stamp for Delay_Req messages only */ 648 ts_master_en = PTP_TCR_TSMSTRENA; 649 ts_event_en = PTP_TCR_TSEVNTENA; 650 651 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 652 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 653 ptp_over_ethernet = PTP_TCR_TSIPENA; 654 break; 655 656 case HWTSTAMP_FILTER_NTP_ALL: 657 case HWTSTAMP_FILTER_ALL: 658 /* time stamp any incoming packet */ 659 config.rx_filter = HWTSTAMP_FILTER_ALL; 660 tstamp_all = PTP_TCR_TSENALL; 661 break; 662 663 default: 664 return -ERANGE; 665 } 666 } else { 667 switch (config.rx_filter) { 668 case HWTSTAMP_FILTER_NONE: 669 config.rx_filter = HWTSTAMP_FILTER_NONE; 670 break; 671 default: 672 /* PTP v1, UDP, any kind of event packet */ 673 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 674 break; 675 } 676 } 677 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 678 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 679 680 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 681 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 682 else { 683 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 684 tstamp_all | ptp_v2 | ptp_over_ethernet | 685 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 686 ts_master_en | snap_type_sel); 687 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 688 689 /* program Sub Second Increment reg */ 690 stmmac_config_sub_second_increment(priv, 691 priv->ptpaddr, priv->plat->clk_ptp_rate, 692 xmac, &sec_inc); 693 temp = div_u64(1000000000ULL, sec_inc); 694 695 /* Store sub second increment and flags for later use */ 696 priv->sub_second_inc = sec_inc; 697 priv->systime_flags = value; 698 699 /* calculate default added value: 700 * formula is : 701 * addend = (2^32)/freq_div_ratio; 702 * where, freq_div_ratio = 1e9ns/sec_inc 703 */ 704 temp = (u64)(temp << 32); 705 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 706 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 707 708 /* initialize system time */ 709 ktime_get_real_ts64(&now); 710 711 /* lower 32 bits of tv_sec are safe until y2106 */ 712 stmmac_init_systime(priv, priv->ptpaddr, 713 (u32)now.tv_sec, now.tv_nsec); 714 } 715 716 memcpy(&priv->tstamp_config, &config, sizeof(config)); 717 718 return copy_to_user(ifr->ifr_data, &config, 719 sizeof(config)) ? -EFAULT : 0; 720 } 721 722 /** 723 * stmmac_hwtstamp_get - read hardware timestamping. 724 * @dev: device pointer. 725 * @ifr: An IOCTL specific structure, that can contain a pointer to 726 * a proprietary structure used to pass information to the driver. 727 * Description: 728 * This function obtain the current hardware timestamping settings 729 as requested. 730 */ 731 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 732 { 733 struct stmmac_priv *priv = netdev_priv(dev); 734 struct hwtstamp_config *config = &priv->tstamp_config; 735 736 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 737 return -EOPNOTSUPP; 738 739 return copy_to_user(ifr->ifr_data, config, 740 sizeof(*config)) ? -EFAULT : 0; 741 } 742 743 /** 744 * stmmac_init_ptp - init PTP 745 * @priv: driver private structure 746 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 747 * This is done by looking at the HW cap. register. 748 * This function also registers the ptp driver. 749 */ 750 static int stmmac_init_ptp(struct stmmac_priv *priv) 751 { 752 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 753 754 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 755 return -EOPNOTSUPP; 756 757 priv->adv_ts = 0; 758 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 759 if (xmac && priv->dma_cap.atime_stamp) 760 priv->adv_ts = 1; 761 /* Dwmac 3.x core with extend_desc can support adv_ts */ 762 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 763 priv->adv_ts = 1; 764 765 if (priv->dma_cap.time_stamp) 766 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 767 768 if (priv->adv_ts) 769 netdev_info(priv->dev, 770 "IEEE 1588-2008 Advanced Timestamp supported\n"); 771 772 priv->hwts_tx_en = 0; 773 priv->hwts_rx_en = 0; 774 775 stmmac_ptp_register(priv); 776 777 return 0; 778 } 779 780 static void stmmac_release_ptp(struct stmmac_priv *priv) 781 { 782 if (priv->plat->clk_ptp_ref) 783 clk_disable_unprepare(priv->plat->clk_ptp_ref); 784 stmmac_ptp_unregister(priv); 785 } 786 787 /** 788 * stmmac_mac_flow_ctrl - Configure flow control in all queues 789 * @priv: driver private structure 790 * Description: It is used for configuring the flow control in all queues 791 */ 792 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 793 { 794 u32 tx_cnt = priv->plat->tx_queues_to_use; 795 796 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 797 priv->pause, tx_cnt); 798 } 799 800 static void stmmac_validate(struct phylink_config *config, 801 unsigned long *supported, 802 struct phylink_link_state *state) 803 { 804 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 805 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 806 int tx_cnt = priv->plat->tx_queues_to_use; 807 int max_speed = priv->plat->max_speed; 808 809 /* Cut down 1G if asked to */ 810 if ((max_speed > 0) && (max_speed < 1000)) { 811 phylink_set(mask, 1000baseT_Full); 812 phylink_set(mask, 1000baseX_Full); 813 } 814 815 /* Half-Duplex can only work with single queue */ 816 if (tx_cnt > 1) { 817 phylink_set(mask, 10baseT_Half); 818 phylink_set(mask, 100baseT_Half); 819 phylink_set(mask, 1000baseT_Half); 820 } 821 822 bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 823 bitmap_andnot(state->advertising, state->advertising, mask, 824 __ETHTOOL_LINK_MODE_MASK_NBITS); 825 } 826 827 static int stmmac_mac_link_state(struct phylink_config *config, 828 struct phylink_link_state *state) 829 { 830 return -EOPNOTSUPP; 831 } 832 833 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 834 const struct phylink_link_state *state) 835 { 836 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 837 u32 ctrl; 838 839 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 840 ctrl &= ~priv->hw->link.speed_mask; 841 842 switch (state->speed) { 843 case SPEED_1000: 844 ctrl |= priv->hw->link.speed1000; 845 break; 846 case SPEED_100: 847 ctrl |= priv->hw->link.speed100; 848 break; 849 case SPEED_10: 850 ctrl |= priv->hw->link.speed10; 851 break; 852 default: 853 return; 854 } 855 856 priv->speed = state->speed; 857 858 if (priv->plat->fix_mac_speed) 859 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); 860 861 if (!state->duplex) 862 ctrl &= ~priv->hw->link.duplex; 863 else 864 ctrl |= priv->hw->link.duplex; 865 866 /* Flow Control operation */ 867 if (state->pause) 868 stmmac_mac_flow_ctrl(priv, state->duplex); 869 870 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 871 } 872 873 static void stmmac_mac_an_restart(struct phylink_config *config) 874 { 875 /* Not Supported */ 876 } 877 878 static void stmmac_mac_link_down(struct phylink_config *config, 879 unsigned int mode, phy_interface_t interface) 880 { 881 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 882 883 stmmac_mac_set(priv, priv->ioaddr, false); 884 priv->eee_active = false; 885 stmmac_eee_init(priv); 886 stmmac_set_eee_pls(priv, priv->hw, false); 887 } 888 889 static void stmmac_mac_link_up(struct phylink_config *config, 890 unsigned int mode, phy_interface_t interface, 891 struct phy_device *phy) 892 { 893 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 894 895 stmmac_mac_set(priv, priv->ioaddr, true); 896 if (phy) { 897 priv->eee_active = phy_init_eee(phy, 1) >= 0; 898 priv->eee_enabled = stmmac_eee_init(priv); 899 stmmac_set_eee_pls(priv, priv->hw, true); 900 } 901 } 902 903 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 904 .validate = stmmac_validate, 905 .mac_link_state = stmmac_mac_link_state, 906 .mac_config = stmmac_mac_config, 907 .mac_an_restart = stmmac_mac_an_restart, 908 .mac_link_down = stmmac_mac_link_down, 909 .mac_link_up = stmmac_mac_link_up, 910 }; 911 912 /** 913 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 914 * @priv: driver private structure 915 * Description: this is to verify if the HW supports the PCS. 916 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 917 * configured for the TBI, RTBI, or SGMII PHY interface. 918 */ 919 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 920 { 921 int interface = priv->plat->interface; 922 923 if (priv->dma_cap.pcs) { 924 if ((interface == PHY_INTERFACE_MODE_RGMII) || 925 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 926 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 927 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 928 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 929 priv->hw->pcs = STMMAC_PCS_RGMII; 930 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 931 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 932 priv->hw->pcs = STMMAC_PCS_SGMII; 933 } 934 } 935 } 936 937 /** 938 * stmmac_init_phy - PHY initialization 939 * @dev: net device structure 940 * Description: it initializes the driver's PHY state, and attaches the PHY 941 * to the mac driver. 942 * Return value: 943 * 0 on success 944 */ 945 static int stmmac_init_phy(struct net_device *dev) 946 { 947 struct stmmac_priv *priv = netdev_priv(dev); 948 struct device_node *node; 949 int ret; 950 951 node = priv->plat->phylink_node; 952 953 if (node) { 954 ret = phylink_of_phy_connect(priv->phylink, node, 0); 955 } else { 956 int addr = priv->plat->phy_addr; 957 struct phy_device *phydev; 958 959 phydev = mdiobus_get_phy(priv->mii, addr); 960 if (!phydev) { 961 netdev_err(priv->dev, "no phy at addr %d\n", addr); 962 return -ENODEV; 963 } 964 965 ret = phylink_connect_phy(priv->phylink, phydev); 966 } 967 968 return ret; 969 } 970 971 static int stmmac_phy_setup(struct stmmac_priv *priv) 972 { 973 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 974 int mode = priv->plat->interface; 975 struct phylink *phylink; 976 977 priv->phylink_config.dev = &priv->dev->dev; 978 priv->phylink_config.type = PHYLINK_NETDEV; 979 980 phylink = phylink_create(&priv->phylink_config, fwnode, 981 mode, &stmmac_phylink_mac_ops); 982 if (IS_ERR(phylink)) 983 return PTR_ERR(phylink); 984 985 priv->phylink = phylink; 986 return 0; 987 } 988 989 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 990 { 991 u32 rx_cnt = priv->plat->rx_queues_to_use; 992 void *head_rx; 993 u32 queue; 994 995 /* Display RX rings */ 996 for (queue = 0; queue < rx_cnt; queue++) { 997 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 998 999 pr_info("\tRX Queue %u rings\n", queue); 1000 1001 if (priv->extend_desc) 1002 head_rx = (void *)rx_q->dma_erx; 1003 else 1004 head_rx = (void *)rx_q->dma_rx; 1005 1006 /* Display RX ring */ 1007 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1008 } 1009 } 1010 1011 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1012 { 1013 u32 tx_cnt = priv->plat->tx_queues_to_use; 1014 void *head_tx; 1015 u32 queue; 1016 1017 /* Display TX rings */ 1018 for (queue = 0; queue < tx_cnt; queue++) { 1019 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1020 1021 pr_info("\tTX Queue %d rings\n", queue); 1022 1023 if (priv->extend_desc) 1024 head_tx = (void *)tx_q->dma_etx; 1025 else 1026 head_tx = (void *)tx_q->dma_tx; 1027 1028 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1029 } 1030 } 1031 1032 static void stmmac_display_rings(struct stmmac_priv *priv) 1033 { 1034 /* Display RX ring */ 1035 stmmac_display_rx_rings(priv); 1036 1037 /* Display TX ring */ 1038 stmmac_display_tx_rings(priv); 1039 } 1040 1041 static int stmmac_set_bfsize(int mtu, int bufsize) 1042 { 1043 int ret = bufsize; 1044 1045 if (mtu >= BUF_SIZE_4KiB) 1046 ret = BUF_SIZE_8KiB; 1047 else if (mtu >= BUF_SIZE_2KiB) 1048 ret = BUF_SIZE_4KiB; 1049 else if (mtu > DEFAULT_BUFSIZE) 1050 ret = BUF_SIZE_2KiB; 1051 else 1052 ret = DEFAULT_BUFSIZE; 1053 1054 return ret; 1055 } 1056 1057 /** 1058 * stmmac_clear_rx_descriptors - clear RX descriptors 1059 * @priv: driver private structure 1060 * @queue: RX queue index 1061 * Description: this function is called to clear the RX descriptors 1062 * in case of both basic and extended descriptors are used. 1063 */ 1064 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1065 { 1066 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1067 int i; 1068 1069 /* Clear the RX descriptors */ 1070 for (i = 0; i < DMA_RX_SIZE; i++) 1071 if (priv->extend_desc) 1072 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1073 priv->use_riwt, priv->mode, 1074 (i == DMA_RX_SIZE - 1), 1075 priv->dma_buf_sz); 1076 else 1077 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1078 priv->use_riwt, priv->mode, 1079 (i == DMA_RX_SIZE - 1), 1080 priv->dma_buf_sz); 1081 } 1082 1083 /** 1084 * stmmac_clear_tx_descriptors - clear tx descriptors 1085 * @priv: driver private structure 1086 * @queue: TX queue index. 1087 * Description: this function is called to clear the TX descriptors 1088 * in case of both basic and extended descriptors are used. 1089 */ 1090 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1091 { 1092 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1093 int i; 1094 1095 /* Clear the TX descriptors */ 1096 for (i = 0; i < DMA_TX_SIZE; i++) 1097 if (priv->extend_desc) 1098 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1099 priv->mode, (i == DMA_TX_SIZE - 1)); 1100 else 1101 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1102 priv->mode, (i == DMA_TX_SIZE - 1)); 1103 } 1104 1105 /** 1106 * stmmac_clear_descriptors - clear descriptors 1107 * @priv: driver private structure 1108 * Description: this function is called to clear the TX and RX descriptors 1109 * in case of both basic and extended descriptors are used. 1110 */ 1111 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1112 { 1113 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1114 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1115 u32 queue; 1116 1117 /* Clear the RX descriptors */ 1118 for (queue = 0; queue < rx_queue_cnt; queue++) 1119 stmmac_clear_rx_descriptors(priv, queue); 1120 1121 /* Clear the TX descriptors */ 1122 for (queue = 0; queue < tx_queue_cnt; queue++) 1123 stmmac_clear_tx_descriptors(priv, queue); 1124 } 1125 1126 /** 1127 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1128 * @priv: driver private structure 1129 * @p: descriptor pointer 1130 * @i: descriptor index 1131 * @flags: gfp flag 1132 * @queue: RX queue index 1133 * Description: this function is called to allocate a receive buffer, perform 1134 * the DMA mapping and init the descriptor. 1135 */ 1136 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1137 int i, gfp_t flags, u32 queue) 1138 { 1139 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1140 struct sk_buff *skb; 1141 1142 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); 1143 if (!skb) { 1144 netdev_err(priv->dev, 1145 "%s: Rx init fails; skb is NULL\n", __func__); 1146 return -ENOMEM; 1147 } 1148 rx_q->rx_skbuff[i] = skb; 1149 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 1150 priv->dma_buf_sz, 1151 DMA_FROM_DEVICE); 1152 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) { 1153 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 1154 dev_kfree_skb_any(skb); 1155 return -EINVAL; 1156 } 1157 1158 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]); 1159 1160 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1161 stmmac_init_desc3(priv, p); 1162 1163 return 0; 1164 } 1165 1166 /** 1167 * stmmac_free_rx_buffer - free RX dma buffers 1168 * @priv: private structure 1169 * @queue: RX queue index 1170 * @i: buffer index. 1171 */ 1172 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1173 { 1174 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1175 1176 if (rx_q->rx_skbuff[i]) { 1177 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i], 1178 priv->dma_buf_sz, DMA_FROM_DEVICE); 1179 dev_kfree_skb_any(rx_q->rx_skbuff[i]); 1180 } 1181 rx_q->rx_skbuff[i] = NULL; 1182 } 1183 1184 /** 1185 * stmmac_free_tx_buffer - free RX dma buffers 1186 * @priv: private structure 1187 * @queue: RX queue index 1188 * @i: buffer index. 1189 */ 1190 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1191 { 1192 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1193 1194 if (tx_q->tx_skbuff_dma[i].buf) { 1195 if (tx_q->tx_skbuff_dma[i].map_as_page) 1196 dma_unmap_page(priv->device, 1197 tx_q->tx_skbuff_dma[i].buf, 1198 tx_q->tx_skbuff_dma[i].len, 1199 DMA_TO_DEVICE); 1200 else 1201 dma_unmap_single(priv->device, 1202 tx_q->tx_skbuff_dma[i].buf, 1203 tx_q->tx_skbuff_dma[i].len, 1204 DMA_TO_DEVICE); 1205 } 1206 1207 if (tx_q->tx_skbuff[i]) { 1208 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1209 tx_q->tx_skbuff[i] = NULL; 1210 tx_q->tx_skbuff_dma[i].buf = 0; 1211 tx_q->tx_skbuff_dma[i].map_as_page = false; 1212 } 1213 } 1214 1215 /** 1216 * init_dma_rx_desc_rings - init the RX descriptor rings 1217 * @dev: net device structure 1218 * @flags: gfp flag. 1219 * Description: this function initializes the DMA RX descriptors 1220 * and allocates the socket buffers. It supports the chained and ring 1221 * modes. 1222 */ 1223 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1224 { 1225 struct stmmac_priv *priv = netdev_priv(dev); 1226 u32 rx_count = priv->plat->rx_queues_to_use; 1227 int ret = -ENOMEM; 1228 int bfsize = 0; 1229 int queue; 1230 int i; 1231 1232 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 1233 if (bfsize < 0) 1234 bfsize = 0; 1235 1236 if (bfsize < BUF_SIZE_16KiB) 1237 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1238 1239 priv->dma_buf_sz = bfsize; 1240 1241 /* RX INITIALIZATION */ 1242 netif_dbg(priv, probe, priv->dev, 1243 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1244 1245 for (queue = 0; queue < rx_count; queue++) { 1246 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1247 1248 netif_dbg(priv, probe, priv->dev, 1249 "(%s) dma_rx_phy=0x%08x\n", __func__, 1250 (u32)rx_q->dma_rx_phy); 1251 1252 for (i = 0; i < DMA_RX_SIZE; i++) { 1253 struct dma_desc *p; 1254 1255 if (priv->extend_desc) 1256 p = &((rx_q->dma_erx + i)->basic); 1257 else 1258 p = rx_q->dma_rx + i; 1259 1260 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1261 queue); 1262 if (ret) 1263 goto err_init_rx_buffers; 1264 1265 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n", 1266 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data, 1267 (unsigned int)rx_q->rx_skbuff_dma[i]); 1268 } 1269 1270 rx_q->cur_rx = 0; 1271 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1272 1273 stmmac_clear_rx_descriptors(priv, queue); 1274 1275 /* Setup the chained descriptor addresses */ 1276 if (priv->mode == STMMAC_CHAIN_MODE) { 1277 if (priv->extend_desc) 1278 stmmac_mode_init(priv, rx_q->dma_erx, 1279 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1280 else 1281 stmmac_mode_init(priv, rx_q->dma_rx, 1282 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1283 } 1284 } 1285 1286 buf_sz = bfsize; 1287 1288 return 0; 1289 1290 err_init_rx_buffers: 1291 while (queue >= 0) { 1292 while (--i >= 0) 1293 stmmac_free_rx_buffer(priv, queue, i); 1294 1295 if (queue == 0) 1296 break; 1297 1298 i = DMA_RX_SIZE; 1299 queue--; 1300 } 1301 1302 return ret; 1303 } 1304 1305 /** 1306 * init_dma_tx_desc_rings - init the TX descriptor rings 1307 * @dev: net device structure. 1308 * Description: this function initializes the DMA TX descriptors 1309 * and allocates the socket buffers. It supports the chained and ring 1310 * modes. 1311 */ 1312 static int init_dma_tx_desc_rings(struct net_device *dev) 1313 { 1314 struct stmmac_priv *priv = netdev_priv(dev); 1315 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1316 u32 queue; 1317 int i; 1318 1319 for (queue = 0; queue < tx_queue_cnt; queue++) { 1320 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1321 1322 netif_dbg(priv, probe, priv->dev, 1323 "(%s) dma_tx_phy=0x%08x\n", __func__, 1324 (u32)tx_q->dma_tx_phy); 1325 1326 /* Setup the chained descriptor addresses */ 1327 if (priv->mode == STMMAC_CHAIN_MODE) { 1328 if (priv->extend_desc) 1329 stmmac_mode_init(priv, tx_q->dma_etx, 1330 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1331 else 1332 stmmac_mode_init(priv, tx_q->dma_tx, 1333 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1334 } 1335 1336 for (i = 0; i < DMA_TX_SIZE; i++) { 1337 struct dma_desc *p; 1338 if (priv->extend_desc) 1339 p = &((tx_q->dma_etx + i)->basic); 1340 else 1341 p = tx_q->dma_tx + i; 1342 1343 stmmac_clear_desc(priv, p); 1344 1345 tx_q->tx_skbuff_dma[i].buf = 0; 1346 tx_q->tx_skbuff_dma[i].map_as_page = false; 1347 tx_q->tx_skbuff_dma[i].len = 0; 1348 tx_q->tx_skbuff_dma[i].last_segment = false; 1349 tx_q->tx_skbuff[i] = NULL; 1350 } 1351 1352 tx_q->dirty_tx = 0; 1353 tx_q->cur_tx = 0; 1354 tx_q->mss = 0; 1355 1356 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1357 } 1358 1359 return 0; 1360 } 1361 1362 /** 1363 * init_dma_desc_rings - init the RX/TX descriptor rings 1364 * @dev: net device structure 1365 * @flags: gfp flag. 1366 * Description: this function initializes the DMA RX/TX descriptors 1367 * and allocates the socket buffers. It supports the chained and ring 1368 * modes. 1369 */ 1370 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1371 { 1372 struct stmmac_priv *priv = netdev_priv(dev); 1373 int ret; 1374 1375 ret = init_dma_rx_desc_rings(dev, flags); 1376 if (ret) 1377 return ret; 1378 1379 ret = init_dma_tx_desc_rings(dev); 1380 1381 stmmac_clear_descriptors(priv); 1382 1383 if (netif_msg_hw(priv)) 1384 stmmac_display_rings(priv); 1385 1386 return ret; 1387 } 1388 1389 /** 1390 * dma_free_rx_skbufs - free RX dma buffers 1391 * @priv: private structure 1392 * @queue: RX queue index 1393 */ 1394 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1395 { 1396 int i; 1397 1398 for (i = 0; i < DMA_RX_SIZE; i++) 1399 stmmac_free_rx_buffer(priv, queue, i); 1400 } 1401 1402 /** 1403 * dma_free_tx_skbufs - free TX dma buffers 1404 * @priv: private structure 1405 * @queue: TX queue index 1406 */ 1407 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1408 { 1409 int i; 1410 1411 for (i = 0; i < DMA_TX_SIZE; i++) 1412 stmmac_free_tx_buffer(priv, queue, i); 1413 } 1414 1415 /** 1416 * free_dma_rx_desc_resources - free RX dma desc resources 1417 * @priv: private structure 1418 */ 1419 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1420 { 1421 u32 rx_count = priv->plat->rx_queues_to_use; 1422 u32 queue; 1423 1424 /* Free RX queue resources */ 1425 for (queue = 0; queue < rx_count; queue++) { 1426 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1427 1428 /* Release the DMA RX socket buffers */ 1429 dma_free_rx_skbufs(priv, queue); 1430 1431 /* Free DMA regions of consistent memory previously allocated */ 1432 if (!priv->extend_desc) 1433 dma_free_coherent(priv->device, 1434 DMA_RX_SIZE * sizeof(struct dma_desc), 1435 rx_q->dma_rx, rx_q->dma_rx_phy); 1436 else 1437 dma_free_coherent(priv->device, DMA_RX_SIZE * 1438 sizeof(struct dma_extended_desc), 1439 rx_q->dma_erx, rx_q->dma_rx_phy); 1440 1441 kfree(rx_q->rx_skbuff_dma); 1442 kfree(rx_q->rx_skbuff); 1443 } 1444 } 1445 1446 /** 1447 * free_dma_tx_desc_resources - free TX dma desc resources 1448 * @priv: private structure 1449 */ 1450 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1451 { 1452 u32 tx_count = priv->plat->tx_queues_to_use; 1453 u32 queue; 1454 1455 /* Free TX queue resources */ 1456 for (queue = 0; queue < tx_count; queue++) { 1457 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1458 1459 /* Release the DMA TX socket buffers */ 1460 dma_free_tx_skbufs(priv, queue); 1461 1462 /* Free DMA regions of consistent memory previously allocated */ 1463 if (!priv->extend_desc) 1464 dma_free_coherent(priv->device, 1465 DMA_TX_SIZE * sizeof(struct dma_desc), 1466 tx_q->dma_tx, tx_q->dma_tx_phy); 1467 else 1468 dma_free_coherent(priv->device, DMA_TX_SIZE * 1469 sizeof(struct dma_extended_desc), 1470 tx_q->dma_etx, tx_q->dma_tx_phy); 1471 1472 kfree(tx_q->tx_skbuff_dma); 1473 kfree(tx_q->tx_skbuff); 1474 } 1475 } 1476 1477 /** 1478 * alloc_dma_rx_desc_resources - alloc RX resources. 1479 * @priv: private structure 1480 * Description: according to which descriptor can be used (extend or basic) 1481 * this function allocates the resources for TX and RX paths. In case of 1482 * reception, for example, it pre-allocated the RX socket buffer in order to 1483 * allow zero-copy mechanism. 1484 */ 1485 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1486 { 1487 u32 rx_count = priv->plat->rx_queues_to_use; 1488 int ret = -ENOMEM; 1489 u32 queue; 1490 1491 /* RX queues buffers and DMA */ 1492 for (queue = 0; queue < rx_count; queue++) { 1493 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1494 1495 rx_q->queue_index = queue; 1496 rx_q->priv_data = priv; 1497 1498 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, 1499 sizeof(dma_addr_t), 1500 GFP_KERNEL); 1501 if (!rx_q->rx_skbuff_dma) 1502 goto err_dma; 1503 1504 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE, 1505 sizeof(struct sk_buff *), 1506 GFP_KERNEL); 1507 if (!rx_q->rx_skbuff) 1508 goto err_dma; 1509 1510 if (priv->extend_desc) { 1511 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1512 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1513 &rx_q->dma_rx_phy, 1514 GFP_KERNEL); 1515 if (!rx_q->dma_erx) 1516 goto err_dma; 1517 1518 } else { 1519 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1520 DMA_RX_SIZE * sizeof(struct dma_desc), 1521 &rx_q->dma_rx_phy, 1522 GFP_KERNEL); 1523 if (!rx_q->dma_rx) 1524 goto err_dma; 1525 } 1526 } 1527 1528 return 0; 1529 1530 err_dma: 1531 free_dma_rx_desc_resources(priv); 1532 1533 return ret; 1534 } 1535 1536 /** 1537 * alloc_dma_tx_desc_resources - alloc TX resources. 1538 * @priv: private structure 1539 * Description: according to which descriptor can be used (extend or basic) 1540 * this function allocates the resources for TX and RX paths. In case of 1541 * reception, for example, it pre-allocated the RX socket buffer in order to 1542 * allow zero-copy mechanism. 1543 */ 1544 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1545 { 1546 u32 tx_count = priv->plat->tx_queues_to_use; 1547 int ret = -ENOMEM; 1548 u32 queue; 1549 1550 /* TX queues buffers and DMA */ 1551 for (queue = 0; queue < tx_count; queue++) { 1552 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1553 1554 tx_q->queue_index = queue; 1555 tx_q->priv_data = priv; 1556 1557 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, 1558 sizeof(*tx_q->tx_skbuff_dma), 1559 GFP_KERNEL); 1560 if (!tx_q->tx_skbuff_dma) 1561 goto err_dma; 1562 1563 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE, 1564 sizeof(struct sk_buff *), 1565 GFP_KERNEL); 1566 if (!tx_q->tx_skbuff) 1567 goto err_dma; 1568 1569 if (priv->extend_desc) { 1570 tx_q->dma_etx = dma_alloc_coherent(priv->device, 1571 DMA_TX_SIZE * sizeof(struct dma_extended_desc), 1572 &tx_q->dma_tx_phy, 1573 GFP_KERNEL); 1574 if (!tx_q->dma_etx) 1575 goto err_dma; 1576 } else { 1577 tx_q->dma_tx = dma_alloc_coherent(priv->device, 1578 DMA_TX_SIZE * sizeof(struct dma_desc), 1579 &tx_q->dma_tx_phy, 1580 GFP_KERNEL); 1581 if (!tx_q->dma_tx) 1582 goto err_dma; 1583 } 1584 } 1585 1586 return 0; 1587 1588 err_dma: 1589 free_dma_tx_desc_resources(priv); 1590 1591 return ret; 1592 } 1593 1594 /** 1595 * alloc_dma_desc_resources - alloc TX/RX resources. 1596 * @priv: private structure 1597 * Description: according to which descriptor can be used (extend or basic) 1598 * this function allocates the resources for TX and RX paths. In case of 1599 * reception, for example, it pre-allocated the RX socket buffer in order to 1600 * allow zero-copy mechanism. 1601 */ 1602 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1603 { 1604 /* RX Allocation */ 1605 int ret = alloc_dma_rx_desc_resources(priv); 1606 1607 if (ret) 1608 return ret; 1609 1610 ret = alloc_dma_tx_desc_resources(priv); 1611 1612 return ret; 1613 } 1614 1615 /** 1616 * free_dma_desc_resources - free dma desc resources 1617 * @priv: private structure 1618 */ 1619 static void free_dma_desc_resources(struct stmmac_priv *priv) 1620 { 1621 /* Release the DMA RX socket buffers */ 1622 free_dma_rx_desc_resources(priv); 1623 1624 /* Release the DMA TX socket buffers */ 1625 free_dma_tx_desc_resources(priv); 1626 } 1627 1628 /** 1629 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1630 * @priv: driver private structure 1631 * Description: It is used for enabling the rx queues in the MAC 1632 */ 1633 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1634 { 1635 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1636 int queue; 1637 u8 mode; 1638 1639 for (queue = 0; queue < rx_queues_count; queue++) { 1640 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1641 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1642 } 1643 } 1644 1645 /** 1646 * stmmac_start_rx_dma - start RX DMA channel 1647 * @priv: driver private structure 1648 * @chan: RX channel index 1649 * Description: 1650 * This starts a RX DMA channel 1651 */ 1652 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1653 { 1654 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1655 stmmac_start_rx(priv, priv->ioaddr, chan); 1656 } 1657 1658 /** 1659 * stmmac_start_tx_dma - start TX DMA channel 1660 * @priv: driver private structure 1661 * @chan: TX channel index 1662 * Description: 1663 * This starts a TX DMA channel 1664 */ 1665 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1666 { 1667 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1668 stmmac_start_tx(priv, priv->ioaddr, chan); 1669 } 1670 1671 /** 1672 * stmmac_stop_rx_dma - stop RX DMA channel 1673 * @priv: driver private structure 1674 * @chan: RX channel index 1675 * Description: 1676 * This stops a RX DMA channel 1677 */ 1678 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1679 { 1680 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1681 stmmac_stop_rx(priv, priv->ioaddr, chan); 1682 } 1683 1684 /** 1685 * stmmac_stop_tx_dma - stop TX DMA channel 1686 * @priv: driver private structure 1687 * @chan: TX channel index 1688 * Description: 1689 * This stops a TX DMA channel 1690 */ 1691 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1692 { 1693 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1694 stmmac_stop_tx(priv, priv->ioaddr, chan); 1695 } 1696 1697 /** 1698 * stmmac_start_all_dma - start all RX and TX DMA channels 1699 * @priv: driver private structure 1700 * Description: 1701 * This starts all the RX and TX DMA channels 1702 */ 1703 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1704 { 1705 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1706 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1707 u32 chan = 0; 1708 1709 for (chan = 0; chan < rx_channels_count; chan++) 1710 stmmac_start_rx_dma(priv, chan); 1711 1712 for (chan = 0; chan < tx_channels_count; chan++) 1713 stmmac_start_tx_dma(priv, chan); 1714 } 1715 1716 /** 1717 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1718 * @priv: driver private structure 1719 * Description: 1720 * This stops the RX and TX DMA channels 1721 */ 1722 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1723 { 1724 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1725 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1726 u32 chan = 0; 1727 1728 for (chan = 0; chan < rx_channels_count; chan++) 1729 stmmac_stop_rx_dma(priv, chan); 1730 1731 for (chan = 0; chan < tx_channels_count; chan++) 1732 stmmac_stop_tx_dma(priv, chan); 1733 } 1734 1735 /** 1736 * stmmac_dma_operation_mode - HW DMA operation mode 1737 * @priv: driver private structure 1738 * Description: it is used for configuring the DMA operation mode register in 1739 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1740 */ 1741 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1742 { 1743 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1744 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1745 int rxfifosz = priv->plat->rx_fifo_size; 1746 int txfifosz = priv->plat->tx_fifo_size; 1747 u32 txmode = 0; 1748 u32 rxmode = 0; 1749 u32 chan = 0; 1750 u8 qmode = 0; 1751 1752 if (rxfifosz == 0) 1753 rxfifosz = priv->dma_cap.rx_fifo_size; 1754 if (txfifosz == 0) 1755 txfifosz = priv->dma_cap.tx_fifo_size; 1756 1757 /* Adjust for real per queue fifo size */ 1758 rxfifosz /= rx_channels_count; 1759 txfifosz /= tx_channels_count; 1760 1761 if (priv->plat->force_thresh_dma_mode) { 1762 txmode = tc; 1763 rxmode = tc; 1764 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1765 /* 1766 * In case of GMAC, SF mode can be enabled 1767 * to perform the TX COE in HW. This depends on: 1768 * 1) TX COE if actually supported 1769 * 2) There is no bugged Jumbo frame support 1770 * that needs to not insert csum in the TDES. 1771 */ 1772 txmode = SF_DMA_MODE; 1773 rxmode = SF_DMA_MODE; 1774 priv->xstats.threshold = SF_DMA_MODE; 1775 } else { 1776 txmode = tc; 1777 rxmode = SF_DMA_MODE; 1778 } 1779 1780 /* configure all channels */ 1781 for (chan = 0; chan < rx_channels_count; chan++) { 1782 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1783 1784 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1785 rxfifosz, qmode); 1786 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1787 chan); 1788 } 1789 1790 for (chan = 0; chan < tx_channels_count; chan++) { 1791 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1792 1793 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1794 txfifosz, qmode); 1795 } 1796 } 1797 1798 /** 1799 * stmmac_tx_clean - to manage the transmission completion 1800 * @priv: driver private structure 1801 * @queue: TX queue index 1802 * Description: it reclaims the transmit resources after transmission completes. 1803 */ 1804 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1805 { 1806 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1807 unsigned int bytes_compl = 0, pkts_compl = 0; 1808 unsigned int entry, count = 0; 1809 1810 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1811 1812 priv->xstats.tx_clean++; 1813 1814 entry = tx_q->dirty_tx; 1815 while ((entry != tx_q->cur_tx) && (count < budget)) { 1816 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1817 struct dma_desc *p; 1818 int status; 1819 1820 if (priv->extend_desc) 1821 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1822 else 1823 p = tx_q->dma_tx + entry; 1824 1825 status = stmmac_tx_status(priv, &priv->dev->stats, 1826 &priv->xstats, p, priv->ioaddr); 1827 /* Check if the descriptor is owned by the DMA */ 1828 if (unlikely(status & tx_dma_own)) 1829 break; 1830 1831 count++; 1832 1833 /* Make sure descriptor fields are read after reading 1834 * the own bit. 1835 */ 1836 dma_rmb(); 1837 1838 /* Just consider the last segment and ...*/ 1839 if (likely(!(status & tx_not_ls))) { 1840 /* ... verify the status error condition */ 1841 if (unlikely(status & tx_err)) { 1842 priv->dev->stats.tx_errors++; 1843 } else { 1844 priv->dev->stats.tx_packets++; 1845 priv->xstats.tx_pkt_n++; 1846 } 1847 stmmac_get_tx_hwtstamp(priv, p, skb); 1848 } 1849 1850 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1851 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1852 dma_unmap_page(priv->device, 1853 tx_q->tx_skbuff_dma[entry].buf, 1854 tx_q->tx_skbuff_dma[entry].len, 1855 DMA_TO_DEVICE); 1856 else 1857 dma_unmap_single(priv->device, 1858 tx_q->tx_skbuff_dma[entry].buf, 1859 tx_q->tx_skbuff_dma[entry].len, 1860 DMA_TO_DEVICE); 1861 tx_q->tx_skbuff_dma[entry].buf = 0; 1862 tx_q->tx_skbuff_dma[entry].len = 0; 1863 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1864 } 1865 1866 stmmac_clean_desc3(priv, tx_q, p); 1867 1868 tx_q->tx_skbuff_dma[entry].last_segment = false; 1869 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1870 1871 if (likely(skb != NULL)) { 1872 pkts_compl++; 1873 bytes_compl += skb->len; 1874 dev_consume_skb_any(skb); 1875 tx_q->tx_skbuff[entry] = NULL; 1876 } 1877 1878 stmmac_release_tx_desc(priv, p, priv->mode); 1879 1880 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1881 } 1882 tx_q->dirty_tx = entry; 1883 1884 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1885 pkts_compl, bytes_compl); 1886 1887 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1888 queue))) && 1889 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1890 1891 netif_dbg(priv, tx_done, priv->dev, 1892 "%s: restart transmit\n", __func__); 1893 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1894 } 1895 1896 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1897 stmmac_enable_eee_mode(priv); 1898 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1899 } 1900 1901 /* We still have pending packets, let's call for a new scheduling */ 1902 if (tx_q->dirty_tx != tx_q->cur_tx) 1903 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 1904 1905 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 1906 1907 return count; 1908 } 1909 1910 /** 1911 * stmmac_tx_err - to manage the tx error 1912 * @priv: driver private structure 1913 * @chan: channel index 1914 * Description: it cleans the descriptors and restarts the transmission 1915 * in case of transmission errors. 1916 */ 1917 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 1918 { 1919 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 1920 int i; 1921 1922 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 1923 1924 stmmac_stop_tx_dma(priv, chan); 1925 dma_free_tx_skbufs(priv, chan); 1926 for (i = 0; i < DMA_TX_SIZE; i++) 1927 if (priv->extend_desc) 1928 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1929 priv->mode, (i == DMA_TX_SIZE - 1)); 1930 else 1931 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1932 priv->mode, (i == DMA_TX_SIZE - 1)); 1933 tx_q->dirty_tx = 0; 1934 tx_q->cur_tx = 0; 1935 tx_q->mss = 0; 1936 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 1937 stmmac_start_tx_dma(priv, chan); 1938 1939 priv->dev->stats.tx_errors++; 1940 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 1941 } 1942 1943 /** 1944 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 1945 * @priv: driver private structure 1946 * @txmode: TX operating mode 1947 * @rxmode: RX operating mode 1948 * @chan: channel index 1949 * Description: it is used for configuring of the DMA operation mode in 1950 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 1951 * mode. 1952 */ 1953 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 1954 u32 rxmode, u32 chan) 1955 { 1956 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1957 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1958 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1959 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1960 int rxfifosz = priv->plat->rx_fifo_size; 1961 int txfifosz = priv->plat->tx_fifo_size; 1962 1963 if (rxfifosz == 0) 1964 rxfifosz = priv->dma_cap.rx_fifo_size; 1965 if (txfifosz == 0) 1966 txfifosz = priv->dma_cap.tx_fifo_size; 1967 1968 /* Adjust for real per queue fifo size */ 1969 rxfifosz /= rx_channels_count; 1970 txfifosz /= tx_channels_count; 1971 1972 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 1973 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 1974 } 1975 1976 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 1977 { 1978 int ret; 1979 1980 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 1981 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 1982 if (ret && (ret != -EINVAL)) { 1983 stmmac_global_err(priv); 1984 return true; 1985 } 1986 1987 return false; 1988 } 1989 1990 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 1991 { 1992 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 1993 &priv->xstats, chan); 1994 struct stmmac_channel *ch = &priv->channel[chan]; 1995 1996 if (status) 1997 status |= handle_rx | handle_tx; 1998 1999 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2000 stmmac_disable_dma_irq(priv, priv->ioaddr, chan); 2001 napi_schedule_irqoff(&ch->rx_napi); 2002 } 2003 2004 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2005 stmmac_disable_dma_irq(priv, priv->ioaddr, chan); 2006 napi_schedule_irqoff(&ch->tx_napi); 2007 } 2008 2009 return status; 2010 } 2011 2012 /** 2013 * stmmac_dma_interrupt - DMA ISR 2014 * @priv: driver private structure 2015 * Description: this is the DMA ISR. It is called by the main ISR. 2016 * It calls the dwmac dma routine and schedule poll method in case of some 2017 * work can be done. 2018 */ 2019 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2020 { 2021 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2022 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2023 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2024 tx_channel_count : rx_channel_count; 2025 u32 chan; 2026 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2027 2028 /* Make sure we never check beyond our status buffer. */ 2029 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2030 channels_to_check = ARRAY_SIZE(status); 2031 2032 for (chan = 0; chan < channels_to_check; chan++) 2033 status[chan] = stmmac_napi_check(priv, chan); 2034 2035 for (chan = 0; chan < tx_channel_count; chan++) { 2036 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2037 /* Try to bump up the dma threshold on this failure */ 2038 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2039 (tc <= 256)) { 2040 tc += 64; 2041 if (priv->plat->force_thresh_dma_mode) 2042 stmmac_set_dma_operation_mode(priv, 2043 tc, 2044 tc, 2045 chan); 2046 else 2047 stmmac_set_dma_operation_mode(priv, 2048 tc, 2049 SF_DMA_MODE, 2050 chan); 2051 priv->xstats.threshold = tc; 2052 } 2053 } else if (unlikely(status[chan] == tx_hard_error)) { 2054 stmmac_tx_err(priv, chan); 2055 } 2056 } 2057 } 2058 2059 /** 2060 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2061 * @priv: driver private structure 2062 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2063 */ 2064 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2065 { 2066 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2067 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2068 2069 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2070 2071 if (priv->dma_cap.rmon) { 2072 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2073 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2074 } else 2075 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2076 } 2077 2078 /** 2079 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2080 * @priv: driver private structure 2081 * Description: 2082 * new GMAC chip generations have a new register to indicate the 2083 * presence of the optional feature/functions. 2084 * This can be also used to override the value passed through the 2085 * platform and necessary for old MAC10/100 and GMAC chips. 2086 */ 2087 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2088 { 2089 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2090 } 2091 2092 /** 2093 * stmmac_check_ether_addr - check if the MAC addr is valid 2094 * @priv: driver private structure 2095 * Description: 2096 * it is to verify if the MAC address is valid, in case of failures it 2097 * generates a random MAC address 2098 */ 2099 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2100 { 2101 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2102 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2103 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2104 eth_hw_addr_random(priv->dev); 2105 dev_info(priv->device, "device MAC address %pM\n", 2106 priv->dev->dev_addr); 2107 } 2108 } 2109 2110 /** 2111 * stmmac_init_dma_engine - DMA init. 2112 * @priv: driver private structure 2113 * Description: 2114 * It inits the DMA invoking the specific MAC/GMAC callback. 2115 * Some DMA parameters can be passed from the platform; 2116 * in case of these are not passed a default is kept for the MAC or GMAC. 2117 */ 2118 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2119 { 2120 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2121 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2122 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2123 struct stmmac_rx_queue *rx_q; 2124 struct stmmac_tx_queue *tx_q; 2125 u32 chan = 0; 2126 int atds = 0; 2127 int ret = 0; 2128 2129 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2130 dev_err(priv->device, "Invalid DMA configuration\n"); 2131 return -EINVAL; 2132 } 2133 2134 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2135 atds = 1; 2136 2137 ret = stmmac_reset(priv, priv->ioaddr); 2138 if (ret) { 2139 dev_err(priv->device, "Failed to reset the dma\n"); 2140 return ret; 2141 } 2142 2143 /* DMA Configuration */ 2144 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2145 2146 if (priv->plat->axi) 2147 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2148 2149 /* DMA CSR Channel configuration */ 2150 for (chan = 0; chan < dma_csr_ch; chan++) 2151 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2152 2153 /* DMA RX Channel Configuration */ 2154 for (chan = 0; chan < rx_channels_count; chan++) { 2155 rx_q = &priv->rx_queue[chan]; 2156 2157 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2158 rx_q->dma_rx_phy, chan); 2159 2160 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2161 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2162 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2163 rx_q->rx_tail_addr, chan); 2164 } 2165 2166 /* DMA TX Channel Configuration */ 2167 for (chan = 0; chan < tx_channels_count; chan++) { 2168 tx_q = &priv->tx_queue[chan]; 2169 2170 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2171 tx_q->dma_tx_phy, chan); 2172 2173 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2174 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2175 tx_q->tx_tail_addr, chan); 2176 } 2177 2178 return ret; 2179 } 2180 2181 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2182 { 2183 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2184 2185 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2186 } 2187 2188 /** 2189 * stmmac_tx_timer - mitigation sw timer for tx. 2190 * @data: data pointer 2191 * Description: 2192 * This is the timer handler to directly invoke the stmmac_tx_clean. 2193 */ 2194 static void stmmac_tx_timer(struct timer_list *t) 2195 { 2196 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2197 struct stmmac_priv *priv = tx_q->priv_data; 2198 struct stmmac_channel *ch; 2199 2200 ch = &priv->channel[tx_q->queue_index]; 2201 2202 /* 2203 * If NAPI is already running we can miss some events. Let's rearm 2204 * the timer and try again. 2205 */ 2206 if (likely(napi_schedule_prep(&ch->tx_napi))) 2207 __napi_schedule(&ch->tx_napi); 2208 else 2209 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 2210 } 2211 2212 /** 2213 * stmmac_init_tx_coalesce - init tx mitigation options. 2214 * @priv: driver private structure 2215 * Description: 2216 * This inits the transmit coalesce parameters: i.e. timer rate, 2217 * timer handler and default threshold used for enabling the 2218 * interrupt on completion bit. 2219 */ 2220 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 2221 { 2222 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2223 u32 chan; 2224 2225 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2226 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2227 2228 for (chan = 0; chan < tx_channel_count; chan++) { 2229 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2230 2231 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2232 } 2233 } 2234 2235 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2236 { 2237 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2238 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2239 u32 chan; 2240 2241 /* set TX ring length */ 2242 for (chan = 0; chan < tx_channels_count; chan++) 2243 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2244 (DMA_TX_SIZE - 1), chan); 2245 2246 /* set RX ring length */ 2247 for (chan = 0; chan < rx_channels_count; chan++) 2248 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2249 (DMA_RX_SIZE - 1), chan); 2250 } 2251 2252 /** 2253 * stmmac_set_tx_queue_weight - Set TX queue weight 2254 * @priv: driver private structure 2255 * Description: It is used for setting TX queues weight 2256 */ 2257 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2258 { 2259 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2260 u32 weight; 2261 u32 queue; 2262 2263 for (queue = 0; queue < tx_queues_count; queue++) { 2264 weight = priv->plat->tx_queues_cfg[queue].weight; 2265 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2266 } 2267 } 2268 2269 /** 2270 * stmmac_configure_cbs - Configure CBS in TX queue 2271 * @priv: driver private structure 2272 * Description: It is used for configuring CBS in AVB TX queues 2273 */ 2274 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2275 { 2276 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2277 u32 mode_to_use; 2278 u32 queue; 2279 2280 /* queue 0 is reserved for legacy traffic */ 2281 for (queue = 1; queue < tx_queues_count; queue++) { 2282 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2283 if (mode_to_use == MTL_QUEUE_DCB) 2284 continue; 2285 2286 stmmac_config_cbs(priv, priv->hw, 2287 priv->plat->tx_queues_cfg[queue].send_slope, 2288 priv->plat->tx_queues_cfg[queue].idle_slope, 2289 priv->plat->tx_queues_cfg[queue].high_credit, 2290 priv->plat->tx_queues_cfg[queue].low_credit, 2291 queue); 2292 } 2293 } 2294 2295 /** 2296 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2297 * @priv: driver private structure 2298 * Description: It is used for mapping RX queues to RX dma channels 2299 */ 2300 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2301 { 2302 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2303 u32 queue; 2304 u32 chan; 2305 2306 for (queue = 0; queue < rx_queues_count; queue++) { 2307 chan = priv->plat->rx_queues_cfg[queue].chan; 2308 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2309 } 2310 } 2311 2312 /** 2313 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2314 * @priv: driver private structure 2315 * Description: It is used for configuring the RX Queue Priority 2316 */ 2317 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2318 { 2319 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2320 u32 queue; 2321 u32 prio; 2322 2323 for (queue = 0; queue < rx_queues_count; queue++) { 2324 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2325 continue; 2326 2327 prio = priv->plat->rx_queues_cfg[queue].prio; 2328 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2329 } 2330 } 2331 2332 /** 2333 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2334 * @priv: driver private structure 2335 * Description: It is used for configuring the TX Queue Priority 2336 */ 2337 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2338 { 2339 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2340 u32 queue; 2341 u32 prio; 2342 2343 for (queue = 0; queue < tx_queues_count; queue++) { 2344 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2345 continue; 2346 2347 prio = priv->plat->tx_queues_cfg[queue].prio; 2348 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2349 } 2350 } 2351 2352 /** 2353 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2354 * @priv: driver private structure 2355 * Description: It is used for configuring the RX queue routing 2356 */ 2357 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2358 { 2359 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2360 u32 queue; 2361 u8 packet; 2362 2363 for (queue = 0; queue < rx_queues_count; queue++) { 2364 /* no specific packet type routing specified for the queue */ 2365 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2366 continue; 2367 2368 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2369 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2370 } 2371 } 2372 2373 /** 2374 * stmmac_mtl_configuration - Configure MTL 2375 * @priv: driver private structure 2376 * Description: It is used for configurring MTL 2377 */ 2378 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2379 { 2380 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2381 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2382 2383 if (tx_queues_count > 1) 2384 stmmac_set_tx_queue_weight(priv); 2385 2386 /* Configure MTL RX algorithms */ 2387 if (rx_queues_count > 1) 2388 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2389 priv->plat->rx_sched_algorithm); 2390 2391 /* Configure MTL TX algorithms */ 2392 if (tx_queues_count > 1) 2393 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2394 priv->plat->tx_sched_algorithm); 2395 2396 /* Configure CBS in AVB TX queues */ 2397 if (tx_queues_count > 1) 2398 stmmac_configure_cbs(priv); 2399 2400 /* Map RX MTL to DMA channels */ 2401 stmmac_rx_queue_dma_chan_map(priv); 2402 2403 /* Enable MAC RX Queues */ 2404 stmmac_mac_enable_rx_queues(priv); 2405 2406 /* Set RX priorities */ 2407 if (rx_queues_count > 1) 2408 stmmac_mac_config_rx_queues_prio(priv); 2409 2410 /* Set TX priorities */ 2411 if (tx_queues_count > 1) 2412 stmmac_mac_config_tx_queues_prio(priv); 2413 2414 /* Set RX routing */ 2415 if (rx_queues_count > 1) 2416 stmmac_mac_config_rx_queues_routing(priv); 2417 } 2418 2419 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2420 { 2421 if (priv->dma_cap.asp) { 2422 netdev_info(priv->dev, "Enabling Safety Features\n"); 2423 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2424 } else { 2425 netdev_info(priv->dev, "No Safety Features support found\n"); 2426 } 2427 } 2428 2429 /** 2430 * stmmac_hw_setup - setup mac in a usable state. 2431 * @dev : pointer to the device structure. 2432 * Description: 2433 * this is the main function to setup the HW in a usable state because the 2434 * dma engine is reset, the core registers are configured (e.g. AXI, 2435 * Checksum features, timers). The DMA is ready to start receiving and 2436 * transmitting. 2437 * Return value: 2438 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2439 * file on failure. 2440 */ 2441 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2442 { 2443 struct stmmac_priv *priv = netdev_priv(dev); 2444 u32 rx_cnt = priv->plat->rx_queues_to_use; 2445 u32 tx_cnt = priv->plat->tx_queues_to_use; 2446 u32 chan; 2447 int ret; 2448 2449 /* DMA initialization and SW reset */ 2450 ret = stmmac_init_dma_engine(priv); 2451 if (ret < 0) { 2452 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2453 __func__); 2454 return ret; 2455 } 2456 2457 /* Copy the MAC addr into the HW */ 2458 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2459 2460 /* PS and related bits will be programmed according to the speed */ 2461 if (priv->hw->pcs) { 2462 int speed = priv->plat->mac_port_sel_speed; 2463 2464 if ((speed == SPEED_10) || (speed == SPEED_100) || 2465 (speed == SPEED_1000)) { 2466 priv->hw->ps = speed; 2467 } else { 2468 dev_warn(priv->device, "invalid port speed\n"); 2469 priv->hw->ps = 0; 2470 } 2471 } 2472 2473 /* Initialize the MAC Core */ 2474 stmmac_core_init(priv, priv->hw, dev); 2475 2476 /* Initialize MTL*/ 2477 stmmac_mtl_configuration(priv); 2478 2479 /* Initialize Safety Features */ 2480 stmmac_safety_feat_configuration(priv); 2481 2482 ret = stmmac_rx_ipc(priv, priv->hw); 2483 if (!ret) { 2484 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2485 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2486 priv->hw->rx_csum = 0; 2487 } 2488 2489 /* Enable the MAC Rx/Tx */ 2490 stmmac_mac_set(priv, priv->ioaddr, true); 2491 2492 /* Set the HW DMA mode and the COE */ 2493 stmmac_dma_operation_mode(priv); 2494 2495 stmmac_mmc_setup(priv); 2496 2497 if (init_ptp) { 2498 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2499 if (ret < 0) 2500 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2501 2502 ret = stmmac_init_ptp(priv); 2503 if (ret == -EOPNOTSUPP) 2504 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2505 else if (ret) 2506 netdev_warn(priv->dev, "PTP init failed\n"); 2507 } 2508 2509 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2510 2511 if (priv->use_riwt) { 2512 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt); 2513 if (!ret) 2514 priv->rx_riwt = MAX_DMA_RIWT; 2515 } 2516 2517 if (priv->hw->pcs) 2518 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0); 2519 2520 /* set TX and RX rings length */ 2521 stmmac_set_rings_length(priv); 2522 2523 /* Enable TSO */ 2524 if (priv->tso) { 2525 for (chan = 0; chan < tx_cnt; chan++) 2526 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2527 } 2528 2529 /* Start the ball rolling... */ 2530 stmmac_start_all_dma(priv); 2531 2532 return 0; 2533 } 2534 2535 static void stmmac_hw_teardown(struct net_device *dev) 2536 { 2537 struct stmmac_priv *priv = netdev_priv(dev); 2538 2539 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2540 } 2541 2542 /** 2543 * stmmac_open - open entry point of the driver 2544 * @dev : pointer to the device structure. 2545 * Description: 2546 * This function is the open entry point of the driver. 2547 * Return value: 2548 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2549 * file on failure. 2550 */ 2551 static int stmmac_open(struct net_device *dev) 2552 { 2553 struct stmmac_priv *priv = netdev_priv(dev); 2554 u32 chan; 2555 int ret; 2556 2557 if (priv->hw->pcs != STMMAC_PCS_RGMII && 2558 priv->hw->pcs != STMMAC_PCS_TBI && 2559 priv->hw->pcs != STMMAC_PCS_RTBI) { 2560 ret = stmmac_init_phy(dev); 2561 if (ret) { 2562 netdev_err(priv->dev, 2563 "%s: Cannot attach to PHY (error: %d)\n", 2564 __func__, ret); 2565 return ret; 2566 } 2567 } 2568 2569 /* Extra statistics */ 2570 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2571 priv->xstats.threshold = tc; 2572 2573 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 2574 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2575 2576 ret = alloc_dma_desc_resources(priv); 2577 if (ret < 0) { 2578 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2579 __func__); 2580 goto dma_desc_error; 2581 } 2582 2583 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2584 if (ret < 0) { 2585 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2586 __func__); 2587 goto init_error; 2588 } 2589 2590 ret = stmmac_hw_setup(dev, true); 2591 if (ret < 0) { 2592 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2593 goto init_error; 2594 } 2595 2596 stmmac_init_tx_coalesce(priv); 2597 2598 phylink_start(priv->phylink); 2599 2600 /* Request the IRQ lines */ 2601 ret = request_irq(dev->irq, stmmac_interrupt, 2602 IRQF_SHARED, dev->name, dev); 2603 if (unlikely(ret < 0)) { 2604 netdev_err(priv->dev, 2605 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2606 __func__, dev->irq, ret); 2607 goto irq_error; 2608 } 2609 2610 /* Request the Wake IRQ in case of another line is used for WoL */ 2611 if (priv->wol_irq != dev->irq) { 2612 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2613 IRQF_SHARED, dev->name, dev); 2614 if (unlikely(ret < 0)) { 2615 netdev_err(priv->dev, 2616 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2617 __func__, priv->wol_irq, ret); 2618 goto wolirq_error; 2619 } 2620 } 2621 2622 /* Request the IRQ lines */ 2623 if (priv->lpi_irq > 0) { 2624 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2625 dev->name, dev); 2626 if (unlikely(ret < 0)) { 2627 netdev_err(priv->dev, 2628 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2629 __func__, priv->lpi_irq, ret); 2630 goto lpiirq_error; 2631 } 2632 } 2633 2634 stmmac_enable_all_queues(priv); 2635 stmmac_start_all_queues(priv); 2636 2637 return 0; 2638 2639 lpiirq_error: 2640 if (priv->wol_irq != dev->irq) 2641 free_irq(priv->wol_irq, dev); 2642 wolirq_error: 2643 free_irq(dev->irq, dev); 2644 irq_error: 2645 phylink_stop(priv->phylink); 2646 2647 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2648 del_timer_sync(&priv->tx_queue[chan].txtimer); 2649 2650 stmmac_hw_teardown(dev); 2651 init_error: 2652 free_dma_desc_resources(priv); 2653 dma_desc_error: 2654 phylink_disconnect_phy(priv->phylink); 2655 return ret; 2656 } 2657 2658 /** 2659 * stmmac_release - close entry point of the driver 2660 * @dev : device pointer. 2661 * Description: 2662 * This is the stop entry point of the driver. 2663 */ 2664 static int stmmac_release(struct net_device *dev) 2665 { 2666 struct stmmac_priv *priv = netdev_priv(dev); 2667 u32 chan; 2668 2669 if (priv->eee_enabled) 2670 del_timer_sync(&priv->eee_ctrl_timer); 2671 2672 /* Stop and disconnect the PHY */ 2673 phylink_stop(priv->phylink); 2674 phylink_disconnect_phy(priv->phylink); 2675 2676 stmmac_stop_all_queues(priv); 2677 2678 stmmac_disable_all_queues(priv); 2679 2680 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2681 del_timer_sync(&priv->tx_queue[chan].txtimer); 2682 2683 /* Free the IRQ lines */ 2684 free_irq(dev->irq, dev); 2685 if (priv->wol_irq != dev->irq) 2686 free_irq(priv->wol_irq, dev); 2687 if (priv->lpi_irq > 0) 2688 free_irq(priv->lpi_irq, dev); 2689 2690 /* Stop TX/RX DMA and clear the descriptors */ 2691 stmmac_stop_all_dma(priv); 2692 2693 /* Release and free the Rx/Tx resources */ 2694 free_dma_desc_resources(priv); 2695 2696 /* Disable the MAC Rx/Tx */ 2697 stmmac_mac_set(priv, priv->ioaddr, false); 2698 2699 netif_carrier_off(dev); 2700 2701 stmmac_release_ptp(priv); 2702 2703 return 0; 2704 } 2705 2706 /** 2707 * stmmac_tso_allocator - close entry point of the driver 2708 * @priv: driver private structure 2709 * @des: buffer start address 2710 * @total_len: total length to fill in descriptors 2711 * @last_segmant: condition for the last descriptor 2712 * @queue: TX queue index 2713 * Description: 2714 * This function fills descriptor and request new descriptors according to 2715 * buffer length to fill 2716 */ 2717 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, 2718 int total_len, bool last_segment, u32 queue) 2719 { 2720 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2721 struct dma_desc *desc; 2722 u32 buff_size; 2723 int tmp_len; 2724 2725 tmp_len = total_len; 2726 2727 while (tmp_len > 0) { 2728 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2729 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2730 desc = tx_q->dma_tx + tx_q->cur_tx; 2731 2732 desc->des0 = cpu_to_le32(des + (total_len - tmp_len)); 2733 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2734 TSO_MAX_BUFF_SIZE : tmp_len; 2735 2736 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2737 0, 1, 2738 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2739 0, 0); 2740 2741 tmp_len -= TSO_MAX_BUFF_SIZE; 2742 } 2743 } 2744 2745 /** 2746 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2747 * @skb : the socket buffer 2748 * @dev : device pointer 2749 * Description: this is the transmit function that is called on TSO frames 2750 * (support available on GMAC4 and newer chips). 2751 * Diagram below show the ring programming in case of TSO frames: 2752 * 2753 * First Descriptor 2754 * -------- 2755 * | DES0 |---> buffer1 = L2/L3/L4 header 2756 * | DES1 |---> TCP Payload (can continue on next descr...) 2757 * | DES2 |---> buffer 1 and 2 len 2758 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2759 * -------- 2760 * | 2761 * ... 2762 * | 2763 * -------- 2764 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2765 * | DES1 | --| 2766 * | DES2 | --> buffer 1 and 2 len 2767 * | DES3 | 2768 * -------- 2769 * 2770 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2771 */ 2772 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2773 { 2774 struct dma_desc *desc, *first, *mss_desc = NULL; 2775 struct stmmac_priv *priv = netdev_priv(dev); 2776 int nfrags = skb_shinfo(skb)->nr_frags; 2777 u32 queue = skb_get_queue_mapping(skb); 2778 unsigned int first_entry, des; 2779 struct stmmac_tx_queue *tx_q; 2780 int tmp_pay_len = 0; 2781 u32 pay_len, mss; 2782 u8 proto_hdr_len; 2783 int i; 2784 2785 tx_q = &priv->tx_queue[queue]; 2786 2787 /* Compute header lengths */ 2788 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2789 2790 /* Desc availability based on threshold should be enough safe */ 2791 if (unlikely(stmmac_tx_avail(priv, queue) < 2792 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2793 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 2794 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 2795 queue)); 2796 /* This is a hard error, log it. */ 2797 netdev_err(priv->dev, 2798 "%s: Tx Ring full when queue awake\n", 2799 __func__); 2800 } 2801 return NETDEV_TX_BUSY; 2802 } 2803 2804 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2805 2806 mss = skb_shinfo(skb)->gso_size; 2807 2808 /* set new MSS value if needed */ 2809 if (mss != tx_q->mss) { 2810 mss_desc = tx_q->dma_tx + tx_q->cur_tx; 2811 stmmac_set_mss(priv, mss_desc, mss); 2812 tx_q->mss = mss; 2813 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2814 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2815 } 2816 2817 if (netif_msg_tx_queued(priv)) { 2818 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2819 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2820 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2821 skb->data_len); 2822 } 2823 2824 first_entry = tx_q->cur_tx; 2825 WARN_ON(tx_q->tx_skbuff[first_entry]); 2826 2827 desc = tx_q->dma_tx + first_entry; 2828 first = desc; 2829 2830 /* first descriptor: fill Headers on Buf1 */ 2831 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2832 DMA_TO_DEVICE); 2833 if (dma_mapping_error(priv->device, des)) 2834 goto dma_map_err; 2835 2836 tx_q->tx_skbuff_dma[first_entry].buf = des; 2837 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2838 2839 first->des0 = cpu_to_le32(des); 2840 2841 /* Fill start of payload in buff2 of first descriptor */ 2842 if (pay_len) 2843 first->des1 = cpu_to_le32(des + proto_hdr_len); 2844 2845 /* If needed take extra descriptors to fill the remaining payload */ 2846 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2847 2848 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 2849 2850 /* Prepare fragments */ 2851 for (i = 0; i < nfrags; i++) { 2852 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2853 2854 des = skb_frag_dma_map(priv->device, frag, 0, 2855 skb_frag_size(frag), 2856 DMA_TO_DEVICE); 2857 if (dma_mapping_error(priv->device, des)) 2858 goto dma_map_err; 2859 2860 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 2861 (i == nfrags - 1), queue); 2862 2863 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 2864 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 2865 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 2866 } 2867 2868 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 2869 2870 /* Only the last descriptor gets to point to the skb. */ 2871 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 2872 2873 /* We've used all descriptors we need for this skb, however, 2874 * advance cur_tx so that it references a fresh descriptor. 2875 * ndo_start_xmit will fill this descriptor the next time it's 2876 * called and stmmac_tx_clean may clean up to this descriptor. 2877 */ 2878 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2879 2880 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 2881 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 2882 __func__); 2883 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 2884 } 2885 2886 dev->stats.tx_bytes += skb->len; 2887 priv->xstats.tx_tso_frames++; 2888 priv->xstats.tx_tso_nfrags += nfrags; 2889 2890 /* Manage tx mitigation */ 2891 tx_q->tx_count_frames += nfrags + 1; 2892 if (priv->tx_coal_frames <= tx_q->tx_count_frames) { 2893 stmmac_set_tx_ic(priv, desc); 2894 priv->xstats.tx_set_ic_bit++; 2895 tx_q->tx_count_frames = 0; 2896 } else { 2897 stmmac_tx_timer_arm(priv, queue); 2898 } 2899 2900 skb_tx_timestamp(skb); 2901 2902 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2903 priv->hwts_tx_en)) { 2904 /* declare that device is doing timestamping */ 2905 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2906 stmmac_enable_tx_timestamp(priv, first); 2907 } 2908 2909 /* Complete the first descriptor before granting the DMA */ 2910 stmmac_prepare_tso_tx_desc(priv, first, 1, 2911 proto_hdr_len, 2912 pay_len, 2913 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 2914 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2915 2916 /* If context desc is used to change MSS */ 2917 if (mss_desc) { 2918 /* Make sure that first descriptor has been completely 2919 * written, including its own bit. This is because MSS is 2920 * actually before first descriptor, so we need to make 2921 * sure that MSS's own bit is the last thing written. 2922 */ 2923 dma_wmb(); 2924 stmmac_set_tx_owner(priv, mss_desc); 2925 } 2926 2927 /* The own bit must be the latest setting done when prepare the 2928 * descriptor and then barrier is needed to make sure that 2929 * all is coherent before granting the DMA engine. 2930 */ 2931 wmb(); 2932 2933 if (netif_msg_pktdata(priv)) { 2934 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 2935 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 2936 tx_q->cur_tx, first, nfrags); 2937 2938 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0); 2939 2940 pr_info(">>> frame to be transmitted: "); 2941 print_pkt(skb->data, skb_headlen(skb)); 2942 } 2943 2944 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 2945 2946 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 2947 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 2948 2949 return NETDEV_TX_OK; 2950 2951 dma_map_err: 2952 dev_err(priv->device, "Tx dma map failed\n"); 2953 dev_kfree_skb(skb); 2954 priv->dev->stats.tx_dropped++; 2955 return NETDEV_TX_OK; 2956 } 2957 2958 /** 2959 * stmmac_xmit - Tx entry point of the driver 2960 * @skb : the socket buffer 2961 * @dev : device pointer 2962 * Description : this is the tx entry point of the driver. 2963 * It programs the chain or the ring and supports oversized frames 2964 * and SG feature. 2965 */ 2966 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 2967 { 2968 struct stmmac_priv *priv = netdev_priv(dev); 2969 unsigned int nopaged_len = skb_headlen(skb); 2970 int i, csum_insertion = 0, is_jumbo = 0; 2971 u32 queue = skb_get_queue_mapping(skb); 2972 int nfrags = skb_shinfo(skb)->nr_frags; 2973 int entry; 2974 unsigned int first_entry; 2975 struct dma_desc *desc, *first; 2976 struct stmmac_tx_queue *tx_q; 2977 unsigned int enh_desc; 2978 unsigned int des; 2979 2980 tx_q = &priv->tx_queue[queue]; 2981 2982 if (priv->tx_path_in_lpi_mode) 2983 stmmac_disable_eee_mode(priv); 2984 2985 /* Manage oversized TCP frames for GMAC4 device */ 2986 if (skb_is_gso(skb) && priv->tso) { 2987 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 2988 /* 2989 * There is no way to determine the number of TSO 2990 * capable Queues. Let's use always the Queue 0 2991 * because if TSO is supported then at least this 2992 * one will be capable. 2993 */ 2994 skb_set_queue_mapping(skb, 0); 2995 2996 return stmmac_tso_xmit(skb, dev); 2997 } 2998 } 2999 3000 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3001 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3002 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3003 queue)); 3004 /* This is a hard error, log it. */ 3005 netdev_err(priv->dev, 3006 "%s: Tx Ring full when queue awake\n", 3007 __func__); 3008 } 3009 return NETDEV_TX_BUSY; 3010 } 3011 3012 entry = tx_q->cur_tx; 3013 first_entry = entry; 3014 WARN_ON(tx_q->tx_skbuff[first_entry]); 3015 3016 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3017 3018 if (likely(priv->extend_desc)) 3019 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3020 else 3021 desc = tx_q->dma_tx + entry; 3022 3023 first = desc; 3024 3025 enh_desc = priv->plat->enh_desc; 3026 /* To program the descriptors according to the size of the frame */ 3027 if (enh_desc) 3028 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3029 3030 if (unlikely(is_jumbo)) { 3031 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3032 if (unlikely(entry < 0) && (entry != -EINVAL)) 3033 goto dma_map_err; 3034 } 3035 3036 for (i = 0; i < nfrags; i++) { 3037 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3038 int len = skb_frag_size(frag); 3039 bool last_segment = (i == (nfrags - 1)); 3040 3041 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3042 WARN_ON(tx_q->tx_skbuff[entry]); 3043 3044 if (likely(priv->extend_desc)) 3045 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3046 else 3047 desc = tx_q->dma_tx + entry; 3048 3049 des = skb_frag_dma_map(priv->device, frag, 0, len, 3050 DMA_TO_DEVICE); 3051 if (dma_mapping_error(priv->device, des)) 3052 goto dma_map_err; /* should reuse desc w/o issues */ 3053 3054 tx_q->tx_skbuff_dma[entry].buf = des; 3055 3056 stmmac_set_desc_addr(priv, desc, des); 3057 3058 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3059 tx_q->tx_skbuff_dma[entry].len = len; 3060 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3061 3062 /* Prepare the descriptor and set the own bit too */ 3063 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3064 priv->mode, 1, last_segment, skb->len); 3065 } 3066 3067 /* Only the last descriptor gets to point to the skb. */ 3068 tx_q->tx_skbuff[entry] = skb; 3069 3070 /* We've used all descriptors we need for this skb, however, 3071 * advance cur_tx so that it references a fresh descriptor. 3072 * ndo_start_xmit will fill this descriptor the next time it's 3073 * called and stmmac_tx_clean may clean up to this descriptor. 3074 */ 3075 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3076 tx_q->cur_tx = entry; 3077 3078 if (netif_msg_pktdata(priv)) { 3079 void *tx_head; 3080 3081 netdev_dbg(priv->dev, 3082 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3083 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3084 entry, first, nfrags); 3085 3086 if (priv->extend_desc) 3087 tx_head = (void *)tx_q->dma_etx; 3088 else 3089 tx_head = (void *)tx_q->dma_tx; 3090 3091 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false); 3092 3093 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3094 print_pkt(skb->data, skb->len); 3095 } 3096 3097 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3098 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3099 __func__); 3100 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3101 } 3102 3103 dev->stats.tx_bytes += skb->len; 3104 3105 /* According to the coalesce parameter the IC bit for the latest 3106 * segment is reset and the timer re-started to clean the tx status. 3107 * This approach takes care about the fragments: desc is the first 3108 * element in case of no SG. 3109 */ 3110 tx_q->tx_count_frames += nfrags + 1; 3111 if (priv->tx_coal_frames <= tx_q->tx_count_frames) { 3112 stmmac_set_tx_ic(priv, desc); 3113 priv->xstats.tx_set_ic_bit++; 3114 tx_q->tx_count_frames = 0; 3115 } else { 3116 stmmac_tx_timer_arm(priv, queue); 3117 } 3118 3119 skb_tx_timestamp(skb); 3120 3121 /* Ready to fill the first descriptor and set the OWN bit w/o any 3122 * problems because all the descriptors are actually ready to be 3123 * passed to the DMA engine. 3124 */ 3125 if (likely(!is_jumbo)) { 3126 bool last_segment = (nfrags == 0); 3127 3128 des = dma_map_single(priv->device, skb->data, 3129 nopaged_len, DMA_TO_DEVICE); 3130 if (dma_mapping_error(priv->device, des)) 3131 goto dma_map_err; 3132 3133 tx_q->tx_skbuff_dma[first_entry].buf = des; 3134 3135 stmmac_set_desc_addr(priv, first, des); 3136 3137 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3138 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3139 3140 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3141 priv->hwts_tx_en)) { 3142 /* declare that device is doing timestamping */ 3143 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3144 stmmac_enable_tx_timestamp(priv, first); 3145 } 3146 3147 /* Prepare the first descriptor setting the OWN bit too */ 3148 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3149 csum_insertion, priv->mode, 1, last_segment, 3150 skb->len); 3151 } else { 3152 stmmac_set_tx_owner(priv, first); 3153 } 3154 3155 /* The own bit must be the latest setting done when prepare the 3156 * descriptor and then barrier is needed to make sure that 3157 * all is coherent before granting the DMA engine. 3158 */ 3159 wmb(); 3160 3161 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3162 3163 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3164 3165 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3166 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3167 3168 return NETDEV_TX_OK; 3169 3170 dma_map_err: 3171 netdev_err(priv->dev, "Tx DMA map failed\n"); 3172 dev_kfree_skb(skb); 3173 priv->dev->stats.tx_dropped++; 3174 return NETDEV_TX_OK; 3175 } 3176 3177 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3178 { 3179 struct vlan_ethhdr *veth; 3180 __be16 vlan_proto; 3181 u16 vlanid; 3182 3183 veth = (struct vlan_ethhdr *)skb->data; 3184 vlan_proto = veth->h_vlan_proto; 3185 3186 if ((vlan_proto == htons(ETH_P_8021Q) && 3187 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3188 (vlan_proto == htons(ETH_P_8021AD) && 3189 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3190 /* pop the vlan tag */ 3191 vlanid = ntohs(veth->h_vlan_TCI); 3192 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3193 skb_pull(skb, VLAN_HLEN); 3194 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3195 } 3196 } 3197 3198 3199 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3200 { 3201 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3202 return 0; 3203 3204 return 1; 3205 } 3206 3207 /** 3208 * stmmac_rx_refill - refill used skb preallocated buffers 3209 * @priv: driver private structure 3210 * @queue: RX queue index 3211 * Description : this is to reallocate the skb for the reception process 3212 * that is based on zero-copy. 3213 */ 3214 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3215 { 3216 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3217 int dirty = stmmac_rx_dirty(priv, queue); 3218 unsigned int entry = rx_q->dirty_rx; 3219 3220 int bfsize = priv->dma_buf_sz; 3221 3222 while (dirty-- > 0) { 3223 struct dma_desc *p; 3224 3225 if (priv->extend_desc) 3226 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3227 else 3228 p = rx_q->dma_rx + entry; 3229 3230 if (likely(!rx_q->rx_skbuff[entry])) { 3231 struct sk_buff *skb; 3232 3233 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 3234 if (unlikely(!skb)) { 3235 /* so for a while no zero-copy! */ 3236 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH; 3237 if (unlikely(net_ratelimit())) 3238 dev_err(priv->device, 3239 "fail to alloc skb entry %d\n", 3240 entry); 3241 break; 3242 } 3243 3244 rx_q->rx_skbuff[entry] = skb; 3245 rx_q->rx_skbuff_dma[entry] = 3246 dma_map_single(priv->device, skb->data, bfsize, 3247 DMA_FROM_DEVICE); 3248 if (dma_mapping_error(priv->device, 3249 rx_q->rx_skbuff_dma[entry])) { 3250 netdev_err(priv->dev, "Rx DMA map failed\n"); 3251 dev_kfree_skb(skb); 3252 break; 3253 } 3254 3255 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]); 3256 stmmac_refill_desc3(priv, rx_q, p); 3257 3258 if (rx_q->rx_zeroc_thresh > 0) 3259 rx_q->rx_zeroc_thresh--; 3260 3261 netif_dbg(priv, rx_status, priv->dev, 3262 "refill entry #%d\n", entry); 3263 } 3264 dma_wmb(); 3265 3266 stmmac_set_rx_owner(priv, p, priv->use_riwt); 3267 3268 dma_wmb(); 3269 3270 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3271 } 3272 rx_q->dirty_rx = entry; 3273 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3274 } 3275 3276 /** 3277 * stmmac_rx - manage the receive process 3278 * @priv: driver private structure 3279 * @limit: napi bugget 3280 * @queue: RX queue index. 3281 * Description : this the function called by the napi poll method. 3282 * It gets all the frames inside the ring. 3283 */ 3284 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3285 { 3286 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3287 struct stmmac_channel *ch = &priv->channel[queue]; 3288 unsigned int next_entry = rx_q->cur_rx; 3289 int coe = priv->hw->rx_csum; 3290 unsigned int count = 0; 3291 bool xmac; 3292 3293 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 3294 3295 if (netif_msg_rx_status(priv)) { 3296 void *rx_head; 3297 3298 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3299 if (priv->extend_desc) 3300 rx_head = (void *)rx_q->dma_erx; 3301 else 3302 rx_head = (void *)rx_q->dma_rx; 3303 3304 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3305 } 3306 while (count < limit) { 3307 int entry, status; 3308 struct dma_desc *p; 3309 struct dma_desc *np; 3310 3311 entry = next_entry; 3312 3313 if (priv->extend_desc) 3314 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3315 else 3316 p = rx_q->dma_rx + entry; 3317 3318 /* read the status of the incoming frame */ 3319 status = stmmac_rx_status(priv, &priv->dev->stats, 3320 &priv->xstats, p); 3321 /* check if managed by the DMA otherwise go ahead */ 3322 if (unlikely(status & dma_own)) 3323 break; 3324 3325 count++; 3326 3327 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3328 next_entry = rx_q->cur_rx; 3329 3330 if (priv->extend_desc) 3331 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3332 else 3333 np = rx_q->dma_rx + next_entry; 3334 3335 prefetch(np); 3336 3337 if (priv->extend_desc) 3338 stmmac_rx_extended_status(priv, &priv->dev->stats, 3339 &priv->xstats, rx_q->dma_erx + entry); 3340 if (unlikely(status == discard_frame)) { 3341 priv->dev->stats.rx_errors++; 3342 if (priv->hwts_rx_en && !priv->extend_desc) { 3343 /* DESC2 & DESC3 will be overwritten by device 3344 * with timestamp value, hence reinitialize 3345 * them in stmmac_rx_refill() function so that 3346 * device can reuse it. 3347 */ 3348 dev_kfree_skb_any(rx_q->rx_skbuff[entry]); 3349 rx_q->rx_skbuff[entry] = NULL; 3350 dma_unmap_single(priv->device, 3351 rx_q->rx_skbuff_dma[entry], 3352 priv->dma_buf_sz, 3353 DMA_FROM_DEVICE); 3354 } 3355 } else { 3356 struct sk_buff *skb; 3357 int frame_len; 3358 unsigned int des; 3359 3360 stmmac_get_desc_addr(priv, p, &des); 3361 frame_len = stmmac_get_rx_frame_len(priv, p, coe); 3362 3363 /* If frame length is greater than skb buffer size 3364 * (preallocated during init) then the packet is 3365 * ignored 3366 */ 3367 if (frame_len > priv->dma_buf_sz) { 3368 if (net_ratelimit()) 3369 netdev_err(priv->dev, 3370 "len %d larger than size (%d)\n", 3371 frame_len, priv->dma_buf_sz); 3372 priv->dev->stats.rx_length_errors++; 3373 continue; 3374 } 3375 3376 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3377 * Type frames (LLC/LLC-SNAP) 3378 * 3379 * llc_snap is never checked in GMAC >= 4, so this ACS 3380 * feature is always disabled and packets need to be 3381 * stripped manually. 3382 */ 3383 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3384 unlikely(status != llc_snap)) 3385 frame_len -= ETH_FCS_LEN; 3386 3387 if (netif_msg_rx_status(priv)) { 3388 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n", 3389 p, entry, des); 3390 netdev_dbg(priv->dev, "frame size %d, COE: %d\n", 3391 frame_len, status); 3392 } 3393 3394 /* The zero-copy is always used for all the sizes 3395 * in case of GMAC4 because it needs 3396 * to refill the used descriptors, always. 3397 */ 3398 if (unlikely(!xmac && 3399 ((frame_len < priv->rx_copybreak) || 3400 stmmac_rx_threshold_count(rx_q)))) { 3401 skb = netdev_alloc_skb_ip_align(priv->dev, 3402 frame_len); 3403 if (unlikely(!skb)) { 3404 if (net_ratelimit()) 3405 dev_warn(priv->device, 3406 "packet dropped\n"); 3407 priv->dev->stats.rx_dropped++; 3408 continue; 3409 } 3410 3411 dma_sync_single_for_cpu(priv->device, 3412 rx_q->rx_skbuff_dma 3413 [entry], frame_len, 3414 DMA_FROM_DEVICE); 3415 skb_copy_to_linear_data(skb, 3416 rx_q-> 3417 rx_skbuff[entry]->data, 3418 frame_len); 3419 3420 skb_put(skb, frame_len); 3421 dma_sync_single_for_device(priv->device, 3422 rx_q->rx_skbuff_dma 3423 [entry], frame_len, 3424 DMA_FROM_DEVICE); 3425 } else { 3426 skb = rx_q->rx_skbuff[entry]; 3427 if (unlikely(!skb)) { 3428 if (net_ratelimit()) 3429 netdev_err(priv->dev, 3430 "%s: Inconsistent Rx chain\n", 3431 priv->dev->name); 3432 priv->dev->stats.rx_dropped++; 3433 continue; 3434 } 3435 prefetch(skb->data - NET_IP_ALIGN); 3436 rx_q->rx_skbuff[entry] = NULL; 3437 rx_q->rx_zeroc_thresh++; 3438 3439 skb_put(skb, frame_len); 3440 dma_unmap_single(priv->device, 3441 rx_q->rx_skbuff_dma[entry], 3442 priv->dma_buf_sz, 3443 DMA_FROM_DEVICE); 3444 } 3445 3446 if (netif_msg_pktdata(priv)) { 3447 netdev_dbg(priv->dev, "frame received (%dbytes)", 3448 frame_len); 3449 print_pkt(skb->data, frame_len); 3450 } 3451 3452 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3453 3454 stmmac_rx_vlan(priv->dev, skb); 3455 3456 skb->protocol = eth_type_trans(skb, priv->dev); 3457 3458 if (unlikely(!coe)) 3459 skb_checksum_none_assert(skb); 3460 else 3461 skb->ip_summed = CHECKSUM_UNNECESSARY; 3462 3463 napi_gro_receive(&ch->rx_napi, skb); 3464 3465 priv->dev->stats.rx_packets++; 3466 priv->dev->stats.rx_bytes += frame_len; 3467 } 3468 } 3469 3470 stmmac_rx_refill(priv, queue); 3471 3472 priv->xstats.rx_pkt_n += count; 3473 3474 return count; 3475 } 3476 3477 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3478 { 3479 struct stmmac_channel *ch = 3480 container_of(napi, struct stmmac_channel, rx_napi); 3481 struct stmmac_priv *priv = ch->priv_data; 3482 u32 chan = ch->index; 3483 int work_done; 3484 3485 priv->xstats.napi_poll++; 3486 3487 work_done = stmmac_rx(priv, budget, chan); 3488 if (work_done < budget && napi_complete_done(napi, work_done)) 3489 stmmac_enable_dma_irq(priv, priv->ioaddr, chan); 3490 return work_done; 3491 } 3492 3493 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3494 { 3495 struct stmmac_channel *ch = 3496 container_of(napi, struct stmmac_channel, tx_napi); 3497 struct stmmac_priv *priv = ch->priv_data; 3498 struct stmmac_tx_queue *tx_q; 3499 u32 chan = ch->index; 3500 int work_done; 3501 3502 priv->xstats.napi_poll++; 3503 3504 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3505 work_done = min(work_done, budget); 3506 3507 if (work_done < budget && napi_complete_done(napi, work_done)) 3508 stmmac_enable_dma_irq(priv, priv->ioaddr, chan); 3509 3510 /* Force transmission restart */ 3511 tx_q = &priv->tx_queue[chan]; 3512 if (tx_q->cur_tx != tx_q->dirty_tx) { 3513 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3514 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, 3515 chan); 3516 } 3517 3518 return work_done; 3519 } 3520 3521 /** 3522 * stmmac_tx_timeout 3523 * @dev : Pointer to net device structure 3524 * Description: this function is called when a packet transmission fails to 3525 * complete within a reasonable time. The driver will mark the error in the 3526 * netdev structure and arrange for the device to be reset to a sane state 3527 * in order to transmit a new packet. 3528 */ 3529 static void stmmac_tx_timeout(struct net_device *dev) 3530 { 3531 struct stmmac_priv *priv = netdev_priv(dev); 3532 3533 stmmac_global_err(priv); 3534 } 3535 3536 /** 3537 * stmmac_set_rx_mode - entry point for multicast addressing 3538 * @dev : pointer to the device structure 3539 * Description: 3540 * This function is a driver entry point which gets called by the kernel 3541 * whenever multicast addresses must be enabled/disabled. 3542 * Return value: 3543 * void. 3544 */ 3545 static void stmmac_set_rx_mode(struct net_device *dev) 3546 { 3547 struct stmmac_priv *priv = netdev_priv(dev); 3548 3549 stmmac_set_filter(priv, priv->hw, dev); 3550 } 3551 3552 /** 3553 * stmmac_change_mtu - entry point to change MTU size for the device. 3554 * @dev : device pointer. 3555 * @new_mtu : the new MTU size for the device. 3556 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3557 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3558 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3559 * Return value: 3560 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3561 * file on failure. 3562 */ 3563 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3564 { 3565 struct stmmac_priv *priv = netdev_priv(dev); 3566 3567 if (netif_running(dev)) { 3568 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3569 return -EBUSY; 3570 } 3571 3572 dev->mtu = new_mtu; 3573 3574 netdev_update_features(dev); 3575 3576 return 0; 3577 } 3578 3579 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3580 netdev_features_t features) 3581 { 3582 struct stmmac_priv *priv = netdev_priv(dev); 3583 3584 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3585 features &= ~NETIF_F_RXCSUM; 3586 3587 if (!priv->plat->tx_coe) 3588 features &= ~NETIF_F_CSUM_MASK; 3589 3590 /* Some GMAC devices have a bugged Jumbo frame support that 3591 * needs to have the Tx COE disabled for oversized frames 3592 * (due to limited buffer sizes). In this case we disable 3593 * the TX csum insertion in the TDES and not use SF. 3594 */ 3595 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3596 features &= ~NETIF_F_CSUM_MASK; 3597 3598 /* Disable tso if asked by ethtool */ 3599 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3600 if (features & NETIF_F_TSO) 3601 priv->tso = true; 3602 else 3603 priv->tso = false; 3604 } 3605 3606 return features; 3607 } 3608 3609 static int stmmac_set_features(struct net_device *netdev, 3610 netdev_features_t features) 3611 { 3612 struct stmmac_priv *priv = netdev_priv(netdev); 3613 3614 /* Keep the COE Type in case of csum is supporting */ 3615 if (features & NETIF_F_RXCSUM) 3616 priv->hw->rx_csum = priv->plat->rx_coe; 3617 else 3618 priv->hw->rx_csum = 0; 3619 /* No check needed because rx_coe has been set before and it will be 3620 * fixed in case of issue. 3621 */ 3622 stmmac_rx_ipc(priv, priv->hw); 3623 3624 return 0; 3625 } 3626 3627 /** 3628 * stmmac_interrupt - main ISR 3629 * @irq: interrupt number. 3630 * @dev_id: to pass the net device pointer. 3631 * Description: this is the main driver interrupt service routine. 3632 * It can call: 3633 * o DMA service routine (to manage incoming frame reception and transmission 3634 * status) 3635 * o Core interrupts to manage: remote wake-up, management counter, LPI 3636 * interrupts. 3637 */ 3638 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 3639 { 3640 struct net_device *dev = (struct net_device *)dev_id; 3641 struct stmmac_priv *priv = netdev_priv(dev); 3642 u32 rx_cnt = priv->plat->rx_queues_to_use; 3643 u32 tx_cnt = priv->plat->tx_queues_to_use; 3644 u32 queues_count; 3645 u32 queue; 3646 bool xmac; 3647 3648 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 3649 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 3650 3651 if (priv->irq_wake) 3652 pm_wakeup_event(priv->device, 0); 3653 3654 if (unlikely(!dev)) { 3655 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 3656 return IRQ_NONE; 3657 } 3658 3659 /* Check if adapter is up */ 3660 if (test_bit(STMMAC_DOWN, &priv->state)) 3661 return IRQ_HANDLED; 3662 /* Check if a fatal error happened */ 3663 if (stmmac_safety_feat_interrupt(priv)) 3664 return IRQ_HANDLED; 3665 3666 /* To handle GMAC own interrupts */ 3667 if ((priv->plat->has_gmac) || xmac) { 3668 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 3669 int mtl_status; 3670 3671 if (unlikely(status)) { 3672 /* For LPI we need to save the tx status */ 3673 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 3674 priv->tx_path_in_lpi_mode = true; 3675 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 3676 priv->tx_path_in_lpi_mode = false; 3677 } 3678 3679 for (queue = 0; queue < queues_count; queue++) { 3680 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3681 3682 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 3683 queue); 3684 if (mtl_status != -EINVAL) 3685 status |= mtl_status; 3686 3687 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 3688 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 3689 rx_q->rx_tail_addr, 3690 queue); 3691 } 3692 3693 /* PCS link status */ 3694 if (priv->hw->pcs) { 3695 if (priv->xstats.pcs_link) 3696 netif_carrier_on(dev); 3697 else 3698 netif_carrier_off(dev); 3699 } 3700 } 3701 3702 /* To handle DMA interrupts */ 3703 stmmac_dma_interrupt(priv); 3704 3705 return IRQ_HANDLED; 3706 } 3707 3708 #ifdef CONFIG_NET_POLL_CONTROLLER 3709 /* Polling receive - used by NETCONSOLE and other diagnostic tools 3710 * to allow network I/O with interrupts disabled. 3711 */ 3712 static void stmmac_poll_controller(struct net_device *dev) 3713 { 3714 disable_irq(dev->irq); 3715 stmmac_interrupt(dev->irq, dev); 3716 enable_irq(dev->irq); 3717 } 3718 #endif 3719 3720 /** 3721 * stmmac_ioctl - Entry point for the Ioctl 3722 * @dev: Device pointer. 3723 * @rq: An IOCTL specefic structure, that can contain a pointer to 3724 * a proprietary structure used to pass information to the driver. 3725 * @cmd: IOCTL command 3726 * Description: 3727 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 3728 */ 3729 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3730 { 3731 struct stmmac_priv *priv = netdev_priv (dev); 3732 int ret = -EOPNOTSUPP; 3733 3734 if (!netif_running(dev)) 3735 return -EINVAL; 3736 3737 switch (cmd) { 3738 case SIOCGMIIPHY: 3739 case SIOCGMIIREG: 3740 case SIOCSMIIREG: 3741 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 3742 break; 3743 case SIOCSHWTSTAMP: 3744 ret = stmmac_hwtstamp_set(dev, rq); 3745 break; 3746 case SIOCGHWTSTAMP: 3747 ret = stmmac_hwtstamp_get(dev, rq); 3748 break; 3749 default: 3750 break; 3751 } 3752 3753 return ret; 3754 } 3755 3756 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 3757 void *cb_priv) 3758 { 3759 struct stmmac_priv *priv = cb_priv; 3760 int ret = -EOPNOTSUPP; 3761 3762 stmmac_disable_all_queues(priv); 3763 3764 switch (type) { 3765 case TC_SETUP_CLSU32: 3766 if (tc_cls_can_offload_and_chain0(priv->dev, type_data)) 3767 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 3768 break; 3769 default: 3770 break; 3771 } 3772 3773 stmmac_enable_all_queues(priv); 3774 return ret; 3775 } 3776 3777 static int stmmac_setup_tc_block(struct stmmac_priv *priv, 3778 struct tc_block_offload *f) 3779 { 3780 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 3781 return -EOPNOTSUPP; 3782 3783 switch (f->command) { 3784 case TC_BLOCK_BIND: 3785 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb, 3786 priv, priv, f->extack); 3787 case TC_BLOCK_UNBIND: 3788 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv); 3789 return 0; 3790 default: 3791 return -EOPNOTSUPP; 3792 } 3793 } 3794 3795 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 3796 void *type_data) 3797 { 3798 struct stmmac_priv *priv = netdev_priv(ndev); 3799 3800 switch (type) { 3801 case TC_SETUP_BLOCK: 3802 return stmmac_setup_tc_block(priv, type_data); 3803 case TC_SETUP_QDISC_CBS: 3804 return stmmac_tc_setup_cbs(priv, priv, type_data); 3805 default: 3806 return -EOPNOTSUPP; 3807 } 3808 } 3809 3810 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 3811 { 3812 struct stmmac_priv *priv = netdev_priv(ndev); 3813 int ret = 0; 3814 3815 ret = eth_mac_addr(ndev, addr); 3816 if (ret) 3817 return ret; 3818 3819 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 3820 3821 return ret; 3822 } 3823 3824 #ifdef CONFIG_DEBUG_FS 3825 static struct dentry *stmmac_fs_dir; 3826 3827 static void sysfs_display_ring(void *head, int size, int extend_desc, 3828 struct seq_file *seq) 3829 { 3830 int i; 3831 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 3832 struct dma_desc *p = (struct dma_desc *)head; 3833 3834 for (i = 0; i < size; i++) { 3835 if (extend_desc) { 3836 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 3837 i, (unsigned int)virt_to_phys(ep), 3838 le32_to_cpu(ep->basic.des0), 3839 le32_to_cpu(ep->basic.des1), 3840 le32_to_cpu(ep->basic.des2), 3841 le32_to_cpu(ep->basic.des3)); 3842 ep++; 3843 } else { 3844 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 3845 i, (unsigned int)virt_to_phys(p), 3846 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 3847 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 3848 p++; 3849 } 3850 seq_printf(seq, "\n"); 3851 } 3852 } 3853 3854 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 3855 { 3856 struct net_device *dev = seq->private; 3857 struct stmmac_priv *priv = netdev_priv(dev); 3858 u32 rx_count = priv->plat->rx_queues_to_use; 3859 u32 tx_count = priv->plat->tx_queues_to_use; 3860 u32 queue; 3861 3862 if ((dev->flags & IFF_UP) == 0) 3863 return 0; 3864 3865 for (queue = 0; queue < rx_count; queue++) { 3866 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3867 3868 seq_printf(seq, "RX Queue %d:\n", queue); 3869 3870 if (priv->extend_desc) { 3871 seq_printf(seq, "Extended descriptor ring:\n"); 3872 sysfs_display_ring((void *)rx_q->dma_erx, 3873 DMA_RX_SIZE, 1, seq); 3874 } else { 3875 seq_printf(seq, "Descriptor ring:\n"); 3876 sysfs_display_ring((void *)rx_q->dma_rx, 3877 DMA_RX_SIZE, 0, seq); 3878 } 3879 } 3880 3881 for (queue = 0; queue < tx_count; queue++) { 3882 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3883 3884 seq_printf(seq, "TX Queue %d:\n", queue); 3885 3886 if (priv->extend_desc) { 3887 seq_printf(seq, "Extended descriptor ring:\n"); 3888 sysfs_display_ring((void *)tx_q->dma_etx, 3889 DMA_TX_SIZE, 1, seq); 3890 } else { 3891 seq_printf(seq, "Descriptor ring:\n"); 3892 sysfs_display_ring((void *)tx_q->dma_tx, 3893 DMA_TX_SIZE, 0, seq); 3894 } 3895 } 3896 3897 return 0; 3898 } 3899 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 3900 3901 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 3902 { 3903 struct net_device *dev = seq->private; 3904 struct stmmac_priv *priv = netdev_priv(dev); 3905 3906 if (!priv->hw_cap_support) { 3907 seq_printf(seq, "DMA HW features not supported\n"); 3908 return 0; 3909 } 3910 3911 seq_printf(seq, "==============================\n"); 3912 seq_printf(seq, "\tDMA HW features\n"); 3913 seq_printf(seq, "==============================\n"); 3914 3915 seq_printf(seq, "\t10/100 Mbps: %s\n", 3916 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 3917 seq_printf(seq, "\t1000 Mbps: %s\n", 3918 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 3919 seq_printf(seq, "\tHalf duplex: %s\n", 3920 (priv->dma_cap.half_duplex) ? "Y" : "N"); 3921 seq_printf(seq, "\tHash Filter: %s\n", 3922 (priv->dma_cap.hash_filter) ? "Y" : "N"); 3923 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 3924 (priv->dma_cap.multi_addr) ? "Y" : "N"); 3925 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 3926 (priv->dma_cap.pcs) ? "Y" : "N"); 3927 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 3928 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 3929 seq_printf(seq, "\tPMT Remote wake up: %s\n", 3930 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 3931 seq_printf(seq, "\tPMT Magic Frame: %s\n", 3932 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 3933 seq_printf(seq, "\tRMON module: %s\n", 3934 (priv->dma_cap.rmon) ? "Y" : "N"); 3935 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 3936 (priv->dma_cap.time_stamp) ? "Y" : "N"); 3937 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 3938 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 3939 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 3940 (priv->dma_cap.eee) ? "Y" : "N"); 3941 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 3942 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 3943 (priv->dma_cap.tx_coe) ? "Y" : "N"); 3944 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3945 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 3946 (priv->dma_cap.rx_coe) ? "Y" : "N"); 3947 } else { 3948 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 3949 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 3950 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 3951 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 3952 } 3953 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 3954 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 3955 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 3956 priv->dma_cap.number_rx_channel); 3957 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 3958 priv->dma_cap.number_tx_channel); 3959 seq_printf(seq, "\tEnhanced descriptors: %s\n", 3960 (priv->dma_cap.enh_desc) ? "Y" : "N"); 3961 3962 return 0; 3963 } 3964 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 3965 3966 static int stmmac_init_fs(struct net_device *dev) 3967 { 3968 struct stmmac_priv *priv = netdev_priv(dev); 3969 3970 /* Create per netdev entries */ 3971 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 3972 3973 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 3974 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n"); 3975 3976 return -ENOMEM; 3977 } 3978 3979 /* Entry to report DMA RX/TX rings */ 3980 priv->dbgfs_rings_status = 3981 debugfs_create_file("descriptors_status", 0444, 3982 priv->dbgfs_dir, dev, 3983 &stmmac_rings_status_fops); 3984 3985 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 3986 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n"); 3987 debugfs_remove_recursive(priv->dbgfs_dir); 3988 3989 return -ENOMEM; 3990 } 3991 3992 /* Entry to report the DMA HW features */ 3993 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444, 3994 priv->dbgfs_dir, 3995 dev, &stmmac_dma_cap_fops); 3996 3997 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 3998 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n"); 3999 debugfs_remove_recursive(priv->dbgfs_dir); 4000 4001 return -ENOMEM; 4002 } 4003 4004 return 0; 4005 } 4006 4007 static void stmmac_exit_fs(struct net_device *dev) 4008 { 4009 struct stmmac_priv *priv = netdev_priv(dev); 4010 4011 debugfs_remove_recursive(priv->dbgfs_dir); 4012 } 4013 #endif /* CONFIG_DEBUG_FS */ 4014 4015 static const struct net_device_ops stmmac_netdev_ops = { 4016 .ndo_open = stmmac_open, 4017 .ndo_start_xmit = stmmac_xmit, 4018 .ndo_stop = stmmac_release, 4019 .ndo_change_mtu = stmmac_change_mtu, 4020 .ndo_fix_features = stmmac_fix_features, 4021 .ndo_set_features = stmmac_set_features, 4022 .ndo_set_rx_mode = stmmac_set_rx_mode, 4023 .ndo_tx_timeout = stmmac_tx_timeout, 4024 .ndo_do_ioctl = stmmac_ioctl, 4025 .ndo_setup_tc = stmmac_setup_tc, 4026 #ifdef CONFIG_NET_POLL_CONTROLLER 4027 .ndo_poll_controller = stmmac_poll_controller, 4028 #endif 4029 .ndo_set_mac_address = stmmac_set_mac_address, 4030 }; 4031 4032 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4033 { 4034 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4035 return; 4036 if (test_bit(STMMAC_DOWN, &priv->state)) 4037 return; 4038 4039 netdev_err(priv->dev, "Reset adapter.\n"); 4040 4041 rtnl_lock(); 4042 netif_trans_update(priv->dev); 4043 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4044 usleep_range(1000, 2000); 4045 4046 set_bit(STMMAC_DOWN, &priv->state); 4047 dev_close(priv->dev); 4048 dev_open(priv->dev, NULL); 4049 clear_bit(STMMAC_DOWN, &priv->state); 4050 clear_bit(STMMAC_RESETING, &priv->state); 4051 rtnl_unlock(); 4052 } 4053 4054 static void stmmac_service_task(struct work_struct *work) 4055 { 4056 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4057 service_task); 4058 4059 stmmac_reset_subtask(priv); 4060 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4061 } 4062 4063 /** 4064 * stmmac_hw_init - Init the MAC device 4065 * @priv: driver private structure 4066 * Description: this function is to configure the MAC device according to 4067 * some platform parameters or the HW capability register. It prepares the 4068 * driver to use either ring or chain modes and to setup either enhanced or 4069 * normal descriptors. 4070 */ 4071 static int stmmac_hw_init(struct stmmac_priv *priv) 4072 { 4073 int ret; 4074 4075 /* dwmac-sun8i only work in chain mode */ 4076 if (priv->plat->has_sun8i) 4077 chain_mode = 1; 4078 priv->chain_mode = chain_mode; 4079 4080 /* Initialize HW Interface */ 4081 ret = stmmac_hwif_init(priv); 4082 if (ret) 4083 return ret; 4084 4085 /* Get the HW capability (new GMAC newer than 3.50a) */ 4086 priv->hw_cap_support = stmmac_get_hw_features(priv); 4087 if (priv->hw_cap_support) { 4088 dev_info(priv->device, "DMA HW capability register supported\n"); 4089 4090 /* We can override some gmac/dma configuration fields: e.g. 4091 * enh_desc, tx_coe (e.g. that are passed through the 4092 * platform) with the values from the HW capability 4093 * register (if supported). 4094 */ 4095 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4096 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4097 priv->hw->pmt = priv->plat->pmt; 4098 4099 /* TXCOE doesn't work in thresh DMA mode */ 4100 if (priv->plat->force_thresh_dma_mode) 4101 priv->plat->tx_coe = 0; 4102 else 4103 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4104 4105 /* In case of GMAC4 rx_coe is from HW cap register. */ 4106 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4107 4108 if (priv->dma_cap.rx_coe_type2) 4109 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4110 else if (priv->dma_cap.rx_coe_type1) 4111 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4112 4113 } else { 4114 dev_info(priv->device, "No HW DMA feature register supported\n"); 4115 } 4116 4117 if (priv->plat->rx_coe) { 4118 priv->hw->rx_csum = priv->plat->rx_coe; 4119 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4120 if (priv->synopsys_id < DWMAC_CORE_4_00) 4121 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4122 } 4123 if (priv->plat->tx_coe) 4124 dev_info(priv->device, "TX Checksum insertion supported\n"); 4125 4126 if (priv->plat->pmt) { 4127 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4128 device_set_wakeup_capable(priv->device, 1); 4129 } 4130 4131 if (priv->dma_cap.tsoen) 4132 dev_info(priv->device, "TSO supported\n"); 4133 4134 /* Run HW quirks, if any */ 4135 if (priv->hwif_quirks) { 4136 ret = priv->hwif_quirks(priv); 4137 if (ret) 4138 return ret; 4139 } 4140 4141 /* Rx Watchdog is available in the COREs newer than the 3.40. 4142 * In some case, for example on bugged HW this feature 4143 * has to be disable and this can be done by passing the 4144 * riwt_off field from the platform. 4145 */ 4146 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4147 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4148 priv->use_riwt = 1; 4149 dev_info(priv->device, 4150 "Enable RX Mitigation via HW Watchdog Timer\n"); 4151 } 4152 4153 return 0; 4154 } 4155 4156 /** 4157 * stmmac_dvr_probe 4158 * @device: device pointer 4159 * @plat_dat: platform data pointer 4160 * @res: stmmac resource pointer 4161 * Description: this is the main probe function used to 4162 * call the alloc_etherdev, allocate the priv structure. 4163 * Return: 4164 * returns 0 on success, otherwise errno. 4165 */ 4166 int stmmac_dvr_probe(struct device *device, 4167 struct plat_stmmacenet_data *plat_dat, 4168 struct stmmac_resources *res) 4169 { 4170 struct net_device *ndev = NULL; 4171 struct stmmac_priv *priv; 4172 u32 queue, maxq; 4173 int ret = 0; 4174 4175 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4176 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4177 if (!ndev) 4178 return -ENOMEM; 4179 4180 SET_NETDEV_DEV(ndev, device); 4181 4182 priv = netdev_priv(ndev); 4183 priv->device = device; 4184 priv->dev = ndev; 4185 4186 stmmac_set_ethtool_ops(ndev); 4187 priv->pause = pause; 4188 priv->plat = plat_dat; 4189 priv->ioaddr = res->addr; 4190 priv->dev->base_addr = (unsigned long)res->addr; 4191 4192 priv->dev->irq = res->irq; 4193 priv->wol_irq = res->wol_irq; 4194 priv->lpi_irq = res->lpi_irq; 4195 4196 if (!IS_ERR_OR_NULL(res->mac)) 4197 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4198 4199 dev_set_drvdata(device, priv->dev); 4200 4201 /* Verify driver arguments */ 4202 stmmac_verify_args(); 4203 4204 /* Allocate workqueue */ 4205 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4206 if (!priv->wq) { 4207 dev_err(priv->device, "failed to create workqueue\n"); 4208 return -ENOMEM; 4209 } 4210 4211 INIT_WORK(&priv->service_task, stmmac_service_task); 4212 4213 /* Override with kernel parameters if supplied XXX CRS XXX 4214 * this needs to have multiple instances 4215 */ 4216 if ((phyaddr >= 0) && (phyaddr <= 31)) 4217 priv->plat->phy_addr = phyaddr; 4218 4219 if (priv->plat->stmmac_rst) { 4220 ret = reset_control_assert(priv->plat->stmmac_rst); 4221 reset_control_deassert(priv->plat->stmmac_rst); 4222 /* Some reset controllers have only reset callback instead of 4223 * assert + deassert callbacks pair. 4224 */ 4225 if (ret == -ENOTSUPP) 4226 reset_control_reset(priv->plat->stmmac_rst); 4227 } 4228 4229 /* Init MAC and get the capabilities */ 4230 ret = stmmac_hw_init(priv); 4231 if (ret) 4232 goto error_hw_init; 4233 4234 stmmac_check_ether_addr(priv); 4235 4236 /* Configure real RX and TX queues */ 4237 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4238 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4239 4240 ndev->netdev_ops = &stmmac_netdev_ops; 4241 4242 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4243 NETIF_F_RXCSUM; 4244 4245 ret = stmmac_tc_init(priv, priv); 4246 if (!ret) { 4247 ndev->hw_features |= NETIF_F_HW_TC; 4248 } 4249 4250 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4251 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4252 priv->tso = true; 4253 dev_info(priv->device, "TSO feature enabled\n"); 4254 } 4255 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4256 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4257 #ifdef STMMAC_VLAN_TAG_USED 4258 /* Both mac100 and gmac support receive VLAN tag detection */ 4259 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4260 #endif 4261 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4262 4263 /* MTU range: 46 - hw-specific max */ 4264 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4265 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4266 ndev->max_mtu = JUMBO_LEN; 4267 else if (priv->plat->has_xgmac) 4268 ndev->max_mtu = XGMAC_JUMBO_LEN; 4269 else 4270 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4271 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4272 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4273 */ 4274 if ((priv->plat->maxmtu < ndev->max_mtu) && 4275 (priv->plat->maxmtu >= ndev->min_mtu)) 4276 ndev->max_mtu = priv->plat->maxmtu; 4277 else if (priv->plat->maxmtu < ndev->min_mtu) 4278 dev_warn(priv->device, 4279 "%s: warning: maxmtu having invalid value (%d)\n", 4280 __func__, priv->plat->maxmtu); 4281 4282 if (flow_ctrl) 4283 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4284 4285 /* Setup channels NAPI */ 4286 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4287 4288 for (queue = 0; queue < maxq; queue++) { 4289 struct stmmac_channel *ch = &priv->channel[queue]; 4290 4291 ch->priv_data = priv; 4292 ch->index = queue; 4293 4294 if (queue < priv->plat->rx_queues_to_use) { 4295 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4296 NAPI_POLL_WEIGHT); 4297 } 4298 if (queue < priv->plat->tx_queues_to_use) { 4299 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx, 4300 NAPI_POLL_WEIGHT); 4301 } 4302 } 4303 4304 mutex_init(&priv->lock); 4305 4306 /* If a specific clk_csr value is passed from the platform 4307 * this means that the CSR Clock Range selection cannot be 4308 * changed at run-time and it is fixed. Viceversa the driver'll try to 4309 * set the MDC clock dynamically according to the csr actual 4310 * clock input. 4311 */ 4312 if (priv->plat->clk_csr >= 0) 4313 priv->clk_csr = priv->plat->clk_csr; 4314 else 4315 stmmac_clk_csr_set(priv); 4316 4317 stmmac_check_pcs_mode(priv); 4318 4319 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4320 priv->hw->pcs != STMMAC_PCS_TBI && 4321 priv->hw->pcs != STMMAC_PCS_RTBI) { 4322 /* MDIO bus Registration */ 4323 ret = stmmac_mdio_register(ndev); 4324 if (ret < 0) { 4325 dev_err(priv->device, 4326 "%s: MDIO bus (id: %d) registration failed", 4327 __func__, priv->plat->bus_id); 4328 goto error_mdio_register; 4329 } 4330 } 4331 4332 ret = stmmac_phy_setup(priv); 4333 if (ret) { 4334 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4335 goto error_phy_setup; 4336 } 4337 4338 ret = register_netdev(ndev); 4339 if (ret) { 4340 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4341 __func__, ret); 4342 goto error_netdev_register; 4343 } 4344 4345 #ifdef CONFIG_DEBUG_FS 4346 ret = stmmac_init_fs(ndev); 4347 if (ret < 0) 4348 netdev_warn(priv->dev, "%s: failed debugFS registration\n", 4349 __func__); 4350 #endif 4351 4352 return ret; 4353 4354 error_netdev_register: 4355 phylink_destroy(priv->phylink); 4356 error_phy_setup: 4357 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4358 priv->hw->pcs != STMMAC_PCS_TBI && 4359 priv->hw->pcs != STMMAC_PCS_RTBI) 4360 stmmac_mdio_unregister(ndev); 4361 error_mdio_register: 4362 for (queue = 0; queue < maxq; queue++) { 4363 struct stmmac_channel *ch = &priv->channel[queue]; 4364 4365 if (queue < priv->plat->rx_queues_to_use) 4366 netif_napi_del(&ch->rx_napi); 4367 if (queue < priv->plat->tx_queues_to_use) 4368 netif_napi_del(&ch->tx_napi); 4369 } 4370 error_hw_init: 4371 destroy_workqueue(priv->wq); 4372 4373 return ret; 4374 } 4375 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4376 4377 /** 4378 * stmmac_dvr_remove 4379 * @dev: device pointer 4380 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4381 * changes the link status, releases the DMA descriptor rings. 4382 */ 4383 int stmmac_dvr_remove(struct device *dev) 4384 { 4385 struct net_device *ndev = dev_get_drvdata(dev); 4386 struct stmmac_priv *priv = netdev_priv(ndev); 4387 4388 netdev_info(priv->dev, "%s: removing driver", __func__); 4389 4390 #ifdef CONFIG_DEBUG_FS 4391 stmmac_exit_fs(ndev); 4392 #endif 4393 stmmac_stop_all_dma(priv); 4394 4395 stmmac_mac_set(priv, priv->ioaddr, false); 4396 netif_carrier_off(ndev); 4397 unregister_netdev(ndev); 4398 phylink_destroy(priv->phylink); 4399 if (priv->plat->stmmac_rst) 4400 reset_control_assert(priv->plat->stmmac_rst); 4401 clk_disable_unprepare(priv->plat->pclk); 4402 clk_disable_unprepare(priv->plat->stmmac_clk); 4403 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4404 priv->hw->pcs != STMMAC_PCS_TBI && 4405 priv->hw->pcs != STMMAC_PCS_RTBI) 4406 stmmac_mdio_unregister(ndev); 4407 destroy_workqueue(priv->wq); 4408 mutex_destroy(&priv->lock); 4409 4410 return 0; 4411 } 4412 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4413 4414 /** 4415 * stmmac_suspend - suspend callback 4416 * @dev: device pointer 4417 * Description: this is the function to suspend the device and it is called 4418 * by the platform driver to stop the network queue, release the resources, 4419 * program the PMT register (for WoL), clean and release driver resources. 4420 */ 4421 int stmmac_suspend(struct device *dev) 4422 { 4423 struct net_device *ndev = dev_get_drvdata(dev); 4424 struct stmmac_priv *priv = netdev_priv(ndev); 4425 4426 if (!ndev || !netif_running(ndev)) 4427 return 0; 4428 4429 phylink_stop(priv->phylink); 4430 4431 mutex_lock(&priv->lock); 4432 4433 netif_device_detach(ndev); 4434 stmmac_stop_all_queues(priv); 4435 4436 stmmac_disable_all_queues(priv); 4437 4438 /* Stop TX/RX DMA */ 4439 stmmac_stop_all_dma(priv); 4440 4441 /* Enable Power down mode by programming the PMT regs */ 4442 if (device_may_wakeup(priv->device)) { 4443 stmmac_pmt(priv, priv->hw, priv->wolopts); 4444 priv->irq_wake = 1; 4445 } else { 4446 stmmac_mac_set(priv, priv->ioaddr, false); 4447 pinctrl_pm_select_sleep_state(priv->device); 4448 /* Disable clock in case of PWM is off */ 4449 clk_disable(priv->plat->pclk); 4450 clk_disable(priv->plat->stmmac_clk); 4451 } 4452 mutex_unlock(&priv->lock); 4453 4454 priv->speed = SPEED_UNKNOWN; 4455 return 0; 4456 } 4457 EXPORT_SYMBOL_GPL(stmmac_suspend); 4458 4459 /** 4460 * stmmac_reset_queues_param - reset queue parameters 4461 * @dev: device pointer 4462 */ 4463 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 4464 { 4465 u32 rx_cnt = priv->plat->rx_queues_to_use; 4466 u32 tx_cnt = priv->plat->tx_queues_to_use; 4467 u32 queue; 4468 4469 for (queue = 0; queue < rx_cnt; queue++) { 4470 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4471 4472 rx_q->cur_rx = 0; 4473 rx_q->dirty_rx = 0; 4474 } 4475 4476 for (queue = 0; queue < tx_cnt; queue++) { 4477 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4478 4479 tx_q->cur_tx = 0; 4480 tx_q->dirty_tx = 0; 4481 tx_q->mss = 0; 4482 } 4483 } 4484 4485 /** 4486 * stmmac_resume - resume callback 4487 * @dev: device pointer 4488 * Description: when resume this function is invoked to setup the DMA and CORE 4489 * in a usable state. 4490 */ 4491 int stmmac_resume(struct device *dev) 4492 { 4493 struct net_device *ndev = dev_get_drvdata(dev); 4494 struct stmmac_priv *priv = netdev_priv(ndev); 4495 4496 if (!netif_running(ndev)) 4497 return 0; 4498 4499 /* Power Down bit, into the PM register, is cleared 4500 * automatically as soon as a magic packet or a Wake-up frame 4501 * is received. Anyway, it's better to manually clear 4502 * this bit because it can generate problems while resuming 4503 * from another devices (e.g. serial console). 4504 */ 4505 if (device_may_wakeup(priv->device)) { 4506 mutex_lock(&priv->lock); 4507 stmmac_pmt(priv, priv->hw, 0); 4508 mutex_unlock(&priv->lock); 4509 priv->irq_wake = 0; 4510 } else { 4511 pinctrl_pm_select_default_state(priv->device); 4512 /* enable the clk previously disabled */ 4513 clk_enable(priv->plat->stmmac_clk); 4514 clk_enable(priv->plat->pclk); 4515 /* reset the phy so that it's ready */ 4516 if (priv->mii) 4517 stmmac_mdio_reset(priv->mii); 4518 } 4519 4520 netif_device_attach(ndev); 4521 4522 mutex_lock(&priv->lock); 4523 4524 stmmac_reset_queues_param(priv); 4525 4526 stmmac_clear_descriptors(priv); 4527 4528 stmmac_hw_setup(ndev, false); 4529 stmmac_init_tx_coalesce(priv); 4530 stmmac_set_rx_mode(ndev); 4531 4532 stmmac_enable_all_queues(priv); 4533 4534 stmmac_start_all_queues(priv); 4535 4536 mutex_unlock(&priv->lock); 4537 4538 phylink_start(priv->phylink); 4539 4540 return 0; 4541 } 4542 EXPORT_SYMBOL_GPL(stmmac_resume); 4543 4544 #ifndef MODULE 4545 static int __init stmmac_cmdline_opt(char *str) 4546 { 4547 char *opt; 4548 4549 if (!str || !*str) 4550 return -EINVAL; 4551 while ((opt = strsep(&str, ",")) != NULL) { 4552 if (!strncmp(opt, "debug:", 6)) { 4553 if (kstrtoint(opt + 6, 0, &debug)) 4554 goto err; 4555 } else if (!strncmp(opt, "phyaddr:", 8)) { 4556 if (kstrtoint(opt + 8, 0, &phyaddr)) 4557 goto err; 4558 } else if (!strncmp(opt, "buf_sz:", 7)) { 4559 if (kstrtoint(opt + 7, 0, &buf_sz)) 4560 goto err; 4561 } else if (!strncmp(opt, "tc:", 3)) { 4562 if (kstrtoint(opt + 3, 0, &tc)) 4563 goto err; 4564 } else if (!strncmp(opt, "watchdog:", 9)) { 4565 if (kstrtoint(opt + 9, 0, &watchdog)) 4566 goto err; 4567 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 4568 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 4569 goto err; 4570 } else if (!strncmp(opt, "pause:", 6)) { 4571 if (kstrtoint(opt + 6, 0, &pause)) 4572 goto err; 4573 } else if (!strncmp(opt, "eee_timer:", 10)) { 4574 if (kstrtoint(opt + 10, 0, &eee_timer)) 4575 goto err; 4576 } else if (!strncmp(opt, "chain_mode:", 11)) { 4577 if (kstrtoint(opt + 11, 0, &chain_mode)) 4578 goto err; 4579 } 4580 } 4581 return 0; 4582 4583 err: 4584 pr_err("%s: ERROR broken module parameter conversion", __func__); 4585 return -EINVAL; 4586 } 4587 4588 __setup("stmmaceth=", stmmac_cmdline_opt); 4589 #endif /* MODULE */ 4590 4591 static int __init stmmac_init(void) 4592 { 4593 #ifdef CONFIG_DEBUG_FS 4594 /* Create debugfs main directory if it doesn't exist yet */ 4595 if (!stmmac_fs_dir) { 4596 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 4597 4598 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 4599 pr_err("ERROR %s, debugfs create directory failed\n", 4600 STMMAC_RESOURCE_NAME); 4601 4602 return -ENOMEM; 4603 } 4604 } 4605 #endif 4606 4607 return 0; 4608 } 4609 4610 static void __exit stmmac_exit(void) 4611 { 4612 #ifdef CONFIG_DEBUG_FS 4613 debugfs_remove_recursive(stmmac_fs_dir); 4614 #endif 4615 } 4616 4617 module_init(stmmac_init) 4618 module_exit(stmmac_exit) 4619 4620 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 4621 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 4622 MODULE_LICENSE("GPL"); 4623