1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 67 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 /** 180 * stmmac_stop_all_queues - Stop all queues 181 * @priv: driver private structure 182 */ 183 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 184 { 185 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 186 u32 queue; 187 188 for (queue = 0; queue < tx_queues_cnt; queue++) 189 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 190 } 191 192 /** 193 * stmmac_start_all_queues - Start all queues 194 * @priv: driver private structure 195 */ 196 static void stmmac_start_all_queues(struct stmmac_priv *priv) 197 { 198 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 199 u32 queue; 200 201 for (queue = 0; queue < tx_queues_cnt; queue++) 202 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 203 } 204 205 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 206 { 207 if (!test_bit(STMMAC_DOWN, &priv->state) && 208 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 209 queue_work(priv->wq, &priv->service_task); 210 } 211 212 static void stmmac_global_err(struct stmmac_priv *priv) 213 { 214 netif_carrier_off(priv->dev); 215 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 216 stmmac_service_event_schedule(priv); 217 } 218 219 /** 220 * stmmac_clk_csr_set - dynamically set the MDC clock 221 * @priv: driver private structure 222 * Description: this is to dynamically set the MDC clock according to the csr 223 * clock input. 224 * Note: 225 * If a specific clk_csr value is passed from the platform 226 * this means that the CSR Clock Range selection cannot be 227 * changed at run-time and it is fixed (as reported in the driver 228 * documentation). Viceversa the driver will try to set the MDC 229 * clock dynamically according to the actual clock input. 230 */ 231 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 232 { 233 u32 clk_rate; 234 235 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 236 237 /* Platform provided default clk_csr would be assumed valid 238 * for all other cases except for the below mentioned ones. 239 * For values higher than the IEEE 802.3 specified frequency 240 * we can not estimate the proper divider as it is not known 241 * the frequency of clk_csr_i. So we do not change the default 242 * divider. 243 */ 244 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 245 if (clk_rate < CSR_F_35M) 246 priv->clk_csr = STMMAC_CSR_20_35M; 247 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 248 priv->clk_csr = STMMAC_CSR_35_60M; 249 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 250 priv->clk_csr = STMMAC_CSR_60_100M; 251 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 252 priv->clk_csr = STMMAC_CSR_100_150M; 253 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 254 priv->clk_csr = STMMAC_CSR_150_250M; 255 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 256 priv->clk_csr = STMMAC_CSR_250_300M; 257 } 258 259 if (priv->plat->has_sun8i) { 260 if (clk_rate > 160000000) 261 priv->clk_csr = 0x03; 262 else if (clk_rate > 80000000) 263 priv->clk_csr = 0x02; 264 else if (clk_rate > 40000000) 265 priv->clk_csr = 0x01; 266 else 267 priv->clk_csr = 0; 268 } 269 270 if (priv->plat->has_xgmac) { 271 if (clk_rate > 400000000) 272 priv->clk_csr = 0x5; 273 else if (clk_rate > 350000000) 274 priv->clk_csr = 0x4; 275 else if (clk_rate > 300000000) 276 priv->clk_csr = 0x3; 277 else if (clk_rate > 250000000) 278 priv->clk_csr = 0x2; 279 else if (clk_rate > 150000000) 280 priv->clk_csr = 0x1; 281 else 282 priv->clk_csr = 0x0; 283 } 284 } 285 286 static void print_pkt(unsigned char *buf, int len) 287 { 288 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 289 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 290 } 291 292 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 293 { 294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 295 u32 avail; 296 297 if (tx_q->dirty_tx > tx_q->cur_tx) 298 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 299 else 300 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 301 302 return avail; 303 } 304 305 /** 306 * stmmac_rx_dirty - Get RX queue dirty 307 * @priv: driver private structure 308 * @queue: RX queue index 309 */ 310 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 311 { 312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 313 u32 dirty; 314 315 if (rx_q->dirty_rx <= rx_q->cur_rx) 316 dirty = rx_q->cur_rx - rx_q->dirty_rx; 317 else 318 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 319 320 return dirty; 321 } 322 323 /** 324 * stmmac_enable_eee_mode - check and enter in LPI mode 325 * @priv: driver private structure 326 * Description: this function is to verify and enter in LPI mode in case of 327 * EEE. 328 */ 329 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 330 { 331 u32 tx_cnt = priv->plat->tx_queues_to_use; 332 u32 queue; 333 334 /* check if all TX queues have the work finished */ 335 for (queue = 0; queue < tx_cnt; queue++) { 336 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 337 338 if (tx_q->dirty_tx != tx_q->cur_tx) 339 return; /* still unfinished work */ 340 } 341 342 /* Check and enter in LPI mode */ 343 if (!priv->tx_path_in_lpi_mode) 344 stmmac_set_eee_mode(priv, priv->hw, 345 priv->plat->en_tx_lpi_clockgating); 346 } 347 348 /** 349 * stmmac_disable_eee_mode - disable and exit from LPI mode 350 * @priv: driver private structure 351 * Description: this function is to exit and disable EEE in case of 352 * LPI state is true. This is called by the xmit. 353 */ 354 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 355 { 356 stmmac_reset_eee_mode(priv, priv->hw); 357 del_timer_sync(&priv->eee_ctrl_timer); 358 priv->tx_path_in_lpi_mode = false; 359 } 360 361 /** 362 * stmmac_eee_ctrl_timer - EEE TX SW timer. 363 * @arg : data hook 364 * Description: 365 * if there is no data transfer and if we are not in LPI state, 366 * then MAC Transmitter can be moved to LPI state. 367 */ 368 static void stmmac_eee_ctrl_timer(struct timer_list *t) 369 { 370 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 371 372 stmmac_enable_eee_mode(priv); 373 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 374 } 375 376 /** 377 * stmmac_eee_init - init EEE 378 * @priv: driver private structure 379 * Description: 380 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 381 * can also manage EEE, this function enable the LPI state and start related 382 * timer. 383 */ 384 bool stmmac_eee_init(struct stmmac_priv *priv) 385 { 386 int tx_lpi_timer = priv->tx_lpi_timer; 387 388 /* Using PCS we cannot dial with the phy registers at this stage 389 * so we do not support extra feature like EEE. 390 */ 391 if (priv->hw->pcs == STMMAC_PCS_TBI || 392 priv->hw->pcs == STMMAC_PCS_RTBI) 393 return false; 394 395 /* Check if MAC core supports the EEE feature. */ 396 if (!priv->dma_cap.eee) 397 return false; 398 399 mutex_lock(&priv->lock); 400 401 /* Check if it needs to be deactivated */ 402 if (!priv->eee_active) { 403 if (priv->eee_enabled) { 404 netdev_dbg(priv->dev, "disable EEE\n"); 405 del_timer_sync(&priv->eee_ctrl_timer); 406 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 407 } 408 mutex_unlock(&priv->lock); 409 return false; 410 } 411 412 if (priv->eee_active && !priv->eee_enabled) { 413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 414 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 415 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 416 tx_lpi_timer); 417 } 418 419 mutex_unlock(&priv->lock); 420 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 421 return true; 422 } 423 424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 425 * @priv: driver private structure 426 * @p : descriptor pointer 427 * @skb : the socket buffer 428 * Description : 429 * This function will read timestamp from the descriptor & pass it to stack. 430 * and also perform some sanity checks. 431 */ 432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 433 struct dma_desc *p, struct sk_buff *skb) 434 { 435 struct skb_shared_hwtstamps shhwtstamp; 436 bool found = false; 437 u64 ns = 0; 438 439 if (!priv->hwts_tx_en) 440 return; 441 442 /* exit if skb doesn't support hw tstamp */ 443 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 444 return; 445 446 /* check tx tstamp status */ 447 if (stmmac_get_tx_timestamp_status(priv, p)) { 448 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 449 found = true; 450 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 451 found = true; 452 } 453 454 if (found) { 455 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 456 shhwtstamp.hwtstamp = ns_to_ktime(ns); 457 458 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 459 /* pass tstamp to stack */ 460 skb_tstamp_tx(skb, &shhwtstamp); 461 } 462 } 463 464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 465 * @priv: driver private structure 466 * @p : descriptor pointer 467 * @np : next descriptor pointer 468 * @skb : the socket buffer 469 * Description : 470 * This function will read received packet's timestamp from the descriptor 471 * and pass it to stack. It also perform some sanity checks. 472 */ 473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 474 struct dma_desc *np, struct sk_buff *skb) 475 { 476 struct skb_shared_hwtstamps *shhwtstamp = NULL; 477 struct dma_desc *desc = p; 478 u64 ns = 0; 479 480 if (!priv->hwts_rx_en) 481 return; 482 /* For GMAC4, the valid timestamp is from CTX next desc. */ 483 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 484 desc = np; 485 486 /* Check if timestamp is available */ 487 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 488 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 489 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 490 shhwtstamp = skb_hwtstamps(skb); 491 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 492 shhwtstamp->hwtstamp = ns_to_ktime(ns); 493 } else { 494 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 495 } 496 } 497 498 /** 499 * stmmac_hwtstamp_set - control hardware timestamping. 500 * @dev: device pointer. 501 * @ifr: An IOCTL specific structure, that can contain a pointer to 502 * a proprietary structure used to pass information to the driver. 503 * Description: 504 * This function configures the MAC to enable/disable both outgoing(TX) 505 * and incoming(RX) packets time stamping based on user input. 506 * Return Value: 507 * 0 on success and an appropriate -ve integer on failure. 508 */ 509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 510 { 511 struct stmmac_priv *priv = netdev_priv(dev); 512 struct hwtstamp_config config; 513 struct timespec64 now; 514 u64 temp = 0; 515 u32 ptp_v2 = 0; 516 u32 tstamp_all = 0; 517 u32 ptp_over_ipv4_udp = 0; 518 u32 ptp_over_ipv6_udp = 0; 519 u32 ptp_over_ethernet = 0; 520 u32 snap_type_sel = 0; 521 u32 ts_master_en = 0; 522 u32 ts_event_en = 0; 523 u32 sec_inc = 0; 524 u32 value = 0; 525 bool xmac; 526 527 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 528 529 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 530 netdev_alert(priv->dev, "No support for HW time stamping\n"); 531 priv->hwts_tx_en = 0; 532 priv->hwts_rx_en = 0; 533 534 return -EOPNOTSUPP; 535 } 536 537 if (copy_from_user(&config, ifr->ifr_data, 538 sizeof(config))) 539 return -EFAULT; 540 541 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 542 __func__, config.flags, config.tx_type, config.rx_filter); 543 544 /* reserved for future extensions */ 545 if (config.flags) 546 return -EINVAL; 547 548 if (config.tx_type != HWTSTAMP_TX_OFF && 549 config.tx_type != HWTSTAMP_TX_ON) 550 return -ERANGE; 551 552 if (priv->adv_ts) { 553 switch (config.rx_filter) { 554 case HWTSTAMP_FILTER_NONE: 555 /* time stamp no incoming packet at all */ 556 config.rx_filter = HWTSTAMP_FILTER_NONE; 557 break; 558 559 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 560 /* PTP v1, UDP, any kind of event packet */ 561 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 562 /* 'xmac' hardware can support Sync, Pdelay_Req and 563 * Pdelay_resp by setting bit14 and bits17/16 to 01 564 * This leaves Delay_Req timestamps out. 565 * Enable all events *and* general purpose message 566 * timestamping 567 */ 568 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 571 break; 572 573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 574 /* PTP v1, UDP, Sync packet */ 575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 576 /* take time stamp for SYNC messages only */ 577 ts_event_en = PTP_TCR_TSEVNTENA; 578 579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 581 break; 582 583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 584 /* PTP v1, UDP, Delay_req packet */ 585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 586 /* take time stamp for Delay_Req messages only */ 587 ts_master_en = PTP_TCR_TSMSTRENA; 588 ts_event_en = PTP_TCR_TSEVNTENA; 589 590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 592 break; 593 594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 595 /* PTP v2, UDP, any kind of event packet */ 596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 597 ptp_v2 = PTP_TCR_TSVER2ENA; 598 /* take time stamp for all event messages */ 599 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 600 601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 603 break; 604 605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 606 /* PTP v2, UDP, Sync packet */ 607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 608 ptp_v2 = PTP_TCR_TSVER2ENA; 609 /* take time stamp for SYNC messages only */ 610 ts_event_en = PTP_TCR_TSEVNTENA; 611 612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 614 break; 615 616 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 617 /* PTP v2, UDP, Delay_req packet */ 618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 619 ptp_v2 = PTP_TCR_TSVER2ENA; 620 /* take time stamp for Delay_Req messages only */ 621 ts_master_en = PTP_TCR_TSMSTRENA; 622 ts_event_en = PTP_TCR_TSEVNTENA; 623 624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 626 break; 627 628 case HWTSTAMP_FILTER_PTP_V2_EVENT: 629 /* PTP v2/802.AS1 any layer, any kind of event packet */ 630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 631 ptp_v2 = PTP_TCR_TSVER2ENA; 632 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 633 ts_event_en = PTP_TCR_TSEVNTENA; 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 636 ptp_over_ethernet = PTP_TCR_TSIPENA; 637 break; 638 639 case HWTSTAMP_FILTER_PTP_V2_SYNC: 640 /* PTP v2/802.AS1, any layer, Sync packet */ 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 642 ptp_v2 = PTP_TCR_TSVER2ENA; 643 /* take time stamp for SYNC messages only */ 644 ts_event_en = PTP_TCR_TSEVNTENA; 645 646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 648 ptp_over_ethernet = PTP_TCR_TSIPENA; 649 break; 650 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 652 /* PTP v2/802.AS1, any layer, Delay_req packet */ 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 654 ptp_v2 = PTP_TCR_TSVER2ENA; 655 /* take time stamp for Delay_Req messages only */ 656 ts_master_en = PTP_TCR_TSMSTRENA; 657 ts_event_en = PTP_TCR_TSEVNTENA; 658 659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 661 ptp_over_ethernet = PTP_TCR_TSIPENA; 662 break; 663 664 case HWTSTAMP_FILTER_NTP_ALL: 665 case HWTSTAMP_FILTER_ALL: 666 /* time stamp any incoming packet */ 667 config.rx_filter = HWTSTAMP_FILTER_ALL; 668 tstamp_all = PTP_TCR_TSENALL; 669 break; 670 671 default: 672 return -ERANGE; 673 } 674 } else { 675 switch (config.rx_filter) { 676 case HWTSTAMP_FILTER_NONE: 677 config.rx_filter = HWTSTAMP_FILTER_NONE; 678 break; 679 default: 680 /* PTP v1, UDP, any kind of event packet */ 681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 682 break; 683 } 684 } 685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 687 688 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 690 else { 691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 692 tstamp_all | ptp_v2 | ptp_over_ethernet | 693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 694 ts_master_en | snap_type_sel); 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 696 697 /* program Sub Second Increment reg */ 698 stmmac_config_sub_second_increment(priv, 699 priv->ptpaddr, priv->plat->clk_ptp_rate, 700 xmac, &sec_inc); 701 temp = div_u64(1000000000ULL, sec_inc); 702 703 /* Store sub second increment and flags for later use */ 704 priv->sub_second_inc = sec_inc; 705 priv->systime_flags = value; 706 707 /* calculate default added value: 708 * formula is : 709 * addend = (2^32)/freq_div_ratio; 710 * where, freq_div_ratio = 1e9ns/sec_inc 711 */ 712 temp = (u64)(temp << 32); 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 715 716 /* initialize system time */ 717 ktime_get_real_ts64(&now); 718 719 /* lower 32 bits of tv_sec are safe until y2106 */ 720 stmmac_init_systime(priv, priv->ptpaddr, 721 (u32)now.tv_sec, now.tv_nsec); 722 } 723 724 memcpy(&priv->tstamp_config, &config, sizeof(config)); 725 726 return copy_to_user(ifr->ifr_data, &config, 727 sizeof(config)) ? -EFAULT : 0; 728 } 729 730 /** 731 * stmmac_hwtstamp_get - read hardware timestamping. 732 * @dev: device pointer. 733 * @ifr: An IOCTL specific structure, that can contain a pointer to 734 * a proprietary structure used to pass information to the driver. 735 * Description: 736 * This function obtain the current hardware timestamping settings 737 as requested. 738 */ 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 740 { 741 struct stmmac_priv *priv = netdev_priv(dev); 742 struct hwtstamp_config *config = &priv->tstamp_config; 743 744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 745 return -EOPNOTSUPP; 746 747 return copy_to_user(ifr->ifr_data, config, 748 sizeof(*config)) ? -EFAULT : 0; 749 } 750 751 /** 752 * stmmac_init_ptp - init PTP 753 * @priv: driver private structure 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 755 * This is done by looking at the HW cap. register. 756 * This function also registers the ptp driver. 757 */ 758 static int stmmac_init_ptp(struct stmmac_priv *priv) 759 { 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 761 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 763 return -EOPNOTSUPP; 764 765 priv->adv_ts = 0; 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 767 if (xmac && priv->dma_cap.atime_stamp) 768 priv->adv_ts = 1; 769 /* Dwmac 3.x core with extend_desc can support adv_ts */ 770 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 771 priv->adv_ts = 1; 772 773 if (priv->dma_cap.time_stamp) 774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 775 776 if (priv->adv_ts) 777 netdev_info(priv->dev, 778 "IEEE 1588-2008 Advanced Timestamp supported\n"); 779 780 priv->hwts_tx_en = 0; 781 priv->hwts_rx_en = 0; 782 783 stmmac_ptp_register(priv); 784 785 return 0; 786 } 787 788 static void stmmac_release_ptp(struct stmmac_priv *priv) 789 { 790 if (priv->plat->clk_ptp_ref) 791 clk_disable_unprepare(priv->plat->clk_ptp_ref); 792 stmmac_ptp_unregister(priv); 793 } 794 795 /** 796 * stmmac_mac_flow_ctrl - Configure flow control in all queues 797 * @priv: driver private structure 798 * Description: It is used for configuring the flow control in all queues 799 */ 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 801 { 802 u32 tx_cnt = priv->plat->tx_queues_to_use; 803 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 805 priv->pause, tx_cnt); 806 } 807 808 static void stmmac_validate(struct phylink_config *config, 809 unsigned long *supported, 810 struct phylink_link_state *state) 811 { 812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 815 int tx_cnt = priv->plat->tx_queues_to_use; 816 int max_speed = priv->plat->max_speed; 817 818 phylink_set(mac_supported, 10baseT_Half); 819 phylink_set(mac_supported, 10baseT_Full); 820 phylink_set(mac_supported, 100baseT_Half); 821 phylink_set(mac_supported, 100baseT_Full); 822 phylink_set(mac_supported, 1000baseT_Half); 823 phylink_set(mac_supported, 1000baseT_Full); 824 phylink_set(mac_supported, 1000baseKX_Full); 825 826 phylink_set(mac_supported, Autoneg); 827 phylink_set(mac_supported, Pause); 828 phylink_set(mac_supported, Asym_Pause); 829 phylink_set_port_modes(mac_supported); 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 if (!max_speed || (max_speed >= 2500)) { 837 phylink_set(mac_supported, 2500baseT_Full); 838 phylink_set(mac_supported, 2500baseX_Full); 839 } 840 if (!max_speed || (max_speed >= 5000)) { 841 phylink_set(mac_supported, 5000baseT_Full); 842 } 843 if (!max_speed || (max_speed >= 10000)) { 844 phylink_set(mac_supported, 10000baseSR_Full); 845 phylink_set(mac_supported, 10000baseLR_Full); 846 phylink_set(mac_supported, 10000baseER_Full); 847 phylink_set(mac_supported, 10000baseLRM_Full); 848 phylink_set(mac_supported, 10000baseT_Full); 849 phylink_set(mac_supported, 10000baseKX4_Full); 850 phylink_set(mac_supported, 10000baseKR_Full); 851 } 852 if (!max_speed || (max_speed >= 25000)) { 853 phylink_set(mac_supported, 25000baseCR_Full); 854 phylink_set(mac_supported, 25000baseKR_Full); 855 phylink_set(mac_supported, 25000baseSR_Full); 856 } 857 if (!max_speed || (max_speed >= 40000)) { 858 phylink_set(mac_supported, 40000baseKR4_Full); 859 phylink_set(mac_supported, 40000baseCR4_Full); 860 phylink_set(mac_supported, 40000baseSR4_Full); 861 phylink_set(mac_supported, 40000baseLR4_Full); 862 } 863 if (!max_speed || (max_speed >= 50000)) { 864 phylink_set(mac_supported, 50000baseCR2_Full); 865 phylink_set(mac_supported, 50000baseKR2_Full); 866 phylink_set(mac_supported, 50000baseSR2_Full); 867 phylink_set(mac_supported, 50000baseKR_Full); 868 phylink_set(mac_supported, 50000baseSR_Full); 869 phylink_set(mac_supported, 50000baseCR_Full); 870 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 871 phylink_set(mac_supported, 50000baseDR_Full); 872 } 873 if (!max_speed || (max_speed >= 100000)) { 874 phylink_set(mac_supported, 100000baseKR4_Full); 875 phylink_set(mac_supported, 100000baseSR4_Full); 876 phylink_set(mac_supported, 100000baseCR4_Full); 877 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 878 phylink_set(mac_supported, 100000baseKR2_Full); 879 phylink_set(mac_supported, 100000baseSR2_Full); 880 phylink_set(mac_supported, 100000baseCR2_Full); 881 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 882 phylink_set(mac_supported, 100000baseDR2_Full); 883 } 884 } 885 886 /* Half-Duplex can only work with single queue */ 887 if (tx_cnt > 1) { 888 phylink_set(mask, 10baseT_Half); 889 phylink_set(mask, 100baseT_Half); 890 phylink_set(mask, 1000baseT_Half); 891 } 892 893 linkmode_and(supported, supported, mac_supported); 894 linkmode_andnot(supported, supported, mask); 895 896 linkmode_and(state->advertising, state->advertising, mac_supported); 897 linkmode_andnot(state->advertising, state->advertising, mask); 898 899 /* If PCS is supported, check which modes it supports. */ 900 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 901 } 902 903 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 904 struct phylink_link_state *state) 905 { 906 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 907 908 state->link = 0; 909 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 910 } 911 912 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 913 const struct phylink_link_state *state) 914 { 915 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 916 917 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 918 } 919 920 static void stmmac_mac_an_restart(struct phylink_config *config) 921 { 922 /* Not Supported */ 923 } 924 925 static void stmmac_mac_link_down(struct phylink_config *config, 926 unsigned int mode, phy_interface_t interface) 927 { 928 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 929 930 stmmac_mac_set(priv, priv->ioaddr, false); 931 priv->eee_active = false; 932 stmmac_eee_init(priv); 933 stmmac_set_eee_pls(priv, priv->hw, false); 934 } 935 936 static void stmmac_mac_link_up(struct phylink_config *config, 937 struct phy_device *phy, 938 unsigned int mode, phy_interface_t interface, 939 int speed, int duplex, 940 bool tx_pause, bool rx_pause) 941 { 942 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 943 u32 ctrl; 944 945 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 946 947 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 948 ctrl &= ~priv->hw->link.speed_mask; 949 950 if (interface == PHY_INTERFACE_MODE_USXGMII) { 951 switch (speed) { 952 case SPEED_10000: 953 ctrl |= priv->hw->link.xgmii.speed10000; 954 break; 955 case SPEED_5000: 956 ctrl |= priv->hw->link.xgmii.speed5000; 957 break; 958 case SPEED_2500: 959 ctrl |= priv->hw->link.xgmii.speed2500; 960 break; 961 default: 962 return; 963 } 964 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 965 switch (speed) { 966 case SPEED_100000: 967 ctrl |= priv->hw->link.xlgmii.speed100000; 968 break; 969 case SPEED_50000: 970 ctrl |= priv->hw->link.xlgmii.speed50000; 971 break; 972 case SPEED_40000: 973 ctrl |= priv->hw->link.xlgmii.speed40000; 974 break; 975 case SPEED_25000: 976 ctrl |= priv->hw->link.xlgmii.speed25000; 977 break; 978 case SPEED_10000: 979 ctrl |= priv->hw->link.xgmii.speed10000; 980 break; 981 case SPEED_2500: 982 ctrl |= priv->hw->link.speed2500; 983 break; 984 case SPEED_1000: 985 ctrl |= priv->hw->link.speed1000; 986 break; 987 default: 988 return; 989 } 990 } else { 991 switch (speed) { 992 case SPEED_2500: 993 ctrl |= priv->hw->link.speed2500; 994 break; 995 case SPEED_1000: 996 ctrl |= priv->hw->link.speed1000; 997 break; 998 case SPEED_100: 999 ctrl |= priv->hw->link.speed100; 1000 break; 1001 case SPEED_10: 1002 ctrl |= priv->hw->link.speed10; 1003 break; 1004 default: 1005 return; 1006 } 1007 } 1008 1009 priv->speed = speed; 1010 1011 if (priv->plat->fix_mac_speed) 1012 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1013 1014 if (!duplex) 1015 ctrl &= ~priv->hw->link.duplex; 1016 else 1017 ctrl |= priv->hw->link.duplex; 1018 1019 /* Flow Control operation */ 1020 if (tx_pause && rx_pause) 1021 stmmac_mac_flow_ctrl(priv, duplex); 1022 1023 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1024 1025 stmmac_mac_set(priv, priv->ioaddr, true); 1026 if (phy && priv->dma_cap.eee) { 1027 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1028 priv->eee_enabled = stmmac_eee_init(priv); 1029 stmmac_set_eee_pls(priv, priv->hw, true); 1030 } 1031 } 1032 1033 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1034 .validate = stmmac_validate, 1035 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1036 .mac_config = stmmac_mac_config, 1037 .mac_an_restart = stmmac_mac_an_restart, 1038 .mac_link_down = stmmac_mac_link_down, 1039 .mac_link_up = stmmac_mac_link_up, 1040 }; 1041 1042 /** 1043 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1044 * @priv: driver private structure 1045 * Description: this is to verify if the HW supports the PCS. 1046 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1047 * configured for the TBI, RTBI, or SGMII PHY interface. 1048 */ 1049 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1050 { 1051 int interface = priv->plat->interface; 1052 1053 if (priv->dma_cap.pcs) { 1054 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1055 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1056 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1057 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1058 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1059 priv->hw->pcs = STMMAC_PCS_RGMII; 1060 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1061 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1062 priv->hw->pcs = STMMAC_PCS_SGMII; 1063 } 1064 } 1065 } 1066 1067 /** 1068 * stmmac_init_phy - PHY initialization 1069 * @dev: net device structure 1070 * Description: it initializes the driver's PHY state, and attaches the PHY 1071 * to the mac driver. 1072 * Return value: 1073 * 0 on success 1074 */ 1075 static int stmmac_init_phy(struct net_device *dev) 1076 { 1077 struct stmmac_priv *priv = netdev_priv(dev); 1078 struct device_node *node; 1079 int ret; 1080 1081 node = priv->plat->phylink_node; 1082 1083 if (node) 1084 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1085 1086 /* Some DT bindings do not set-up the PHY handle. Let's try to 1087 * manually parse it 1088 */ 1089 if (!node || ret) { 1090 int addr = priv->plat->phy_addr; 1091 struct phy_device *phydev; 1092 1093 phydev = mdiobus_get_phy(priv->mii, addr); 1094 if (!phydev) { 1095 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1096 return -ENODEV; 1097 } 1098 1099 ret = phylink_connect_phy(priv->phylink, phydev); 1100 } 1101 1102 return ret; 1103 } 1104 1105 static int stmmac_phy_setup(struct stmmac_priv *priv) 1106 { 1107 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1108 int mode = priv->plat->phy_interface; 1109 struct phylink *phylink; 1110 1111 priv->phylink_config.dev = &priv->dev->dev; 1112 priv->phylink_config.type = PHYLINK_NETDEV; 1113 priv->phylink_config.pcs_poll = true; 1114 1115 if (!fwnode) 1116 fwnode = dev_fwnode(priv->device); 1117 1118 phylink = phylink_create(&priv->phylink_config, fwnode, 1119 mode, &stmmac_phylink_mac_ops); 1120 if (IS_ERR(phylink)) 1121 return PTR_ERR(phylink); 1122 1123 priv->phylink = phylink; 1124 return 0; 1125 } 1126 1127 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1128 { 1129 u32 rx_cnt = priv->plat->rx_queues_to_use; 1130 void *head_rx; 1131 u32 queue; 1132 1133 /* Display RX rings */ 1134 for (queue = 0; queue < rx_cnt; queue++) { 1135 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1136 1137 pr_info("\tRX Queue %u rings\n", queue); 1138 1139 if (priv->extend_desc) 1140 head_rx = (void *)rx_q->dma_erx; 1141 else 1142 head_rx = (void *)rx_q->dma_rx; 1143 1144 /* Display RX ring */ 1145 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1146 } 1147 } 1148 1149 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1150 { 1151 u32 tx_cnt = priv->plat->tx_queues_to_use; 1152 void *head_tx; 1153 u32 queue; 1154 1155 /* Display TX rings */ 1156 for (queue = 0; queue < tx_cnt; queue++) { 1157 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1158 1159 pr_info("\tTX Queue %d rings\n", queue); 1160 1161 if (priv->extend_desc) 1162 head_tx = (void *)tx_q->dma_etx; 1163 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1164 head_tx = (void *)tx_q->dma_entx; 1165 else 1166 head_tx = (void *)tx_q->dma_tx; 1167 1168 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1169 } 1170 } 1171 1172 static void stmmac_display_rings(struct stmmac_priv *priv) 1173 { 1174 /* Display RX ring */ 1175 stmmac_display_rx_rings(priv); 1176 1177 /* Display TX ring */ 1178 stmmac_display_tx_rings(priv); 1179 } 1180 1181 static int stmmac_set_bfsize(int mtu, int bufsize) 1182 { 1183 int ret = bufsize; 1184 1185 if (mtu >= BUF_SIZE_8KiB) 1186 ret = BUF_SIZE_16KiB; 1187 else if (mtu >= BUF_SIZE_4KiB) 1188 ret = BUF_SIZE_8KiB; 1189 else if (mtu >= BUF_SIZE_2KiB) 1190 ret = BUF_SIZE_4KiB; 1191 else if (mtu > DEFAULT_BUFSIZE) 1192 ret = BUF_SIZE_2KiB; 1193 else 1194 ret = DEFAULT_BUFSIZE; 1195 1196 return ret; 1197 } 1198 1199 /** 1200 * stmmac_clear_rx_descriptors - clear RX descriptors 1201 * @priv: driver private structure 1202 * @queue: RX queue index 1203 * Description: this function is called to clear the RX descriptors 1204 * in case of both basic and extended descriptors are used. 1205 */ 1206 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1207 { 1208 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1209 int i; 1210 1211 /* Clear the RX descriptors */ 1212 for (i = 0; i < DMA_RX_SIZE; i++) 1213 if (priv->extend_desc) 1214 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1215 priv->use_riwt, priv->mode, 1216 (i == DMA_RX_SIZE - 1), 1217 priv->dma_buf_sz); 1218 else 1219 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1220 priv->use_riwt, priv->mode, 1221 (i == DMA_RX_SIZE - 1), 1222 priv->dma_buf_sz); 1223 } 1224 1225 /** 1226 * stmmac_clear_tx_descriptors - clear tx descriptors 1227 * @priv: driver private structure 1228 * @queue: TX queue index. 1229 * Description: this function is called to clear the TX descriptors 1230 * in case of both basic and extended descriptors are used. 1231 */ 1232 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1233 { 1234 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1235 int i; 1236 1237 /* Clear the TX descriptors */ 1238 for (i = 0; i < DMA_TX_SIZE; i++) { 1239 int last = (i == (DMA_TX_SIZE - 1)); 1240 struct dma_desc *p; 1241 1242 if (priv->extend_desc) 1243 p = &tx_q->dma_etx[i].basic; 1244 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1245 p = &tx_q->dma_entx[i].basic; 1246 else 1247 p = &tx_q->dma_tx[i]; 1248 1249 stmmac_init_tx_desc(priv, p, priv->mode, last); 1250 } 1251 } 1252 1253 /** 1254 * stmmac_clear_descriptors - clear descriptors 1255 * @priv: driver private structure 1256 * Description: this function is called to clear the TX and RX descriptors 1257 * in case of both basic and extended descriptors are used. 1258 */ 1259 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1260 { 1261 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1262 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1263 u32 queue; 1264 1265 /* Clear the RX descriptors */ 1266 for (queue = 0; queue < rx_queue_cnt; queue++) 1267 stmmac_clear_rx_descriptors(priv, queue); 1268 1269 /* Clear the TX descriptors */ 1270 for (queue = 0; queue < tx_queue_cnt; queue++) 1271 stmmac_clear_tx_descriptors(priv, queue); 1272 } 1273 1274 /** 1275 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1276 * @priv: driver private structure 1277 * @p: descriptor pointer 1278 * @i: descriptor index 1279 * @flags: gfp flag 1280 * @queue: RX queue index 1281 * Description: this function is called to allocate a receive buffer, perform 1282 * the DMA mapping and init the descriptor. 1283 */ 1284 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1285 int i, gfp_t flags, u32 queue) 1286 { 1287 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1288 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1289 1290 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1291 if (!buf->page) 1292 return -ENOMEM; 1293 1294 if (priv->sph) { 1295 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1296 if (!buf->sec_page) 1297 return -ENOMEM; 1298 1299 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1300 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1301 } else { 1302 buf->sec_page = NULL; 1303 } 1304 1305 buf->addr = page_pool_get_dma_addr(buf->page); 1306 stmmac_set_desc_addr(priv, p, buf->addr); 1307 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1308 stmmac_init_desc3(priv, p); 1309 1310 return 0; 1311 } 1312 1313 /** 1314 * stmmac_free_rx_buffer - free RX dma buffers 1315 * @priv: private structure 1316 * @queue: RX queue index 1317 * @i: buffer index. 1318 */ 1319 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1320 { 1321 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1322 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1323 1324 if (buf->page) 1325 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1326 buf->page = NULL; 1327 1328 if (buf->sec_page) 1329 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1330 buf->sec_page = NULL; 1331 } 1332 1333 /** 1334 * stmmac_free_tx_buffer - free RX dma buffers 1335 * @priv: private structure 1336 * @queue: RX queue index 1337 * @i: buffer index. 1338 */ 1339 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1340 { 1341 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1342 1343 if (tx_q->tx_skbuff_dma[i].buf) { 1344 if (tx_q->tx_skbuff_dma[i].map_as_page) 1345 dma_unmap_page(priv->device, 1346 tx_q->tx_skbuff_dma[i].buf, 1347 tx_q->tx_skbuff_dma[i].len, 1348 DMA_TO_DEVICE); 1349 else 1350 dma_unmap_single(priv->device, 1351 tx_q->tx_skbuff_dma[i].buf, 1352 tx_q->tx_skbuff_dma[i].len, 1353 DMA_TO_DEVICE); 1354 } 1355 1356 if (tx_q->tx_skbuff[i]) { 1357 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1358 tx_q->tx_skbuff[i] = NULL; 1359 tx_q->tx_skbuff_dma[i].buf = 0; 1360 tx_q->tx_skbuff_dma[i].map_as_page = false; 1361 } 1362 } 1363 1364 /** 1365 * init_dma_rx_desc_rings - init the RX descriptor rings 1366 * @dev: net device structure 1367 * @flags: gfp flag. 1368 * Description: this function initializes the DMA RX descriptors 1369 * and allocates the socket buffers. It supports the chained and ring 1370 * modes. 1371 */ 1372 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1373 { 1374 struct stmmac_priv *priv = netdev_priv(dev); 1375 u32 rx_count = priv->plat->rx_queues_to_use; 1376 int ret = -ENOMEM; 1377 int queue; 1378 int i; 1379 1380 /* RX INITIALIZATION */ 1381 netif_dbg(priv, probe, priv->dev, 1382 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1383 1384 for (queue = 0; queue < rx_count; queue++) { 1385 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1386 1387 netif_dbg(priv, probe, priv->dev, 1388 "(%s) dma_rx_phy=0x%08x\n", __func__, 1389 (u32)rx_q->dma_rx_phy); 1390 1391 stmmac_clear_rx_descriptors(priv, queue); 1392 1393 for (i = 0; i < DMA_RX_SIZE; i++) { 1394 struct dma_desc *p; 1395 1396 if (priv->extend_desc) 1397 p = &((rx_q->dma_erx + i)->basic); 1398 else 1399 p = rx_q->dma_rx + i; 1400 1401 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1402 queue); 1403 if (ret) 1404 goto err_init_rx_buffers; 1405 } 1406 1407 rx_q->cur_rx = 0; 1408 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1409 1410 /* Setup the chained descriptor addresses */ 1411 if (priv->mode == STMMAC_CHAIN_MODE) { 1412 if (priv->extend_desc) 1413 stmmac_mode_init(priv, rx_q->dma_erx, 1414 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1415 else 1416 stmmac_mode_init(priv, rx_q->dma_rx, 1417 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1418 } 1419 } 1420 1421 return 0; 1422 1423 err_init_rx_buffers: 1424 while (queue >= 0) { 1425 while (--i >= 0) 1426 stmmac_free_rx_buffer(priv, queue, i); 1427 1428 if (queue == 0) 1429 break; 1430 1431 i = DMA_RX_SIZE; 1432 queue--; 1433 } 1434 1435 return ret; 1436 } 1437 1438 /** 1439 * init_dma_tx_desc_rings - init the TX descriptor rings 1440 * @dev: net device structure. 1441 * Description: this function initializes the DMA TX descriptors 1442 * and allocates the socket buffers. It supports the chained and ring 1443 * modes. 1444 */ 1445 static int init_dma_tx_desc_rings(struct net_device *dev) 1446 { 1447 struct stmmac_priv *priv = netdev_priv(dev); 1448 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1449 u32 queue; 1450 int i; 1451 1452 for (queue = 0; queue < tx_queue_cnt; queue++) { 1453 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1454 1455 netif_dbg(priv, probe, priv->dev, 1456 "(%s) dma_tx_phy=0x%08x\n", __func__, 1457 (u32)tx_q->dma_tx_phy); 1458 1459 /* Setup the chained descriptor addresses */ 1460 if (priv->mode == STMMAC_CHAIN_MODE) { 1461 if (priv->extend_desc) 1462 stmmac_mode_init(priv, tx_q->dma_etx, 1463 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1464 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1465 stmmac_mode_init(priv, tx_q->dma_tx, 1466 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1467 } 1468 1469 for (i = 0; i < DMA_TX_SIZE; i++) { 1470 struct dma_desc *p; 1471 if (priv->extend_desc) 1472 p = &((tx_q->dma_etx + i)->basic); 1473 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1474 p = &((tx_q->dma_entx + i)->basic); 1475 else 1476 p = tx_q->dma_tx + i; 1477 1478 stmmac_clear_desc(priv, p); 1479 1480 tx_q->tx_skbuff_dma[i].buf = 0; 1481 tx_q->tx_skbuff_dma[i].map_as_page = false; 1482 tx_q->tx_skbuff_dma[i].len = 0; 1483 tx_q->tx_skbuff_dma[i].last_segment = false; 1484 tx_q->tx_skbuff[i] = NULL; 1485 } 1486 1487 tx_q->dirty_tx = 0; 1488 tx_q->cur_tx = 0; 1489 tx_q->mss = 0; 1490 1491 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1492 } 1493 1494 return 0; 1495 } 1496 1497 /** 1498 * init_dma_desc_rings - init the RX/TX descriptor rings 1499 * @dev: net device structure 1500 * @flags: gfp flag. 1501 * Description: this function initializes the DMA RX/TX descriptors 1502 * and allocates the socket buffers. It supports the chained and ring 1503 * modes. 1504 */ 1505 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1506 { 1507 struct stmmac_priv *priv = netdev_priv(dev); 1508 int ret; 1509 1510 ret = init_dma_rx_desc_rings(dev, flags); 1511 if (ret) 1512 return ret; 1513 1514 ret = init_dma_tx_desc_rings(dev); 1515 1516 stmmac_clear_descriptors(priv); 1517 1518 if (netif_msg_hw(priv)) 1519 stmmac_display_rings(priv); 1520 1521 return ret; 1522 } 1523 1524 /** 1525 * dma_free_rx_skbufs - free RX dma buffers 1526 * @priv: private structure 1527 * @queue: RX queue index 1528 */ 1529 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1530 { 1531 int i; 1532 1533 for (i = 0; i < DMA_RX_SIZE; i++) 1534 stmmac_free_rx_buffer(priv, queue, i); 1535 } 1536 1537 /** 1538 * dma_free_tx_skbufs - free TX dma buffers 1539 * @priv: private structure 1540 * @queue: TX queue index 1541 */ 1542 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1543 { 1544 int i; 1545 1546 for (i = 0; i < DMA_TX_SIZE; i++) 1547 stmmac_free_tx_buffer(priv, queue, i); 1548 } 1549 1550 /** 1551 * free_dma_rx_desc_resources - free RX dma desc resources 1552 * @priv: private structure 1553 */ 1554 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1555 { 1556 u32 rx_count = priv->plat->rx_queues_to_use; 1557 u32 queue; 1558 1559 /* Free RX queue resources */ 1560 for (queue = 0; queue < rx_count; queue++) { 1561 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1562 1563 /* Release the DMA RX socket buffers */ 1564 dma_free_rx_skbufs(priv, queue); 1565 1566 /* Free DMA regions of consistent memory previously allocated */ 1567 if (!priv->extend_desc) 1568 dma_free_coherent(priv->device, 1569 DMA_RX_SIZE * sizeof(struct dma_desc), 1570 rx_q->dma_rx, rx_q->dma_rx_phy); 1571 else 1572 dma_free_coherent(priv->device, DMA_RX_SIZE * 1573 sizeof(struct dma_extended_desc), 1574 rx_q->dma_erx, rx_q->dma_rx_phy); 1575 1576 kfree(rx_q->buf_pool); 1577 if (rx_q->page_pool) 1578 page_pool_destroy(rx_q->page_pool); 1579 } 1580 } 1581 1582 /** 1583 * free_dma_tx_desc_resources - free TX dma desc resources 1584 * @priv: private structure 1585 */ 1586 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1587 { 1588 u32 tx_count = priv->plat->tx_queues_to_use; 1589 u32 queue; 1590 1591 /* Free TX queue resources */ 1592 for (queue = 0; queue < tx_count; queue++) { 1593 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1594 size_t size; 1595 void *addr; 1596 1597 /* Release the DMA TX socket buffers */ 1598 dma_free_tx_skbufs(priv, queue); 1599 1600 if (priv->extend_desc) { 1601 size = sizeof(struct dma_extended_desc); 1602 addr = tx_q->dma_etx; 1603 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1604 size = sizeof(struct dma_edesc); 1605 addr = tx_q->dma_entx; 1606 } else { 1607 size = sizeof(struct dma_desc); 1608 addr = tx_q->dma_tx; 1609 } 1610 1611 size *= DMA_TX_SIZE; 1612 1613 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1614 1615 kfree(tx_q->tx_skbuff_dma); 1616 kfree(tx_q->tx_skbuff); 1617 } 1618 } 1619 1620 /** 1621 * alloc_dma_rx_desc_resources - alloc RX resources. 1622 * @priv: private structure 1623 * Description: according to which descriptor can be used (extend or basic) 1624 * this function allocates the resources for TX and RX paths. In case of 1625 * reception, for example, it pre-allocated the RX socket buffer in order to 1626 * allow zero-copy mechanism. 1627 */ 1628 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1629 { 1630 u32 rx_count = priv->plat->rx_queues_to_use; 1631 int ret = -ENOMEM; 1632 u32 queue; 1633 1634 /* RX queues buffers and DMA */ 1635 for (queue = 0; queue < rx_count; queue++) { 1636 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1637 struct page_pool_params pp_params = { 0 }; 1638 unsigned int num_pages; 1639 1640 rx_q->queue_index = queue; 1641 rx_q->priv_data = priv; 1642 1643 pp_params.flags = PP_FLAG_DMA_MAP; 1644 pp_params.pool_size = DMA_RX_SIZE; 1645 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1646 pp_params.order = ilog2(num_pages); 1647 pp_params.nid = dev_to_node(priv->device); 1648 pp_params.dev = priv->device; 1649 pp_params.dma_dir = DMA_FROM_DEVICE; 1650 1651 rx_q->page_pool = page_pool_create(&pp_params); 1652 if (IS_ERR(rx_q->page_pool)) { 1653 ret = PTR_ERR(rx_q->page_pool); 1654 rx_q->page_pool = NULL; 1655 goto err_dma; 1656 } 1657 1658 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1659 GFP_KERNEL); 1660 if (!rx_q->buf_pool) 1661 goto err_dma; 1662 1663 if (priv->extend_desc) { 1664 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1665 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1666 &rx_q->dma_rx_phy, 1667 GFP_KERNEL); 1668 if (!rx_q->dma_erx) 1669 goto err_dma; 1670 1671 } else { 1672 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1673 DMA_RX_SIZE * sizeof(struct dma_desc), 1674 &rx_q->dma_rx_phy, 1675 GFP_KERNEL); 1676 if (!rx_q->dma_rx) 1677 goto err_dma; 1678 } 1679 } 1680 1681 return 0; 1682 1683 err_dma: 1684 free_dma_rx_desc_resources(priv); 1685 1686 return ret; 1687 } 1688 1689 /** 1690 * alloc_dma_tx_desc_resources - alloc TX resources. 1691 * @priv: private structure 1692 * Description: according to which descriptor can be used (extend or basic) 1693 * this function allocates the resources for TX and RX paths. In case of 1694 * reception, for example, it pre-allocated the RX socket buffer in order to 1695 * allow zero-copy mechanism. 1696 */ 1697 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1698 { 1699 u32 tx_count = priv->plat->tx_queues_to_use; 1700 int ret = -ENOMEM; 1701 u32 queue; 1702 1703 /* TX queues buffers and DMA */ 1704 for (queue = 0; queue < tx_count; queue++) { 1705 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1706 size_t size; 1707 void *addr; 1708 1709 tx_q->queue_index = queue; 1710 tx_q->priv_data = priv; 1711 1712 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1713 sizeof(*tx_q->tx_skbuff_dma), 1714 GFP_KERNEL); 1715 if (!tx_q->tx_skbuff_dma) 1716 goto err_dma; 1717 1718 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1719 sizeof(struct sk_buff *), 1720 GFP_KERNEL); 1721 if (!tx_q->tx_skbuff) 1722 goto err_dma; 1723 1724 if (priv->extend_desc) 1725 size = sizeof(struct dma_extended_desc); 1726 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1727 size = sizeof(struct dma_edesc); 1728 else 1729 size = sizeof(struct dma_desc); 1730 1731 size *= DMA_TX_SIZE; 1732 1733 addr = dma_alloc_coherent(priv->device, size, 1734 &tx_q->dma_tx_phy, GFP_KERNEL); 1735 if (!addr) 1736 goto err_dma; 1737 1738 if (priv->extend_desc) 1739 tx_q->dma_etx = addr; 1740 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1741 tx_q->dma_entx = addr; 1742 else 1743 tx_q->dma_tx = addr; 1744 } 1745 1746 return 0; 1747 1748 err_dma: 1749 free_dma_tx_desc_resources(priv); 1750 return ret; 1751 } 1752 1753 /** 1754 * alloc_dma_desc_resources - alloc TX/RX resources. 1755 * @priv: private structure 1756 * Description: according to which descriptor can be used (extend or basic) 1757 * this function allocates the resources for TX and RX paths. In case of 1758 * reception, for example, it pre-allocated the RX socket buffer in order to 1759 * allow zero-copy mechanism. 1760 */ 1761 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1762 { 1763 /* RX Allocation */ 1764 int ret = alloc_dma_rx_desc_resources(priv); 1765 1766 if (ret) 1767 return ret; 1768 1769 ret = alloc_dma_tx_desc_resources(priv); 1770 1771 return ret; 1772 } 1773 1774 /** 1775 * free_dma_desc_resources - free dma desc resources 1776 * @priv: private structure 1777 */ 1778 static void free_dma_desc_resources(struct stmmac_priv *priv) 1779 { 1780 /* Release the DMA RX socket buffers */ 1781 free_dma_rx_desc_resources(priv); 1782 1783 /* Release the DMA TX socket buffers */ 1784 free_dma_tx_desc_resources(priv); 1785 } 1786 1787 /** 1788 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1789 * @priv: driver private structure 1790 * Description: It is used for enabling the rx queues in the MAC 1791 */ 1792 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1793 { 1794 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1795 int queue; 1796 u8 mode; 1797 1798 for (queue = 0; queue < rx_queues_count; queue++) { 1799 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1800 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1801 } 1802 } 1803 1804 /** 1805 * stmmac_start_rx_dma - start RX DMA channel 1806 * @priv: driver private structure 1807 * @chan: RX channel index 1808 * Description: 1809 * This starts a RX DMA channel 1810 */ 1811 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1812 { 1813 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1814 stmmac_start_rx(priv, priv->ioaddr, chan); 1815 } 1816 1817 /** 1818 * stmmac_start_tx_dma - start TX DMA channel 1819 * @priv: driver private structure 1820 * @chan: TX channel index 1821 * Description: 1822 * This starts a TX DMA channel 1823 */ 1824 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1825 { 1826 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1827 stmmac_start_tx(priv, priv->ioaddr, chan); 1828 } 1829 1830 /** 1831 * stmmac_stop_rx_dma - stop RX DMA channel 1832 * @priv: driver private structure 1833 * @chan: RX channel index 1834 * Description: 1835 * This stops a RX DMA channel 1836 */ 1837 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1838 { 1839 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1840 stmmac_stop_rx(priv, priv->ioaddr, chan); 1841 } 1842 1843 /** 1844 * stmmac_stop_tx_dma - stop TX DMA channel 1845 * @priv: driver private structure 1846 * @chan: TX channel index 1847 * Description: 1848 * This stops a TX DMA channel 1849 */ 1850 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1851 { 1852 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1853 stmmac_stop_tx(priv, priv->ioaddr, chan); 1854 } 1855 1856 /** 1857 * stmmac_start_all_dma - start all RX and TX DMA channels 1858 * @priv: driver private structure 1859 * Description: 1860 * This starts all the RX and TX DMA channels 1861 */ 1862 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1863 { 1864 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1865 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1866 u32 chan = 0; 1867 1868 for (chan = 0; chan < rx_channels_count; chan++) 1869 stmmac_start_rx_dma(priv, chan); 1870 1871 for (chan = 0; chan < tx_channels_count; chan++) 1872 stmmac_start_tx_dma(priv, chan); 1873 } 1874 1875 /** 1876 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1877 * @priv: driver private structure 1878 * Description: 1879 * This stops the RX and TX DMA channels 1880 */ 1881 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1882 { 1883 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1884 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1885 u32 chan = 0; 1886 1887 for (chan = 0; chan < rx_channels_count; chan++) 1888 stmmac_stop_rx_dma(priv, chan); 1889 1890 for (chan = 0; chan < tx_channels_count; chan++) 1891 stmmac_stop_tx_dma(priv, chan); 1892 } 1893 1894 /** 1895 * stmmac_dma_operation_mode - HW DMA operation mode 1896 * @priv: driver private structure 1897 * Description: it is used for configuring the DMA operation mode register in 1898 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1899 */ 1900 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1901 { 1902 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1903 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1904 int rxfifosz = priv->plat->rx_fifo_size; 1905 int txfifosz = priv->plat->tx_fifo_size; 1906 u32 txmode = 0; 1907 u32 rxmode = 0; 1908 u32 chan = 0; 1909 u8 qmode = 0; 1910 1911 if (rxfifosz == 0) 1912 rxfifosz = priv->dma_cap.rx_fifo_size; 1913 if (txfifosz == 0) 1914 txfifosz = priv->dma_cap.tx_fifo_size; 1915 1916 /* Adjust for real per queue fifo size */ 1917 rxfifosz /= rx_channels_count; 1918 txfifosz /= tx_channels_count; 1919 1920 if (priv->plat->force_thresh_dma_mode) { 1921 txmode = tc; 1922 rxmode = tc; 1923 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1924 /* 1925 * In case of GMAC, SF mode can be enabled 1926 * to perform the TX COE in HW. This depends on: 1927 * 1) TX COE if actually supported 1928 * 2) There is no bugged Jumbo frame support 1929 * that needs to not insert csum in the TDES. 1930 */ 1931 txmode = SF_DMA_MODE; 1932 rxmode = SF_DMA_MODE; 1933 priv->xstats.threshold = SF_DMA_MODE; 1934 } else { 1935 txmode = tc; 1936 rxmode = SF_DMA_MODE; 1937 } 1938 1939 /* configure all channels */ 1940 for (chan = 0; chan < rx_channels_count; chan++) { 1941 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1942 1943 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1944 rxfifosz, qmode); 1945 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1946 chan); 1947 } 1948 1949 for (chan = 0; chan < tx_channels_count; chan++) { 1950 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1951 1952 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1953 txfifosz, qmode); 1954 } 1955 } 1956 1957 /** 1958 * stmmac_tx_clean - to manage the transmission completion 1959 * @priv: driver private structure 1960 * @queue: TX queue index 1961 * Description: it reclaims the transmit resources after transmission completes. 1962 */ 1963 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1964 { 1965 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1966 unsigned int bytes_compl = 0, pkts_compl = 0; 1967 unsigned int entry, count = 0; 1968 1969 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1970 1971 priv->xstats.tx_clean++; 1972 1973 entry = tx_q->dirty_tx; 1974 while ((entry != tx_q->cur_tx) && (count < budget)) { 1975 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1976 struct dma_desc *p; 1977 int status; 1978 1979 if (priv->extend_desc) 1980 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1981 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1982 p = &tx_q->dma_entx[entry].basic; 1983 else 1984 p = tx_q->dma_tx + entry; 1985 1986 status = stmmac_tx_status(priv, &priv->dev->stats, 1987 &priv->xstats, p, priv->ioaddr); 1988 /* Check if the descriptor is owned by the DMA */ 1989 if (unlikely(status & tx_dma_own)) 1990 break; 1991 1992 count++; 1993 1994 /* Make sure descriptor fields are read after reading 1995 * the own bit. 1996 */ 1997 dma_rmb(); 1998 1999 /* Just consider the last segment and ...*/ 2000 if (likely(!(status & tx_not_ls))) { 2001 /* ... verify the status error condition */ 2002 if (unlikely(status & tx_err)) { 2003 priv->dev->stats.tx_errors++; 2004 } else { 2005 priv->dev->stats.tx_packets++; 2006 priv->xstats.tx_pkt_n++; 2007 } 2008 stmmac_get_tx_hwtstamp(priv, p, skb); 2009 } 2010 2011 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 2012 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2013 dma_unmap_page(priv->device, 2014 tx_q->tx_skbuff_dma[entry].buf, 2015 tx_q->tx_skbuff_dma[entry].len, 2016 DMA_TO_DEVICE); 2017 else 2018 dma_unmap_single(priv->device, 2019 tx_q->tx_skbuff_dma[entry].buf, 2020 tx_q->tx_skbuff_dma[entry].len, 2021 DMA_TO_DEVICE); 2022 tx_q->tx_skbuff_dma[entry].buf = 0; 2023 tx_q->tx_skbuff_dma[entry].len = 0; 2024 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2025 } 2026 2027 stmmac_clean_desc3(priv, tx_q, p); 2028 2029 tx_q->tx_skbuff_dma[entry].last_segment = false; 2030 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2031 2032 if (likely(skb != NULL)) { 2033 pkts_compl++; 2034 bytes_compl += skb->len; 2035 dev_consume_skb_any(skb); 2036 tx_q->tx_skbuff[entry] = NULL; 2037 } 2038 2039 stmmac_release_tx_desc(priv, p, priv->mode); 2040 2041 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2042 } 2043 tx_q->dirty_tx = entry; 2044 2045 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2046 pkts_compl, bytes_compl); 2047 2048 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2049 queue))) && 2050 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 2051 2052 netif_dbg(priv, tx_done, priv->dev, 2053 "%s: restart transmit\n", __func__); 2054 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2055 } 2056 2057 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 2058 stmmac_enable_eee_mode(priv); 2059 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 2060 } 2061 2062 /* We still have pending packets, let's call for a new scheduling */ 2063 if (tx_q->dirty_tx != tx_q->cur_tx) 2064 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2065 2066 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2067 2068 return count; 2069 } 2070 2071 /** 2072 * stmmac_tx_err - to manage the tx error 2073 * @priv: driver private structure 2074 * @chan: channel index 2075 * Description: it cleans the descriptors and restarts the transmission 2076 * in case of transmission errors. 2077 */ 2078 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2079 { 2080 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2081 2082 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2083 2084 stmmac_stop_tx_dma(priv, chan); 2085 dma_free_tx_skbufs(priv, chan); 2086 stmmac_clear_tx_descriptors(priv, chan); 2087 tx_q->dirty_tx = 0; 2088 tx_q->cur_tx = 0; 2089 tx_q->mss = 0; 2090 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2091 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2092 tx_q->dma_tx_phy, chan); 2093 stmmac_start_tx_dma(priv, chan); 2094 2095 priv->dev->stats.tx_errors++; 2096 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2097 } 2098 2099 /** 2100 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2101 * @priv: driver private structure 2102 * @txmode: TX operating mode 2103 * @rxmode: RX operating mode 2104 * @chan: channel index 2105 * Description: it is used for configuring of the DMA operation mode in 2106 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2107 * mode. 2108 */ 2109 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2110 u32 rxmode, u32 chan) 2111 { 2112 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2113 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2114 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2115 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2116 int rxfifosz = priv->plat->rx_fifo_size; 2117 int txfifosz = priv->plat->tx_fifo_size; 2118 2119 if (rxfifosz == 0) 2120 rxfifosz = priv->dma_cap.rx_fifo_size; 2121 if (txfifosz == 0) 2122 txfifosz = priv->dma_cap.tx_fifo_size; 2123 2124 /* Adjust for real per queue fifo size */ 2125 rxfifosz /= rx_channels_count; 2126 txfifosz /= tx_channels_count; 2127 2128 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2129 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2130 } 2131 2132 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2133 { 2134 int ret; 2135 2136 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2137 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2138 if (ret && (ret != -EINVAL)) { 2139 stmmac_global_err(priv); 2140 return true; 2141 } 2142 2143 return false; 2144 } 2145 2146 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2147 { 2148 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2149 &priv->xstats, chan); 2150 struct stmmac_channel *ch = &priv->channel[chan]; 2151 unsigned long flags; 2152 2153 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2154 if (napi_schedule_prep(&ch->rx_napi)) { 2155 spin_lock_irqsave(&ch->lock, flags); 2156 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2157 spin_unlock_irqrestore(&ch->lock, flags); 2158 __napi_schedule_irqoff(&ch->rx_napi); 2159 } 2160 } 2161 2162 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2163 if (napi_schedule_prep(&ch->tx_napi)) { 2164 spin_lock_irqsave(&ch->lock, flags); 2165 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2166 spin_unlock_irqrestore(&ch->lock, flags); 2167 __napi_schedule_irqoff(&ch->tx_napi); 2168 } 2169 } 2170 2171 return status; 2172 } 2173 2174 /** 2175 * stmmac_dma_interrupt - DMA ISR 2176 * @priv: driver private structure 2177 * Description: this is the DMA ISR. It is called by the main ISR. 2178 * It calls the dwmac dma routine and schedule poll method in case of some 2179 * work can be done. 2180 */ 2181 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2182 { 2183 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2184 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2185 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2186 tx_channel_count : rx_channel_count; 2187 u32 chan; 2188 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2189 2190 /* Make sure we never check beyond our status buffer. */ 2191 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2192 channels_to_check = ARRAY_SIZE(status); 2193 2194 for (chan = 0; chan < channels_to_check; chan++) 2195 status[chan] = stmmac_napi_check(priv, chan); 2196 2197 for (chan = 0; chan < tx_channel_count; chan++) { 2198 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2199 /* Try to bump up the dma threshold on this failure */ 2200 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2201 (tc <= 256)) { 2202 tc += 64; 2203 if (priv->plat->force_thresh_dma_mode) 2204 stmmac_set_dma_operation_mode(priv, 2205 tc, 2206 tc, 2207 chan); 2208 else 2209 stmmac_set_dma_operation_mode(priv, 2210 tc, 2211 SF_DMA_MODE, 2212 chan); 2213 priv->xstats.threshold = tc; 2214 } 2215 } else if (unlikely(status[chan] == tx_hard_error)) { 2216 stmmac_tx_err(priv, chan); 2217 } 2218 } 2219 } 2220 2221 /** 2222 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2223 * @priv: driver private structure 2224 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2225 */ 2226 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2227 { 2228 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2229 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2230 2231 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2232 2233 if (priv->dma_cap.rmon) { 2234 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2235 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2236 } else 2237 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2238 } 2239 2240 /** 2241 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2242 * @priv: driver private structure 2243 * Description: 2244 * new GMAC chip generations have a new register to indicate the 2245 * presence of the optional feature/functions. 2246 * This can be also used to override the value passed through the 2247 * platform and necessary for old MAC10/100 and GMAC chips. 2248 */ 2249 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2250 { 2251 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2252 } 2253 2254 /** 2255 * stmmac_check_ether_addr - check if the MAC addr is valid 2256 * @priv: driver private structure 2257 * Description: 2258 * it is to verify if the MAC address is valid, in case of failures it 2259 * generates a random MAC address 2260 */ 2261 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2262 { 2263 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2264 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2265 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2266 eth_hw_addr_random(priv->dev); 2267 dev_info(priv->device, "device MAC address %pM\n", 2268 priv->dev->dev_addr); 2269 } 2270 } 2271 2272 /** 2273 * stmmac_init_dma_engine - DMA init. 2274 * @priv: driver private structure 2275 * Description: 2276 * It inits the DMA invoking the specific MAC/GMAC callback. 2277 * Some DMA parameters can be passed from the platform; 2278 * in case of these are not passed a default is kept for the MAC or GMAC. 2279 */ 2280 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2281 { 2282 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2283 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2284 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2285 struct stmmac_rx_queue *rx_q; 2286 struct stmmac_tx_queue *tx_q; 2287 u32 chan = 0; 2288 int atds = 0; 2289 int ret = 0; 2290 2291 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2292 dev_err(priv->device, "Invalid DMA configuration\n"); 2293 return -EINVAL; 2294 } 2295 2296 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2297 atds = 1; 2298 2299 ret = stmmac_reset(priv, priv->ioaddr); 2300 if (ret) { 2301 dev_err(priv->device, "Failed to reset the dma\n"); 2302 return ret; 2303 } 2304 2305 /* DMA Configuration */ 2306 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2307 2308 if (priv->plat->axi) 2309 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2310 2311 /* DMA CSR Channel configuration */ 2312 for (chan = 0; chan < dma_csr_ch; chan++) 2313 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2314 2315 /* DMA RX Channel Configuration */ 2316 for (chan = 0; chan < rx_channels_count; chan++) { 2317 rx_q = &priv->rx_queue[chan]; 2318 2319 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2320 rx_q->dma_rx_phy, chan); 2321 2322 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2323 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2324 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2325 rx_q->rx_tail_addr, chan); 2326 } 2327 2328 /* DMA TX Channel Configuration */ 2329 for (chan = 0; chan < tx_channels_count; chan++) { 2330 tx_q = &priv->tx_queue[chan]; 2331 2332 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2333 tx_q->dma_tx_phy, chan); 2334 2335 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2336 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2337 tx_q->tx_tail_addr, chan); 2338 } 2339 2340 return ret; 2341 } 2342 2343 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2344 { 2345 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2346 2347 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2348 } 2349 2350 /** 2351 * stmmac_tx_timer - mitigation sw timer for tx. 2352 * @data: data pointer 2353 * Description: 2354 * This is the timer handler to directly invoke the stmmac_tx_clean. 2355 */ 2356 static void stmmac_tx_timer(struct timer_list *t) 2357 { 2358 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2359 struct stmmac_priv *priv = tx_q->priv_data; 2360 struct stmmac_channel *ch; 2361 2362 ch = &priv->channel[tx_q->queue_index]; 2363 2364 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2365 unsigned long flags; 2366 2367 spin_lock_irqsave(&ch->lock, flags); 2368 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2369 spin_unlock_irqrestore(&ch->lock, flags); 2370 __napi_schedule(&ch->tx_napi); 2371 } 2372 } 2373 2374 /** 2375 * stmmac_init_coalesce - init mitigation options. 2376 * @priv: driver private structure 2377 * Description: 2378 * This inits the coalesce parameters: i.e. timer rate, 2379 * timer handler and default threshold used for enabling the 2380 * interrupt on completion bit. 2381 */ 2382 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2383 { 2384 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2385 u32 chan; 2386 2387 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2388 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2389 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2390 2391 for (chan = 0; chan < tx_channel_count; chan++) { 2392 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2393 2394 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2395 } 2396 } 2397 2398 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2399 { 2400 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2401 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2402 u32 chan; 2403 2404 /* set TX ring length */ 2405 for (chan = 0; chan < tx_channels_count; chan++) 2406 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2407 (DMA_TX_SIZE - 1), chan); 2408 2409 /* set RX ring length */ 2410 for (chan = 0; chan < rx_channels_count; chan++) 2411 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2412 (DMA_RX_SIZE - 1), chan); 2413 } 2414 2415 /** 2416 * stmmac_set_tx_queue_weight - Set TX queue weight 2417 * @priv: driver private structure 2418 * Description: It is used for setting TX queues weight 2419 */ 2420 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2421 { 2422 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2423 u32 weight; 2424 u32 queue; 2425 2426 for (queue = 0; queue < tx_queues_count; queue++) { 2427 weight = priv->plat->tx_queues_cfg[queue].weight; 2428 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2429 } 2430 } 2431 2432 /** 2433 * stmmac_configure_cbs - Configure CBS in TX queue 2434 * @priv: driver private structure 2435 * Description: It is used for configuring CBS in AVB TX queues 2436 */ 2437 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2438 { 2439 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2440 u32 mode_to_use; 2441 u32 queue; 2442 2443 /* queue 0 is reserved for legacy traffic */ 2444 for (queue = 1; queue < tx_queues_count; queue++) { 2445 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2446 if (mode_to_use == MTL_QUEUE_DCB) 2447 continue; 2448 2449 stmmac_config_cbs(priv, priv->hw, 2450 priv->plat->tx_queues_cfg[queue].send_slope, 2451 priv->plat->tx_queues_cfg[queue].idle_slope, 2452 priv->plat->tx_queues_cfg[queue].high_credit, 2453 priv->plat->tx_queues_cfg[queue].low_credit, 2454 queue); 2455 } 2456 } 2457 2458 /** 2459 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2460 * @priv: driver private structure 2461 * Description: It is used for mapping RX queues to RX dma channels 2462 */ 2463 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2464 { 2465 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2466 u32 queue; 2467 u32 chan; 2468 2469 for (queue = 0; queue < rx_queues_count; queue++) { 2470 chan = priv->plat->rx_queues_cfg[queue].chan; 2471 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2472 } 2473 } 2474 2475 /** 2476 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2477 * @priv: driver private structure 2478 * Description: It is used for configuring the RX Queue Priority 2479 */ 2480 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2481 { 2482 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2483 u32 queue; 2484 u32 prio; 2485 2486 for (queue = 0; queue < rx_queues_count; queue++) { 2487 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2488 continue; 2489 2490 prio = priv->plat->rx_queues_cfg[queue].prio; 2491 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2492 } 2493 } 2494 2495 /** 2496 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2497 * @priv: driver private structure 2498 * Description: It is used for configuring the TX Queue Priority 2499 */ 2500 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2501 { 2502 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2503 u32 queue; 2504 u32 prio; 2505 2506 for (queue = 0; queue < tx_queues_count; queue++) { 2507 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2508 continue; 2509 2510 prio = priv->plat->tx_queues_cfg[queue].prio; 2511 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2512 } 2513 } 2514 2515 /** 2516 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2517 * @priv: driver private structure 2518 * Description: It is used for configuring the RX queue routing 2519 */ 2520 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2521 { 2522 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2523 u32 queue; 2524 u8 packet; 2525 2526 for (queue = 0; queue < rx_queues_count; queue++) { 2527 /* no specific packet type routing specified for the queue */ 2528 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2529 continue; 2530 2531 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2532 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2533 } 2534 } 2535 2536 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2537 { 2538 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2539 priv->rss.enable = false; 2540 return; 2541 } 2542 2543 if (priv->dev->features & NETIF_F_RXHASH) 2544 priv->rss.enable = true; 2545 else 2546 priv->rss.enable = false; 2547 2548 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2549 priv->plat->rx_queues_to_use); 2550 } 2551 2552 /** 2553 * stmmac_mtl_configuration - Configure MTL 2554 * @priv: driver private structure 2555 * Description: It is used for configurring MTL 2556 */ 2557 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2558 { 2559 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2560 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2561 2562 if (tx_queues_count > 1) 2563 stmmac_set_tx_queue_weight(priv); 2564 2565 /* Configure MTL RX algorithms */ 2566 if (rx_queues_count > 1) 2567 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2568 priv->plat->rx_sched_algorithm); 2569 2570 /* Configure MTL TX algorithms */ 2571 if (tx_queues_count > 1) 2572 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2573 priv->plat->tx_sched_algorithm); 2574 2575 /* Configure CBS in AVB TX queues */ 2576 if (tx_queues_count > 1) 2577 stmmac_configure_cbs(priv); 2578 2579 /* Map RX MTL to DMA channels */ 2580 stmmac_rx_queue_dma_chan_map(priv); 2581 2582 /* Enable MAC RX Queues */ 2583 stmmac_mac_enable_rx_queues(priv); 2584 2585 /* Set RX priorities */ 2586 if (rx_queues_count > 1) 2587 stmmac_mac_config_rx_queues_prio(priv); 2588 2589 /* Set TX priorities */ 2590 if (tx_queues_count > 1) 2591 stmmac_mac_config_tx_queues_prio(priv); 2592 2593 /* Set RX routing */ 2594 if (rx_queues_count > 1) 2595 stmmac_mac_config_rx_queues_routing(priv); 2596 2597 /* Receive Side Scaling */ 2598 if (rx_queues_count > 1) 2599 stmmac_mac_config_rss(priv); 2600 } 2601 2602 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2603 { 2604 if (priv->dma_cap.asp) { 2605 netdev_info(priv->dev, "Enabling Safety Features\n"); 2606 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2607 } else { 2608 netdev_info(priv->dev, "No Safety Features support found\n"); 2609 } 2610 } 2611 2612 /** 2613 * stmmac_hw_setup - setup mac in a usable state. 2614 * @dev : pointer to the device structure. 2615 * Description: 2616 * this is the main function to setup the HW in a usable state because the 2617 * dma engine is reset, the core registers are configured (e.g. AXI, 2618 * Checksum features, timers). The DMA is ready to start receiving and 2619 * transmitting. 2620 * Return value: 2621 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2622 * file on failure. 2623 */ 2624 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2625 { 2626 struct stmmac_priv *priv = netdev_priv(dev); 2627 u32 rx_cnt = priv->plat->rx_queues_to_use; 2628 u32 tx_cnt = priv->plat->tx_queues_to_use; 2629 u32 chan; 2630 int ret; 2631 2632 /* DMA initialization and SW reset */ 2633 ret = stmmac_init_dma_engine(priv); 2634 if (ret < 0) { 2635 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2636 __func__); 2637 return ret; 2638 } 2639 2640 /* Copy the MAC addr into the HW */ 2641 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2642 2643 /* PS and related bits will be programmed according to the speed */ 2644 if (priv->hw->pcs) { 2645 int speed = priv->plat->mac_port_sel_speed; 2646 2647 if ((speed == SPEED_10) || (speed == SPEED_100) || 2648 (speed == SPEED_1000)) { 2649 priv->hw->ps = speed; 2650 } else { 2651 dev_warn(priv->device, "invalid port speed\n"); 2652 priv->hw->ps = 0; 2653 } 2654 } 2655 2656 /* Initialize the MAC Core */ 2657 stmmac_core_init(priv, priv->hw, dev); 2658 2659 /* Initialize MTL*/ 2660 stmmac_mtl_configuration(priv); 2661 2662 /* Initialize Safety Features */ 2663 stmmac_safety_feat_configuration(priv); 2664 2665 ret = stmmac_rx_ipc(priv, priv->hw); 2666 if (!ret) { 2667 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2668 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2669 priv->hw->rx_csum = 0; 2670 } 2671 2672 /* Enable the MAC Rx/Tx */ 2673 stmmac_mac_set(priv, priv->ioaddr, true); 2674 2675 /* Set the HW DMA mode and the COE */ 2676 stmmac_dma_operation_mode(priv); 2677 2678 stmmac_mmc_setup(priv); 2679 2680 if (init_ptp) { 2681 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2682 if (ret < 0) 2683 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2684 2685 ret = stmmac_init_ptp(priv); 2686 if (ret == -EOPNOTSUPP) 2687 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2688 else if (ret) 2689 netdev_warn(priv->dev, "PTP init failed\n"); 2690 } 2691 2692 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2693 2694 if (priv->use_riwt) { 2695 if (!priv->rx_riwt) 2696 priv->rx_riwt = DEF_DMA_RIWT; 2697 2698 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2699 } 2700 2701 if (priv->hw->pcs) 2702 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2703 2704 /* set TX and RX rings length */ 2705 stmmac_set_rings_length(priv); 2706 2707 /* Enable TSO */ 2708 if (priv->tso) { 2709 for (chan = 0; chan < tx_cnt; chan++) 2710 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2711 } 2712 2713 /* Enable Split Header */ 2714 if (priv->sph && priv->hw->rx_csum) { 2715 for (chan = 0; chan < rx_cnt; chan++) 2716 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2717 } 2718 2719 /* VLAN Tag Insertion */ 2720 if (priv->dma_cap.vlins) 2721 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2722 2723 /* TBS */ 2724 for (chan = 0; chan < tx_cnt; chan++) { 2725 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2726 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2727 2728 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2729 } 2730 2731 /* Start the ball rolling... */ 2732 stmmac_start_all_dma(priv); 2733 2734 return 0; 2735 } 2736 2737 static void stmmac_hw_teardown(struct net_device *dev) 2738 { 2739 struct stmmac_priv *priv = netdev_priv(dev); 2740 2741 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2742 } 2743 2744 /** 2745 * stmmac_open - open entry point of the driver 2746 * @dev : pointer to the device structure. 2747 * Description: 2748 * This function is the open entry point of the driver. 2749 * Return value: 2750 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2751 * file on failure. 2752 */ 2753 static int stmmac_open(struct net_device *dev) 2754 { 2755 struct stmmac_priv *priv = netdev_priv(dev); 2756 int bfsize = 0; 2757 u32 chan; 2758 int ret; 2759 2760 if (priv->hw->pcs != STMMAC_PCS_TBI && 2761 priv->hw->pcs != STMMAC_PCS_RTBI && 2762 priv->hw->xpcs == NULL) { 2763 ret = stmmac_init_phy(dev); 2764 if (ret) { 2765 netdev_err(priv->dev, 2766 "%s: Cannot attach to PHY (error: %d)\n", 2767 __func__, ret); 2768 return ret; 2769 } 2770 } 2771 2772 /* Extra statistics */ 2773 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2774 priv->xstats.threshold = tc; 2775 2776 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2777 if (bfsize < 0) 2778 bfsize = 0; 2779 2780 if (bfsize < BUF_SIZE_16KiB) 2781 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2782 2783 priv->dma_buf_sz = bfsize; 2784 buf_sz = bfsize; 2785 2786 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2787 2788 /* Earlier check for TBS */ 2789 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2790 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2791 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2792 2793 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2794 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2795 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2796 } 2797 2798 ret = alloc_dma_desc_resources(priv); 2799 if (ret < 0) { 2800 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2801 __func__); 2802 goto dma_desc_error; 2803 } 2804 2805 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2806 if (ret < 0) { 2807 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2808 __func__); 2809 goto init_error; 2810 } 2811 2812 ret = stmmac_hw_setup(dev, true); 2813 if (ret < 0) { 2814 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2815 goto init_error; 2816 } 2817 2818 stmmac_init_coalesce(priv); 2819 2820 phylink_start(priv->phylink); 2821 2822 /* Request the IRQ lines */ 2823 ret = request_irq(dev->irq, stmmac_interrupt, 2824 IRQF_SHARED, dev->name, dev); 2825 if (unlikely(ret < 0)) { 2826 netdev_err(priv->dev, 2827 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2828 __func__, dev->irq, ret); 2829 goto irq_error; 2830 } 2831 2832 /* Request the Wake IRQ in case of another line is used for WoL */ 2833 if (priv->wol_irq != dev->irq) { 2834 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2835 IRQF_SHARED, dev->name, dev); 2836 if (unlikely(ret < 0)) { 2837 netdev_err(priv->dev, 2838 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2839 __func__, priv->wol_irq, ret); 2840 goto wolirq_error; 2841 } 2842 } 2843 2844 /* Request the IRQ lines */ 2845 if (priv->lpi_irq > 0) { 2846 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2847 dev->name, dev); 2848 if (unlikely(ret < 0)) { 2849 netdev_err(priv->dev, 2850 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2851 __func__, priv->lpi_irq, ret); 2852 goto lpiirq_error; 2853 } 2854 } 2855 2856 stmmac_enable_all_queues(priv); 2857 stmmac_start_all_queues(priv); 2858 2859 return 0; 2860 2861 lpiirq_error: 2862 if (priv->wol_irq != dev->irq) 2863 free_irq(priv->wol_irq, dev); 2864 wolirq_error: 2865 free_irq(dev->irq, dev); 2866 irq_error: 2867 phylink_stop(priv->phylink); 2868 2869 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2870 del_timer_sync(&priv->tx_queue[chan].txtimer); 2871 2872 stmmac_hw_teardown(dev); 2873 init_error: 2874 free_dma_desc_resources(priv); 2875 dma_desc_error: 2876 phylink_disconnect_phy(priv->phylink); 2877 return ret; 2878 } 2879 2880 /** 2881 * stmmac_release - close entry point of the driver 2882 * @dev : device pointer. 2883 * Description: 2884 * This is the stop entry point of the driver. 2885 */ 2886 static int stmmac_release(struct net_device *dev) 2887 { 2888 struct stmmac_priv *priv = netdev_priv(dev); 2889 u32 chan; 2890 2891 if (priv->eee_enabled) 2892 del_timer_sync(&priv->eee_ctrl_timer); 2893 2894 /* Stop and disconnect the PHY */ 2895 phylink_stop(priv->phylink); 2896 phylink_disconnect_phy(priv->phylink); 2897 2898 stmmac_stop_all_queues(priv); 2899 2900 stmmac_disable_all_queues(priv); 2901 2902 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2903 del_timer_sync(&priv->tx_queue[chan].txtimer); 2904 2905 /* Free the IRQ lines */ 2906 free_irq(dev->irq, dev); 2907 if (priv->wol_irq != dev->irq) 2908 free_irq(priv->wol_irq, dev); 2909 if (priv->lpi_irq > 0) 2910 free_irq(priv->lpi_irq, dev); 2911 2912 /* Stop TX/RX DMA and clear the descriptors */ 2913 stmmac_stop_all_dma(priv); 2914 2915 /* Release and free the Rx/Tx resources */ 2916 free_dma_desc_resources(priv); 2917 2918 /* Disable the MAC Rx/Tx */ 2919 stmmac_mac_set(priv, priv->ioaddr, false); 2920 2921 netif_carrier_off(dev); 2922 2923 stmmac_release_ptp(priv); 2924 2925 return 0; 2926 } 2927 2928 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2929 struct stmmac_tx_queue *tx_q) 2930 { 2931 u16 tag = 0x0, inner_tag = 0x0; 2932 u32 inner_type = 0x0; 2933 struct dma_desc *p; 2934 2935 if (!priv->dma_cap.vlins) 2936 return false; 2937 if (!skb_vlan_tag_present(skb)) 2938 return false; 2939 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2940 inner_tag = skb_vlan_tag_get(skb); 2941 inner_type = STMMAC_VLAN_INSERT; 2942 } 2943 2944 tag = skb_vlan_tag_get(skb); 2945 2946 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2947 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2948 else 2949 p = &tx_q->dma_tx[tx_q->cur_tx]; 2950 2951 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2952 return false; 2953 2954 stmmac_set_tx_owner(priv, p); 2955 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2956 return true; 2957 } 2958 2959 /** 2960 * stmmac_tso_allocator - close entry point of the driver 2961 * @priv: driver private structure 2962 * @des: buffer start address 2963 * @total_len: total length to fill in descriptors 2964 * @last_segmant: condition for the last descriptor 2965 * @queue: TX queue index 2966 * Description: 2967 * This function fills descriptor and request new descriptors according to 2968 * buffer length to fill 2969 */ 2970 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2971 int total_len, bool last_segment, u32 queue) 2972 { 2973 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2974 struct dma_desc *desc; 2975 u32 buff_size; 2976 int tmp_len; 2977 2978 tmp_len = total_len; 2979 2980 while (tmp_len > 0) { 2981 dma_addr_t curr_addr; 2982 2983 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2984 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2985 2986 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2987 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 2988 else 2989 desc = &tx_q->dma_tx[tx_q->cur_tx]; 2990 2991 curr_addr = des + (total_len - tmp_len); 2992 if (priv->dma_cap.addr64 <= 32) 2993 desc->des0 = cpu_to_le32(curr_addr); 2994 else 2995 stmmac_set_desc_addr(priv, desc, curr_addr); 2996 2997 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2998 TSO_MAX_BUFF_SIZE : tmp_len; 2999 3000 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3001 0, 1, 3002 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3003 0, 0); 3004 3005 tmp_len -= TSO_MAX_BUFF_SIZE; 3006 } 3007 } 3008 3009 /** 3010 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3011 * @skb : the socket buffer 3012 * @dev : device pointer 3013 * Description: this is the transmit function that is called on TSO frames 3014 * (support available on GMAC4 and newer chips). 3015 * Diagram below show the ring programming in case of TSO frames: 3016 * 3017 * First Descriptor 3018 * -------- 3019 * | DES0 |---> buffer1 = L2/L3/L4 header 3020 * | DES1 |---> TCP Payload (can continue on next descr...) 3021 * | DES2 |---> buffer 1 and 2 len 3022 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3023 * -------- 3024 * | 3025 * ... 3026 * | 3027 * -------- 3028 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3029 * | DES1 | --| 3030 * | DES2 | --> buffer 1 and 2 len 3031 * | DES3 | 3032 * -------- 3033 * 3034 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3035 */ 3036 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3037 { 3038 struct dma_desc *desc, *first, *mss_desc = NULL; 3039 struct stmmac_priv *priv = netdev_priv(dev); 3040 int desc_size, tmp_pay_len = 0, first_tx; 3041 int nfrags = skb_shinfo(skb)->nr_frags; 3042 u32 queue = skb_get_queue_mapping(skb); 3043 unsigned int first_entry, tx_packets; 3044 struct stmmac_tx_queue *tx_q; 3045 bool has_vlan, set_ic; 3046 u8 proto_hdr_len, hdr; 3047 u32 pay_len, mss; 3048 dma_addr_t des; 3049 int i; 3050 3051 tx_q = &priv->tx_queue[queue]; 3052 first_tx = tx_q->cur_tx; 3053 3054 /* Compute header lengths */ 3055 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3056 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3057 hdr = sizeof(struct udphdr); 3058 } else { 3059 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3060 hdr = tcp_hdrlen(skb); 3061 } 3062 3063 /* Desc availability based on threshold should be enough safe */ 3064 if (unlikely(stmmac_tx_avail(priv, queue) < 3065 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3066 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3067 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3068 queue)); 3069 /* This is a hard error, log it. */ 3070 netdev_err(priv->dev, 3071 "%s: Tx Ring full when queue awake\n", 3072 __func__); 3073 } 3074 return NETDEV_TX_BUSY; 3075 } 3076 3077 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3078 3079 mss = skb_shinfo(skb)->gso_size; 3080 3081 /* set new MSS value if needed */ 3082 if (mss != tx_q->mss) { 3083 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3084 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3085 else 3086 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3087 3088 stmmac_set_mss(priv, mss_desc, mss); 3089 tx_q->mss = mss; 3090 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3091 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3092 } 3093 3094 if (netif_msg_tx_queued(priv)) { 3095 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3096 __func__, hdr, proto_hdr_len, pay_len, mss); 3097 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3098 skb->data_len); 3099 } 3100 3101 /* Check if VLAN can be inserted by HW */ 3102 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3103 3104 first_entry = tx_q->cur_tx; 3105 WARN_ON(tx_q->tx_skbuff[first_entry]); 3106 3107 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3108 desc = &tx_q->dma_entx[first_entry].basic; 3109 else 3110 desc = &tx_q->dma_tx[first_entry]; 3111 first = desc; 3112 3113 if (has_vlan) 3114 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3115 3116 /* first descriptor: fill Headers on Buf1 */ 3117 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3118 DMA_TO_DEVICE); 3119 if (dma_mapping_error(priv->device, des)) 3120 goto dma_map_err; 3121 3122 tx_q->tx_skbuff_dma[first_entry].buf = des; 3123 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3124 3125 if (priv->dma_cap.addr64 <= 32) { 3126 first->des0 = cpu_to_le32(des); 3127 3128 /* Fill start of payload in buff2 of first descriptor */ 3129 if (pay_len) 3130 first->des1 = cpu_to_le32(des + proto_hdr_len); 3131 3132 /* If needed take extra descriptors to fill the remaining payload */ 3133 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3134 } else { 3135 stmmac_set_desc_addr(priv, first, des); 3136 tmp_pay_len = pay_len; 3137 des += proto_hdr_len; 3138 pay_len = 0; 3139 } 3140 3141 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3142 3143 /* Prepare fragments */ 3144 for (i = 0; i < nfrags; i++) { 3145 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3146 3147 des = skb_frag_dma_map(priv->device, frag, 0, 3148 skb_frag_size(frag), 3149 DMA_TO_DEVICE); 3150 if (dma_mapping_error(priv->device, des)) 3151 goto dma_map_err; 3152 3153 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3154 (i == nfrags - 1), queue); 3155 3156 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3157 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3158 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3159 } 3160 3161 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3162 3163 /* Only the last descriptor gets to point to the skb. */ 3164 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3165 3166 /* Manage tx mitigation */ 3167 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3168 tx_q->tx_count_frames += tx_packets; 3169 3170 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3171 set_ic = true; 3172 else if (!priv->tx_coal_frames) 3173 set_ic = false; 3174 else if (tx_packets > priv->tx_coal_frames) 3175 set_ic = true; 3176 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3177 set_ic = true; 3178 else 3179 set_ic = false; 3180 3181 if (set_ic) { 3182 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3183 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3184 else 3185 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3186 3187 tx_q->tx_count_frames = 0; 3188 stmmac_set_tx_ic(priv, desc); 3189 priv->xstats.tx_set_ic_bit++; 3190 } 3191 3192 /* We've used all descriptors we need for this skb, however, 3193 * advance cur_tx so that it references a fresh descriptor. 3194 * ndo_start_xmit will fill this descriptor the next time it's 3195 * called and stmmac_tx_clean may clean up to this descriptor. 3196 */ 3197 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3198 3199 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3200 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3201 __func__); 3202 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3203 } 3204 3205 dev->stats.tx_bytes += skb->len; 3206 priv->xstats.tx_tso_frames++; 3207 priv->xstats.tx_tso_nfrags += nfrags; 3208 3209 if (priv->sarc_type) 3210 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3211 3212 skb_tx_timestamp(skb); 3213 3214 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3215 priv->hwts_tx_en)) { 3216 /* declare that device is doing timestamping */ 3217 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3218 stmmac_enable_tx_timestamp(priv, first); 3219 } 3220 3221 /* Complete the first descriptor before granting the DMA */ 3222 stmmac_prepare_tso_tx_desc(priv, first, 1, 3223 proto_hdr_len, 3224 pay_len, 3225 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3226 hdr / 4, (skb->len - proto_hdr_len)); 3227 3228 /* If context desc is used to change MSS */ 3229 if (mss_desc) { 3230 /* Make sure that first descriptor has been completely 3231 * written, including its own bit. This is because MSS is 3232 * actually before first descriptor, so we need to make 3233 * sure that MSS's own bit is the last thing written. 3234 */ 3235 dma_wmb(); 3236 stmmac_set_tx_owner(priv, mss_desc); 3237 } 3238 3239 /* The own bit must be the latest setting done when prepare the 3240 * descriptor and then barrier is needed to make sure that 3241 * all is coherent before granting the DMA engine. 3242 */ 3243 wmb(); 3244 3245 if (netif_msg_pktdata(priv)) { 3246 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3247 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3248 tx_q->cur_tx, first, nfrags); 3249 pr_info(">>> frame to be transmitted: "); 3250 print_pkt(skb->data, skb_headlen(skb)); 3251 } 3252 3253 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3254 3255 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3256 desc_size = sizeof(struct dma_edesc); 3257 else 3258 desc_size = sizeof(struct dma_desc); 3259 3260 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3261 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3262 stmmac_tx_timer_arm(priv, queue); 3263 3264 return NETDEV_TX_OK; 3265 3266 dma_map_err: 3267 dev_err(priv->device, "Tx dma map failed\n"); 3268 dev_kfree_skb(skb); 3269 priv->dev->stats.tx_dropped++; 3270 return NETDEV_TX_OK; 3271 } 3272 3273 /** 3274 * stmmac_xmit - Tx entry point of the driver 3275 * @skb : the socket buffer 3276 * @dev : device pointer 3277 * Description : this is the tx entry point of the driver. 3278 * It programs the chain or the ring and supports oversized frames 3279 * and SG feature. 3280 */ 3281 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3282 { 3283 unsigned int first_entry, tx_packets, enh_desc; 3284 struct stmmac_priv *priv = netdev_priv(dev); 3285 unsigned int nopaged_len = skb_headlen(skb); 3286 int i, csum_insertion = 0, is_jumbo = 0; 3287 u32 queue = skb_get_queue_mapping(skb); 3288 int nfrags = skb_shinfo(skb)->nr_frags; 3289 int gso = skb_shinfo(skb)->gso_type; 3290 struct dma_edesc *tbs_desc = NULL; 3291 int entry, desc_size, first_tx; 3292 struct dma_desc *desc, *first; 3293 struct stmmac_tx_queue *tx_q; 3294 bool has_vlan, set_ic; 3295 dma_addr_t des; 3296 3297 tx_q = &priv->tx_queue[queue]; 3298 first_tx = tx_q->cur_tx; 3299 3300 if (priv->tx_path_in_lpi_mode) 3301 stmmac_disable_eee_mode(priv); 3302 3303 /* Manage oversized TCP frames for GMAC4 device */ 3304 if (skb_is_gso(skb) && priv->tso) { 3305 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3306 return stmmac_tso_xmit(skb, dev); 3307 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3308 return stmmac_tso_xmit(skb, dev); 3309 } 3310 3311 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3312 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3313 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3314 queue)); 3315 /* This is a hard error, log it. */ 3316 netdev_err(priv->dev, 3317 "%s: Tx Ring full when queue awake\n", 3318 __func__); 3319 } 3320 return NETDEV_TX_BUSY; 3321 } 3322 3323 /* Check if VLAN can be inserted by HW */ 3324 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3325 3326 entry = tx_q->cur_tx; 3327 first_entry = entry; 3328 WARN_ON(tx_q->tx_skbuff[first_entry]); 3329 3330 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3331 3332 if (likely(priv->extend_desc)) 3333 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3334 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3335 desc = &tx_q->dma_entx[entry].basic; 3336 else 3337 desc = tx_q->dma_tx + entry; 3338 3339 first = desc; 3340 3341 if (has_vlan) 3342 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3343 3344 enh_desc = priv->plat->enh_desc; 3345 /* To program the descriptors according to the size of the frame */ 3346 if (enh_desc) 3347 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3348 3349 if (unlikely(is_jumbo)) { 3350 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3351 if (unlikely(entry < 0) && (entry != -EINVAL)) 3352 goto dma_map_err; 3353 } 3354 3355 for (i = 0; i < nfrags; i++) { 3356 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3357 int len = skb_frag_size(frag); 3358 bool last_segment = (i == (nfrags - 1)); 3359 3360 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3361 WARN_ON(tx_q->tx_skbuff[entry]); 3362 3363 if (likely(priv->extend_desc)) 3364 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3365 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3366 desc = &tx_q->dma_entx[entry].basic; 3367 else 3368 desc = tx_q->dma_tx + entry; 3369 3370 des = skb_frag_dma_map(priv->device, frag, 0, len, 3371 DMA_TO_DEVICE); 3372 if (dma_mapping_error(priv->device, des)) 3373 goto dma_map_err; /* should reuse desc w/o issues */ 3374 3375 tx_q->tx_skbuff_dma[entry].buf = des; 3376 3377 stmmac_set_desc_addr(priv, desc, des); 3378 3379 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3380 tx_q->tx_skbuff_dma[entry].len = len; 3381 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3382 3383 /* Prepare the descriptor and set the own bit too */ 3384 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3385 priv->mode, 1, last_segment, skb->len); 3386 } 3387 3388 /* Only the last descriptor gets to point to the skb. */ 3389 tx_q->tx_skbuff[entry] = skb; 3390 3391 /* According to the coalesce parameter the IC bit for the latest 3392 * segment is reset and the timer re-started to clean the tx status. 3393 * This approach takes care about the fragments: desc is the first 3394 * element in case of no SG. 3395 */ 3396 tx_packets = (entry + 1) - first_tx; 3397 tx_q->tx_count_frames += tx_packets; 3398 3399 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3400 set_ic = true; 3401 else if (!priv->tx_coal_frames) 3402 set_ic = false; 3403 else if (tx_packets > priv->tx_coal_frames) 3404 set_ic = true; 3405 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3406 set_ic = true; 3407 else 3408 set_ic = false; 3409 3410 if (set_ic) { 3411 if (likely(priv->extend_desc)) 3412 desc = &tx_q->dma_etx[entry].basic; 3413 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3414 desc = &tx_q->dma_entx[entry].basic; 3415 else 3416 desc = &tx_q->dma_tx[entry]; 3417 3418 tx_q->tx_count_frames = 0; 3419 stmmac_set_tx_ic(priv, desc); 3420 priv->xstats.tx_set_ic_bit++; 3421 } 3422 3423 /* We've used all descriptors we need for this skb, however, 3424 * advance cur_tx so that it references a fresh descriptor. 3425 * ndo_start_xmit will fill this descriptor the next time it's 3426 * called and stmmac_tx_clean may clean up to this descriptor. 3427 */ 3428 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3429 tx_q->cur_tx = entry; 3430 3431 if (netif_msg_pktdata(priv)) { 3432 netdev_dbg(priv->dev, 3433 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3434 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3435 entry, first, nfrags); 3436 3437 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3438 print_pkt(skb->data, skb->len); 3439 } 3440 3441 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3442 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3443 __func__); 3444 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3445 } 3446 3447 dev->stats.tx_bytes += skb->len; 3448 3449 if (priv->sarc_type) 3450 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3451 3452 skb_tx_timestamp(skb); 3453 3454 /* Ready to fill the first descriptor and set the OWN bit w/o any 3455 * problems because all the descriptors are actually ready to be 3456 * passed to the DMA engine. 3457 */ 3458 if (likely(!is_jumbo)) { 3459 bool last_segment = (nfrags == 0); 3460 3461 des = dma_map_single(priv->device, skb->data, 3462 nopaged_len, DMA_TO_DEVICE); 3463 if (dma_mapping_error(priv->device, des)) 3464 goto dma_map_err; 3465 3466 tx_q->tx_skbuff_dma[first_entry].buf = des; 3467 3468 stmmac_set_desc_addr(priv, first, des); 3469 3470 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3471 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3472 3473 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3474 priv->hwts_tx_en)) { 3475 /* declare that device is doing timestamping */ 3476 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3477 stmmac_enable_tx_timestamp(priv, first); 3478 } 3479 3480 /* Prepare the first descriptor setting the OWN bit too */ 3481 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3482 csum_insertion, priv->mode, 0, last_segment, 3483 skb->len); 3484 } 3485 3486 if (tx_q->tbs & STMMAC_TBS_EN) { 3487 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3488 3489 tbs_desc = &tx_q->dma_entx[first_entry]; 3490 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3491 } 3492 3493 stmmac_set_tx_owner(priv, first); 3494 3495 /* The own bit must be the latest setting done when prepare the 3496 * descriptor and then barrier is needed to make sure that 3497 * all is coherent before granting the DMA engine. 3498 */ 3499 wmb(); 3500 3501 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3502 3503 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3504 3505 if (likely(priv->extend_desc)) 3506 desc_size = sizeof(struct dma_extended_desc); 3507 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3508 desc_size = sizeof(struct dma_edesc); 3509 else 3510 desc_size = sizeof(struct dma_desc); 3511 3512 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3513 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3514 stmmac_tx_timer_arm(priv, queue); 3515 3516 return NETDEV_TX_OK; 3517 3518 dma_map_err: 3519 netdev_err(priv->dev, "Tx DMA map failed\n"); 3520 dev_kfree_skb(skb); 3521 priv->dev->stats.tx_dropped++; 3522 return NETDEV_TX_OK; 3523 } 3524 3525 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3526 { 3527 struct vlan_ethhdr *veth; 3528 __be16 vlan_proto; 3529 u16 vlanid; 3530 3531 veth = (struct vlan_ethhdr *)skb->data; 3532 vlan_proto = veth->h_vlan_proto; 3533 3534 if ((vlan_proto == htons(ETH_P_8021Q) && 3535 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3536 (vlan_proto == htons(ETH_P_8021AD) && 3537 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3538 /* pop the vlan tag */ 3539 vlanid = ntohs(veth->h_vlan_TCI); 3540 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3541 skb_pull(skb, VLAN_HLEN); 3542 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3543 } 3544 } 3545 3546 /** 3547 * stmmac_rx_refill - refill used skb preallocated buffers 3548 * @priv: driver private structure 3549 * @queue: RX queue index 3550 * Description : this is to reallocate the skb for the reception process 3551 * that is based on zero-copy. 3552 */ 3553 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3554 { 3555 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3556 int len, dirty = stmmac_rx_dirty(priv, queue); 3557 unsigned int entry = rx_q->dirty_rx; 3558 3559 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3560 3561 while (dirty-- > 0) { 3562 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3563 struct dma_desc *p; 3564 bool use_rx_wd; 3565 3566 if (priv->extend_desc) 3567 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3568 else 3569 p = rx_q->dma_rx + entry; 3570 3571 if (!buf->page) { 3572 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3573 if (!buf->page) 3574 break; 3575 } 3576 3577 if (priv->sph && !buf->sec_page) { 3578 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3579 if (!buf->sec_page) 3580 break; 3581 3582 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3583 3584 dma_sync_single_for_device(priv->device, buf->sec_addr, 3585 len, DMA_FROM_DEVICE); 3586 } 3587 3588 buf->addr = page_pool_get_dma_addr(buf->page); 3589 3590 /* Sync whole allocation to device. This will invalidate old 3591 * data. 3592 */ 3593 dma_sync_single_for_device(priv->device, buf->addr, len, 3594 DMA_FROM_DEVICE); 3595 3596 stmmac_set_desc_addr(priv, p, buf->addr); 3597 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3598 stmmac_refill_desc3(priv, rx_q, p); 3599 3600 rx_q->rx_count_frames++; 3601 rx_q->rx_count_frames += priv->rx_coal_frames; 3602 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3603 rx_q->rx_count_frames = 0; 3604 3605 use_rx_wd = !priv->rx_coal_frames; 3606 use_rx_wd |= rx_q->rx_count_frames > 0; 3607 if (!priv->use_riwt) 3608 use_rx_wd = false; 3609 3610 dma_wmb(); 3611 stmmac_set_rx_owner(priv, p, use_rx_wd); 3612 3613 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3614 } 3615 rx_q->dirty_rx = entry; 3616 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3617 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3618 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3619 } 3620 3621 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3622 struct dma_desc *p, 3623 int status, unsigned int len) 3624 { 3625 int ret, coe = priv->hw->rx_csum; 3626 unsigned int plen = 0, hlen = 0; 3627 3628 /* Not first descriptor, buffer is always zero */ 3629 if (priv->sph && len) 3630 return 0; 3631 3632 /* First descriptor, get split header length */ 3633 ret = stmmac_get_rx_header_len(priv, p, &hlen); 3634 if (priv->sph && hlen) { 3635 priv->xstats.rx_split_hdr_pkt_n++; 3636 return hlen; 3637 } 3638 3639 /* First descriptor, not last descriptor and not split header */ 3640 if (status & rx_not_ls) 3641 return priv->dma_buf_sz; 3642 3643 plen = stmmac_get_rx_frame_len(priv, p, coe); 3644 3645 /* First descriptor and last descriptor and not split header */ 3646 return min_t(unsigned int, priv->dma_buf_sz, plen); 3647 } 3648 3649 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3650 struct dma_desc *p, 3651 int status, unsigned int len) 3652 { 3653 int coe = priv->hw->rx_csum; 3654 unsigned int plen = 0; 3655 3656 /* Not split header, buffer is not available */ 3657 if (!priv->sph) 3658 return 0; 3659 3660 /* Not last descriptor */ 3661 if (status & rx_not_ls) 3662 return priv->dma_buf_sz; 3663 3664 plen = stmmac_get_rx_frame_len(priv, p, coe); 3665 3666 /* Last descriptor */ 3667 return plen - len; 3668 } 3669 3670 /** 3671 * stmmac_rx - manage the receive process 3672 * @priv: driver private structure 3673 * @limit: napi bugget 3674 * @queue: RX queue index. 3675 * Description : this the function called by the napi poll method. 3676 * It gets all the frames inside the ring. 3677 */ 3678 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3679 { 3680 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3681 struct stmmac_channel *ch = &priv->channel[queue]; 3682 unsigned int count = 0, error = 0, len = 0; 3683 int status = 0, coe = priv->hw->rx_csum; 3684 unsigned int next_entry = rx_q->cur_rx; 3685 struct sk_buff *skb = NULL; 3686 3687 if (netif_msg_rx_status(priv)) { 3688 void *rx_head; 3689 3690 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3691 if (priv->extend_desc) 3692 rx_head = (void *)rx_q->dma_erx; 3693 else 3694 rx_head = (void *)rx_q->dma_rx; 3695 3696 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3697 } 3698 while (count < limit) { 3699 unsigned int buf1_len = 0, buf2_len = 0; 3700 enum pkt_hash_types hash_type; 3701 struct stmmac_rx_buffer *buf; 3702 struct dma_desc *np, *p; 3703 int entry; 3704 u32 hash; 3705 3706 if (!count && rx_q->state_saved) { 3707 skb = rx_q->state.skb; 3708 error = rx_q->state.error; 3709 len = rx_q->state.len; 3710 } else { 3711 rx_q->state_saved = false; 3712 skb = NULL; 3713 error = 0; 3714 len = 0; 3715 } 3716 3717 if (count >= limit) 3718 break; 3719 3720 read_again: 3721 buf1_len = 0; 3722 buf2_len = 0; 3723 entry = next_entry; 3724 buf = &rx_q->buf_pool[entry]; 3725 3726 if (priv->extend_desc) 3727 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3728 else 3729 p = rx_q->dma_rx + entry; 3730 3731 /* read the status of the incoming frame */ 3732 status = stmmac_rx_status(priv, &priv->dev->stats, 3733 &priv->xstats, p); 3734 /* check if managed by the DMA otherwise go ahead */ 3735 if (unlikely(status & dma_own)) 3736 break; 3737 3738 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3739 next_entry = rx_q->cur_rx; 3740 3741 if (priv->extend_desc) 3742 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3743 else 3744 np = rx_q->dma_rx + next_entry; 3745 3746 prefetch(np); 3747 3748 if (priv->extend_desc) 3749 stmmac_rx_extended_status(priv, &priv->dev->stats, 3750 &priv->xstats, rx_q->dma_erx + entry); 3751 if (unlikely(status == discard_frame)) { 3752 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3753 buf->page = NULL; 3754 error = 1; 3755 if (!priv->hwts_rx_en) 3756 priv->dev->stats.rx_errors++; 3757 } 3758 3759 if (unlikely(error && (status & rx_not_ls))) 3760 goto read_again; 3761 if (unlikely(error)) { 3762 dev_kfree_skb(skb); 3763 skb = NULL; 3764 count++; 3765 continue; 3766 } 3767 3768 /* Buffer is good. Go on. */ 3769 3770 prefetch(page_address(buf->page)); 3771 if (buf->sec_page) 3772 prefetch(page_address(buf->sec_page)); 3773 3774 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3775 len += buf1_len; 3776 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3777 len += buf2_len; 3778 3779 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3780 * Type frames (LLC/LLC-SNAP) 3781 * 3782 * llc_snap is never checked in GMAC >= 4, so this ACS 3783 * feature is always disabled and packets need to be 3784 * stripped manually. 3785 */ 3786 if (likely(!(status & rx_not_ls)) && 3787 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3788 unlikely(status != llc_snap))) { 3789 if (buf2_len) 3790 buf2_len -= ETH_FCS_LEN; 3791 else 3792 buf1_len -= ETH_FCS_LEN; 3793 3794 len -= ETH_FCS_LEN; 3795 } 3796 3797 if (!skb) { 3798 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3799 if (!skb) { 3800 priv->dev->stats.rx_dropped++; 3801 count++; 3802 goto drain_data; 3803 } 3804 3805 dma_sync_single_for_cpu(priv->device, buf->addr, 3806 buf1_len, DMA_FROM_DEVICE); 3807 skb_copy_to_linear_data(skb, page_address(buf->page), 3808 buf1_len); 3809 skb_put(skb, buf1_len); 3810 3811 /* Data payload copied into SKB, page ready for recycle */ 3812 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3813 buf->page = NULL; 3814 } else if (buf1_len) { 3815 dma_sync_single_for_cpu(priv->device, buf->addr, 3816 buf1_len, DMA_FROM_DEVICE); 3817 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3818 buf->page, 0, buf1_len, 3819 priv->dma_buf_sz); 3820 3821 /* Data payload appended into SKB */ 3822 page_pool_release_page(rx_q->page_pool, buf->page); 3823 buf->page = NULL; 3824 } 3825 3826 if (buf2_len) { 3827 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3828 buf2_len, DMA_FROM_DEVICE); 3829 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3830 buf->sec_page, 0, buf2_len, 3831 priv->dma_buf_sz); 3832 3833 /* Data payload appended into SKB */ 3834 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3835 buf->sec_page = NULL; 3836 } 3837 3838 drain_data: 3839 if (likely(status & rx_not_ls)) 3840 goto read_again; 3841 if (!skb) 3842 continue; 3843 3844 /* Got entire packet into SKB. Finish it. */ 3845 3846 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3847 stmmac_rx_vlan(priv->dev, skb); 3848 skb->protocol = eth_type_trans(skb, priv->dev); 3849 3850 if (unlikely(!coe)) 3851 skb_checksum_none_assert(skb); 3852 else 3853 skb->ip_summed = CHECKSUM_UNNECESSARY; 3854 3855 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3856 skb_set_hash(skb, hash, hash_type); 3857 3858 skb_record_rx_queue(skb, queue); 3859 napi_gro_receive(&ch->rx_napi, skb); 3860 skb = NULL; 3861 3862 priv->dev->stats.rx_packets++; 3863 priv->dev->stats.rx_bytes += len; 3864 count++; 3865 } 3866 3867 if (status & rx_not_ls || skb) { 3868 rx_q->state_saved = true; 3869 rx_q->state.skb = skb; 3870 rx_q->state.error = error; 3871 rx_q->state.len = len; 3872 } 3873 3874 stmmac_rx_refill(priv, queue); 3875 3876 priv->xstats.rx_pkt_n += count; 3877 3878 return count; 3879 } 3880 3881 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3882 { 3883 struct stmmac_channel *ch = 3884 container_of(napi, struct stmmac_channel, rx_napi); 3885 struct stmmac_priv *priv = ch->priv_data; 3886 u32 chan = ch->index; 3887 int work_done; 3888 3889 priv->xstats.napi_poll++; 3890 3891 work_done = stmmac_rx(priv, budget, chan); 3892 if (work_done < budget && napi_complete_done(napi, work_done)) { 3893 unsigned long flags; 3894 3895 spin_lock_irqsave(&ch->lock, flags); 3896 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3897 spin_unlock_irqrestore(&ch->lock, flags); 3898 } 3899 3900 return work_done; 3901 } 3902 3903 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3904 { 3905 struct stmmac_channel *ch = 3906 container_of(napi, struct stmmac_channel, tx_napi); 3907 struct stmmac_priv *priv = ch->priv_data; 3908 u32 chan = ch->index; 3909 int work_done; 3910 3911 priv->xstats.napi_poll++; 3912 3913 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3914 work_done = min(work_done, budget); 3915 3916 if (work_done < budget && napi_complete_done(napi, work_done)) { 3917 unsigned long flags; 3918 3919 spin_lock_irqsave(&ch->lock, flags); 3920 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3921 spin_unlock_irqrestore(&ch->lock, flags); 3922 } 3923 3924 return work_done; 3925 } 3926 3927 /** 3928 * stmmac_tx_timeout 3929 * @dev : Pointer to net device structure 3930 * Description: this function is called when a packet transmission fails to 3931 * complete within a reasonable time. The driver will mark the error in the 3932 * netdev structure and arrange for the device to be reset to a sane state 3933 * in order to transmit a new packet. 3934 */ 3935 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3936 { 3937 struct stmmac_priv *priv = netdev_priv(dev); 3938 3939 stmmac_global_err(priv); 3940 } 3941 3942 /** 3943 * stmmac_set_rx_mode - entry point for multicast addressing 3944 * @dev : pointer to the device structure 3945 * Description: 3946 * This function is a driver entry point which gets called by the kernel 3947 * whenever multicast addresses must be enabled/disabled. 3948 * Return value: 3949 * void. 3950 */ 3951 static void stmmac_set_rx_mode(struct net_device *dev) 3952 { 3953 struct stmmac_priv *priv = netdev_priv(dev); 3954 3955 stmmac_set_filter(priv, priv->hw, dev); 3956 } 3957 3958 /** 3959 * stmmac_change_mtu - entry point to change MTU size for the device. 3960 * @dev : device pointer. 3961 * @new_mtu : the new MTU size for the device. 3962 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3963 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3964 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3965 * Return value: 3966 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3967 * file on failure. 3968 */ 3969 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3970 { 3971 struct stmmac_priv *priv = netdev_priv(dev); 3972 int txfifosz = priv->plat->tx_fifo_size; 3973 3974 if (txfifosz == 0) 3975 txfifosz = priv->dma_cap.tx_fifo_size; 3976 3977 txfifosz /= priv->plat->tx_queues_to_use; 3978 3979 if (netif_running(dev)) { 3980 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3981 return -EBUSY; 3982 } 3983 3984 new_mtu = STMMAC_ALIGN(new_mtu); 3985 3986 /* If condition true, FIFO is too small or MTU too large */ 3987 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 3988 return -EINVAL; 3989 3990 dev->mtu = new_mtu; 3991 3992 netdev_update_features(dev); 3993 3994 return 0; 3995 } 3996 3997 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3998 netdev_features_t features) 3999 { 4000 struct stmmac_priv *priv = netdev_priv(dev); 4001 4002 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 4003 features &= ~NETIF_F_RXCSUM; 4004 4005 if (!priv->plat->tx_coe) 4006 features &= ~NETIF_F_CSUM_MASK; 4007 4008 /* Some GMAC devices have a bugged Jumbo frame support that 4009 * needs to have the Tx COE disabled for oversized frames 4010 * (due to limited buffer sizes). In this case we disable 4011 * the TX csum insertion in the TDES and not use SF. 4012 */ 4013 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 4014 features &= ~NETIF_F_CSUM_MASK; 4015 4016 /* Disable tso if asked by ethtool */ 4017 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4018 if (features & NETIF_F_TSO) 4019 priv->tso = true; 4020 else 4021 priv->tso = false; 4022 } 4023 4024 return features; 4025 } 4026 4027 static int stmmac_set_features(struct net_device *netdev, 4028 netdev_features_t features) 4029 { 4030 struct stmmac_priv *priv = netdev_priv(netdev); 4031 bool sph_en; 4032 u32 chan; 4033 4034 /* Keep the COE Type in case of csum is supporting */ 4035 if (features & NETIF_F_RXCSUM) 4036 priv->hw->rx_csum = priv->plat->rx_coe; 4037 else 4038 priv->hw->rx_csum = 0; 4039 /* No check needed because rx_coe has been set before and it will be 4040 * fixed in case of issue. 4041 */ 4042 stmmac_rx_ipc(priv, priv->hw); 4043 4044 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 4045 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 4046 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 4047 4048 return 0; 4049 } 4050 4051 /** 4052 * stmmac_interrupt - main ISR 4053 * @irq: interrupt number. 4054 * @dev_id: to pass the net device pointer (must be valid). 4055 * Description: this is the main driver interrupt service routine. 4056 * It can call: 4057 * o DMA service routine (to manage incoming frame reception and transmission 4058 * status) 4059 * o Core interrupts to manage: remote wake-up, management counter, LPI 4060 * interrupts. 4061 */ 4062 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4063 { 4064 struct net_device *dev = (struct net_device *)dev_id; 4065 struct stmmac_priv *priv = netdev_priv(dev); 4066 u32 rx_cnt = priv->plat->rx_queues_to_use; 4067 u32 tx_cnt = priv->plat->tx_queues_to_use; 4068 u32 queues_count; 4069 u32 queue; 4070 bool xmac; 4071 4072 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4073 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4074 4075 if (priv->irq_wake) 4076 pm_wakeup_event(priv->device, 0); 4077 4078 /* Check if adapter is up */ 4079 if (test_bit(STMMAC_DOWN, &priv->state)) 4080 return IRQ_HANDLED; 4081 /* Check if a fatal error happened */ 4082 if (stmmac_safety_feat_interrupt(priv)) 4083 return IRQ_HANDLED; 4084 4085 /* To handle GMAC own interrupts */ 4086 if ((priv->plat->has_gmac) || xmac) { 4087 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4088 int mtl_status; 4089 4090 if (unlikely(status)) { 4091 /* For LPI we need to save the tx status */ 4092 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4093 priv->tx_path_in_lpi_mode = true; 4094 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4095 priv->tx_path_in_lpi_mode = false; 4096 } 4097 4098 for (queue = 0; queue < queues_count; queue++) { 4099 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4100 4101 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4102 queue); 4103 if (mtl_status != -EINVAL) 4104 status |= mtl_status; 4105 4106 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4107 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4108 rx_q->rx_tail_addr, 4109 queue); 4110 } 4111 4112 /* PCS link status */ 4113 if (priv->hw->pcs) { 4114 if (priv->xstats.pcs_link) 4115 netif_carrier_on(dev); 4116 else 4117 netif_carrier_off(dev); 4118 } 4119 } 4120 4121 /* To handle DMA interrupts */ 4122 stmmac_dma_interrupt(priv); 4123 4124 return IRQ_HANDLED; 4125 } 4126 4127 #ifdef CONFIG_NET_POLL_CONTROLLER 4128 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4129 * to allow network I/O with interrupts disabled. 4130 */ 4131 static void stmmac_poll_controller(struct net_device *dev) 4132 { 4133 disable_irq(dev->irq); 4134 stmmac_interrupt(dev->irq, dev); 4135 enable_irq(dev->irq); 4136 } 4137 #endif 4138 4139 /** 4140 * stmmac_ioctl - Entry point for the Ioctl 4141 * @dev: Device pointer. 4142 * @rq: An IOCTL specefic structure, that can contain a pointer to 4143 * a proprietary structure used to pass information to the driver. 4144 * @cmd: IOCTL command 4145 * Description: 4146 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4147 */ 4148 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4149 { 4150 struct stmmac_priv *priv = netdev_priv (dev); 4151 int ret = -EOPNOTSUPP; 4152 4153 if (!netif_running(dev)) 4154 return -EINVAL; 4155 4156 switch (cmd) { 4157 case SIOCGMIIPHY: 4158 case SIOCGMIIREG: 4159 case SIOCSMIIREG: 4160 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4161 break; 4162 case SIOCSHWTSTAMP: 4163 ret = stmmac_hwtstamp_set(dev, rq); 4164 break; 4165 case SIOCGHWTSTAMP: 4166 ret = stmmac_hwtstamp_get(dev, rq); 4167 break; 4168 default: 4169 break; 4170 } 4171 4172 return ret; 4173 } 4174 4175 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4176 void *cb_priv) 4177 { 4178 struct stmmac_priv *priv = cb_priv; 4179 int ret = -EOPNOTSUPP; 4180 4181 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4182 return ret; 4183 4184 stmmac_disable_all_queues(priv); 4185 4186 switch (type) { 4187 case TC_SETUP_CLSU32: 4188 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4189 break; 4190 case TC_SETUP_CLSFLOWER: 4191 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4192 break; 4193 default: 4194 break; 4195 } 4196 4197 stmmac_enable_all_queues(priv); 4198 return ret; 4199 } 4200 4201 static LIST_HEAD(stmmac_block_cb_list); 4202 4203 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4204 void *type_data) 4205 { 4206 struct stmmac_priv *priv = netdev_priv(ndev); 4207 4208 switch (type) { 4209 case TC_SETUP_BLOCK: 4210 return flow_block_cb_setup_simple(type_data, 4211 &stmmac_block_cb_list, 4212 stmmac_setup_tc_block_cb, 4213 priv, priv, true); 4214 case TC_SETUP_QDISC_CBS: 4215 return stmmac_tc_setup_cbs(priv, priv, type_data); 4216 case TC_SETUP_QDISC_TAPRIO: 4217 return stmmac_tc_setup_taprio(priv, priv, type_data); 4218 case TC_SETUP_QDISC_ETF: 4219 return stmmac_tc_setup_etf(priv, priv, type_data); 4220 default: 4221 return -EOPNOTSUPP; 4222 } 4223 } 4224 4225 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4226 struct net_device *sb_dev) 4227 { 4228 int gso = skb_shinfo(skb)->gso_type; 4229 4230 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4231 /* 4232 * There is no way to determine the number of TSO/USO 4233 * capable Queues. Let's use always the Queue 0 4234 * because if TSO/USO is supported then at least this 4235 * one will be capable. 4236 */ 4237 return 0; 4238 } 4239 4240 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4241 } 4242 4243 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4244 { 4245 struct stmmac_priv *priv = netdev_priv(ndev); 4246 int ret = 0; 4247 4248 ret = eth_mac_addr(ndev, addr); 4249 if (ret) 4250 return ret; 4251 4252 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4253 4254 return ret; 4255 } 4256 4257 #ifdef CONFIG_DEBUG_FS 4258 static struct dentry *stmmac_fs_dir; 4259 4260 static void sysfs_display_ring(void *head, int size, int extend_desc, 4261 struct seq_file *seq) 4262 { 4263 int i; 4264 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4265 struct dma_desc *p = (struct dma_desc *)head; 4266 4267 for (i = 0; i < size; i++) { 4268 if (extend_desc) { 4269 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4270 i, (unsigned int)virt_to_phys(ep), 4271 le32_to_cpu(ep->basic.des0), 4272 le32_to_cpu(ep->basic.des1), 4273 le32_to_cpu(ep->basic.des2), 4274 le32_to_cpu(ep->basic.des3)); 4275 ep++; 4276 } else { 4277 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4278 i, (unsigned int)virt_to_phys(p), 4279 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4280 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4281 p++; 4282 } 4283 seq_printf(seq, "\n"); 4284 } 4285 } 4286 4287 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4288 { 4289 struct net_device *dev = seq->private; 4290 struct stmmac_priv *priv = netdev_priv(dev); 4291 u32 rx_count = priv->plat->rx_queues_to_use; 4292 u32 tx_count = priv->plat->tx_queues_to_use; 4293 u32 queue; 4294 4295 if ((dev->flags & IFF_UP) == 0) 4296 return 0; 4297 4298 for (queue = 0; queue < rx_count; queue++) { 4299 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4300 4301 seq_printf(seq, "RX Queue %d:\n", queue); 4302 4303 if (priv->extend_desc) { 4304 seq_printf(seq, "Extended descriptor ring:\n"); 4305 sysfs_display_ring((void *)rx_q->dma_erx, 4306 DMA_RX_SIZE, 1, seq); 4307 } else { 4308 seq_printf(seq, "Descriptor ring:\n"); 4309 sysfs_display_ring((void *)rx_q->dma_rx, 4310 DMA_RX_SIZE, 0, seq); 4311 } 4312 } 4313 4314 for (queue = 0; queue < tx_count; queue++) { 4315 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4316 4317 seq_printf(seq, "TX Queue %d:\n", queue); 4318 4319 if (priv->extend_desc) { 4320 seq_printf(seq, "Extended descriptor ring:\n"); 4321 sysfs_display_ring((void *)tx_q->dma_etx, 4322 DMA_TX_SIZE, 1, seq); 4323 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4324 seq_printf(seq, "Descriptor ring:\n"); 4325 sysfs_display_ring((void *)tx_q->dma_tx, 4326 DMA_TX_SIZE, 0, seq); 4327 } 4328 } 4329 4330 return 0; 4331 } 4332 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4333 4334 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4335 { 4336 struct net_device *dev = seq->private; 4337 struct stmmac_priv *priv = netdev_priv(dev); 4338 4339 if (!priv->hw_cap_support) { 4340 seq_printf(seq, "DMA HW features not supported\n"); 4341 return 0; 4342 } 4343 4344 seq_printf(seq, "==============================\n"); 4345 seq_printf(seq, "\tDMA HW features\n"); 4346 seq_printf(seq, "==============================\n"); 4347 4348 seq_printf(seq, "\t10/100 Mbps: %s\n", 4349 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4350 seq_printf(seq, "\t1000 Mbps: %s\n", 4351 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4352 seq_printf(seq, "\tHalf duplex: %s\n", 4353 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4354 seq_printf(seq, "\tHash Filter: %s\n", 4355 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4356 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4357 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4358 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4359 (priv->dma_cap.pcs) ? "Y" : "N"); 4360 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4361 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4362 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4363 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4364 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4365 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4366 seq_printf(seq, "\tRMON module: %s\n", 4367 (priv->dma_cap.rmon) ? "Y" : "N"); 4368 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4369 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4370 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4371 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4372 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4373 (priv->dma_cap.eee) ? "Y" : "N"); 4374 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4375 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4376 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4377 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4378 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4379 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4380 } else { 4381 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4382 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4383 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4384 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4385 } 4386 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4387 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4388 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4389 priv->dma_cap.number_rx_channel); 4390 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4391 priv->dma_cap.number_tx_channel); 4392 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4393 priv->dma_cap.number_rx_queues); 4394 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4395 priv->dma_cap.number_tx_queues); 4396 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4397 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4398 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4399 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4400 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4401 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4402 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4403 priv->dma_cap.pps_out_num); 4404 seq_printf(seq, "\tSafety Features: %s\n", 4405 priv->dma_cap.asp ? "Y" : "N"); 4406 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4407 priv->dma_cap.frpsel ? "Y" : "N"); 4408 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4409 priv->dma_cap.addr64); 4410 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4411 priv->dma_cap.rssen ? "Y" : "N"); 4412 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4413 priv->dma_cap.vlhash ? "Y" : "N"); 4414 seq_printf(seq, "\tSplit Header: %s\n", 4415 priv->dma_cap.sphen ? "Y" : "N"); 4416 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4417 priv->dma_cap.vlins ? "Y" : "N"); 4418 seq_printf(seq, "\tDouble VLAN: %s\n", 4419 priv->dma_cap.dvlan ? "Y" : "N"); 4420 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4421 priv->dma_cap.l3l4fnum); 4422 seq_printf(seq, "\tARP Offloading: %s\n", 4423 priv->dma_cap.arpoffsel ? "Y" : "N"); 4424 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4425 priv->dma_cap.estsel ? "Y" : "N"); 4426 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4427 priv->dma_cap.fpesel ? "Y" : "N"); 4428 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4429 priv->dma_cap.tbssel ? "Y" : "N"); 4430 return 0; 4431 } 4432 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4433 4434 /* Use network device events to rename debugfs file entries. 4435 */ 4436 static int stmmac_device_event(struct notifier_block *unused, 4437 unsigned long event, void *ptr) 4438 { 4439 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4440 struct stmmac_priv *priv = netdev_priv(dev); 4441 4442 if (dev->netdev_ops != &stmmac_netdev_ops) 4443 goto done; 4444 4445 switch (event) { 4446 case NETDEV_CHANGENAME: 4447 if (priv->dbgfs_dir) 4448 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4449 priv->dbgfs_dir, 4450 stmmac_fs_dir, 4451 dev->name); 4452 break; 4453 } 4454 done: 4455 return NOTIFY_DONE; 4456 } 4457 4458 static struct notifier_block stmmac_notifier = { 4459 .notifier_call = stmmac_device_event, 4460 }; 4461 4462 static void stmmac_init_fs(struct net_device *dev) 4463 { 4464 struct stmmac_priv *priv = netdev_priv(dev); 4465 4466 rtnl_lock(); 4467 4468 /* Create per netdev entries */ 4469 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4470 4471 /* Entry to report DMA RX/TX rings */ 4472 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4473 &stmmac_rings_status_fops); 4474 4475 /* Entry to report the DMA HW features */ 4476 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4477 &stmmac_dma_cap_fops); 4478 4479 rtnl_unlock(); 4480 } 4481 4482 static void stmmac_exit_fs(struct net_device *dev) 4483 { 4484 struct stmmac_priv *priv = netdev_priv(dev); 4485 4486 debugfs_remove_recursive(priv->dbgfs_dir); 4487 } 4488 #endif /* CONFIG_DEBUG_FS */ 4489 4490 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4491 { 4492 unsigned char *data = (unsigned char *)&vid_le; 4493 unsigned char data_byte = 0; 4494 u32 crc = ~0x0; 4495 u32 temp = 0; 4496 int i, bits; 4497 4498 bits = get_bitmask_order(VLAN_VID_MASK); 4499 for (i = 0; i < bits; i++) { 4500 if ((i % 8) == 0) 4501 data_byte = data[i / 8]; 4502 4503 temp = ((crc & 1) ^ data_byte) & 1; 4504 crc >>= 1; 4505 data_byte >>= 1; 4506 4507 if (temp) 4508 crc ^= 0xedb88320; 4509 } 4510 4511 return crc; 4512 } 4513 4514 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4515 { 4516 u32 crc, hash = 0; 4517 __le16 pmatch = 0; 4518 int count = 0; 4519 u16 vid = 0; 4520 4521 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4522 __le16 vid_le = cpu_to_le16(vid); 4523 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4524 hash |= (1 << crc); 4525 count++; 4526 } 4527 4528 if (!priv->dma_cap.vlhash) { 4529 if (count > 2) /* VID = 0 always passes filter */ 4530 return -EOPNOTSUPP; 4531 4532 pmatch = cpu_to_le16(vid); 4533 hash = 0; 4534 } 4535 4536 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4537 } 4538 4539 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4540 { 4541 struct stmmac_priv *priv = netdev_priv(ndev); 4542 bool is_double = false; 4543 int ret; 4544 4545 if (be16_to_cpu(proto) == ETH_P_8021AD) 4546 is_double = true; 4547 4548 set_bit(vid, priv->active_vlans); 4549 ret = stmmac_vlan_update(priv, is_double); 4550 if (ret) { 4551 clear_bit(vid, priv->active_vlans); 4552 return ret; 4553 } 4554 4555 if (priv->hw->num_vlan) { 4556 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4557 if (ret) 4558 return ret; 4559 } 4560 4561 return 0; 4562 } 4563 4564 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4565 { 4566 struct stmmac_priv *priv = netdev_priv(ndev); 4567 bool is_double = false; 4568 int ret; 4569 4570 if (be16_to_cpu(proto) == ETH_P_8021AD) 4571 is_double = true; 4572 4573 clear_bit(vid, priv->active_vlans); 4574 4575 if (priv->hw->num_vlan) { 4576 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4577 if (ret) 4578 return ret; 4579 } 4580 4581 return stmmac_vlan_update(priv, is_double); 4582 } 4583 4584 static const struct net_device_ops stmmac_netdev_ops = { 4585 .ndo_open = stmmac_open, 4586 .ndo_start_xmit = stmmac_xmit, 4587 .ndo_stop = stmmac_release, 4588 .ndo_change_mtu = stmmac_change_mtu, 4589 .ndo_fix_features = stmmac_fix_features, 4590 .ndo_set_features = stmmac_set_features, 4591 .ndo_set_rx_mode = stmmac_set_rx_mode, 4592 .ndo_tx_timeout = stmmac_tx_timeout, 4593 .ndo_do_ioctl = stmmac_ioctl, 4594 .ndo_setup_tc = stmmac_setup_tc, 4595 .ndo_select_queue = stmmac_select_queue, 4596 #ifdef CONFIG_NET_POLL_CONTROLLER 4597 .ndo_poll_controller = stmmac_poll_controller, 4598 #endif 4599 .ndo_set_mac_address = stmmac_set_mac_address, 4600 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4601 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4602 }; 4603 4604 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4605 { 4606 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4607 return; 4608 if (test_bit(STMMAC_DOWN, &priv->state)) 4609 return; 4610 4611 netdev_err(priv->dev, "Reset adapter.\n"); 4612 4613 rtnl_lock(); 4614 netif_trans_update(priv->dev); 4615 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4616 usleep_range(1000, 2000); 4617 4618 set_bit(STMMAC_DOWN, &priv->state); 4619 dev_close(priv->dev); 4620 dev_open(priv->dev, NULL); 4621 clear_bit(STMMAC_DOWN, &priv->state); 4622 clear_bit(STMMAC_RESETING, &priv->state); 4623 rtnl_unlock(); 4624 } 4625 4626 static void stmmac_service_task(struct work_struct *work) 4627 { 4628 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4629 service_task); 4630 4631 stmmac_reset_subtask(priv); 4632 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4633 } 4634 4635 /** 4636 * stmmac_hw_init - Init the MAC device 4637 * @priv: driver private structure 4638 * Description: this function is to configure the MAC device according to 4639 * some platform parameters or the HW capability register. It prepares the 4640 * driver to use either ring or chain modes and to setup either enhanced or 4641 * normal descriptors. 4642 */ 4643 static int stmmac_hw_init(struct stmmac_priv *priv) 4644 { 4645 int ret; 4646 4647 /* dwmac-sun8i only work in chain mode */ 4648 if (priv->plat->has_sun8i) 4649 chain_mode = 1; 4650 priv->chain_mode = chain_mode; 4651 4652 /* Initialize HW Interface */ 4653 ret = stmmac_hwif_init(priv); 4654 if (ret) 4655 return ret; 4656 4657 /* Get the HW capability (new GMAC newer than 3.50a) */ 4658 priv->hw_cap_support = stmmac_get_hw_features(priv); 4659 if (priv->hw_cap_support) { 4660 dev_info(priv->device, "DMA HW capability register supported\n"); 4661 4662 /* We can override some gmac/dma configuration fields: e.g. 4663 * enh_desc, tx_coe (e.g. that are passed through the 4664 * platform) with the values from the HW capability 4665 * register (if supported). 4666 */ 4667 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4668 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4669 priv->hw->pmt = priv->plat->pmt; 4670 if (priv->dma_cap.hash_tb_sz) { 4671 priv->hw->multicast_filter_bins = 4672 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4673 priv->hw->mcast_bits_log2 = 4674 ilog2(priv->hw->multicast_filter_bins); 4675 } 4676 4677 /* TXCOE doesn't work in thresh DMA mode */ 4678 if (priv->plat->force_thresh_dma_mode) 4679 priv->plat->tx_coe = 0; 4680 else 4681 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4682 4683 /* In case of GMAC4 rx_coe is from HW cap register. */ 4684 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4685 4686 if (priv->dma_cap.rx_coe_type2) 4687 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4688 else if (priv->dma_cap.rx_coe_type1) 4689 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4690 4691 } else { 4692 dev_info(priv->device, "No HW DMA feature register supported\n"); 4693 } 4694 4695 if (priv->plat->rx_coe) { 4696 priv->hw->rx_csum = priv->plat->rx_coe; 4697 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4698 if (priv->synopsys_id < DWMAC_CORE_4_00) 4699 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4700 } 4701 if (priv->plat->tx_coe) 4702 dev_info(priv->device, "TX Checksum insertion supported\n"); 4703 4704 if (priv->plat->pmt) { 4705 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4706 device_set_wakeup_capable(priv->device, 1); 4707 } 4708 4709 if (priv->dma_cap.tsoen) 4710 dev_info(priv->device, "TSO supported\n"); 4711 4712 /* Run HW quirks, if any */ 4713 if (priv->hwif_quirks) { 4714 ret = priv->hwif_quirks(priv); 4715 if (ret) 4716 return ret; 4717 } 4718 4719 /* Rx Watchdog is available in the COREs newer than the 3.40. 4720 * In some case, for example on bugged HW this feature 4721 * has to be disable and this can be done by passing the 4722 * riwt_off field from the platform. 4723 */ 4724 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4725 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4726 priv->use_riwt = 1; 4727 dev_info(priv->device, 4728 "Enable RX Mitigation via HW Watchdog Timer\n"); 4729 } 4730 4731 return 0; 4732 } 4733 4734 /** 4735 * stmmac_dvr_probe 4736 * @device: device pointer 4737 * @plat_dat: platform data pointer 4738 * @res: stmmac resource pointer 4739 * Description: this is the main probe function used to 4740 * call the alloc_etherdev, allocate the priv structure. 4741 * Return: 4742 * returns 0 on success, otherwise errno. 4743 */ 4744 int stmmac_dvr_probe(struct device *device, 4745 struct plat_stmmacenet_data *plat_dat, 4746 struct stmmac_resources *res) 4747 { 4748 struct net_device *ndev = NULL; 4749 struct stmmac_priv *priv; 4750 u32 queue, rxq, maxq; 4751 int i, ret = 0; 4752 4753 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4754 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4755 if (!ndev) 4756 return -ENOMEM; 4757 4758 SET_NETDEV_DEV(ndev, device); 4759 4760 priv = netdev_priv(ndev); 4761 priv->device = device; 4762 priv->dev = ndev; 4763 4764 stmmac_set_ethtool_ops(ndev); 4765 priv->pause = pause; 4766 priv->plat = plat_dat; 4767 priv->ioaddr = res->addr; 4768 priv->dev->base_addr = (unsigned long)res->addr; 4769 4770 priv->dev->irq = res->irq; 4771 priv->wol_irq = res->wol_irq; 4772 priv->lpi_irq = res->lpi_irq; 4773 4774 if (!IS_ERR_OR_NULL(res->mac)) 4775 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4776 4777 dev_set_drvdata(device, priv->dev); 4778 4779 /* Verify driver arguments */ 4780 stmmac_verify_args(); 4781 4782 /* Allocate workqueue */ 4783 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4784 if (!priv->wq) { 4785 dev_err(priv->device, "failed to create workqueue\n"); 4786 return -ENOMEM; 4787 } 4788 4789 INIT_WORK(&priv->service_task, stmmac_service_task); 4790 4791 /* Override with kernel parameters if supplied XXX CRS XXX 4792 * this needs to have multiple instances 4793 */ 4794 if ((phyaddr >= 0) && (phyaddr <= 31)) 4795 priv->plat->phy_addr = phyaddr; 4796 4797 if (priv->plat->stmmac_rst) { 4798 ret = reset_control_assert(priv->plat->stmmac_rst); 4799 reset_control_deassert(priv->plat->stmmac_rst); 4800 /* Some reset controllers have only reset callback instead of 4801 * assert + deassert callbacks pair. 4802 */ 4803 if (ret == -ENOTSUPP) 4804 reset_control_reset(priv->plat->stmmac_rst); 4805 } 4806 4807 /* Init MAC and get the capabilities */ 4808 ret = stmmac_hw_init(priv); 4809 if (ret) 4810 goto error_hw_init; 4811 4812 stmmac_check_ether_addr(priv); 4813 4814 /* Configure real RX and TX queues */ 4815 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4816 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4817 4818 ndev->netdev_ops = &stmmac_netdev_ops; 4819 4820 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4821 NETIF_F_RXCSUM; 4822 4823 ret = stmmac_tc_init(priv, priv); 4824 if (!ret) { 4825 ndev->hw_features |= NETIF_F_HW_TC; 4826 } 4827 4828 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4829 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4830 if (priv->plat->has_gmac4) 4831 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4832 priv->tso = true; 4833 dev_info(priv->device, "TSO feature enabled\n"); 4834 } 4835 4836 if (priv->dma_cap.sphen) { 4837 ndev->hw_features |= NETIF_F_GRO; 4838 priv->sph = true; 4839 dev_info(priv->device, "SPH feature enabled\n"); 4840 } 4841 4842 if (priv->dma_cap.addr64) { 4843 ret = dma_set_mask_and_coherent(device, 4844 DMA_BIT_MASK(priv->dma_cap.addr64)); 4845 if (!ret) { 4846 dev_info(priv->device, "Using %d bits DMA width\n", 4847 priv->dma_cap.addr64); 4848 4849 /* 4850 * If more than 32 bits can be addressed, make sure to 4851 * enable enhanced addressing mode. 4852 */ 4853 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4854 priv->plat->dma_cfg->eame = true; 4855 } else { 4856 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4857 if (ret) { 4858 dev_err(priv->device, "Failed to set DMA Mask\n"); 4859 goto error_hw_init; 4860 } 4861 4862 priv->dma_cap.addr64 = 32; 4863 } 4864 } 4865 4866 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4867 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4868 #ifdef STMMAC_VLAN_TAG_USED 4869 /* Both mac100 and gmac support receive VLAN tag detection */ 4870 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4871 if (priv->dma_cap.vlhash) { 4872 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4873 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4874 } 4875 if (priv->dma_cap.vlins) { 4876 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4877 if (priv->dma_cap.dvlan) 4878 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4879 } 4880 #endif 4881 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4882 4883 /* Initialize RSS */ 4884 rxq = priv->plat->rx_queues_to_use; 4885 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4886 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4887 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4888 4889 if (priv->dma_cap.rssen && priv->plat->rss_en) 4890 ndev->features |= NETIF_F_RXHASH; 4891 4892 /* MTU range: 46 - hw-specific max */ 4893 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4894 if (priv->plat->has_xgmac) 4895 ndev->max_mtu = XGMAC_JUMBO_LEN; 4896 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4897 ndev->max_mtu = JUMBO_LEN; 4898 else 4899 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4900 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4901 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4902 */ 4903 if ((priv->plat->maxmtu < ndev->max_mtu) && 4904 (priv->plat->maxmtu >= ndev->min_mtu)) 4905 ndev->max_mtu = priv->plat->maxmtu; 4906 else if (priv->plat->maxmtu < ndev->min_mtu) 4907 dev_warn(priv->device, 4908 "%s: warning: maxmtu having invalid value (%d)\n", 4909 __func__, priv->plat->maxmtu); 4910 4911 if (flow_ctrl) 4912 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4913 4914 /* Setup channels NAPI */ 4915 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4916 4917 for (queue = 0; queue < maxq; queue++) { 4918 struct stmmac_channel *ch = &priv->channel[queue]; 4919 4920 spin_lock_init(&ch->lock); 4921 ch->priv_data = priv; 4922 ch->index = queue; 4923 4924 if (queue < priv->plat->rx_queues_to_use) { 4925 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4926 NAPI_POLL_WEIGHT); 4927 } 4928 if (queue < priv->plat->tx_queues_to_use) { 4929 netif_tx_napi_add(ndev, &ch->tx_napi, 4930 stmmac_napi_poll_tx, 4931 NAPI_POLL_WEIGHT); 4932 } 4933 } 4934 4935 mutex_init(&priv->lock); 4936 4937 /* If a specific clk_csr value is passed from the platform 4938 * this means that the CSR Clock Range selection cannot be 4939 * changed at run-time and it is fixed. Viceversa the driver'll try to 4940 * set the MDC clock dynamically according to the csr actual 4941 * clock input. 4942 */ 4943 if (priv->plat->clk_csr >= 0) 4944 priv->clk_csr = priv->plat->clk_csr; 4945 else 4946 stmmac_clk_csr_set(priv); 4947 4948 stmmac_check_pcs_mode(priv); 4949 4950 if (priv->hw->pcs != STMMAC_PCS_TBI && 4951 priv->hw->pcs != STMMAC_PCS_RTBI) { 4952 /* MDIO bus Registration */ 4953 ret = stmmac_mdio_register(ndev); 4954 if (ret < 0) { 4955 dev_err(priv->device, 4956 "%s: MDIO bus (id: %d) registration failed", 4957 __func__, priv->plat->bus_id); 4958 goto error_mdio_register; 4959 } 4960 } 4961 4962 ret = stmmac_phy_setup(priv); 4963 if (ret) { 4964 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4965 goto error_phy_setup; 4966 } 4967 4968 ret = register_netdev(ndev); 4969 if (ret) { 4970 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4971 __func__, ret); 4972 goto error_netdev_register; 4973 } 4974 4975 if (priv->plat->serdes_powerup) { 4976 ret = priv->plat->serdes_powerup(ndev, 4977 priv->plat->bsp_priv); 4978 4979 if (ret < 0) 4980 goto error_serdes_powerup; 4981 } 4982 4983 #ifdef CONFIG_DEBUG_FS 4984 stmmac_init_fs(ndev); 4985 #endif 4986 4987 return ret; 4988 4989 error_serdes_powerup: 4990 unregister_netdev(ndev); 4991 error_netdev_register: 4992 phylink_destroy(priv->phylink); 4993 error_phy_setup: 4994 if (priv->hw->pcs != STMMAC_PCS_TBI && 4995 priv->hw->pcs != STMMAC_PCS_RTBI) 4996 stmmac_mdio_unregister(ndev); 4997 error_mdio_register: 4998 for (queue = 0; queue < maxq; queue++) { 4999 struct stmmac_channel *ch = &priv->channel[queue]; 5000 5001 if (queue < priv->plat->rx_queues_to_use) 5002 netif_napi_del(&ch->rx_napi); 5003 if (queue < priv->plat->tx_queues_to_use) 5004 netif_napi_del(&ch->tx_napi); 5005 } 5006 error_hw_init: 5007 destroy_workqueue(priv->wq); 5008 5009 return ret; 5010 } 5011 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 5012 5013 /** 5014 * stmmac_dvr_remove 5015 * @dev: device pointer 5016 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 5017 * changes the link status, releases the DMA descriptor rings. 5018 */ 5019 int stmmac_dvr_remove(struct device *dev) 5020 { 5021 struct net_device *ndev = dev_get_drvdata(dev); 5022 struct stmmac_priv *priv = netdev_priv(ndev); 5023 5024 netdev_info(priv->dev, "%s: removing driver", __func__); 5025 5026 stmmac_stop_all_dma(priv); 5027 5028 if (priv->plat->serdes_powerdown) 5029 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5030 5031 stmmac_mac_set(priv, priv->ioaddr, false); 5032 netif_carrier_off(ndev); 5033 unregister_netdev(ndev); 5034 #ifdef CONFIG_DEBUG_FS 5035 stmmac_exit_fs(ndev); 5036 #endif 5037 phylink_destroy(priv->phylink); 5038 if (priv->plat->stmmac_rst) 5039 reset_control_assert(priv->plat->stmmac_rst); 5040 clk_disable_unprepare(priv->plat->pclk); 5041 clk_disable_unprepare(priv->plat->stmmac_clk); 5042 if (priv->hw->pcs != STMMAC_PCS_TBI && 5043 priv->hw->pcs != STMMAC_PCS_RTBI) 5044 stmmac_mdio_unregister(ndev); 5045 destroy_workqueue(priv->wq); 5046 mutex_destroy(&priv->lock); 5047 5048 return 0; 5049 } 5050 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 5051 5052 /** 5053 * stmmac_suspend - suspend callback 5054 * @dev: device pointer 5055 * Description: this is the function to suspend the device and it is called 5056 * by the platform driver to stop the network queue, release the resources, 5057 * program the PMT register (for WoL), clean and release driver resources. 5058 */ 5059 int stmmac_suspend(struct device *dev) 5060 { 5061 struct net_device *ndev = dev_get_drvdata(dev); 5062 struct stmmac_priv *priv = netdev_priv(ndev); 5063 u32 chan; 5064 5065 if (!ndev || !netif_running(ndev)) 5066 return 0; 5067 5068 phylink_mac_change(priv->phylink, false); 5069 5070 mutex_lock(&priv->lock); 5071 5072 netif_device_detach(ndev); 5073 stmmac_stop_all_queues(priv); 5074 5075 stmmac_disable_all_queues(priv); 5076 5077 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5078 del_timer_sync(&priv->tx_queue[chan].txtimer); 5079 5080 /* Stop TX/RX DMA */ 5081 stmmac_stop_all_dma(priv); 5082 5083 if (priv->plat->serdes_powerdown) 5084 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5085 5086 /* Enable Power down mode by programming the PMT regs */ 5087 if (device_may_wakeup(priv->device)) { 5088 stmmac_pmt(priv, priv->hw, priv->wolopts); 5089 priv->irq_wake = 1; 5090 } else { 5091 mutex_unlock(&priv->lock); 5092 rtnl_lock(); 5093 phylink_stop(priv->phylink); 5094 rtnl_unlock(); 5095 mutex_lock(&priv->lock); 5096 5097 stmmac_mac_set(priv, priv->ioaddr, false); 5098 pinctrl_pm_select_sleep_state(priv->device); 5099 /* Disable clock in case of PWM is off */ 5100 if (priv->plat->clk_ptp_ref) 5101 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5102 clk_disable_unprepare(priv->plat->pclk); 5103 clk_disable_unprepare(priv->plat->stmmac_clk); 5104 } 5105 mutex_unlock(&priv->lock); 5106 5107 priv->speed = SPEED_UNKNOWN; 5108 return 0; 5109 } 5110 EXPORT_SYMBOL_GPL(stmmac_suspend); 5111 5112 /** 5113 * stmmac_reset_queues_param - reset queue parameters 5114 * @dev: device pointer 5115 */ 5116 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5117 { 5118 u32 rx_cnt = priv->plat->rx_queues_to_use; 5119 u32 tx_cnt = priv->plat->tx_queues_to_use; 5120 u32 queue; 5121 5122 for (queue = 0; queue < rx_cnt; queue++) { 5123 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5124 5125 rx_q->cur_rx = 0; 5126 rx_q->dirty_rx = 0; 5127 } 5128 5129 for (queue = 0; queue < tx_cnt; queue++) { 5130 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5131 5132 tx_q->cur_tx = 0; 5133 tx_q->dirty_tx = 0; 5134 tx_q->mss = 0; 5135 } 5136 } 5137 5138 /** 5139 * stmmac_resume - resume callback 5140 * @dev: device pointer 5141 * Description: when resume this function is invoked to setup the DMA and CORE 5142 * in a usable state. 5143 */ 5144 int stmmac_resume(struct device *dev) 5145 { 5146 struct net_device *ndev = dev_get_drvdata(dev); 5147 struct stmmac_priv *priv = netdev_priv(ndev); 5148 int ret; 5149 5150 if (!netif_running(ndev)) 5151 return 0; 5152 5153 /* Power Down bit, into the PM register, is cleared 5154 * automatically as soon as a magic packet or a Wake-up frame 5155 * is received. Anyway, it's better to manually clear 5156 * this bit because it can generate problems while resuming 5157 * from another devices (e.g. serial console). 5158 */ 5159 if (device_may_wakeup(priv->device)) { 5160 mutex_lock(&priv->lock); 5161 stmmac_pmt(priv, priv->hw, 0); 5162 mutex_unlock(&priv->lock); 5163 priv->irq_wake = 0; 5164 } else { 5165 pinctrl_pm_select_default_state(priv->device); 5166 /* enable the clk previously disabled */ 5167 clk_prepare_enable(priv->plat->stmmac_clk); 5168 clk_prepare_enable(priv->plat->pclk); 5169 if (priv->plat->clk_ptp_ref) 5170 clk_prepare_enable(priv->plat->clk_ptp_ref); 5171 /* reset the phy so that it's ready */ 5172 if (priv->mii) 5173 stmmac_mdio_reset(priv->mii); 5174 } 5175 5176 if (priv->plat->serdes_powerup) { 5177 ret = priv->plat->serdes_powerup(ndev, 5178 priv->plat->bsp_priv); 5179 5180 if (ret < 0) 5181 return ret; 5182 } 5183 5184 netif_device_attach(ndev); 5185 5186 mutex_lock(&priv->lock); 5187 5188 stmmac_reset_queues_param(priv); 5189 5190 stmmac_clear_descriptors(priv); 5191 5192 stmmac_hw_setup(ndev, false); 5193 stmmac_init_coalesce(priv); 5194 stmmac_set_rx_mode(ndev); 5195 5196 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 5197 5198 stmmac_enable_all_queues(priv); 5199 5200 stmmac_start_all_queues(priv); 5201 5202 mutex_unlock(&priv->lock); 5203 5204 if (!device_may_wakeup(priv->device)) { 5205 rtnl_lock(); 5206 phylink_start(priv->phylink); 5207 rtnl_unlock(); 5208 } 5209 5210 phylink_mac_change(priv->phylink, true); 5211 5212 return 0; 5213 } 5214 EXPORT_SYMBOL_GPL(stmmac_resume); 5215 5216 #ifndef MODULE 5217 static int __init stmmac_cmdline_opt(char *str) 5218 { 5219 char *opt; 5220 5221 if (!str || !*str) 5222 return -EINVAL; 5223 while ((opt = strsep(&str, ",")) != NULL) { 5224 if (!strncmp(opt, "debug:", 6)) { 5225 if (kstrtoint(opt + 6, 0, &debug)) 5226 goto err; 5227 } else if (!strncmp(opt, "phyaddr:", 8)) { 5228 if (kstrtoint(opt + 8, 0, &phyaddr)) 5229 goto err; 5230 } else if (!strncmp(opt, "buf_sz:", 7)) { 5231 if (kstrtoint(opt + 7, 0, &buf_sz)) 5232 goto err; 5233 } else if (!strncmp(opt, "tc:", 3)) { 5234 if (kstrtoint(opt + 3, 0, &tc)) 5235 goto err; 5236 } else if (!strncmp(opt, "watchdog:", 9)) { 5237 if (kstrtoint(opt + 9, 0, &watchdog)) 5238 goto err; 5239 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5240 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5241 goto err; 5242 } else if (!strncmp(opt, "pause:", 6)) { 5243 if (kstrtoint(opt + 6, 0, &pause)) 5244 goto err; 5245 } else if (!strncmp(opt, "eee_timer:", 10)) { 5246 if (kstrtoint(opt + 10, 0, &eee_timer)) 5247 goto err; 5248 } else if (!strncmp(opt, "chain_mode:", 11)) { 5249 if (kstrtoint(opt + 11, 0, &chain_mode)) 5250 goto err; 5251 } 5252 } 5253 return 0; 5254 5255 err: 5256 pr_err("%s: ERROR broken module parameter conversion", __func__); 5257 return -EINVAL; 5258 } 5259 5260 __setup("stmmaceth=", stmmac_cmdline_opt); 5261 #endif /* MODULE */ 5262 5263 static int __init stmmac_init(void) 5264 { 5265 #ifdef CONFIG_DEBUG_FS 5266 /* Create debugfs main directory if it doesn't exist yet */ 5267 if (!stmmac_fs_dir) 5268 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5269 register_netdevice_notifier(&stmmac_notifier); 5270 #endif 5271 5272 return 0; 5273 } 5274 5275 static void __exit stmmac_exit(void) 5276 { 5277 #ifdef CONFIG_DEBUG_FS 5278 unregister_netdevice_notifier(&stmmac_notifier); 5279 debugfs_remove_recursive(stmmac_fs_dir); 5280 #endif 5281 } 5282 5283 module_init(stmmac_init) 5284 module_exit(stmmac_exit) 5285 5286 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5287 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5288 MODULE_LICENSE("GPL"); 5289