1 /******************************************************************************* 2 STMMAC Ethtool support 3 4 Copyright (C) 2007-2009 STMicroelectronics Ltd 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 23 *******************************************************************************/ 24 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/interrupt.h> 28 #include <linux/mii.h> 29 #include <linux/phy.h> 30 #include <linux/net_tstamp.h> 31 #include <asm/io.h> 32 33 #include "stmmac.h" 34 #include "dwmac_dma.h" 35 36 #define REG_SPACE_SIZE 0x1054 37 #define MAC100_ETHTOOL_NAME "st_mac100" 38 #define GMAC_ETHTOOL_NAME "st_gmac" 39 40 struct stmmac_stats { 41 char stat_string[ETH_GSTRING_LEN]; 42 int sizeof_stat; 43 int stat_offset; 44 }; 45 46 #define STMMAC_STAT(m) \ 47 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \ 48 offsetof(struct stmmac_priv, xstats.m)} 49 50 static const struct stmmac_stats stmmac_gstrings_stats[] = { 51 /* Transmit errors */ 52 STMMAC_STAT(tx_underflow), 53 STMMAC_STAT(tx_carrier), 54 STMMAC_STAT(tx_losscarrier), 55 STMMAC_STAT(vlan_tag), 56 STMMAC_STAT(tx_deferred), 57 STMMAC_STAT(tx_vlan), 58 STMMAC_STAT(tx_jabber), 59 STMMAC_STAT(tx_frame_flushed), 60 STMMAC_STAT(tx_payload_error), 61 STMMAC_STAT(tx_ip_header_error), 62 /* Receive errors */ 63 STMMAC_STAT(rx_desc), 64 STMMAC_STAT(sa_filter_fail), 65 STMMAC_STAT(overflow_error), 66 STMMAC_STAT(ipc_csum_error), 67 STMMAC_STAT(rx_collision), 68 STMMAC_STAT(rx_crc), 69 STMMAC_STAT(dribbling_bit), 70 STMMAC_STAT(rx_length), 71 STMMAC_STAT(rx_mii), 72 STMMAC_STAT(rx_multicast), 73 STMMAC_STAT(rx_gmac_overflow), 74 STMMAC_STAT(rx_watchdog), 75 STMMAC_STAT(da_rx_filter_fail), 76 STMMAC_STAT(sa_rx_filter_fail), 77 STMMAC_STAT(rx_missed_cntr), 78 STMMAC_STAT(rx_overflow_cntr), 79 STMMAC_STAT(rx_vlan), 80 /* Tx/Rx IRQ error info */ 81 STMMAC_STAT(tx_undeflow_irq), 82 STMMAC_STAT(tx_process_stopped_irq), 83 STMMAC_STAT(tx_jabber_irq), 84 STMMAC_STAT(rx_overflow_irq), 85 STMMAC_STAT(rx_buf_unav_irq), 86 STMMAC_STAT(rx_process_stopped_irq), 87 STMMAC_STAT(rx_watchdog_irq), 88 STMMAC_STAT(tx_early_irq), 89 STMMAC_STAT(fatal_bus_error_irq), 90 /* Tx/Rx IRQ Events */ 91 STMMAC_STAT(rx_early_irq), 92 STMMAC_STAT(threshold), 93 STMMAC_STAT(tx_pkt_n), 94 STMMAC_STAT(rx_pkt_n), 95 STMMAC_STAT(normal_irq_n), 96 STMMAC_STAT(rx_normal_irq_n), 97 STMMAC_STAT(napi_poll), 98 STMMAC_STAT(tx_normal_irq_n), 99 STMMAC_STAT(tx_clean), 100 STMMAC_STAT(tx_reset_ic_bit), 101 STMMAC_STAT(irq_receive_pmt_irq_n), 102 /* MMC info */ 103 STMMAC_STAT(mmc_tx_irq_n), 104 STMMAC_STAT(mmc_rx_irq_n), 105 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 106 /* EEE */ 107 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 108 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 109 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 110 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 111 STMMAC_STAT(phy_eee_wakeup_error_n), 112 /* Extended RDES status */ 113 STMMAC_STAT(ip_hdr_err), 114 STMMAC_STAT(ip_payload_err), 115 STMMAC_STAT(ip_csum_bypassed), 116 STMMAC_STAT(ipv4_pkt_rcvd), 117 STMMAC_STAT(ipv6_pkt_rcvd), 118 STMMAC_STAT(rx_msg_type_ext_no_ptp), 119 STMMAC_STAT(rx_msg_type_sync), 120 STMMAC_STAT(rx_msg_type_follow_up), 121 STMMAC_STAT(rx_msg_type_delay_req), 122 STMMAC_STAT(rx_msg_type_delay_resp), 123 STMMAC_STAT(rx_msg_type_pdelay_req), 124 STMMAC_STAT(rx_msg_type_pdelay_resp), 125 STMMAC_STAT(rx_msg_type_pdelay_follow_up), 126 STMMAC_STAT(ptp_frame_type), 127 STMMAC_STAT(ptp_ver), 128 STMMAC_STAT(timestamp_dropped), 129 STMMAC_STAT(av_pkt_rcvd), 130 STMMAC_STAT(av_tagged_pkt_rcvd), 131 STMMAC_STAT(vlan_tag_priority_val), 132 STMMAC_STAT(l3_filter_match), 133 STMMAC_STAT(l4_filter_match), 134 STMMAC_STAT(l3_l4_filter_no_match), 135 /* PCS */ 136 STMMAC_STAT(irq_pcs_ane_n), 137 STMMAC_STAT(irq_pcs_link_n), 138 STMMAC_STAT(irq_rgmii_n), 139 }; 140 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 141 142 /* HW MAC Management counters (if supported) */ 143 #define STMMAC_MMC_STAT(m) \ 144 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \ 145 offsetof(struct stmmac_priv, mmc.m)} 146 147 static const struct stmmac_stats stmmac_mmc[] = { 148 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 149 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 150 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 151 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 152 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 153 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 154 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 155 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 156 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 157 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 158 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 159 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 160 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 161 STMMAC_MMC_STAT(mmc_tx_underflow_error), 162 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 163 STMMAC_MMC_STAT(mmc_tx_multicol_g), 164 STMMAC_MMC_STAT(mmc_tx_deferred), 165 STMMAC_MMC_STAT(mmc_tx_latecol), 166 STMMAC_MMC_STAT(mmc_tx_exesscol), 167 STMMAC_MMC_STAT(mmc_tx_carrier_error), 168 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 169 STMMAC_MMC_STAT(mmc_tx_framecount_g), 170 STMMAC_MMC_STAT(mmc_tx_excessdef), 171 STMMAC_MMC_STAT(mmc_tx_pause_frame), 172 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 173 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 174 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 175 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 176 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 177 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 178 STMMAC_MMC_STAT(mmc_rx_crc_error), 179 STMMAC_MMC_STAT(mmc_rx_align_error), 180 STMMAC_MMC_STAT(mmc_rx_run_error), 181 STMMAC_MMC_STAT(mmc_rx_jabber_error), 182 STMMAC_MMC_STAT(mmc_rx_undersize_g), 183 STMMAC_MMC_STAT(mmc_rx_oversize_g), 184 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 185 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 186 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 187 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 188 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 189 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 190 STMMAC_MMC_STAT(mmc_rx_unicast_g), 191 STMMAC_MMC_STAT(mmc_rx_length_error), 192 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 193 STMMAC_MMC_STAT(mmc_rx_pause_frames), 194 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 195 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 196 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 197 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 198 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 199 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 200 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 201 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 202 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 203 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 204 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 205 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 206 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 207 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 208 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 209 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 210 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 211 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 212 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 213 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 214 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 215 STMMAC_MMC_STAT(mmc_rx_udp_gd), 216 STMMAC_MMC_STAT(mmc_rx_udp_err), 217 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 218 STMMAC_MMC_STAT(mmc_rx_tcp_err), 219 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 220 STMMAC_MMC_STAT(mmc_rx_icmp_err), 221 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 222 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 223 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 224 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 225 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 226 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 227 }; 228 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 229 230 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 231 struct ethtool_drvinfo *info) 232 { 233 struct stmmac_priv *priv = netdev_priv(dev); 234 235 if (priv->plat->has_gmac) 236 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 237 else 238 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 239 sizeof(info->driver)); 240 241 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 242 } 243 244 static int stmmac_ethtool_getsettings(struct net_device *dev, 245 struct ethtool_cmd *cmd) 246 { 247 struct stmmac_priv *priv = netdev_priv(dev); 248 struct phy_device *phy = priv->phydev; 249 int rc; 250 251 if ((priv->pcs & STMMAC_PCS_RGMII) || (priv->pcs & STMMAC_PCS_SGMII)) { 252 struct rgmii_adv adv; 253 254 if (!priv->xstats.pcs_link) { 255 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 256 cmd->duplex = DUPLEX_UNKNOWN; 257 return 0; 258 } 259 cmd->duplex = priv->xstats.pcs_duplex; 260 261 ethtool_cmd_speed_set(cmd, priv->xstats.pcs_speed); 262 263 /* Get and convert ADV/LP_ADV from the HW AN registers */ 264 if (!priv->hw->mac->get_adv) 265 return -EOPNOTSUPP; /* should never happen indeed */ 266 267 priv->hw->mac->get_adv(priv->hw, &adv); 268 269 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 270 271 if (adv.pause & STMMAC_PCS_PAUSE) 272 cmd->advertising |= ADVERTISED_Pause; 273 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 274 cmd->advertising |= ADVERTISED_Asym_Pause; 275 if (adv.lp_pause & STMMAC_PCS_PAUSE) 276 cmd->lp_advertising |= ADVERTISED_Pause; 277 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 278 cmd->lp_advertising |= ADVERTISED_Asym_Pause; 279 280 /* Reg49[3] always set because ANE is always supported */ 281 cmd->autoneg = ADVERTISED_Autoneg; 282 cmd->supported |= SUPPORTED_Autoneg; 283 cmd->advertising |= ADVERTISED_Autoneg; 284 cmd->lp_advertising |= ADVERTISED_Autoneg; 285 286 if (adv.duplex) { 287 cmd->supported |= (SUPPORTED_1000baseT_Full | 288 SUPPORTED_100baseT_Full | 289 SUPPORTED_10baseT_Full); 290 cmd->advertising |= (ADVERTISED_1000baseT_Full | 291 ADVERTISED_100baseT_Full | 292 ADVERTISED_10baseT_Full); 293 } else { 294 cmd->supported |= (SUPPORTED_1000baseT_Half | 295 SUPPORTED_100baseT_Half | 296 SUPPORTED_10baseT_Half); 297 cmd->advertising |= (ADVERTISED_1000baseT_Half | 298 ADVERTISED_100baseT_Half | 299 ADVERTISED_10baseT_Half); 300 } 301 if (adv.lp_duplex) 302 cmd->lp_advertising |= (ADVERTISED_1000baseT_Full | 303 ADVERTISED_100baseT_Full | 304 ADVERTISED_10baseT_Full); 305 else 306 cmd->lp_advertising |= (ADVERTISED_1000baseT_Half | 307 ADVERTISED_100baseT_Half | 308 ADVERTISED_10baseT_Half); 309 cmd->port = PORT_OTHER; 310 311 return 0; 312 } 313 314 if (phy == NULL) { 315 pr_err("%s: %s: PHY is not registered\n", 316 __func__, dev->name); 317 return -ENODEV; 318 } 319 if (!netif_running(dev)) { 320 pr_err("%s: interface is disabled: we cannot track " 321 "link speed / duplex setting\n", dev->name); 322 return -EBUSY; 323 } 324 cmd->transceiver = XCVR_INTERNAL; 325 rc = phy_ethtool_gset(phy, cmd); 326 return rc; 327 } 328 329 static int stmmac_ethtool_setsettings(struct net_device *dev, 330 struct ethtool_cmd *cmd) 331 { 332 struct stmmac_priv *priv = netdev_priv(dev); 333 struct phy_device *phy = priv->phydev; 334 int rc; 335 336 if ((priv->pcs & STMMAC_PCS_RGMII) || (priv->pcs & STMMAC_PCS_SGMII)) { 337 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 338 339 /* Only support ANE */ 340 if (cmd->autoneg != AUTONEG_ENABLE) 341 return -EINVAL; 342 343 mask &= (ADVERTISED_1000baseT_Half | 344 ADVERTISED_1000baseT_Full | 345 ADVERTISED_100baseT_Half | 346 ADVERTISED_100baseT_Full | 347 ADVERTISED_10baseT_Half | 348 ADVERTISED_10baseT_Full); 349 350 spin_lock(&priv->lock); 351 if (priv->hw->mac->ctrl_ane) 352 priv->hw->mac->ctrl_ane(priv->hw, 1); 353 spin_unlock(&priv->lock); 354 355 return 0; 356 } 357 358 spin_lock(&priv->lock); 359 rc = phy_ethtool_sset(phy, cmd); 360 spin_unlock(&priv->lock); 361 362 return rc; 363 } 364 365 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 366 { 367 struct stmmac_priv *priv = netdev_priv(dev); 368 return priv->msg_enable; 369 } 370 371 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 372 { 373 struct stmmac_priv *priv = netdev_priv(dev); 374 priv->msg_enable = level; 375 376 } 377 378 static int stmmac_check_if_running(struct net_device *dev) 379 { 380 if (!netif_running(dev)) 381 return -EBUSY; 382 return 0; 383 } 384 385 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 386 { 387 return REG_SPACE_SIZE; 388 } 389 390 static void stmmac_ethtool_gregs(struct net_device *dev, 391 struct ethtool_regs *regs, void *space) 392 { 393 int i; 394 u32 *reg_space = (u32 *) space; 395 396 struct stmmac_priv *priv = netdev_priv(dev); 397 398 memset(reg_space, 0x0, REG_SPACE_SIZE); 399 400 if (!priv->plat->has_gmac) { 401 /* MAC registers */ 402 for (i = 0; i < 12; i++) 403 reg_space[i] = readl(priv->ioaddr + (i * 4)); 404 /* DMA registers */ 405 for (i = 0; i < 9; i++) 406 reg_space[i + 12] = 407 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4))); 408 reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR); 409 reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR); 410 } else { 411 /* MAC registers */ 412 for (i = 0; i < 55; i++) 413 reg_space[i] = readl(priv->ioaddr + (i * 4)); 414 /* DMA registers */ 415 for (i = 0; i < 22; i++) 416 reg_space[i + 55] = 417 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4))); 418 } 419 } 420 421 static void 422 stmmac_get_pauseparam(struct net_device *netdev, 423 struct ethtool_pauseparam *pause) 424 { 425 struct stmmac_priv *priv = netdev_priv(netdev); 426 427 if (priv->pcs) /* FIXME */ 428 return; 429 430 pause->rx_pause = 0; 431 pause->tx_pause = 0; 432 pause->autoneg = priv->phydev->autoneg; 433 434 if (priv->flow_ctrl & FLOW_RX) 435 pause->rx_pause = 1; 436 if (priv->flow_ctrl & FLOW_TX) 437 pause->tx_pause = 1; 438 439 } 440 441 static int 442 stmmac_set_pauseparam(struct net_device *netdev, 443 struct ethtool_pauseparam *pause) 444 { 445 struct stmmac_priv *priv = netdev_priv(netdev); 446 struct phy_device *phy = priv->phydev; 447 int new_pause = FLOW_OFF; 448 int ret = 0; 449 450 if (priv->pcs) /* FIXME */ 451 return -EOPNOTSUPP; 452 453 if (pause->rx_pause) 454 new_pause |= FLOW_RX; 455 if (pause->tx_pause) 456 new_pause |= FLOW_TX; 457 458 priv->flow_ctrl = new_pause; 459 phy->autoneg = pause->autoneg; 460 461 if (phy->autoneg) { 462 if (netif_running(netdev)) 463 ret = phy_start_aneg(phy); 464 } else 465 priv->hw->mac->flow_ctrl(priv->hw, phy->duplex, 466 priv->flow_ctrl, priv->pause); 467 return ret; 468 } 469 470 static void stmmac_get_ethtool_stats(struct net_device *dev, 471 struct ethtool_stats *dummy, u64 *data) 472 { 473 struct stmmac_priv *priv = netdev_priv(dev); 474 int i, j = 0; 475 476 /* Update the DMA HW counters for dwmac10/100 */ 477 if (!priv->plat->has_gmac) 478 priv->hw->dma->dma_diagnostic_fr(&dev->stats, 479 (void *) &priv->xstats, 480 priv->ioaddr); 481 else { 482 /* If supported, for new GMAC chips expose the MMC counters */ 483 if (priv->dma_cap.rmon) { 484 dwmac_mmc_read(priv->ioaddr, &priv->mmc); 485 486 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 487 char *p; 488 p = (char *)priv + stmmac_mmc[i].stat_offset; 489 490 data[j++] = (stmmac_mmc[i].sizeof_stat == 491 sizeof(u64)) ? (*(u64 *)p) : 492 (*(u32 *)p); 493 } 494 } 495 if (priv->eee_enabled) { 496 int val = phy_get_eee_err(priv->phydev); 497 if (val) 498 priv->xstats.phy_eee_wakeup_error_n = val; 499 } 500 } 501 for (i = 0; i < STMMAC_STATS_LEN; i++) { 502 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 503 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 504 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 505 } 506 } 507 508 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 509 { 510 struct stmmac_priv *priv = netdev_priv(netdev); 511 int len; 512 513 switch (sset) { 514 case ETH_SS_STATS: 515 len = STMMAC_STATS_LEN; 516 517 if (priv->dma_cap.rmon) 518 len += STMMAC_MMC_STATS_LEN; 519 520 return len; 521 default: 522 return -EOPNOTSUPP; 523 } 524 } 525 526 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 527 { 528 int i; 529 u8 *p = data; 530 struct stmmac_priv *priv = netdev_priv(dev); 531 532 switch (stringset) { 533 case ETH_SS_STATS: 534 if (priv->dma_cap.rmon) 535 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 536 memcpy(p, stmmac_mmc[i].stat_string, 537 ETH_GSTRING_LEN); 538 p += ETH_GSTRING_LEN; 539 } 540 for (i = 0; i < STMMAC_STATS_LEN; i++) { 541 memcpy(p, stmmac_gstrings_stats[i].stat_string, 542 ETH_GSTRING_LEN); 543 p += ETH_GSTRING_LEN; 544 } 545 break; 546 default: 547 WARN_ON(1); 548 break; 549 } 550 } 551 552 /* Currently only support WOL through Magic packet. */ 553 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 554 { 555 struct stmmac_priv *priv = netdev_priv(dev); 556 557 spin_lock_irq(&priv->lock); 558 if (device_can_wakeup(priv->device)) { 559 wol->supported = WAKE_MAGIC | WAKE_UCAST; 560 wol->wolopts = priv->wolopts; 561 } 562 spin_unlock_irq(&priv->lock); 563 } 564 565 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 566 { 567 struct stmmac_priv *priv = netdev_priv(dev); 568 u32 support = WAKE_MAGIC | WAKE_UCAST; 569 570 /* By default almost all GMAC devices support the WoL via 571 * magic frame but we can disable it if the HW capability 572 * register shows no support for pmt_magic_frame. */ 573 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 574 wol->wolopts &= ~WAKE_MAGIC; 575 576 if (!device_can_wakeup(priv->device)) 577 return -EINVAL; 578 579 if (wol->wolopts & ~support) 580 return -EINVAL; 581 582 if (wol->wolopts) { 583 pr_info("stmmac: wakeup enable\n"); 584 device_set_wakeup_enable(priv->device, 1); 585 enable_irq_wake(priv->wol_irq); 586 } else { 587 device_set_wakeup_enable(priv->device, 0); 588 disable_irq_wake(priv->wol_irq); 589 } 590 591 spin_lock_irq(&priv->lock); 592 priv->wolopts = wol->wolopts; 593 spin_unlock_irq(&priv->lock); 594 595 return 0; 596 } 597 598 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 599 struct ethtool_eee *edata) 600 { 601 struct stmmac_priv *priv = netdev_priv(dev); 602 603 if (!priv->dma_cap.eee) 604 return -EOPNOTSUPP; 605 606 edata->eee_enabled = priv->eee_enabled; 607 edata->eee_active = priv->eee_active; 608 edata->tx_lpi_timer = priv->tx_lpi_timer; 609 610 return phy_ethtool_get_eee(priv->phydev, edata); 611 } 612 613 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 614 struct ethtool_eee *edata) 615 { 616 struct stmmac_priv *priv = netdev_priv(dev); 617 618 priv->eee_enabled = edata->eee_enabled; 619 620 if (!priv->eee_enabled) 621 stmmac_disable_eee_mode(priv); 622 else { 623 /* We are asking for enabling the EEE but it is safe 624 * to verify all by invoking the eee_init function. 625 * In case of failure it will return an error. 626 */ 627 priv->eee_enabled = stmmac_eee_init(priv); 628 if (!priv->eee_enabled) 629 return -EOPNOTSUPP; 630 631 /* Do not change tx_lpi_timer in case of failure */ 632 priv->tx_lpi_timer = edata->tx_lpi_timer; 633 } 634 635 return phy_ethtool_set_eee(priv->phydev, edata); 636 } 637 638 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 639 { 640 unsigned long clk = clk_get_rate(priv->stmmac_clk); 641 642 if (!clk) 643 return 0; 644 645 return (usec * (clk / 1000000)) / 256; 646 } 647 648 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 649 { 650 unsigned long clk = clk_get_rate(priv->stmmac_clk); 651 652 if (!clk) 653 return 0; 654 655 return (riwt * 256) / (clk / 1000000); 656 } 657 658 static int stmmac_get_coalesce(struct net_device *dev, 659 struct ethtool_coalesce *ec) 660 { 661 struct stmmac_priv *priv = netdev_priv(dev); 662 663 ec->tx_coalesce_usecs = priv->tx_coal_timer; 664 ec->tx_max_coalesced_frames = priv->tx_coal_frames; 665 666 if (priv->use_riwt) 667 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv); 668 669 return 0; 670 } 671 672 static int stmmac_set_coalesce(struct net_device *dev, 673 struct ethtool_coalesce *ec) 674 { 675 struct stmmac_priv *priv = netdev_priv(dev); 676 unsigned int rx_riwt; 677 678 /* Check not supported parameters */ 679 if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) || 680 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) || 681 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) || 682 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) || 683 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) || 684 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) || 685 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) || 686 (ec->rx_max_coalesced_frames_high) || 687 (ec->tx_max_coalesced_frames_irq) || 688 (ec->stats_block_coalesce_usecs) || 689 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval)) 690 return -EOPNOTSUPP; 691 692 if (ec->rx_coalesce_usecs == 0) 693 return -EINVAL; 694 695 if ((ec->tx_coalesce_usecs == 0) && 696 (ec->tx_max_coalesced_frames == 0)) 697 return -EINVAL; 698 699 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 700 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 701 return -EINVAL; 702 703 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 704 705 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 706 return -EINVAL; 707 else if (!priv->use_riwt) 708 return -EOPNOTSUPP; 709 710 /* Only copy relevant parameters, ignore all others. */ 711 priv->tx_coal_frames = ec->tx_max_coalesced_frames; 712 priv->tx_coal_timer = ec->tx_coalesce_usecs; 713 priv->rx_riwt = rx_riwt; 714 priv->hw->dma->rx_watchdog(priv->ioaddr, priv->rx_riwt); 715 716 return 0; 717 } 718 719 static int stmmac_get_ts_info(struct net_device *dev, 720 struct ethtool_ts_info *info) 721 { 722 struct stmmac_priv *priv = netdev_priv(dev); 723 724 if ((priv->hwts_tx_en) && (priv->hwts_rx_en)) { 725 726 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 727 SOF_TIMESTAMPING_RX_HARDWARE | 728 SOF_TIMESTAMPING_RAW_HARDWARE; 729 730 if (priv->ptp_clock) 731 info->phc_index = ptp_clock_index(priv->ptp_clock); 732 733 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 734 735 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 736 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 737 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 738 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 739 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 740 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 741 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 742 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 743 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 744 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 745 (1 << HWTSTAMP_FILTER_ALL)); 746 return 0; 747 } else 748 return ethtool_op_get_ts_info(dev, info); 749 } 750 751 static const struct ethtool_ops stmmac_ethtool_ops = { 752 .begin = stmmac_check_if_running, 753 .get_drvinfo = stmmac_ethtool_getdrvinfo, 754 .get_settings = stmmac_ethtool_getsettings, 755 .set_settings = stmmac_ethtool_setsettings, 756 .get_msglevel = stmmac_ethtool_getmsglevel, 757 .set_msglevel = stmmac_ethtool_setmsglevel, 758 .get_regs = stmmac_ethtool_gregs, 759 .get_regs_len = stmmac_ethtool_get_regs_len, 760 .get_link = ethtool_op_get_link, 761 .get_pauseparam = stmmac_get_pauseparam, 762 .set_pauseparam = stmmac_set_pauseparam, 763 .get_ethtool_stats = stmmac_get_ethtool_stats, 764 .get_strings = stmmac_get_strings, 765 .get_wol = stmmac_get_wol, 766 .set_wol = stmmac_set_wol, 767 .get_eee = stmmac_ethtool_op_get_eee, 768 .set_eee = stmmac_ethtool_op_set_eee, 769 .get_sset_count = stmmac_get_sset_count, 770 .get_ts_info = stmmac_get_ts_info, 771 .get_coalesce = stmmac_get_coalesce, 772 .set_coalesce = stmmac_set_coalesce, 773 }; 774 775 void stmmac_set_ethtool_ops(struct net_device *netdev) 776 { 777 netdev->ethtool_ops = &stmmac_ethtool_ops; 778 } 779