1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define GMAC4_REG_SPACE_SIZE 0x116C 25 #define MAC100_ETHTOOL_NAME "st_mac100" 26 #define GMAC_ETHTOOL_NAME "st_gmac" 27 #define XGMAC_ETHTOOL_NAME "st_xgmac" 28 29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 30 * 31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 32 * same time due to the conflicting macro names. 33 */ 34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 35 36 #define ETHTOOL_DMA_OFFSET 55 37 38 struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42 }; 43 44 #define STMMAC_STAT(m) \ 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48 static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 STMMAC_STAT(rx_split_hdr_pkt_n), 79 /* Tx/Rx IRQ error info */ 80 STMMAC_STAT(tx_undeflow_irq), 81 STMMAC_STAT(tx_process_stopped_irq), 82 STMMAC_STAT(tx_jabber_irq), 83 STMMAC_STAT(rx_overflow_irq), 84 STMMAC_STAT(rx_buf_unav_irq), 85 STMMAC_STAT(rx_process_stopped_irq), 86 STMMAC_STAT(rx_watchdog_irq), 87 STMMAC_STAT(tx_early_irq), 88 STMMAC_STAT(fatal_bus_error_irq), 89 /* Tx/Rx IRQ Events */ 90 STMMAC_STAT(rx_early_irq), 91 STMMAC_STAT(threshold), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* EST */ 159 STMMAC_STAT(mtl_est_cgce), 160 STMMAC_STAT(mtl_est_hlbs), 161 STMMAC_STAT(mtl_est_hlbf), 162 STMMAC_STAT(mtl_est_btre), 163 STMMAC_STAT(mtl_est_btrlm), 164 }; 165 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 166 167 /* statistics collected in queue which will be summed up for all TX or RX 168 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). 169 */ 170 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = { 171 "rx_pkt_n", 172 "rx_normal_irq_n", 173 "tx_pkt_n", 174 "tx_normal_irq_n", 175 "tx_clean", 176 "tx_set_ic_bit", 177 "tx_tso_frames", 178 "tx_tso_nfrags", 179 "normal_irq_n", 180 "napi_poll", 181 }; 182 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string) 183 184 /* HW MAC Management counters (if supported) */ 185 #define STMMAC_MMC_STAT(m) \ 186 { #m, sizeof_field(struct stmmac_counters, m), \ 187 offsetof(struct stmmac_priv, mmc.m)} 188 189 static const struct stmmac_stats stmmac_mmc[] = { 190 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 191 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 192 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 193 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 194 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 195 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 196 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 197 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 198 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 199 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 200 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 201 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 202 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 203 STMMAC_MMC_STAT(mmc_tx_underflow_error), 204 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 205 STMMAC_MMC_STAT(mmc_tx_multicol_g), 206 STMMAC_MMC_STAT(mmc_tx_deferred), 207 STMMAC_MMC_STAT(mmc_tx_latecol), 208 STMMAC_MMC_STAT(mmc_tx_exesscol), 209 STMMAC_MMC_STAT(mmc_tx_carrier_error), 210 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 211 STMMAC_MMC_STAT(mmc_tx_framecount_g), 212 STMMAC_MMC_STAT(mmc_tx_excessdef), 213 STMMAC_MMC_STAT(mmc_tx_pause_frame), 214 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 215 STMMAC_MMC_STAT(mmc_tx_lpi_usec), 216 STMMAC_MMC_STAT(mmc_tx_lpi_tran), 217 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 218 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 219 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 220 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 221 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 222 STMMAC_MMC_STAT(mmc_rx_crc_error), 223 STMMAC_MMC_STAT(mmc_rx_align_error), 224 STMMAC_MMC_STAT(mmc_rx_run_error), 225 STMMAC_MMC_STAT(mmc_rx_jabber_error), 226 STMMAC_MMC_STAT(mmc_rx_undersize_g), 227 STMMAC_MMC_STAT(mmc_rx_oversize_g), 228 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 229 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 230 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 231 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 232 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 233 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 234 STMMAC_MMC_STAT(mmc_rx_unicast_g), 235 STMMAC_MMC_STAT(mmc_rx_length_error), 236 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 237 STMMAC_MMC_STAT(mmc_rx_pause_frames), 238 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 239 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 240 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 241 STMMAC_MMC_STAT(mmc_rx_lpi_usec), 242 STMMAC_MMC_STAT(mmc_rx_lpi_tran), 243 STMMAC_MMC_STAT(mmc_rx_discard_frames_gb), 244 STMMAC_MMC_STAT(mmc_rx_discard_octets_gb), 245 STMMAC_MMC_STAT(mmc_rx_align_err_frames), 246 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 247 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 248 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 249 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 250 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 251 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 252 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 253 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 254 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 255 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 256 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 257 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 258 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 259 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 260 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 261 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 262 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 263 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 264 STMMAC_MMC_STAT(mmc_rx_udp_gd), 265 STMMAC_MMC_STAT(mmc_rx_udp_err), 266 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 267 STMMAC_MMC_STAT(mmc_rx_tcp_err), 268 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 269 STMMAC_MMC_STAT(mmc_rx_icmp_err), 270 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 271 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 272 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 273 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 274 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 275 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 276 STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr), 277 STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr), 278 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 279 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 280 STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr), 281 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 282 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 283 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 284 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 285 }; 286 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 287 288 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 289 "tx_pkt_n", 290 "tx_irq_n", 291 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 292 }; 293 294 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 295 "rx_pkt_n", 296 "rx_irq_n", 297 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 298 }; 299 300 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 301 struct ethtool_drvinfo *info) 302 { 303 struct stmmac_priv *priv = netdev_priv(dev); 304 305 if (priv->plat->has_gmac || priv->plat->has_gmac4) 306 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 307 else if (priv->plat->has_xgmac) 308 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 309 else 310 strscpy(info->driver, MAC100_ETHTOOL_NAME, 311 sizeof(info->driver)); 312 313 if (priv->plat->pdev) { 314 strscpy(info->bus_info, pci_name(priv->plat->pdev), 315 sizeof(info->bus_info)); 316 } 317 } 318 319 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 320 struct ethtool_link_ksettings *cmd) 321 { 322 struct stmmac_priv *priv = netdev_priv(dev); 323 324 if (priv->hw->pcs & STMMAC_PCS_RGMII || 325 priv->hw->pcs & STMMAC_PCS_SGMII) { 326 struct rgmii_adv adv; 327 u32 supported, advertising, lp_advertising; 328 329 if (!priv->xstats.pcs_link) { 330 cmd->base.speed = SPEED_UNKNOWN; 331 cmd->base.duplex = DUPLEX_UNKNOWN; 332 return 0; 333 } 334 cmd->base.duplex = priv->xstats.pcs_duplex; 335 336 cmd->base.speed = priv->xstats.pcs_speed; 337 338 /* Get and convert ADV/LP_ADV from the HW AN registers */ 339 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 340 return -EOPNOTSUPP; /* should never happen indeed */ 341 342 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 343 344 ethtool_convert_link_mode_to_legacy_u32( 345 &supported, cmd->link_modes.supported); 346 ethtool_convert_link_mode_to_legacy_u32( 347 &advertising, cmd->link_modes.advertising); 348 ethtool_convert_link_mode_to_legacy_u32( 349 &lp_advertising, cmd->link_modes.lp_advertising); 350 351 if (adv.pause & STMMAC_PCS_PAUSE) 352 advertising |= ADVERTISED_Pause; 353 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 354 advertising |= ADVERTISED_Asym_Pause; 355 if (adv.lp_pause & STMMAC_PCS_PAUSE) 356 lp_advertising |= ADVERTISED_Pause; 357 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 358 lp_advertising |= ADVERTISED_Asym_Pause; 359 360 /* Reg49[3] always set because ANE is always supported */ 361 cmd->base.autoneg = ADVERTISED_Autoneg; 362 supported |= SUPPORTED_Autoneg; 363 advertising |= ADVERTISED_Autoneg; 364 lp_advertising |= ADVERTISED_Autoneg; 365 366 if (adv.duplex) { 367 supported |= (SUPPORTED_1000baseT_Full | 368 SUPPORTED_100baseT_Full | 369 SUPPORTED_10baseT_Full); 370 advertising |= (ADVERTISED_1000baseT_Full | 371 ADVERTISED_100baseT_Full | 372 ADVERTISED_10baseT_Full); 373 } else { 374 supported |= (SUPPORTED_1000baseT_Half | 375 SUPPORTED_100baseT_Half | 376 SUPPORTED_10baseT_Half); 377 advertising |= (ADVERTISED_1000baseT_Half | 378 ADVERTISED_100baseT_Half | 379 ADVERTISED_10baseT_Half); 380 } 381 if (adv.lp_duplex) 382 lp_advertising |= (ADVERTISED_1000baseT_Full | 383 ADVERTISED_100baseT_Full | 384 ADVERTISED_10baseT_Full); 385 else 386 lp_advertising |= (ADVERTISED_1000baseT_Half | 387 ADVERTISED_100baseT_Half | 388 ADVERTISED_10baseT_Half); 389 cmd->base.port = PORT_OTHER; 390 391 ethtool_convert_legacy_u32_to_link_mode( 392 cmd->link_modes.supported, supported); 393 ethtool_convert_legacy_u32_to_link_mode( 394 cmd->link_modes.advertising, advertising); 395 ethtool_convert_legacy_u32_to_link_mode( 396 cmd->link_modes.lp_advertising, lp_advertising); 397 398 return 0; 399 } 400 401 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 402 } 403 404 static int 405 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 406 const struct ethtool_link_ksettings *cmd) 407 { 408 struct stmmac_priv *priv = netdev_priv(dev); 409 410 if (priv->hw->pcs & STMMAC_PCS_RGMII || 411 priv->hw->pcs & STMMAC_PCS_SGMII) { 412 /* Only support ANE */ 413 if (cmd->base.autoneg != AUTONEG_ENABLE) 414 return -EINVAL; 415 416 mutex_lock(&priv->lock); 417 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 418 mutex_unlock(&priv->lock); 419 420 return 0; 421 } 422 423 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 424 } 425 426 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 427 { 428 struct stmmac_priv *priv = netdev_priv(dev); 429 return priv->msg_enable; 430 } 431 432 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 433 { 434 struct stmmac_priv *priv = netdev_priv(dev); 435 priv->msg_enable = level; 436 437 } 438 439 static int stmmac_check_if_running(struct net_device *dev) 440 { 441 if (!netif_running(dev)) 442 return -EBUSY; 443 return 0; 444 } 445 446 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 447 { 448 struct stmmac_priv *priv = netdev_priv(dev); 449 450 if (priv->plat->has_xgmac) 451 return XGMAC_REGSIZE * 4; 452 else if (priv->plat->has_gmac4) 453 return GMAC4_REG_SPACE_SIZE; 454 return REG_SPACE_SIZE; 455 } 456 457 static void stmmac_ethtool_gregs(struct net_device *dev, 458 struct ethtool_regs *regs, void *space) 459 { 460 struct stmmac_priv *priv = netdev_priv(dev); 461 u32 *reg_space = (u32 *) space; 462 463 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 464 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 465 466 /* Copy DMA registers to where ethtool expects them */ 467 if (priv->plat->has_gmac4) { 468 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 469 memcpy(®_space[ETHTOOL_DMA_OFFSET], 470 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 471 NUM_DWMAC4_DMA_REGS * 4); 472 } else if (!priv->plat->has_xgmac) { 473 memcpy(®_space[ETHTOOL_DMA_OFFSET], 474 ®_space[DMA_BUS_MODE / 4], 475 NUM_DWMAC1000_DMA_REGS * 4); 476 } 477 } 478 479 static int stmmac_nway_reset(struct net_device *dev) 480 { 481 struct stmmac_priv *priv = netdev_priv(dev); 482 483 return phylink_ethtool_nway_reset(priv->phylink); 484 } 485 486 static void stmmac_get_ringparam(struct net_device *netdev, 487 struct ethtool_ringparam *ring, 488 struct kernel_ethtool_ringparam *kernel_ring, 489 struct netlink_ext_ack *extack) 490 { 491 struct stmmac_priv *priv = netdev_priv(netdev); 492 493 ring->rx_max_pending = DMA_MAX_RX_SIZE; 494 ring->tx_max_pending = DMA_MAX_TX_SIZE; 495 ring->rx_pending = priv->dma_conf.dma_rx_size; 496 ring->tx_pending = priv->dma_conf.dma_tx_size; 497 } 498 499 static int stmmac_set_ringparam(struct net_device *netdev, 500 struct ethtool_ringparam *ring, 501 struct kernel_ethtool_ringparam *kernel_ring, 502 struct netlink_ext_ack *extack) 503 { 504 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 505 ring->rx_pending < DMA_MIN_RX_SIZE || 506 ring->rx_pending > DMA_MAX_RX_SIZE || 507 !is_power_of_2(ring->rx_pending) || 508 ring->tx_pending < DMA_MIN_TX_SIZE || 509 ring->tx_pending > DMA_MAX_TX_SIZE || 510 !is_power_of_2(ring->tx_pending)) 511 return -EINVAL; 512 513 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 514 ring->tx_pending); 515 } 516 517 static void 518 stmmac_get_pauseparam(struct net_device *netdev, 519 struct ethtool_pauseparam *pause) 520 { 521 struct stmmac_priv *priv = netdev_priv(netdev); 522 struct rgmii_adv adv_lp; 523 524 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 525 pause->autoneg = 1; 526 if (!adv_lp.pause) 527 return; 528 } else { 529 phylink_ethtool_get_pauseparam(priv->phylink, pause); 530 } 531 } 532 533 static int 534 stmmac_set_pauseparam(struct net_device *netdev, 535 struct ethtool_pauseparam *pause) 536 { 537 struct stmmac_priv *priv = netdev_priv(netdev); 538 struct rgmii_adv adv_lp; 539 540 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 541 pause->autoneg = 1; 542 if (!adv_lp.pause) 543 return -EOPNOTSUPP; 544 return 0; 545 } else { 546 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 547 } 548 } 549 550 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 551 { 552 u32 tx_cnt = priv->plat->tx_queues_to_use; 553 u32 rx_cnt = priv->plat->rx_queues_to_use; 554 unsigned int start; 555 int q, stat; 556 u64 *pos; 557 char *p; 558 559 pos = data; 560 for (q = 0; q < tx_cnt; q++) { 561 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q]; 562 struct stmmac_txq_stats snapshot; 563 564 data = pos; 565 do { 566 start = u64_stats_fetch_begin(&txq_stats->syncp); 567 snapshot = *txq_stats; 568 } while (u64_stats_fetch_retry(&txq_stats->syncp, start)); 569 570 p = (char *)&snapshot + offsetof(struct stmmac_txq_stats, tx_pkt_n); 571 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 572 *data++ += (*(u64 *)p); 573 p += sizeof(u64); 574 } 575 } 576 577 pos = data; 578 for (q = 0; q < rx_cnt; q++) { 579 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q]; 580 struct stmmac_rxq_stats snapshot; 581 582 data = pos; 583 do { 584 start = u64_stats_fetch_begin(&rxq_stats->syncp); 585 snapshot = *rxq_stats; 586 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); 587 588 p = (char *)&snapshot + offsetof(struct stmmac_rxq_stats, rx_pkt_n); 589 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 590 *data++ += (*(u64 *)p); 591 p += sizeof(u64); 592 } 593 } 594 } 595 596 static void stmmac_get_ethtool_stats(struct net_device *dev, 597 struct ethtool_stats *dummy, u64 *data) 598 { 599 struct stmmac_priv *priv = netdev_priv(dev); 600 u32 rx_queues_count = priv->plat->rx_queues_to_use; 601 u32 tx_queues_count = priv->plat->tx_queues_to_use; 602 u64 napi_poll = 0, normal_irq_n = 0; 603 int i, j = 0, pos, ret; 604 unsigned long count; 605 unsigned int start; 606 607 if (priv->dma_cap.asp) { 608 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 609 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 610 &count, NULL)) 611 data[j++] = count; 612 } 613 } 614 615 /* Update the DMA HW counters for dwmac10/100 */ 616 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr); 617 if (ret) { 618 /* If supported, for new GMAC chips expose the MMC counters */ 619 if (priv->dma_cap.rmon) { 620 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 621 622 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 623 char *p; 624 p = (char *)priv + stmmac_mmc[i].stat_offset; 625 626 data[j++] = (stmmac_mmc[i].sizeof_stat == 627 sizeof(u64)) ? (*(u64 *)p) : 628 (*(u32 *)p); 629 } 630 } 631 if (priv->eee_enabled) { 632 int val = phylink_get_eee_err(priv->phylink); 633 if (val) 634 priv->xstats.phy_eee_wakeup_error_n = val; 635 } 636 637 if (priv->synopsys_id >= DWMAC_CORE_3_50) 638 stmmac_mac_debug(priv, priv->ioaddr, 639 (void *)&priv->xstats, 640 rx_queues_count, tx_queues_count); 641 } 642 for (i = 0; i < STMMAC_STATS_LEN; i++) { 643 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 644 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 645 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 646 } 647 648 pos = j; 649 for (i = 0; i < rx_queues_count; i++) { 650 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i]; 651 struct stmmac_rxq_stats snapshot; 652 653 j = pos; 654 do { 655 start = u64_stats_fetch_begin(&rxq_stats->syncp); 656 snapshot = *rxq_stats; 657 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); 658 659 data[j++] += snapshot.rx_pkt_n; 660 data[j++] += snapshot.rx_normal_irq_n; 661 normal_irq_n += snapshot.rx_normal_irq_n; 662 napi_poll += snapshot.napi_poll; 663 } 664 665 pos = j; 666 for (i = 0; i < tx_queues_count; i++) { 667 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i]; 668 struct stmmac_txq_stats snapshot; 669 670 j = pos; 671 do { 672 start = u64_stats_fetch_begin(&txq_stats->syncp); 673 snapshot = *txq_stats; 674 } while (u64_stats_fetch_retry(&txq_stats->syncp, start)); 675 676 data[j++] += snapshot.tx_pkt_n; 677 data[j++] += snapshot.tx_normal_irq_n; 678 normal_irq_n += snapshot.tx_normal_irq_n; 679 data[j++] += snapshot.tx_clean; 680 data[j++] += snapshot.tx_set_ic_bit; 681 data[j++] += snapshot.tx_tso_frames; 682 data[j++] += snapshot.tx_tso_nfrags; 683 napi_poll += snapshot.napi_poll; 684 } 685 normal_irq_n += priv->xstats.rx_early_irq; 686 data[j++] = normal_irq_n; 687 data[j++] = napi_poll; 688 689 stmmac_get_per_qstats(priv, &data[j]); 690 } 691 692 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 693 { 694 struct stmmac_priv *priv = netdev_priv(netdev); 695 u32 tx_cnt = priv->plat->tx_queues_to_use; 696 u32 rx_cnt = priv->plat->rx_queues_to_use; 697 int i, len, safety_len = 0; 698 699 switch (sset) { 700 case ETH_SS_STATS: 701 len = STMMAC_STATS_LEN + STMMAC_QSTATS + 702 STMMAC_TXQ_STATS * tx_cnt + 703 STMMAC_RXQ_STATS * rx_cnt; 704 705 if (priv->dma_cap.rmon) 706 len += STMMAC_MMC_STATS_LEN; 707 if (priv->dma_cap.asp) { 708 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 709 if (!stmmac_safety_feat_dump(priv, 710 &priv->sstats, i, 711 NULL, NULL)) 712 safety_len++; 713 } 714 715 len += safety_len; 716 } 717 718 return len; 719 case ETH_SS_TEST: 720 return stmmac_selftest_get_count(priv); 721 default: 722 return -EOPNOTSUPP; 723 } 724 } 725 726 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 727 { 728 u32 tx_cnt = priv->plat->tx_queues_to_use; 729 u32 rx_cnt = priv->plat->rx_queues_to_use; 730 int q, stat; 731 732 for (q = 0; q < tx_cnt; q++) { 733 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 734 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 735 stmmac_qstats_tx_string[stat]); 736 data += ETH_GSTRING_LEN; 737 } 738 } 739 for (q = 0; q < rx_cnt; q++) { 740 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 741 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 742 stmmac_qstats_rx_string[stat]); 743 data += ETH_GSTRING_LEN; 744 } 745 } 746 } 747 748 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 749 { 750 int i; 751 u8 *p = data; 752 struct stmmac_priv *priv = netdev_priv(dev); 753 754 switch (stringset) { 755 case ETH_SS_STATS: 756 if (priv->dma_cap.asp) { 757 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 758 const char *desc; 759 if (!stmmac_safety_feat_dump(priv, 760 &priv->sstats, i, 761 NULL, &desc)) { 762 memcpy(p, desc, ETH_GSTRING_LEN); 763 p += ETH_GSTRING_LEN; 764 } 765 } 766 } 767 if (priv->dma_cap.rmon) 768 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 769 memcpy(p, stmmac_mmc[i].stat_string, 770 ETH_GSTRING_LEN); 771 p += ETH_GSTRING_LEN; 772 } 773 for (i = 0; i < STMMAC_STATS_LEN; i++) { 774 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN); 775 p += ETH_GSTRING_LEN; 776 } 777 for (i = 0; i < STMMAC_QSTATS; i++) { 778 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN); 779 p += ETH_GSTRING_LEN; 780 } 781 stmmac_get_qstats_string(priv, p); 782 break; 783 case ETH_SS_TEST: 784 stmmac_selftest_get_strings(priv, p); 785 break; 786 default: 787 WARN_ON(1); 788 break; 789 } 790 } 791 792 /* Currently only support WOL through Magic packet. */ 793 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 794 { 795 struct stmmac_priv *priv = netdev_priv(dev); 796 797 if (!priv->plat->pmt) 798 return phylink_ethtool_get_wol(priv->phylink, wol); 799 800 mutex_lock(&priv->lock); 801 if (device_can_wakeup(priv->device)) { 802 wol->supported = WAKE_MAGIC | WAKE_UCAST; 803 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 804 wol->supported &= ~WAKE_MAGIC; 805 wol->wolopts = priv->wolopts; 806 } 807 mutex_unlock(&priv->lock); 808 } 809 810 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 811 { 812 struct stmmac_priv *priv = netdev_priv(dev); 813 u32 support = WAKE_MAGIC | WAKE_UCAST; 814 815 if (!device_can_wakeup(priv->device)) 816 return -EOPNOTSUPP; 817 818 if (!priv->plat->pmt) { 819 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 820 821 if (!ret) 822 device_set_wakeup_enable(priv->device, !!wol->wolopts); 823 return ret; 824 } 825 826 /* By default almost all GMAC devices support the WoL via 827 * magic frame but we can disable it if the HW capability 828 * register shows no support for pmt_magic_frame. */ 829 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 830 wol->wolopts &= ~WAKE_MAGIC; 831 832 if (wol->wolopts & ~support) 833 return -EINVAL; 834 835 if (wol->wolopts) { 836 pr_info("stmmac: wakeup enable\n"); 837 device_set_wakeup_enable(priv->device, 1); 838 enable_irq_wake(priv->wol_irq); 839 } else { 840 device_set_wakeup_enable(priv->device, 0); 841 disable_irq_wake(priv->wol_irq); 842 } 843 844 mutex_lock(&priv->lock); 845 priv->wolopts = wol->wolopts; 846 mutex_unlock(&priv->lock); 847 848 return 0; 849 } 850 851 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 852 struct ethtool_eee *edata) 853 { 854 struct stmmac_priv *priv = netdev_priv(dev); 855 856 if (!priv->dma_cap.eee) 857 return -EOPNOTSUPP; 858 859 edata->eee_enabled = priv->eee_enabled; 860 edata->eee_active = priv->eee_active; 861 edata->tx_lpi_timer = priv->tx_lpi_timer; 862 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 863 864 return phylink_ethtool_get_eee(priv->phylink, edata); 865 } 866 867 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 868 struct ethtool_eee *edata) 869 { 870 struct stmmac_priv *priv = netdev_priv(dev); 871 int ret; 872 873 if (!priv->dma_cap.eee) 874 return -EOPNOTSUPP; 875 876 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 877 netdev_warn(priv->dev, 878 "Setting EEE tx-lpi is not supported\n"); 879 880 if (!edata->eee_enabled) 881 stmmac_disable_eee_mode(priv); 882 883 ret = phylink_ethtool_set_eee(priv->phylink, edata); 884 if (ret) 885 return ret; 886 887 if (edata->eee_enabled && 888 priv->tx_lpi_timer != edata->tx_lpi_timer) { 889 priv->tx_lpi_timer = edata->tx_lpi_timer; 890 stmmac_eee_init(priv); 891 } 892 893 return 0; 894 } 895 896 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 897 { 898 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 899 900 if (!clk) { 901 clk = priv->plat->clk_ref_rate; 902 if (!clk) 903 return 0; 904 } 905 906 return (usec * (clk / 1000000)) / 256; 907 } 908 909 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 910 { 911 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 912 913 if (!clk) { 914 clk = priv->plat->clk_ref_rate; 915 if (!clk) 916 return 0; 917 } 918 919 return (riwt * 256) / (clk / 1000000); 920 } 921 922 static int __stmmac_get_coalesce(struct net_device *dev, 923 struct ethtool_coalesce *ec, 924 int queue) 925 { 926 struct stmmac_priv *priv = netdev_priv(dev); 927 u32 max_cnt; 928 u32 rx_cnt; 929 u32 tx_cnt; 930 931 rx_cnt = priv->plat->rx_queues_to_use; 932 tx_cnt = priv->plat->tx_queues_to_use; 933 max_cnt = max(rx_cnt, tx_cnt); 934 935 if (queue < 0) 936 queue = 0; 937 else if (queue >= max_cnt) 938 return -EINVAL; 939 940 if (queue < tx_cnt) { 941 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 942 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 943 } else { 944 ec->tx_coalesce_usecs = 0; 945 ec->tx_max_coalesced_frames = 0; 946 } 947 948 if (priv->use_riwt && queue < rx_cnt) { 949 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 950 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 951 priv); 952 } else { 953 ec->rx_max_coalesced_frames = 0; 954 ec->rx_coalesce_usecs = 0; 955 } 956 957 return 0; 958 } 959 960 static int stmmac_get_coalesce(struct net_device *dev, 961 struct ethtool_coalesce *ec, 962 struct kernel_ethtool_coalesce *kernel_coal, 963 struct netlink_ext_ack *extack) 964 { 965 return __stmmac_get_coalesce(dev, ec, -1); 966 } 967 968 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 969 struct ethtool_coalesce *ec) 970 { 971 return __stmmac_get_coalesce(dev, ec, queue); 972 } 973 974 static int __stmmac_set_coalesce(struct net_device *dev, 975 struct ethtool_coalesce *ec, 976 int queue) 977 { 978 struct stmmac_priv *priv = netdev_priv(dev); 979 bool all_queues = false; 980 unsigned int rx_riwt; 981 u32 max_cnt; 982 u32 rx_cnt; 983 u32 tx_cnt; 984 985 rx_cnt = priv->plat->rx_queues_to_use; 986 tx_cnt = priv->plat->tx_queues_to_use; 987 max_cnt = max(rx_cnt, tx_cnt); 988 989 if (queue < 0) 990 all_queues = true; 991 else if (queue >= max_cnt) 992 return -EINVAL; 993 994 if (priv->use_riwt) { 995 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 996 997 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 998 return -EINVAL; 999 1000 if (all_queues) { 1001 int i; 1002 1003 for (i = 0; i < rx_cnt; i++) { 1004 priv->rx_riwt[i] = rx_riwt; 1005 stmmac_rx_watchdog(priv, priv->ioaddr, 1006 rx_riwt, i); 1007 priv->rx_coal_frames[i] = 1008 ec->rx_max_coalesced_frames; 1009 } 1010 } else if (queue < rx_cnt) { 1011 priv->rx_riwt[queue] = rx_riwt; 1012 stmmac_rx_watchdog(priv, priv->ioaddr, 1013 rx_riwt, queue); 1014 priv->rx_coal_frames[queue] = 1015 ec->rx_max_coalesced_frames; 1016 } 1017 } 1018 1019 if ((ec->tx_coalesce_usecs == 0) && 1020 (ec->tx_max_coalesced_frames == 0)) 1021 return -EINVAL; 1022 1023 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 1024 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 1025 return -EINVAL; 1026 1027 if (all_queues) { 1028 int i; 1029 1030 for (i = 0; i < tx_cnt; i++) { 1031 priv->tx_coal_frames[i] = 1032 ec->tx_max_coalesced_frames; 1033 priv->tx_coal_timer[i] = 1034 ec->tx_coalesce_usecs; 1035 } 1036 } else if (queue < tx_cnt) { 1037 priv->tx_coal_frames[queue] = 1038 ec->tx_max_coalesced_frames; 1039 priv->tx_coal_timer[queue] = 1040 ec->tx_coalesce_usecs; 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int stmmac_set_coalesce(struct net_device *dev, 1047 struct ethtool_coalesce *ec, 1048 struct kernel_ethtool_coalesce *kernel_coal, 1049 struct netlink_ext_ack *extack) 1050 { 1051 return __stmmac_set_coalesce(dev, ec, -1); 1052 } 1053 1054 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1055 struct ethtool_coalesce *ec) 1056 { 1057 return __stmmac_set_coalesce(dev, ec, queue); 1058 } 1059 1060 static int stmmac_get_rxnfc(struct net_device *dev, 1061 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1062 { 1063 struct stmmac_priv *priv = netdev_priv(dev); 1064 1065 switch (rxnfc->cmd) { 1066 case ETHTOOL_GRXRINGS: 1067 rxnfc->data = priv->plat->rx_queues_to_use; 1068 break; 1069 default: 1070 return -EOPNOTSUPP; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 1077 { 1078 struct stmmac_priv *priv = netdev_priv(dev); 1079 1080 return sizeof(priv->rss.key); 1081 } 1082 1083 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1084 { 1085 struct stmmac_priv *priv = netdev_priv(dev); 1086 1087 return ARRAY_SIZE(priv->rss.table); 1088 } 1089 1090 static int stmmac_get_rxfh(struct net_device *dev, 1091 struct ethtool_rxfh_param *rxfh) 1092 { 1093 struct stmmac_priv *priv = netdev_priv(dev); 1094 int i; 1095 1096 if (rxfh->indir) { 1097 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1098 rxfh->indir[i] = priv->rss.table[i]; 1099 } 1100 1101 if (rxfh->key) 1102 memcpy(rxfh->key, priv->rss.key, sizeof(priv->rss.key)); 1103 rxfh->hfunc = ETH_RSS_HASH_TOP; 1104 1105 return 0; 1106 } 1107 1108 static int stmmac_set_rxfh(struct net_device *dev, 1109 struct ethtool_rxfh_param *rxfh, 1110 struct netlink_ext_ack *extack) 1111 { 1112 struct stmmac_priv *priv = netdev_priv(dev); 1113 int i; 1114 1115 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 1116 rxfh->hfunc != ETH_RSS_HASH_TOP) 1117 return -EOPNOTSUPP; 1118 1119 if (rxfh->indir) { 1120 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1121 priv->rss.table[i] = rxfh->indir[i]; 1122 } 1123 1124 if (rxfh->key) 1125 memcpy(priv->rss.key, rxfh->key, sizeof(priv->rss.key)); 1126 1127 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1128 priv->plat->rx_queues_to_use); 1129 } 1130 1131 static void stmmac_get_channels(struct net_device *dev, 1132 struct ethtool_channels *chan) 1133 { 1134 struct stmmac_priv *priv = netdev_priv(dev); 1135 1136 chan->rx_count = priv->plat->rx_queues_to_use; 1137 chan->tx_count = priv->plat->tx_queues_to_use; 1138 chan->max_rx = priv->dma_cap.number_rx_queues; 1139 chan->max_tx = priv->dma_cap.number_tx_queues; 1140 } 1141 1142 static int stmmac_set_channels(struct net_device *dev, 1143 struct ethtool_channels *chan) 1144 { 1145 struct stmmac_priv *priv = netdev_priv(dev); 1146 1147 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1148 chan->tx_count > priv->dma_cap.number_tx_queues || 1149 !chan->rx_count || !chan->tx_count) 1150 return -EINVAL; 1151 1152 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1153 } 1154 1155 static int stmmac_get_ts_info(struct net_device *dev, 1156 struct ethtool_ts_info *info) 1157 { 1158 struct stmmac_priv *priv = netdev_priv(dev); 1159 1160 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1161 1162 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1163 SOF_TIMESTAMPING_TX_HARDWARE | 1164 SOF_TIMESTAMPING_RX_SOFTWARE | 1165 SOF_TIMESTAMPING_RX_HARDWARE | 1166 SOF_TIMESTAMPING_SOFTWARE | 1167 SOF_TIMESTAMPING_RAW_HARDWARE; 1168 1169 if (priv->ptp_clock) 1170 info->phc_index = ptp_clock_index(priv->ptp_clock); 1171 1172 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1173 1174 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1175 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1176 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1177 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1178 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1179 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1180 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1181 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1182 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1183 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1184 (1 << HWTSTAMP_FILTER_ALL)); 1185 return 0; 1186 } else 1187 return ethtool_op_get_ts_info(dev, info); 1188 } 1189 1190 static int stmmac_get_tunable(struct net_device *dev, 1191 const struct ethtool_tunable *tuna, void *data) 1192 { 1193 struct stmmac_priv *priv = netdev_priv(dev); 1194 int ret = 0; 1195 1196 switch (tuna->id) { 1197 case ETHTOOL_RX_COPYBREAK: 1198 *(u32 *)data = priv->rx_copybreak; 1199 break; 1200 default: 1201 ret = -EINVAL; 1202 break; 1203 } 1204 1205 return ret; 1206 } 1207 1208 static int stmmac_set_tunable(struct net_device *dev, 1209 const struct ethtool_tunable *tuna, 1210 const void *data) 1211 { 1212 struct stmmac_priv *priv = netdev_priv(dev); 1213 int ret = 0; 1214 1215 switch (tuna->id) { 1216 case ETHTOOL_RX_COPYBREAK: 1217 priv->rx_copybreak = *(u32 *)data; 1218 break; 1219 default: 1220 ret = -EINVAL; 1221 break; 1222 } 1223 1224 return ret; 1225 } 1226 1227 static const struct ethtool_ops stmmac_ethtool_ops = { 1228 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1229 ETHTOOL_COALESCE_MAX_FRAMES, 1230 .begin = stmmac_check_if_running, 1231 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1232 .get_msglevel = stmmac_ethtool_getmsglevel, 1233 .set_msglevel = stmmac_ethtool_setmsglevel, 1234 .get_regs = stmmac_ethtool_gregs, 1235 .get_regs_len = stmmac_ethtool_get_regs_len, 1236 .get_link = ethtool_op_get_link, 1237 .nway_reset = stmmac_nway_reset, 1238 .get_ringparam = stmmac_get_ringparam, 1239 .set_ringparam = stmmac_set_ringparam, 1240 .get_pauseparam = stmmac_get_pauseparam, 1241 .set_pauseparam = stmmac_set_pauseparam, 1242 .self_test = stmmac_selftest_run, 1243 .get_ethtool_stats = stmmac_get_ethtool_stats, 1244 .get_strings = stmmac_get_strings, 1245 .get_wol = stmmac_get_wol, 1246 .set_wol = stmmac_set_wol, 1247 .get_eee = stmmac_ethtool_op_get_eee, 1248 .set_eee = stmmac_ethtool_op_set_eee, 1249 .get_sset_count = stmmac_get_sset_count, 1250 .get_rxnfc = stmmac_get_rxnfc, 1251 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1252 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1253 .get_rxfh = stmmac_get_rxfh, 1254 .set_rxfh = stmmac_set_rxfh, 1255 .get_ts_info = stmmac_get_ts_info, 1256 .get_coalesce = stmmac_get_coalesce, 1257 .set_coalesce = stmmac_set_coalesce, 1258 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1259 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1260 .get_channels = stmmac_get_channels, 1261 .set_channels = stmmac_set_channels, 1262 .get_tunable = stmmac_get_tunable, 1263 .set_tunable = stmmac_set_tunable, 1264 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1265 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1266 }; 1267 1268 void stmmac_set_ethtool_ops(struct net_device *netdev) 1269 { 1270 netdev->ethtool_ops = &stmmac_ethtool_ops; 1271 } 1272