1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/mii.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 19 #include "stmmac.h" 20 #include "stmmac_fpe.h" 21 #include "dwmac_dma.h" 22 #include "dwxgmac2.h" 23 24 #define REG_SPACE_SIZE 0x1060 25 #define GMAC4_REG_SPACE_SIZE 0x116C 26 #define MAC100_ETHTOOL_NAME "st_mac100" 27 #define GMAC_ETHTOOL_NAME "st_gmac" 28 #define XGMAC_ETHTOOL_NAME "st_xgmac" 29 30 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 31 * 32 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 33 * same time due to the conflicting macro names. 34 */ 35 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 36 37 #define ETHTOOL_DMA_OFFSET 55 38 39 struct stmmac_stats { 40 char stat_string[ETH_GSTRING_LEN] __nonstring; 41 int sizeof_stat; 42 int stat_offset; 43 }; 44 45 #define STMMAC_STAT(m) \ 46 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 47 offsetof(struct stmmac_priv, xstats.m)} 48 49 static const struct stmmac_stats stmmac_gstrings_stats[] = { 50 /* Transmit errors */ 51 STMMAC_STAT(tx_underflow), 52 STMMAC_STAT(tx_carrier), 53 STMMAC_STAT(tx_losscarrier), 54 STMMAC_STAT(vlan_tag), 55 STMMAC_STAT(tx_deferred), 56 STMMAC_STAT(tx_vlan), 57 STMMAC_STAT(tx_jabber), 58 STMMAC_STAT(tx_frame_flushed), 59 STMMAC_STAT(tx_payload_error), 60 STMMAC_STAT(tx_ip_header_error), 61 /* Receive errors */ 62 STMMAC_STAT(rx_desc), 63 STMMAC_STAT(sa_filter_fail), 64 STMMAC_STAT(overflow_error), 65 STMMAC_STAT(ipc_csum_error), 66 STMMAC_STAT(rx_collision), 67 STMMAC_STAT(rx_crc_errors), 68 STMMAC_STAT(dribbling_bit), 69 STMMAC_STAT(rx_length), 70 STMMAC_STAT(rx_mii), 71 STMMAC_STAT(rx_multicast), 72 STMMAC_STAT(rx_gmac_overflow), 73 STMMAC_STAT(rx_watchdog), 74 STMMAC_STAT(da_rx_filter_fail), 75 STMMAC_STAT(sa_rx_filter_fail), 76 STMMAC_STAT(rx_missed_cntr), 77 STMMAC_STAT(rx_overflow_cntr), 78 STMMAC_STAT(rx_vlan), 79 STMMAC_STAT(rx_split_hdr_pkt_n), 80 /* Tx/Rx IRQ error info */ 81 STMMAC_STAT(tx_undeflow_irq), 82 STMMAC_STAT(tx_process_stopped_irq), 83 STMMAC_STAT(tx_jabber_irq), 84 STMMAC_STAT(rx_overflow_irq), 85 STMMAC_STAT(rx_buf_unav_irq), 86 STMMAC_STAT(rx_process_stopped_irq), 87 STMMAC_STAT(rx_watchdog_irq), 88 STMMAC_STAT(tx_early_irq), 89 STMMAC_STAT(fatal_bus_error_irq), 90 /* Tx/Rx IRQ Events */ 91 STMMAC_STAT(rx_early_irq), 92 STMMAC_STAT(threshold), 93 STMMAC_STAT(irq_receive_pmt_irq_n), 94 /* MMC info */ 95 STMMAC_STAT(mmc_tx_irq_n), 96 STMMAC_STAT(mmc_rx_irq_n), 97 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 98 /* EEE */ 99 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 100 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 102 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 103 STMMAC_STAT(phy_eee_wakeup_error_n), 104 /* Extended RDES status */ 105 STMMAC_STAT(ip_hdr_err), 106 STMMAC_STAT(ip_payload_err), 107 STMMAC_STAT(ip_csum_bypassed), 108 STMMAC_STAT(ipv4_pkt_rcvd), 109 STMMAC_STAT(ipv6_pkt_rcvd), 110 STMMAC_STAT(no_ptp_rx_msg_type_ext), 111 STMMAC_STAT(ptp_rx_msg_type_sync), 112 STMMAC_STAT(ptp_rx_msg_type_follow_up), 113 STMMAC_STAT(ptp_rx_msg_type_delay_req), 114 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 117 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 118 STMMAC_STAT(ptp_rx_msg_type_announce), 119 STMMAC_STAT(ptp_rx_msg_type_management), 120 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 121 STMMAC_STAT(ptp_frame_type), 122 STMMAC_STAT(ptp_ver), 123 STMMAC_STAT(timestamp_dropped), 124 STMMAC_STAT(av_pkt_rcvd), 125 STMMAC_STAT(av_tagged_pkt_rcvd), 126 STMMAC_STAT(vlan_tag_priority_val), 127 STMMAC_STAT(l3_filter_match), 128 STMMAC_STAT(l4_filter_match), 129 STMMAC_STAT(l3_l4_filter_no_match), 130 /* PCS */ 131 STMMAC_STAT(irq_pcs_ane_n), 132 STMMAC_STAT(irq_pcs_link_n), 133 STMMAC_STAT(irq_rgmii_n), 134 /* DEBUG */ 135 STMMAC_STAT(mtl_tx_status_fifo_full), 136 STMMAC_STAT(mtl_tx_fifo_not_empty), 137 STMMAC_STAT(mmtl_fifo_ctrl), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 141 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 142 STMMAC_STAT(mac_tx_in_pause), 143 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 144 STMMAC_STAT(mac_tx_frame_ctrl_idle), 145 STMMAC_STAT(mac_tx_frame_ctrl_wait), 146 STMMAC_STAT(mac_tx_frame_ctrl_pause), 147 STMMAC_STAT(mac_gmii_tx_proto_engine), 148 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 149 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 151 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 155 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 156 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 157 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 158 STMMAC_STAT(mac_gmii_rx_proto_engine), 159 /* EST */ 160 STMMAC_STAT(mtl_est_cgce), 161 STMMAC_STAT(mtl_est_hlbs), 162 STMMAC_STAT(mtl_est_hlbf), 163 STMMAC_STAT(mtl_est_btre), 164 STMMAC_STAT(mtl_est_btrlm), 165 }; 166 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 167 168 /* statistics collected in queue which will be summed up for all TX or RX 169 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). 170 */ 171 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = { 172 "rx_pkt_n", 173 "rx_normal_irq_n", 174 "tx_pkt_n", 175 "tx_normal_irq_n", 176 "tx_clean", 177 "tx_set_ic_bit", 178 "tx_tso_frames", 179 "tx_tso_nfrags", 180 "normal_irq_n", 181 "napi_poll", 182 }; 183 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string) 184 185 /* HW MAC Management counters (if supported) */ 186 #define STMMAC_MMC_STAT(m) \ 187 { #m, sizeof_field(struct stmmac_counters, m), \ 188 offsetof(struct stmmac_priv, mmc.m)} 189 190 static const struct stmmac_stats stmmac_mmc[] = { 191 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 192 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 193 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 194 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 195 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 196 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 197 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 198 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 199 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 200 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 201 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 202 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 203 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 204 STMMAC_MMC_STAT(mmc_tx_underflow_error), 205 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 206 STMMAC_MMC_STAT(mmc_tx_multicol_g), 207 STMMAC_MMC_STAT(mmc_tx_deferred), 208 STMMAC_MMC_STAT(mmc_tx_latecol), 209 STMMAC_MMC_STAT(mmc_tx_exesscol), 210 STMMAC_MMC_STAT(mmc_tx_carrier_error), 211 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 212 STMMAC_MMC_STAT(mmc_tx_framecount_g), 213 STMMAC_MMC_STAT(mmc_tx_excessdef), 214 STMMAC_MMC_STAT(mmc_tx_pause_frame), 215 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 216 STMMAC_MMC_STAT(mmc_tx_oversize_g), 217 STMMAC_MMC_STAT(mmc_tx_lpi_usec), 218 STMMAC_MMC_STAT(mmc_tx_lpi_tran), 219 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 220 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 221 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 222 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 223 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 224 STMMAC_MMC_STAT(mmc_rx_crc_error), 225 STMMAC_MMC_STAT(mmc_rx_align_error), 226 STMMAC_MMC_STAT(mmc_rx_run_error), 227 STMMAC_MMC_STAT(mmc_rx_jabber_error), 228 STMMAC_MMC_STAT(mmc_rx_undersize_g), 229 STMMAC_MMC_STAT(mmc_rx_oversize_g), 230 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 231 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 232 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 233 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 234 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 235 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 236 STMMAC_MMC_STAT(mmc_rx_unicast_g), 237 STMMAC_MMC_STAT(mmc_rx_length_error), 238 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 239 STMMAC_MMC_STAT(mmc_rx_pause_frames), 240 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 241 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 242 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 243 STMMAC_MMC_STAT(mmc_rx_error), 244 STMMAC_MMC_STAT(mmc_rx_lpi_usec), 245 STMMAC_MMC_STAT(mmc_rx_lpi_tran), 246 STMMAC_MMC_STAT(mmc_rx_discard_frames_gb), 247 STMMAC_MMC_STAT(mmc_rx_discard_octets_gb), 248 STMMAC_MMC_STAT(mmc_rx_align_err_frames), 249 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 250 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 251 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 252 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 253 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 254 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 255 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 256 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 257 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 258 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 259 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 260 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 261 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 262 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 263 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 264 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 265 STMMAC_MMC_STAT(mmc_rx_udp_gd), 266 STMMAC_MMC_STAT(mmc_rx_udp_err), 267 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 268 STMMAC_MMC_STAT(mmc_rx_tcp_err), 269 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 270 STMMAC_MMC_STAT(mmc_rx_icmp_err), 271 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 272 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 273 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 274 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 275 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 276 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 277 STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr), 278 STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr), 279 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 280 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 281 STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr), 282 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 283 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 284 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 285 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 286 }; 287 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 288 289 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 290 "tx_pkt_n", 291 "tx_irq_n", 292 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 293 }; 294 295 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 296 "rx_pkt_n", 297 "rx_irq_n", 298 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 299 }; 300 301 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 302 struct ethtool_drvinfo *info) 303 { 304 struct stmmac_priv *priv = netdev_priv(dev); 305 306 if (priv->plat->has_gmac || priv->plat->has_gmac4) 307 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 308 else if (priv->plat->has_xgmac) 309 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 310 else 311 strscpy(info->driver, MAC100_ETHTOOL_NAME, 312 sizeof(info->driver)); 313 314 if (priv->plat->pdev) { 315 strscpy(info->bus_info, pci_name(priv->plat->pdev), 316 sizeof(info->bus_info)); 317 } 318 } 319 320 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 321 struct ethtool_link_ksettings *cmd) 322 { 323 struct stmmac_priv *priv = netdev_priv(dev); 324 325 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) && 326 (priv->hw->pcs & STMMAC_PCS_RGMII || 327 priv->hw->pcs & STMMAC_PCS_SGMII)) { 328 u32 supported, advertising, lp_advertising; 329 330 if (!priv->xstats.pcs_link) { 331 cmd->base.speed = SPEED_UNKNOWN; 332 cmd->base.duplex = DUPLEX_UNKNOWN; 333 return 0; 334 } 335 cmd->base.duplex = priv->xstats.pcs_duplex; 336 337 cmd->base.speed = priv->xstats.pcs_speed; 338 339 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 340 341 ethtool_convert_link_mode_to_legacy_u32( 342 &supported, cmd->link_modes.supported); 343 ethtool_convert_link_mode_to_legacy_u32( 344 &advertising, cmd->link_modes.advertising); 345 ethtool_convert_link_mode_to_legacy_u32( 346 &lp_advertising, cmd->link_modes.lp_advertising); 347 348 /* Reg49[3] always set because ANE is always supported */ 349 cmd->base.autoneg = ADVERTISED_Autoneg; 350 supported |= SUPPORTED_Autoneg; 351 advertising |= ADVERTISED_Autoneg; 352 lp_advertising |= ADVERTISED_Autoneg; 353 354 cmd->base.port = PORT_OTHER; 355 356 ethtool_convert_legacy_u32_to_link_mode( 357 cmd->link_modes.supported, supported); 358 ethtool_convert_legacy_u32_to_link_mode( 359 cmd->link_modes.advertising, advertising); 360 ethtool_convert_legacy_u32_to_link_mode( 361 cmd->link_modes.lp_advertising, lp_advertising); 362 363 return 0; 364 } 365 366 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 367 } 368 369 static int 370 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 371 const struct ethtool_link_ksettings *cmd) 372 { 373 struct stmmac_priv *priv = netdev_priv(dev); 374 375 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) && 376 (priv->hw->pcs & STMMAC_PCS_RGMII || 377 priv->hw->pcs & STMMAC_PCS_SGMII)) { 378 /* Only support ANE */ 379 if (cmd->base.autoneg != AUTONEG_ENABLE) 380 return -EINVAL; 381 382 mutex_lock(&priv->lock); 383 stmmac_pcs_ctrl_ane(priv, 1, priv->hw->ps, 0); 384 mutex_unlock(&priv->lock); 385 386 return 0; 387 } 388 389 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 390 } 391 392 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 393 { 394 struct stmmac_priv *priv = netdev_priv(dev); 395 return priv->msg_enable; 396 } 397 398 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 399 { 400 struct stmmac_priv *priv = netdev_priv(dev); 401 priv->msg_enable = level; 402 403 } 404 405 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 406 { 407 struct stmmac_priv *priv = netdev_priv(dev); 408 409 if (priv->plat->has_xgmac) 410 return XGMAC_REGSIZE * 4; 411 else if (priv->plat->has_gmac4) 412 return GMAC4_REG_SPACE_SIZE; 413 return REG_SPACE_SIZE; 414 } 415 416 static void stmmac_ethtool_gregs(struct net_device *dev, 417 struct ethtool_regs *regs, void *space) 418 { 419 struct stmmac_priv *priv = netdev_priv(dev); 420 u32 *reg_space = (u32 *) space; 421 422 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 423 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 424 425 /* Copy DMA registers to where ethtool expects them */ 426 if (priv->plat->has_gmac4) { 427 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 428 memcpy(®_space[ETHTOOL_DMA_OFFSET], 429 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 430 NUM_DWMAC4_DMA_REGS * 4); 431 } else if (!priv->plat->has_xgmac) { 432 memcpy(®_space[ETHTOOL_DMA_OFFSET], 433 ®_space[DMA_BUS_MODE / 4], 434 NUM_DWMAC1000_DMA_REGS * 4); 435 } 436 } 437 438 static int stmmac_nway_reset(struct net_device *dev) 439 { 440 struct stmmac_priv *priv = netdev_priv(dev); 441 442 return phylink_ethtool_nway_reset(priv->phylink); 443 } 444 445 static void stmmac_get_ringparam(struct net_device *netdev, 446 struct ethtool_ringparam *ring, 447 struct kernel_ethtool_ringparam *kernel_ring, 448 struct netlink_ext_ack *extack) 449 { 450 struct stmmac_priv *priv = netdev_priv(netdev); 451 452 ring->rx_max_pending = DMA_MAX_RX_SIZE; 453 ring->tx_max_pending = DMA_MAX_TX_SIZE; 454 ring->rx_pending = priv->dma_conf.dma_rx_size; 455 ring->tx_pending = priv->dma_conf.dma_tx_size; 456 } 457 458 static int stmmac_set_ringparam(struct net_device *netdev, 459 struct ethtool_ringparam *ring, 460 struct kernel_ethtool_ringparam *kernel_ring, 461 struct netlink_ext_ack *extack) 462 { 463 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 464 ring->rx_pending < DMA_MIN_RX_SIZE || 465 ring->rx_pending > DMA_MAX_RX_SIZE || 466 !is_power_of_2(ring->rx_pending) || 467 ring->tx_pending < DMA_MIN_TX_SIZE || 468 ring->tx_pending > DMA_MAX_TX_SIZE || 469 !is_power_of_2(ring->tx_pending)) 470 return -EINVAL; 471 472 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 473 ring->tx_pending); 474 } 475 476 static void 477 stmmac_get_pauseparam(struct net_device *netdev, 478 struct ethtool_pauseparam *pause) 479 { 480 struct stmmac_priv *priv = netdev_priv(netdev); 481 482 if (priv->hw->pcs) { 483 pause->autoneg = 1; 484 } else { 485 phylink_ethtool_get_pauseparam(priv->phylink, pause); 486 } 487 } 488 489 static int 490 stmmac_set_pauseparam(struct net_device *netdev, 491 struct ethtool_pauseparam *pause) 492 { 493 struct stmmac_priv *priv = netdev_priv(netdev); 494 495 if (priv->hw->pcs) { 496 pause->autoneg = 1; 497 return 0; 498 } else { 499 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 500 } 501 } 502 503 static u64 stmmac_get_rx_normal_irq_n(struct stmmac_priv *priv, int q) 504 { 505 u64 total; 506 int cpu; 507 508 total = 0; 509 for_each_possible_cpu(cpu) { 510 struct stmmac_pcpu_stats *pcpu; 511 unsigned int start; 512 u64 irq_n; 513 514 pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu); 515 do { 516 start = u64_stats_fetch_begin(&pcpu->syncp); 517 irq_n = u64_stats_read(&pcpu->rx_normal_irq_n[q]); 518 } while (u64_stats_fetch_retry(&pcpu->syncp, start)); 519 total += irq_n; 520 } 521 return total; 522 } 523 524 static u64 stmmac_get_tx_normal_irq_n(struct stmmac_priv *priv, int q) 525 { 526 u64 total; 527 int cpu; 528 529 total = 0; 530 for_each_possible_cpu(cpu) { 531 struct stmmac_pcpu_stats *pcpu; 532 unsigned int start; 533 u64 irq_n; 534 535 pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu); 536 do { 537 start = u64_stats_fetch_begin(&pcpu->syncp); 538 irq_n = u64_stats_read(&pcpu->tx_normal_irq_n[q]); 539 } while (u64_stats_fetch_retry(&pcpu->syncp, start)); 540 total += irq_n; 541 } 542 return total; 543 } 544 545 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 546 { 547 u32 tx_cnt = priv->plat->tx_queues_to_use; 548 u32 rx_cnt = priv->plat->rx_queues_to_use; 549 unsigned int start; 550 int q; 551 552 for (q = 0; q < tx_cnt; q++) { 553 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q]; 554 u64 pkt_n; 555 556 do { 557 start = u64_stats_fetch_begin(&txq_stats->napi_syncp); 558 pkt_n = u64_stats_read(&txq_stats->napi.tx_pkt_n); 559 } while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start)); 560 561 *data++ = pkt_n; 562 *data++ = stmmac_get_tx_normal_irq_n(priv, q); 563 } 564 565 for (q = 0; q < rx_cnt; q++) { 566 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q]; 567 u64 pkt_n; 568 569 do { 570 start = u64_stats_fetch_begin(&rxq_stats->napi_syncp); 571 pkt_n = u64_stats_read(&rxq_stats->napi.rx_pkt_n); 572 } while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start)); 573 574 *data++ = pkt_n; 575 *data++ = stmmac_get_rx_normal_irq_n(priv, q); 576 } 577 } 578 579 static void stmmac_get_ethtool_stats(struct net_device *dev, 580 struct ethtool_stats *dummy, u64 *data) 581 { 582 struct stmmac_priv *priv = netdev_priv(dev); 583 u32 rx_queues_count = priv->plat->rx_queues_to_use; 584 u32 tx_queues_count = priv->plat->tx_queues_to_use; 585 u64 napi_poll = 0, normal_irq_n = 0; 586 int i, j = 0, pos, ret; 587 unsigned long count; 588 unsigned int start; 589 590 if (priv->dma_cap.asp) { 591 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 592 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 593 &count, NULL)) 594 data[j++] = count; 595 } 596 } 597 598 /* Update the DMA HW counters for dwmac10/100 */ 599 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr); 600 if (ret) { 601 /* If supported, for new GMAC chips expose the MMC counters */ 602 if (priv->dma_cap.rmon) { 603 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 604 605 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 606 char *p; 607 p = (char *)priv + stmmac_mmc[i].stat_offset; 608 609 data[j++] = (stmmac_mmc[i].sizeof_stat == 610 sizeof(u64)) ? (*(u64 *)p) : 611 (*(u32 *)p); 612 } 613 } 614 if (priv->dma_cap.eee) { 615 int val = phylink_get_eee_err(priv->phylink); 616 if (val) 617 priv->xstats.phy_eee_wakeup_error_n = val; 618 } 619 620 if (priv->synopsys_id >= DWMAC_CORE_3_50) 621 stmmac_mac_debug(priv, priv->ioaddr, 622 (void *)&priv->xstats, 623 rx_queues_count, tx_queues_count); 624 } 625 for (i = 0; i < STMMAC_STATS_LEN; i++) { 626 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 627 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 628 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 629 } 630 631 pos = j; 632 for (i = 0; i < rx_queues_count; i++) { 633 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i]; 634 struct stmmac_napi_rx_stats snapshot; 635 u64 n_irq; 636 637 j = pos; 638 do { 639 start = u64_stats_fetch_begin(&rxq_stats->napi_syncp); 640 snapshot = rxq_stats->napi; 641 } while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start)); 642 643 data[j++] += u64_stats_read(&snapshot.rx_pkt_n); 644 n_irq = stmmac_get_rx_normal_irq_n(priv, i); 645 data[j++] += n_irq; 646 normal_irq_n += n_irq; 647 napi_poll += u64_stats_read(&snapshot.poll); 648 } 649 650 pos = j; 651 for (i = 0; i < tx_queues_count; i++) { 652 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i]; 653 struct stmmac_napi_tx_stats napi_snapshot; 654 struct stmmac_q_tx_stats q_snapshot; 655 u64 n_irq; 656 657 j = pos; 658 do { 659 start = u64_stats_fetch_begin(&txq_stats->q_syncp); 660 q_snapshot = txq_stats->q; 661 } while (u64_stats_fetch_retry(&txq_stats->q_syncp, start)); 662 do { 663 start = u64_stats_fetch_begin(&txq_stats->napi_syncp); 664 napi_snapshot = txq_stats->napi; 665 } while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start)); 666 667 data[j++] += u64_stats_read(&napi_snapshot.tx_pkt_n); 668 n_irq = stmmac_get_tx_normal_irq_n(priv, i); 669 data[j++] += n_irq; 670 normal_irq_n += n_irq; 671 data[j++] += u64_stats_read(&napi_snapshot.tx_clean); 672 data[j++] += u64_stats_read(&q_snapshot.tx_set_ic_bit) + 673 u64_stats_read(&napi_snapshot.tx_set_ic_bit); 674 data[j++] += u64_stats_read(&q_snapshot.tx_tso_frames); 675 data[j++] += u64_stats_read(&q_snapshot.tx_tso_nfrags); 676 napi_poll += u64_stats_read(&napi_snapshot.poll); 677 } 678 normal_irq_n += priv->xstats.rx_early_irq; 679 data[j++] = normal_irq_n; 680 data[j++] = napi_poll; 681 682 stmmac_get_per_qstats(priv, &data[j]); 683 } 684 685 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 686 { 687 struct stmmac_priv *priv = netdev_priv(netdev); 688 u32 tx_cnt = priv->plat->tx_queues_to_use; 689 u32 rx_cnt = priv->plat->rx_queues_to_use; 690 int i, len, safety_len = 0; 691 692 switch (sset) { 693 case ETH_SS_STATS: 694 len = STMMAC_STATS_LEN + STMMAC_QSTATS + 695 STMMAC_TXQ_STATS * tx_cnt + 696 STMMAC_RXQ_STATS * rx_cnt; 697 698 if (priv->dma_cap.rmon) 699 len += STMMAC_MMC_STATS_LEN; 700 if (priv->dma_cap.asp) { 701 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 702 if (!stmmac_safety_feat_dump(priv, 703 &priv->sstats, i, 704 NULL, NULL)) 705 safety_len++; 706 } 707 708 len += safety_len; 709 } 710 711 return len; 712 case ETH_SS_TEST: 713 return stmmac_selftest_get_count(priv); 714 default: 715 return -EOPNOTSUPP; 716 } 717 } 718 719 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 720 { 721 u32 tx_cnt = priv->plat->tx_queues_to_use; 722 u32 rx_cnt = priv->plat->rx_queues_to_use; 723 int q, stat; 724 725 for (q = 0; q < tx_cnt; q++) { 726 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 727 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 728 stmmac_qstats_tx_string[stat]); 729 data += ETH_GSTRING_LEN; 730 } 731 } 732 for (q = 0; q < rx_cnt; q++) { 733 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 734 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 735 stmmac_qstats_rx_string[stat]); 736 data += ETH_GSTRING_LEN; 737 } 738 } 739 } 740 741 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 742 { 743 int i; 744 u8 *p = data; 745 struct stmmac_priv *priv = netdev_priv(dev); 746 747 switch (stringset) { 748 case ETH_SS_STATS: 749 if (priv->dma_cap.asp) { 750 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 751 const char *desc; 752 if (!stmmac_safety_feat_dump(priv, 753 &priv->sstats, i, 754 NULL, &desc)) { 755 memcpy(p, desc, ETH_GSTRING_LEN); 756 p += ETH_GSTRING_LEN; 757 } 758 } 759 } 760 if (priv->dma_cap.rmon) 761 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 762 memcpy(p, stmmac_mmc[i].stat_string, 763 ETH_GSTRING_LEN); 764 p += ETH_GSTRING_LEN; 765 } 766 for (i = 0; i < STMMAC_STATS_LEN; i++) { 767 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN); 768 p += ETH_GSTRING_LEN; 769 } 770 for (i = 0; i < STMMAC_QSTATS; i++) { 771 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN); 772 p += ETH_GSTRING_LEN; 773 } 774 stmmac_get_qstats_string(priv, p); 775 break; 776 case ETH_SS_TEST: 777 stmmac_selftest_get_strings(priv, p); 778 break; 779 default: 780 WARN_ON(1); 781 break; 782 } 783 } 784 785 /* Currently only support WOL through Magic packet. */ 786 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 787 { 788 struct stmmac_priv *priv = netdev_priv(dev); 789 790 if (!priv->plat->pmt) 791 return phylink_ethtool_get_wol(priv->phylink, wol); 792 793 mutex_lock(&priv->lock); 794 if (device_can_wakeup(priv->device)) { 795 wol->supported = WAKE_MAGIC | WAKE_UCAST; 796 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 797 wol->supported &= ~WAKE_MAGIC; 798 wol->wolopts = priv->wolopts; 799 } 800 mutex_unlock(&priv->lock); 801 } 802 803 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 804 { 805 struct stmmac_priv *priv = netdev_priv(dev); 806 u32 support = WAKE_MAGIC | WAKE_UCAST; 807 808 if (!device_can_wakeup(priv->device)) 809 return -EOPNOTSUPP; 810 811 if (!priv->plat->pmt) { 812 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 813 814 if (!ret) 815 device_set_wakeup_enable(priv->device, !!wol->wolopts); 816 return ret; 817 } 818 819 /* By default almost all GMAC devices support the WoL via 820 * magic frame but we can disable it if the HW capability 821 * register shows no support for pmt_magic_frame. */ 822 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 823 wol->wolopts &= ~WAKE_MAGIC; 824 825 if (wol->wolopts & ~support) 826 return -EINVAL; 827 828 if (wol->wolopts) { 829 pr_info("stmmac: wakeup enable\n"); 830 device_set_wakeup_enable(priv->device, 1); 831 /* Avoid unbalanced enable_irq_wake calls */ 832 if (priv->wol_irq_disabled) 833 enable_irq_wake(priv->wol_irq); 834 priv->wol_irq_disabled = false; 835 } else { 836 device_set_wakeup_enable(priv->device, 0); 837 /* Avoid unbalanced disable_irq_wake calls */ 838 if (!priv->wol_irq_disabled) 839 disable_irq_wake(priv->wol_irq); 840 priv->wol_irq_disabled = true; 841 } 842 843 mutex_lock(&priv->lock); 844 priv->wolopts = wol->wolopts; 845 mutex_unlock(&priv->lock); 846 847 return 0; 848 } 849 850 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 851 struct ethtool_keee *edata) 852 { 853 struct stmmac_priv *priv = netdev_priv(dev); 854 855 if (!priv->dma_cap.eee) 856 return -EOPNOTSUPP; 857 858 return phylink_ethtool_get_eee(priv->phylink, edata); 859 } 860 861 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 862 struct ethtool_keee *edata) 863 { 864 struct stmmac_priv *priv = netdev_priv(dev); 865 866 if (!priv->dma_cap.eee) 867 return -EOPNOTSUPP; 868 869 return phylink_ethtool_set_eee(priv->phylink, edata); 870 } 871 872 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 873 { 874 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 875 876 if (!clk) { 877 clk = priv->plat->clk_ref_rate; 878 if (!clk) 879 return 0; 880 } 881 882 return (usec * (clk / 1000000)) / 256; 883 } 884 885 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 886 { 887 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 888 889 if (!clk) { 890 clk = priv->plat->clk_ref_rate; 891 if (!clk) 892 return 0; 893 } 894 895 return (riwt * 256) / (clk / 1000000); 896 } 897 898 static int __stmmac_get_coalesce(struct net_device *dev, 899 struct ethtool_coalesce *ec, 900 int queue) 901 { 902 struct stmmac_priv *priv = netdev_priv(dev); 903 u32 max_cnt; 904 u32 rx_cnt; 905 u32 tx_cnt; 906 907 rx_cnt = priv->plat->rx_queues_to_use; 908 tx_cnt = priv->plat->tx_queues_to_use; 909 max_cnt = max(rx_cnt, tx_cnt); 910 911 if (queue < 0) 912 queue = 0; 913 else if (queue >= max_cnt) 914 return -EINVAL; 915 916 if (queue < tx_cnt) { 917 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 918 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 919 } else { 920 ec->tx_coalesce_usecs = 0; 921 ec->tx_max_coalesced_frames = 0; 922 } 923 924 if (priv->use_riwt && queue < rx_cnt) { 925 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 926 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 927 priv); 928 } else { 929 ec->rx_max_coalesced_frames = 0; 930 ec->rx_coalesce_usecs = 0; 931 } 932 933 return 0; 934 } 935 936 static int stmmac_get_coalesce(struct net_device *dev, 937 struct ethtool_coalesce *ec, 938 struct kernel_ethtool_coalesce *kernel_coal, 939 struct netlink_ext_ack *extack) 940 { 941 return __stmmac_get_coalesce(dev, ec, -1); 942 } 943 944 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 945 struct ethtool_coalesce *ec) 946 { 947 return __stmmac_get_coalesce(dev, ec, queue); 948 } 949 950 static int __stmmac_set_coalesce(struct net_device *dev, 951 struct ethtool_coalesce *ec, 952 int queue) 953 { 954 struct stmmac_priv *priv = netdev_priv(dev); 955 bool all_queues = false; 956 unsigned int rx_riwt; 957 u32 max_cnt; 958 u32 rx_cnt; 959 u32 tx_cnt; 960 961 rx_cnt = priv->plat->rx_queues_to_use; 962 tx_cnt = priv->plat->tx_queues_to_use; 963 max_cnt = max(rx_cnt, tx_cnt); 964 965 if (queue < 0) 966 all_queues = true; 967 else if (queue >= max_cnt) 968 return -EINVAL; 969 970 if (priv->use_riwt) { 971 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 972 973 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 974 return -EINVAL; 975 976 if (all_queues) { 977 int i; 978 979 for (i = 0; i < rx_cnt; i++) { 980 priv->rx_riwt[i] = rx_riwt; 981 stmmac_rx_watchdog(priv, priv->ioaddr, 982 rx_riwt, i); 983 priv->rx_coal_frames[i] = 984 ec->rx_max_coalesced_frames; 985 } 986 } else if (queue < rx_cnt) { 987 priv->rx_riwt[queue] = rx_riwt; 988 stmmac_rx_watchdog(priv, priv->ioaddr, 989 rx_riwt, queue); 990 priv->rx_coal_frames[queue] = 991 ec->rx_max_coalesced_frames; 992 } 993 } 994 995 if ((ec->tx_coalesce_usecs == 0) && 996 (ec->tx_max_coalesced_frames == 0)) 997 return -EINVAL; 998 999 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 1000 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 1001 return -EINVAL; 1002 1003 if (all_queues) { 1004 int i; 1005 1006 for (i = 0; i < tx_cnt; i++) { 1007 priv->tx_coal_frames[i] = 1008 ec->tx_max_coalesced_frames; 1009 priv->tx_coal_timer[i] = 1010 ec->tx_coalesce_usecs; 1011 } 1012 } else if (queue < tx_cnt) { 1013 priv->tx_coal_frames[queue] = 1014 ec->tx_max_coalesced_frames; 1015 priv->tx_coal_timer[queue] = 1016 ec->tx_coalesce_usecs; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static int stmmac_set_coalesce(struct net_device *dev, 1023 struct ethtool_coalesce *ec, 1024 struct kernel_ethtool_coalesce *kernel_coal, 1025 struct netlink_ext_ack *extack) 1026 { 1027 return __stmmac_set_coalesce(dev, ec, -1); 1028 } 1029 1030 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1031 struct ethtool_coalesce *ec) 1032 { 1033 return __stmmac_set_coalesce(dev, ec, queue); 1034 } 1035 1036 static int stmmac_get_rxnfc(struct net_device *dev, 1037 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1038 { 1039 struct stmmac_priv *priv = netdev_priv(dev); 1040 1041 switch (rxnfc->cmd) { 1042 case ETHTOOL_GRXRINGS: 1043 rxnfc->data = priv->plat->rx_queues_to_use; 1044 break; 1045 default: 1046 return -EOPNOTSUPP; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 1053 { 1054 struct stmmac_priv *priv = netdev_priv(dev); 1055 1056 return sizeof(priv->rss.key); 1057 } 1058 1059 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1060 { 1061 struct stmmac_priv *priv = netdev_priv(dev); 1062 1063 return ARRAY_SIZE(priv->rss.table); 1064 } 1065 1066 static int stmmac_get_rxfh(struct net_device *dev, 1067 struct ethtool_rxfh_param *rxfh) 1068 { 1069 struct stmmac_priv *priv = netdev_priv(dev); 1070 int i; 1071 1072 if (rxfh->indir) { 1073 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1074 rxfh->indir[i] = priv->rss.table[i]; 1075 } 1076 1077 if (rxfh->key) 1078 memcpy(rxfh->key, priv->rss.key, sizeof(priv->rss.key)); 1079 rxfh->hfunc = ETH_RSS_HASH_TOP; 1080 1081 return 0; 1082 } 1083 1084 static int stmmac_set_rxfh(struct net_device *dev, 1085 struct ethtool_rxfh_param *rxfh, 1086 struct netlink_ext_ack *extack) 1087 { 1088 struct stmmac_priv *priv = netdev_priv(dev); 1089 int i; 1090 1091 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 1092 rxfh->hfunc != ETH_RSS_HASH_TOP) 1093 return -EOPNOTSUPP; 1094 1095 if (rxfh->indir) { 1096 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1097 priv->rss.table[i] = rxfh->indir[i]; 1098 } 1099 1100 if (rxfh->key) 1101 memcpy(priv->rss.key, rxfh->key, sizeof(priv->rss.key)); 1102 1103 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1104 priv->plat->rx_queues_to_use); 1105 } 1106 1107 static void stmmac_get_channels(struct net_device *dev, 1108 struct ethtool_channels *chan) 1109 { 1110 struct stmmac_priv *priv = netdev_priv(dev); 1111 1112 chan->rx_count = priv->plat->rx_queues_to_use; 1113 chan->tx_count = priv->plat->tx_queues_to_use; 1114 chan->max_rx = priv->dma_cap.number_rx_queues; 1115 chan->max_tx = priv->dma_cap.number_tx_queues; 1116 } 1117 1118 static int stmmac_set_channels(struct net_device *dev, 1119 struct ethtool_channels *chan) 1120 { 1121 struct stmmac_priv *priv = netdev_priv(dev); 1122 1123 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1124 chan->tx_count > priv->dma_cap.number_tx_queues || 1125 !chan->rx_count || !chan->tx_count) 1126 return -EINVAL; 1127 1128 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1129 } 1130 1131 static int stmmac_get_ts_info(struct net_device *dev, 1132 struct kernel_ethtool_ts_info *info) 1133 { 1134 struct stmmac_priv *priv = netdev_priv(dev); 1135 1136 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1137 1138 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1139 SOF_TIMESTAMPING_TX_HARDWARE | 1140 SOF_TIMESTAMPING_RX_HARDWARE | 1141 SOF_TIMESTAMPING_RAW_HARDWARE; 1142 1143 if (priv->ptp_clock) 1144 info->phc_index = ptp_clock_index(priv->ptp_clock); 1145 else 1146 info->phc_index = 0; 1147 1148 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1149 1150 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1151 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1152 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1153 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1154 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1155 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1156 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1157 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1158 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1159 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1160 (1 << HWTSTAMP_FILTER_ALL)); 1161 return 0; 1162 } else 1163 return ethtool_op_get_ts_info(dev, info); 1164 } 1165 1166 static int stmmac_get_mm(struct net_device *ndev, 1167 struct ethtool_mm_state *state) 1168 { 1169 struct stmmac_priv *priv = netdev_priv(ndev); 1170 u32 frag_size; 1171 1172 if (!stmmac_fpe_supported(priv)) 1173 return -EOPNOTSUPP; 1174 1175 state->rx_min_frag_size = ETH_ZLEN; 1176 frag_size = stmmac_fpe_get_add_frag_size(priv); 1177 state->tx_min_frag_size = ethtool_mm_frag_size_add_to_min(frag_size); 1178 1179 ethtool_mmsv_get_mm(&priv->fpe_cfg.mmsv, state); 1180 1181 return 0; 1182 } 1183 1184 static int stmmac_set_mm(struct net_device *ndev, struct ethtool_mm_cfg *cfg, 1185 struct netlink_ext_ack *extack) 1186 { 1187 struct stmmac_priv *priv = netdev_priv(ndev); 1188 u32 frag_size; 1189 int err; 1190 1191 err = ethtool_mm_frag_size_min_to_add(cfg->tx_min_frag_size, 1192 &frag_size, extack); 1193 if (err) 1194 return err; 1195 1196 stmmac_fpe_set_add_frag_size(priv, frag_size); 1197 ethtool_mmsv_set_mm(&priv->fpe_cfg.mmsv, cfg); 1198 1199 return 0; 1200 } 1201 1202 static void stmmac_get_mm_stats(struct net_device *ndev, 1203 struct ethtool_mm_stats *s) 1204 { 1205 struct stmmac_priv *priv = netdev_priv(ndev); 1206 struct stmmac_counters *mmc = &priv->mmc; 1207 1208 if (!priv->dma_cap.rmon) 1209 return; 1210 1211 stmmac_mmc_read(priv, priv->mmcaddr, mmc); 1212 1213 s->MACMergeFrameAssErrorCount = mmc->mmc_rx_packet_assembly_err_cntr; 1214 s->MACMergeFrameAssOkCount = mmc->mmc_rx_packet_assembly_ok_cntr; 1215 s->MACMergeFrameSmdErrorCount = mmc->mmc_rx_packet_smd_err_cntr; 1216 s->MACMergeFragCountRx = mmc->mmc_rx_fpe_fragment_cntr; 1217 s->MACMergeFragCountTx = mmc->mmc_tx_fpe_fragment_cntr; 1218 s->MACMergeHoldCount = mmc->mmc_tx_hold_req_cntr; 1219 } 1220 1221 static const struct ethtool_ops stmmac_ethtool_ops = { 1222 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1223 ETHTOOL_COALESCE_MAX_FRAMES, 1224 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1225 .get_msglevel = stmmac_ethtool_getmsglevel, 1226 .set_msglevel = stmmac_ethtool_setmsglevel, 1227 .get_regs = stmmac_ethtool_gregs, 1228 .get_regs_len = stmmac_ethtool_get_regs_len, 1229 .get_link = ethtool_op_get_link, 1230 .nway_reset = stmmac_nway_reset, 1231 .get_ringparam = stmmac_get_ringparam, 1232 .set_ringparam = stmmac_set_ringparam, 1233 .get_pauseparam = stmmac_get_pauseparam, 1234 .set_pauseparam = stmmac_set_pauseparam, 1235 .self_test = stmmac_selftest_run, 1236 .get_ethtool_stats = stmmac_get_ethtool_stats, 1237 .get_strings = stmmac_get_strings, 1238 .get_wol = stmmac_get_wol, 1239 .set_wol = stmmac_set_wol, 1240 .get_eee = stmmac_ethtool_op_get_eee, 1241 .set_eee = stmmac_ethtool_op_set_eee, 1242 .get_sset_count = stmmac_get_sset_count, 1243 .get_rxnfc = stmmac_get_rxnfc, 1244 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1245 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1246 .get_rxfh = stmmac_get_rxfh, 1247 .set_rxfh = stmmac_set_rxfh, 1248 .get_ts_info = stmmac_get_ts_info, 1249 .get_coalesce = stmmac_get_coalesce, 1250 .set_coalesce = stmmac_set_coalesce, 1251 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1252 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1253 .get_channels = stmmac_get_channels, 1254 .set_channels = stmmac_set_channels, 1255 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1256 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1257 .get_mm = stmmac_get_mm, 1258 .set_mm = stmmac_set_mm, 1259 .get_mm_stats = stmmac_get_mm_stats, 1260 }; 1261 1262 void stmmac_set_ethtool_ops(struct net_device *netdev) 1263 { 1264 netdev->ethtool_ops = &stmmac_ethtool_ops; 1265 } 1266