1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define GMAC4_REG_SPACE_SIZE 0x116C 25 #define MAC100_ETHTOOL_NAME "st_mac100" 26 #define GMAC_ETHTOOL_NAME "st_gmac" 27 #define XGMAC_ETHTOOL_NAME "st_xgmac" 28 29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 30 * 31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 32 * same time due to the conflicting macro names. 33 */ 34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 35 36 #define ETHTOOL_DMA_OFFSET 55 37 38 struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42 }; 43 44 #define STMMAC_STAT(m) \ 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48 static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 STMMAC_STAT(rx_split_hdr_pkt_n), 79 /* Tx/Rx IRQ error info */ 80 STMMAC_STAT(tx_undeflow_irq), 81 STMMAC_STAT(tx_process_stopped_irq), 82 STMMAC_STAT(tx_jabber_irq), 83 STMMAC_STAT(rx_overflow_irq), 84 STMMAC_STAT(rx_buf_unav_irq), 85 STMMAC_STAT(rx_process_stopped_irq), 86 STMMAC_STAT(rx_watchdog_irq), 87 STMMAC_STAT(tx_early_irq), 88 STMMAC_STAT(fatal_bus_error_irq), 89 /* Tx/Rx IRQ Events */ 90 STMMAC_STAT(rx_early_irq), 91 STMMAC_STAT(threshold), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* EST */ 159 STMMAC_STAT(mtl_est_cgce), 160 STMMAC_STAT(mtl_est_hlbs), 161 STMMAC_STAT(mtl_est_hlbf), 162 STMMAC_STAT(mtl_est_btre), 163 STMMAC_STAT(mtl_est_btrlm), 164 }; 165 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 166 167 /* statistics collected in queue which will be summed up for all TX or RX 168 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). 169 */ 170 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = { 171 "rx_pkt_n", 172 "rx_normal_irq_n", 173 "tx_pkt_n", 174 "tx_normal_irq_n", 175 "tx_clean", 176 "tx_set_ic_bit", 177 "tx_tso_frames", 178 "tx_tso_nfrags", 179 "normal_irq_n", 180 "napi_poll", 181 }; 182 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string) 183 184 /* HW MAC Management counters (if supported) */ 185 #define STMMAC_MMC_STAT(m) \ 186 { #m, sizeof_field(struct stmmac_counters, m), \ 187 offsetof(struct stmmac_priv, mmc.m)} 188 189 static const struct stmmac_stats stmmac_mmc[] = { 190 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 191 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 192 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 193 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 194 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 195 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 196 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 197 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 198 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 199 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 200 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 201 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 202 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 203 STMMAC_MMC_STAT(mmc_tx_underflow_error), 204 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 205 STMMAC_MMC_STAT(mmc_tx_multicol_g), 206 STMMAC_MMC_STAT(mmc_tx_deferred), 207 STMMAC_MMC_STAT(mmc_tx_latecol), 208 STMMAC_MMC_STAT(mmc_tx_exesscol), 209 STMMAC_MMC_STAT(mmc_tx_carrier_error), 210 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 211 STMMAC_MMC_STAT(mmc_tx_framecount_g), 212 STMMAC_MMC_STAT(mmc_tx_excessdef), 213 STMMAC_MMC_STAT(mmc_tx_pause_frame), 214 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 215 STMMAC_MMC_STAT(mmc_tx_lpi_usec), 216 STMMAC_MMC_STAT(mmc_tx_lpi_tran), 217 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 218 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 219 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 220 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 221 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 222 STMMAC_MMC_STAT(mmc_rx_crc_error), 223 STMMAC_MMC_STAT(mmc_rx_align_error), 224 STMMAC_MMC_STAT(mmc_rx_run_error), 225 STMMAC_MMC_STAT(mmc_rx_jabber_error), 226 STMMAC_MMC_STAT(mmc_rx_undersize_g), 227 STMMAC_MMC_STAT(mmc_rx_oversize_g), 228 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 229 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 230 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 231 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 232 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 233 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 234 STMMAC_MMC_STAT(mmc_rx_unicast_g), 235 STMMAC_MMC_STAT(mmc_rx_length_error), 236 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 237 STMMAC_MMC_STAT(mmc_rx_pause_frames), 238 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 239 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 240 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 241 STMMAC_MMC_STAT(mmc_rx_lpi_usec), 242 STMMAC_MMC_STAT(mmc_rx_lpi_tran), 243 STMMAC_MMC_STAT(mmc_rx_discard_frames_gb), 244 STMMAC_MMC_STAT(mmc_rx_discard_octets_gb), 245 STMMAC_MMC_STAT(mmc_rx_align_err_frames), 246 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 247 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 248 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 249 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 250 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 251 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 252 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 253 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 254 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 255 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 256 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 257 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 258 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 259 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 260 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 261 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 262 STMMAC_MMC_STAT(mmc_rx_udp_gd), 263 STMMAC_MMC_STAT(mmc_rx_udp_err), 264 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 265 STMMAC_MMC_STAT(mmc_rx_tcp_err), 266 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 267 STMMAC_MMC_STAT(mmc_rx_icmp_err), 268 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 269 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 270 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 271 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 272 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 273 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 274 STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr), 275 STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr), 276 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 277 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 278 STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr), 279 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 280 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 281 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 282 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 283 }; 284 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 285 286 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 287 "tx_pkt_n", 288 "tx_irq_n", 289 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 290 }; 291 292 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 293 "rx_pkt_n", 294 "rx_irq_n", 295 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 296 }; 297 298 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 299 struct ethtool_drvinfo *info) 300 { 301 struct stmmac_priv *priv = netdev_priv(dev); 302 303 if (priv->plat->has_gmac || priv->plat->has_gmac4) 304 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 305 else if (priv->plat->has_xgmac) 306 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 307 else 308 strscpy(info->driver, MAC100_ETHTOOL_NAME, 309 sizeof(info->driver)); 310 311 if (priv->plat->pdev) { 312 strscpy(info->bus_info, pci_name(priv->plat->pdev), 313 sizeof(info->bus_info)); 314 } 315 } 316 317 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 318 struct ethtool_link_ksettings *cmd) 319 { 320 struct stmmac_priv *priv = netdev_priv(dev); 321 322 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) && 323 (priv->hw->pcs & STMMAC_PCS_RGMII || 324 priv->hw->pcs & STMMAC_PCS_SGMII)) { 325 struct rgmii_adv adv; 326 u32 supported, advertising, lp_advertising; 327 328 if (!priv->xstats.pcs_link) { 329 cmd->base.speed = SPEED_UNKNOWN; 330 cmd->base.duplex = DUPLEX_UNKNOWN; 331 return 0; 332 } 333 cmd->base.duplex = priv->xstats.pcs_duplex; 334 335 cmd->base.speed = priv->xstats.pcs_speed; 336 337 /* Get and convert ADV/LP_ADV from the HW AN registers */ 338 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 339 return -EOPNOTSUPP; /* should never happen indeed */ 340 341 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 342 343 ethtool_convert_link_mode_to_legacy_u32( 344 &supported, cmd->link_modes.supported); 345 ethtool_convert_link_mode_to_legacy_u32( 346 &advertising, cmd->link_modes.advertising); 347 ethtool_convert_link_mode_to_legacy_u32( 348 &lp_advertising, cmd->link_modes.lp_advertising); 349 350 if (adv.pause & STMMAC_PCS_PAUSE) 351 advertising |= ADVERTISED_Pause; 352 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 353 advertising |= ADVERTISED_Asym_Pause; 354 if (adv.lp_pause & STMMAC_PCS_PAUSE) 355 lp_advertising |= ADVERTISED_Pause; 356 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 357 lp_advertising |= ADVERTISED_Asym_Pause; 358 359 /* Reg49[3] always set because ANE is always supported */ 360 cmd->base.autoneg = ADVERTISED_Autoneg; 361 supported |= SUPPORTED_Autoneg; 362 advertising |= ADVERTISED_Autoneg; 363 lp_advertising |= ADVERTISED_Autoneg; 364 365 if (adv.duplex) { 366 supported |= (SUPPORTED_1000baseT_Full | 367 SUPPORTED_100baseT_Full | 368 SUPPORTED_10baseT_Full); 369 advertising |= (ADVERTISED_1000baseT_Full | 370 ADVERTISED_100baseT_Full | 371 ADVERTISED_10baseT_Full); 372 } else { 373 supported |= (SUPPORTED_1000baseT_Half | 374 SUPPORTED_100baseT_Half | 375 SUPPORTED_10baseT_Half); 376 advertising |= (ADVERTISED_1000baseT_Half | 377 ADVERTISED_100baseT_Half | 378 ADVERTISED_10baseT_Half); 379 } 380 if (adv.lp_duplex) 381 lp_advertising |= (ADVERTISED_1000baseT_Full | 382 ADVERTISED_100baseT_Full | 383 ADVERTISED_10baseT_Full); 384 else 385 lp_advertising |= (ADVERTISED_1000baseT_Half | 386 ADVERTISED_100baseT_Half | 387 ADVERTISED_10baseT_Half); 388 cmd->base.port = PORT_OTHER; 389 390 ethtool_convert_legacy_u32_to_link_mode( 391 cmd->link_modes.supported, supported); 392 ethtool_convert_legacy_u32_to_link_mode( 393 cmd->link_modes.advertising, advertising); 394 ethtool_convert_legacy_u32_to_link_mode( 395 cmd->link_modes.lp_advertising, lp_advertising); 396 397 return 0; 398 } 399 400 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 401 } 402 403 static int 404 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 405 const struct ethtool_link_ksettings *cmd) 406 { 407 struct stmmac_priv *priv = netdev_priv(dev); 408 409 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) && 410 (priv->hw->pcs & STMMAC_PCS_RGMII || 411 priv->hw->pcs & STMMAC_PCS_SGMII)) { 412 /* Only support ANE */ 413 if (cmd->base.autoneg != AUTONEG_ENABLE) 414 return -EINVAL; 415 416 mutex_lock(&priv->lock); 417 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 418 mutex_unlock(&priv->lock); 419 420 return 0; 421 } 422 423 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 424 } 425 426 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 427 { 428 struct stmmac_priv *priv = netdev_priv(dev); 429 return priv->msg_enable; 430 } 431 432 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 433 { 434 struct stmmac_priv *priv = netdev_priv(dev); 435 priv->msg_enable = level; 436 437 } 438 439 static int stmmac_check_if_running(struct net_device *dev) 440 { 441 if (!netif_running(dev)) 442 return -EBUSY; 443 return 0; 444 } 445 446 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 447 { 448 struct stmmac_priv *priv = netdev_priv(dev); 449 450 if (priv->plat->has_xgmac) 451 return XGMAC_REGSIZE * 4; 452 else if (priv->plat->has_gmac4) 453 return GMAC4_REG_SPACE_SIZE; 454 return REG_SPACE_SIZE; 455 } 456 457 static void stmmac_ethtool_gregs(struct net_device *dev, 458 struct ethtool_regs *regs, void *space) 459 { 460 struct stmmac_priv *priv = netdev_priv(dev); 461 u32 *reg_space = (u32 *) space; 462 463 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 464 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 465 466 /* Copy DMA registers to where ethtool expects them */ 467 if (priv->plat->has_gmac4) { 468 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 469 memcpy(®_space[ETHTOOL_DMA_OFFSET], 470 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 471 NUM_DWMAC4_DMA_REGS * 4); 472 } else if (!priv->plat->has_xgmac) { 473 memcpy(®_space[ETHTOOL_DMA_OFFSET], 474 ®_space[DMA_BUS_MODE / 4], 475 NUM_DWMAC1000_DMA_REGS * 4); 476 } 477 } 478 479 static int stmmac_nway_reset(struct net_device *dev) 480 { 481 struct stmmac_priv *priv = netdev_priv(dev); 482 483 return phylink_ethtool_nway_reset(priv->phylink); 484 } 485 486 static void stmmac_get_ringparam(struct net_device *netdev, 487 struct ethtool_ringparam *ring, 488 struct kernel_ethtool_ringparam *kernel_ring, 489 struct netlink_ext_ack *extack) 490 { 491 struct stmmac_priv *priv = netdev_priv(netdev); 492 493 ring->rx_max_pending = DMA_MAX_RX_SIZE; 494 ring->tx_max_pending = DMA_MAX_TX_SIZE; 495 ring->rx_pending = priv->dma_conf.dma_rx_size; 496 ring->tx_pending = priv->dma_conf.dma_tx_size; 497 } 498 499 static int stmmac_set_ringparam(struct net_device *netdev, 500 struct ethtool_ringparam *ring, 501 struct kernel_ethtool_ringparam *kernel_ring, 502 struct netlink_ext_ack *extack) 503 { 504 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 505 ring->rx_pending < DMA_MIN_RX_SIZE || 506 ring->rx_pending > DMA_MAX_RX_SIZE || 507 !is_power_of_2(ring->rx_pending) || 508 ring->tx_pending < DMA_MIN_TX_SIZE || 509 ring->tx_pending > DMA_MAX_TX_SIZE || 510 !is_power_of_2(ring->tx_pending)) 511 return -EINVAL; 512 513 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 514 ring->tx_pending); 515 } 516 517 static void 518 stmmac_get_pauseparam(struct net_device *netdev, 519 struct ethtool_pauseparam *pause) 520 { 521 struct stmmac_priv *priv = netdev_priv(netdev); 522 struct rgmii_adv adv_lp; 523 524 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 525 pause->autoneg = 1; 526 if (!adv_lp.pause) 527 return; 528 } else { 529 phylink_ethtool_get_pauseparam(priv->phylink, pause); 530 } 531 } 532 533 static int 534 stmmac_set_pauseparam(struct net_device *netdev, 535 struct ethtool_pauseparam *pause) 536 { 537 struct stmmac_priv *priv = netdev_priv(netdev); 538 struct rgmii_adv adv_lp; 539 540 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 541 pause->autoneg = 1; 542 if (!adv_lp.pause) 543 return -EOPNOTSUPP; 544 return 0; 545 } else { 546 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 547 } 548 } 549 550 static u64 stmmac_get_rx_normal_irq_n(struct stmmac_priv *priv, int q) 551 { 552 u64 total; 553 int cpu; 554 555 total = 0; 556 for_each_possible_cpu(cpu) { 557 struct stmmac_pcpu_stats *pcpu; 558 unsigned int start; 559 u64 irq_n; 560 561 pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu); 562 do { 563 start = u64_stats_fetch_begin(&pcpu->syncp); 564 irq_n = u64_stats_read(&pcpu->rx_normal_irq_n[q]); 565 } while (u64_stats_fetch_retry(&pcpu->syncp, start)); 566 total += irq_n; 567 } 568 return total; 569 } 570 571 static u64 stmmac_get_tx_normal_irq_n(struct stmmac_priv *priv, int q) 572 { 573 u64 total; 574 int cpu; 575 576 total = 0; 577 for_each_possible_cpu(cpu) { 578 struct stmmac_pcpu_stats *pcpu; 579 unsigned int start; 580 u64 irq_n; 581 582 pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu); 583 do { 584 start = u64_stats_fetch_begin(&pcpu->syncp); 585 irq_n = u64_stats_read(&pcpu->tx_normal_irq_n[q]); 586 } while (u64_stats_fetch_retry(&pcpu->syncp, start)); 587 total += irq_n; 588 } 589 return total; 590 } 591 592 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 593 { 594 u32 tx_cnt = priv->plat->tx_queues_to_use; 595 u32 rx_cnt = priv->plat->rx_queues_to_use; 596 unsigned int start; 597 int q; 598 599 for (q = 0; q < tx_cnt; q++) { 600 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q]; 601 u64 pkt_n; 602 603 do { 604 start = u64_stats_fetch_begin(&txq_stats->napi_syncp); 605 pkt_n = u64_stats_read(&txq_stats->napi.tx_pkt_n); 606 } while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start)); 607 608 *data++ = pkt_n; 609 *data++ = stmmac_get_tx_normal_irq_n(priv, q); 610 } 611 612 for (q = 0; q < rx_cnt; q++) { 613 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q]; 614 u64 pkt_n; 615 616 do { 617 start = u64_stats_fetch_begin(&rxq_stats->napi_syncp); 618 pkt_n = u64_stats_read(&rxq_stats->napi.rx_pkt_n); 619 } while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start)); 620 621 *data++ = pkt_n; 622 *data++ = stmmac_get_rx_normal_irq_n(priv, q); 623 } 624 } 625 626 static void stmmac_get_ethtool_stats(struct net_device *dev, 627 struct ethtool_stats *dummy, u64 *data) 628 { 629 struct stmmac_priv *priv = netdev_priv(dev); 630 u32 rx_queues_count = priv->plat->rx_queues_to_use; 631 u32 tx_queues_count = priv->plat->tx_queues_to_use; 632 u64 napi_poll = 0, normal_irq_n = 0; 633 int i, j = 0, pos, ret; 634 unsigned long count; 635 unsigned int start; 636 637 if (priv->dma_cap.asp) { 638 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 639 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 640 &count, NULL)) 641 data[j++] = count; 642 } 643 } 644 645 /* Update the DMA HW counters for dwmac10/100 */ 646 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr); 647 if (ret) { 648 /* If supported, for new GMAC chips expose the MMC counters */ 649 if (priv->dma_cap.rmon) { 650 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 651 652 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 653 char *p; 654 p = (char *)priv + stmmac_mmc[i].stat_offset; 655 656 data[j++] = (stmmac_mmc[i].sizeof_stat == 657 sizeof(u64)) ? (*(u64 *)p) : 658 (*(u32 *)p); 659 } 660 } 661 if (priv->eee_enabled) { 662 int val = phylink_get_eee_err(priv->phylink); 663 if (val) 664 priv->xstats.phy_eee_wakeup_error_n = val; 665 } 666 667 if (priv->synopsys_id >= DWMAC_CORE_3_50) 668 stmmac_mac_debug(priv, priv->ioaddr, 669 (void *)&priv->xstats, 670 rx_queues_count, tx_queues_count); 671 } 672 for (i = 0; i < STMMAC_STATS_LEN; i++) { 673 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 674 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 675 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 676 } 677 678 pos = j; 679 for (i = 0; i < rx_queues_count; i++) { 680 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i]; 681 struct stmmac_napi_rx_stats snapshot; 682 u64 n_irq; 683 684 j = pos; 685 do { 686 start = u64_stats_fetch_begin(&rxq_stats->napi_syncp); 687 snapshot = rxq_stats->napi; 688 } while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start)); 689 690 data[j++] += u64_stats_read(&snapshot.rx_pkt_n); 691 n_irq = stmmac_get_rx_normal_irq_n(priv, i); 692 data[j++] += n_irq; 693 normal_irq_n += n_irq; 694 napi_poll += u64_stats_read(&snapshot.poll); 695 } 696 697 pos = j; 698 for (i = 0; i < tx_queues_count; i++) { 699 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i]; 700 struct stmmac_napi_tx_stats napi_snapshot; 701 struct stmmac_q_tx_stats q_snapshot; 702 u64 n_irq; 703 704 j = pos; 705 do { 706 start = u64_stats_fetch_begin(&txq_stats->q_syncp); 707 q_snapshot = txq_stats->q; 708 } while (u64_stats_fetch_retry(&txq_stats->q_syncp, start)); 709 do { 710 start = u64_stats_fetch_begin(&txq_stats->napi_syncp); 711 napi_snapshot = txq_stats->napi; 712 } while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start)); 713 714 data[j++] += u64_stats_read(&napi_snapshot.tx_pkt_n); 715 n_irq = stmmac_get_tx_normal_irq_n(priv, i); 716 data[j++] += n_irq; 717 normal_irq_n += n_irq; 718 data[j++] += u64_stats_read(&napi_snapshot.tx_clean); 719 data[j++] += u64_stats_read(&q_snapshot.tx_set_ic_bit) + 720 u64_stats_read(&napi_snapshot.tx_set_ic_bit); 721 data[j++] += u64_stats_read(&q_snapshot.tx_tso_frames); 722 data[j++] += u64_stats_read(&q_snapshot.tx_tso_nfrags); 723 napi_poll += u64_stats_read(&napi_snapshot.poll); 724 } 725 normal_irq_n += priv->xstats.rx_early_irq; 726 data[j++] = normal_irq_n; 727 data[j++] = napi_poll; 728 729 stmmac_get_per_qstats(priv, &data[j]); 730 } 731 732 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 733 { 734 struct stmmac_priv *priv = netdev_priv(netdev); 735 u32 tx_cnt = priv->plat->tx_queues_to_use; 736 u32 rx_cnt = priv->plat->rx_queues_to_use; 737 int i, len, safety_len = 0; 738 739 switch (sset) { 740 case ETH_SS_STATS: 741 len = STMMAC_STATS_LEN + STMMAC_QSTATS + 742 STMMAC_TXQ_STATS * tx_cnt + 743 STMMAC_RXQ_STATS * rx_cnt; 744 745 if (priv->dma_cap.rmon) 746 len += STMMAC_MMC_STATS_LEN; 747 if (priv->dma_cap.asp) { 748 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 749 if (!stmmac_safety_feat_dump(priv, 750 &priv->sstats, i, 751 NULL, NULL)) 752 safety_len++; 753 } 754 755 len += safety_len; 756 } 757 758 return len; 759 case ETH_SS_TEST: 760 return stmmac_selftest_get_count(priv); 761 default: 762 return -EOPNOTSUPP; 763 } 764 } 765 766 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 767 { 768 u32 tx_cnt = priv->plat->tx_queues_to_use; 769 u32 rx_cnt = priv->plat->rx_queues_to_use; 770 int q, stat; 771 772 for (q = 0; q < tx_cnt; q++) { 773 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 774 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 775 stmmac_qstats_tx_string[stat]); 776 data += ETH_GSTRING_LEN; 777 } 778 } 779 for (q = 0; q < rx_cnt; q++) { 780 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 781 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 782 stmmac_qstats_rx_string[stat]); 783 data += ETH_GSTRING_LEN; 784 } 785 } 786 } 787 788 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 789 { 790 int i; 791 u8 *p = data; 792 struct stmmac_priv *priv = netdev_priv(dev); 793 794 switch (stringset) { 795 case ETH_SS_STATS: 796 if (priv->dma_cap.asp) { 797 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 798 const char *desc; 799 if (!stmmac_safety_feat_dump(priv, 800 &priv->sstats, i, 801 NULL, &desc)) { 802 memcpy(p, desc, ETH_GSTRING_LEN); 803 p += ETH_GSTRING_LEN; 804 } 805 } 806 } 807 if (priv->dma_cap.rmon) 808 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 809 memcpy(p, stmmac_mmc[i].stat_string, 810 ETH_GSTRING_LEN); 811 p += ETH_GSTRING_LEN; 812 } 813 for (i = 0; i < STMMAC_STATS_LEN; i++) { 814 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN); 815 p += ETH_GSTRING_LEN; 816 } 817 for (i = 0; i < STMMAC_QSTATS; i++) { 818 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN); 819 p += ETH_GSTRING_LEN; 820 } 821 stmmac_get_qstats_string(priv, p); 822 break; 823 case ETH_SS_TEST: 824 stmmac_selftest_get_strings(priv, p); 825 break; 826 default: 827 WARN_ON(1); 828 break; 829 } 830 } 831 832 /* Currently only support WOL through Magic packet. */ 833 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 834 { 835 struct stmmac_priv *priv = netdev_priv(dev); 836 837 if (!priv->plat->pmt) 838 return phylink_ethtool_get_wol(priv->phylink, wol); 839 840 mutex_lock(&priv->lock); 841 if (device_can_wakeup(priv->device)) { 842 wol->supported = WAKE_MAGIC | WAKE_UCAST; 843 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 844 wol->supported &= ~WAKE_MAGIC; 845 wol->wolopts = priv->wolopts; 846 } 847 mutex_unlock(&priv->lock); 848 } 849 850 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 851 { 852 struct stmmac_priv *priv = netdev_priv(dev); 853 u32 support = WAKE_MAGIC | WAKE_UCAST; 854 855 if (!device_can_wakeup(priv->device)) 856 return -EOPNOTSUPP; 857 858 if (!priv->plat->pmt) { 859 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 860 861 if (!ret) 862 device_set_wakeup_enable(priv->device, !!wol->wolopts); 863 return ret; 864 } 865 866 /* By default almost all GMAC devices support the WoL via 867 * magic frame but we can disable it if the HW capability 868 * register shows no support for pmt_magic_frame. */ 869 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 870 wol->wolopts &= ~WAKE_MAGIC; 871 872 if (wol->wolopts & ~support) 873 return -EINVAL; 874 875 if (wol->wolopts) { 876 pr_info("stmmac: wakeup enable\n"); 877 device_set_wakeup_enable(priv->device, 1); 878 /* Avoid unbalanced enable_irq_wake calls */ 879 if (priv->wol_irq_disabled) 880 enable_irq_wake(priv->wol_irq); 881 priv->wol_irq_disabled = false; 882 } else { 883 device_set_wakeup_enable(priv->device, 0); 884 /* Avoid unbalanced disable_irq_wake calls */ 885 if (!priv->wol_irq_disabled) 886 disable_irq_wake(priv->wol_irq); 887 priv->wol_irq_disabled = true; 888 } 889 890 mutex_lock(&priv->lock); 891 priv->wolopts = wol->wolopts; 892 mutex_unlock(&priv->lock); 893 894 return 0; 895 } 896 897 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 898 struct ethtool_keee *edata) 899 { 900 struct stmmac_priv *priv = netdev_priv(dev); 901 902 if (!priv->dma_cap.eee) 903 return -EOPNOTSUPP; 904 905 edata->tx_lpi_timer = priv->tx_lpi_timer; 906 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 907 908 return phylink_ethtool_get_eee(priv->phylink, edata); 909 } 910 911 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 912 struct ethtool_keee *edata) 913 { 914 struct stmmac_priv *priv = netdev_priv(dev); 915 int ret; 916 917 if (!priv->dma_cap.eee) 918 return -EOPNOTSUPP; 919 920 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 921 netdev_warn(priv->dev, 922 "Setting EEE tx-lpi is not supported\n"); 923 924 if (!edata->eee_enabled) 925 stmmac_disable_eee_mode(priv); 926 927 ret = phylink_ethtool_set_eee(priv->phylink, edata); 928 if (ret) 929 return ret; 930 931 if (edata->eee_enabled && 932 priv->tx_lpi_timer != edata->tx_lpi_timer) { 933 priv->tx_lpi_timer = edata->tx_lpi_timer; 934 stmmac_eee_init(priv); 935 } 936 937 return 0; 938 } 939 940 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 941 { 942 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 943 944 if (!clk) { 945 clk = priv->plat->clk_ref_rate; 946 if (!clk) 947 return 0; 948 } 949 950 return (usec * (clk / 1000000)) / 256; 951 } 952 953 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 954 { 955 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 956 957 if (!clk) { 958 clk = priv->plat->clk_ref_rate; 959 if (!clk) 960 return 0; 961 } 962 963 return (riwt * 256) / (clk / 1000000); 964 } 965 966 static int __stmmac_get_coalesce(struct net_device *dev, 967 struct ethtool_coalesce *ec, 968 int queue) 969 { 970 struct stmmac_priv *priv = netdev_priv(dev); 971 u32 max_cnt; 972 u32 rx_cnt; 973 u32 tx_cnt; 974 975 rx_cnt = priv->plat->rx_queues_to_use; 976 tx_cnt = priv->plat->tx_queues_to_use; 977 max_cnt = max(rx_cnt, tx_cnt); 978 979 if (queue < 0) 980 queue = 0; 981 else if (queue >= max_cnt) 982 return -EINVAL; 983 984 if (queue < tx_cnt) { 985 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 986 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 987 } else { 988 ec->tx_coalesce_usecs = 0; 989 ec->tx_max_coalesced_frames = 0; 990 } 991 992 if (priv->use_riwt && queue < rx_cnt) { 993 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 994 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 995 priv); 996 } else { 997 ec->rx_max_coalesced_frames = 0; 998 ec->rx_coalesce_usecs = 0; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int stmmac_get_coalesce(struct net_device *dev, 1005 struct ethtool_coalesce *ec, 1006 struct kernel_ethtool_coalesce *kernel_coal, 1007 struct netlink_ext_ack *extack) 1008 { 1009 return __stmmac_get_coalesce(dev, ec, -1); 1010 } 1011 1012 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 1013 struct ethtool_coalesce *ec) 1014 { 1015 return __stmmac_get_coalesce(dev, ec, queue); 1016 } 1017 1018 static int __stmmac_set_coalesce(struct net_device *dev, 1019 struct ethtool_coalesce *ec, 1020 int queue) 1021 { 1022 struct stmmac_priv *priv = netdev_priv(dev); 1023 bool all_queues = false; 1024 unsigned int rx_riwt; 1025 u32 max_cnt; 1026 u32 rx_cnt; 1027 u32 tx_cnt; 1028 1029 rx_cnt = priv->plat->rx_queues_to_use; 1030 tx_cnt = priv->plat->tx_queues_to_use; 1031 max_cnt = max(rx_cnt, tx_cnt); 1032 1033 if (queue < 0) 1034 all_queues = true; 1035 else if (queue >= max_cnt) 1036 return -EINVAL; 1037 1038 if (priv->use_riwt) { 1039 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 1040 1041 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 1042 return -EINVAL; 1043 1044 if (all_queues) { 1045 int i; 1046 1047 for (i = 0; i < rx_cnt; i++) { 1048 priv->rx_riwt[i] = rx_riwt; 1049 stmmac_rx_watchdog(priv, priv->ioaddr, 1050 rx_riwt, i); 1051 priv->rx_coal_frames[i] = 1052 ec->rx_max_coalesced_frames; 1053 } 1054 } else if (queue < rx_cnt) { 1055 priv->rx_riwt[queue] = rx_riwt; 1056 stmmac_rx_watchdog(priv, priv->ioaddr, 1057 rx_riwt, queue); 1058 priv->rx_coal_frames[queue] = 1059 ec->rx_max_coalesced_frames; 1060 } 1061 } 1062 1063 if ((ec->tx_coalesce_usecs == 0) && 1064 (ec->tx_max_coalesced_frames == 0)) 1065 return -EINVAL; 1066 1067 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 1068 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 1069 return -EINVAL; 1070 1071 if (all_queues) { 1072 int i; 1073 1074 for (i = 0; i < tx_cnt; i++) { 1075 priv->tx_coal_frames[i] = 1076 ec->tx_max_coalesced_frames; 1077 priv->tx_coal_timer[i] = 1078 ec->tx_coalesce_usecs; 1079 } 1080 } else if (queue < tx_cnt) { 1081 priv->tx_coal_frames[queue] = 1082 ec->tx_max_coalesced_frames; 1083 priv->tx_coal_timer[queue] = 1084 ec->tx_coalesce_usecs; 1085 } 1086 1087 return 0; 1088 } 1089 1090 static int stmmac_set_coalesce(struct net_device *dev, 1091 struct ethtool_coalesce *ec, 1092 struct kernel_ethtool_coalesce *kernel_coal, 1093 struct netlink_ext_ack *extack) 1094 { 1095 return __stmmac_set_coalesce(dev, ec, -1); 1096 } 1097 1098 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1099 struct ethtool_coalesce *ec) 1100 { 1101 return __stmmac_set_coalesce(dev, ec, queue); 1102 } 1103 1104 static int stmmac_get_rxnfc(struct net_device *dev, 1105 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1106 { 1107 struct stmmac_priv *priv = netdev_priv(dev); 1108 1109 switch (rxnfc->cmd) { 1110 case ETHTOOL_GRXRINGS: 1111 rxnfc->data = priv->plat->rx_queues_to_use; 1112 break; 1113 default: 1114 return -EOPNOTSUPP; 1115 } 1116 1117 return 0; 1118 } 1119 1120 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 1121 { 1122 struct stmmac_priv *priv = netdev_priv(dev); 1123 1124 return sizeof(priv->rss.key); 1125 } 1126 1127 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1128 { 1129 struct stmmac_priv *priv = netdev_priv(dev); 1130 1131 return ARRAY_SIZE(priv->rss.table); 1132 } 1133 1134 static int stmmac_get_rxfh(struct net_device *dev, 1135 struct ethtool_rxfh_param *rxfh) 1136 { 1137 struct stmmac_priv *priv = netdev_priv(dev); 1138 int i; 1139 1140 if (rxfh->indir) { 1141 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1142 rxfh->indir[i] = priv->rss.table[i]; 1143 } 1144 1145 if (rxfh->key) 1146 memcpy(rxfh->key, priv->rss.key, sizeof(priv->rss.key)); 1147 rxfh->hfunc = ETH_RSS_HASH_TOP; 1148 1149 return 0; 1150 } 1151 1152 static int stmmac_set_rxfh(struct net_device *dev, 1153 struct ethtool_rxfh_param *rxfh, 1154 struct netlink_ext_ack *extack) 1155 { 1156 struct stmmac_priv *priv = netdev_priv(dev); 1157 int i; 1158 1159 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 1160 rxfh->hfunc != ETH_RSS_HASH_TOP) 1161 return -EOPNOTSUPP; 1162 1163 if (rxfh->indir) { 1164 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1165 priv->rss.table[i] = rxfh->indir[i]; 1166 } 1167 1168 if (rxfh->key) 1169 memcpy(priv->rss.key, rxfh->key, sizeof(priv->rss.key)); 1170 1171 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1172 priv->plat->rx_queues_to_use); 1173 } 1174 1175 static void stmmac_get_channels(struct net_device *dev, 1176 struct ethtool_channels *chan) 1177 { 1178 struct stmmac_priv *priv = netdev_priv(dev); 1179 1180 chan->rx_count = priv->plat->rx_queues_to_use; 1181 chan->tx_count = priv->plat->tx_queues_to_use; 1182 chan->max_rx = priv->dma_cap.number_rx_queues; 1183 chan->max_tx = priv->dma_cap.number_tx_queues; 1184 } 1185 1186 static int stmmac_set_channels(struct net_device *dev, 1187 struct ethtool_channels *chan) 1188 { 1189 struct stmmac_priv *priv = netdev_priv(dev); 1190 1191 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1192 chan->tx_count > priv->dma_cap.number_tx_queues || 1193 !chan->rx_count || !chan->tx_count) 1194 return -EINVAL; 1195 1196 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1197 } 1198 1199 static int stmmac_get_ts_info(struct net_device *dev, 1200 struct ethtool_ts_info *info) 1201 { 1202 struct stmmac_priv *priv = netdev_priv(dev); 1203 1204 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1205 1206 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1207 SOF_TIMESTAMPING_TX_HARDWARE | 1208 SOF_TIMESTAMPING_RX_SOFTWARE | 1209 SOF_TIMESTAMPING_RX_HARDWARE | 1210 SOF_TIMESTAMPING_SOFTWARE | 1211 SOF_TIMESTAMPING_RAW_HARDWARE; 1212 1213 if (priv->ptp_clock) 1214 info->phc_index = ptp_clock_index(priv->ptp_clock); 1215 1216 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1217 1218 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1219 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1220 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1221 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1222 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1223 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1224 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1225 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1226 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1227 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1228 (1 << HWTSTAMP_FILTER_ALL)); 1229 return 0; 1230 } else 1231 return ethtool_op_get_ts_info(dev, info); 1232 } 1233 1234 static int stmmac_get_tunable(struct net_device *dev, 1235 const struct ethtool_tunable *tuna, void *data) 1236 { 1237 struct stmmac_priv *priv = netdev_priv(dev); 1238 int ret = 0; 1239 1240 switch (tuna->id) { 1241 case ETHTOOL_RX_COPYBREAK: 1242 *(u32 *)data = priv->rx_copybreak; 1243 break; 1244 default: 1245 ret = -EINVAL; 1246 break; 1247 } 1248 1249 return ret; 1250 } 1251 1252 static int stmmac_set_tunable(struct net_device *dev, 1253 const struct ethtool_tunable *tuna, 1254 const void *data) 1255 { 1256 struct stmmac_priv *priv = netdev_priv(dev); 1257 int ret = 0; 1258 1259 switch (tuna->id) { 1260 case ETHTOOL_RX_COPYBREAK: 1261 priv->rx_copybreak = *(u32 *)data; 1262 break; 1263 default: 1264 ret = -EINVAL; 1265 break; 1266 } 1267 1268 return ret; 1269 } 1270 1271 static const struct ethtool_ops stmmac_ethtool_ops = { 1272 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1273 ETHTOOL_COALESCE_MAX_FRAMES, 1274 .begin = stmmac_check_if_running, 1275 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1276 .get_msglevel = stmmac_ethtool_getmsglevel, 1277 .set_msglevel = stmmac_ethtool_setmsglevel, 1278 .get_regs = stmmac_ethtool_gregs, 1279 .get_regs_len = stmmac_ethtool_get_regs_len, 1280 .get_link = ethtool_op_get_link, 1281 .nway_reset = stmmac_nway_reset, 1282 .get_ringparam = stmmac_get_ringparam, 1283 .set_ringparam = stmmac_set_ringparam, 1284 .get_pauseparam = stmmac_get_pauseparam, 1285 .set_pauseparam = stmmac_set_pauseparam, 1286 .self_test = stmmac_selftest_run, 1287 .get_ethtool_stats = stmmac_get_ethtool_stats, 1288 .get_strings = stmmac_get_strings, 1289 .get_wol = stmmac_get_wol, 1290 .set_wol = stmmac_set_wol, 1291 .get_eee = stmmac_ethtool_op_get_eee, 1292 .set_eee = stmmac_ethtool_op_set_eee, 1293 .get_sset_count = stmmac_get_sset_count, 1294 .get_rxnfc = stmmac_get_rxnfc, 1295 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1296 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1297 .get_rxfh = stmmac_get_rxfh, 1298 .set_rxfh = stmmac_set_rxfh, 1299 .get_ts_info = stmmac_get_ts_info, 1300 .get_coalesce = stmmac_get_coalesce, 1301 .set_coalesce = stmmac_set_coalesce, 1302 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1303 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1304 .get_channels = stmmac_get_channels, 1305 .set_channels = stmmac_set_channels, 1306 .get_tunable = stmmac_get_tunable, 1307 .set_tunable = stmmac_set_tunable, 1308 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1309 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1310 }; 1311 1312 void stmmac_set_ethtool_ops(struct net_device *netdev) 1313 { 1314 netdev->ethtool_ops = &stmmac_ethtool_ops; 1315 } 1316