1 /******************************************************************************* 2 STMMAC Ethtool support 3 4 Copyright (C) 2007-2009 STMicroelectronics Ltd 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 The full GNU General Public License is included in this distribution in 16 the file called "COPYING". 17 18 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 19 *******************************************************************************/ 20 21 #include <linux/etherdevice.h> 22 #include <linux/ethtool.h> 23 #include <linux/interrupt.h> 24 #include <linux/mii.h> 25 #include <linux/phylink.h> 26 #include <linux/net_tstamp.h> 27 #include <asm/io.h> 28 29 #include "stmmac.h" 30 #include "dwmac_dma.h" 31 32 #define REG_SPACE_SIZE 0x1060 33 #define MAC100_ETHTOOL_NAME "st_mac100" 34 #define GMAC_ETHTOOL_NAME "st_gmac" 35 36 #define ETHTOOL_DMA_OFFSET 55 37 38 struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42 }; 43 44 #define STMMAC_STAT(m) \ 45 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48 static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 /* Tx/Rx IRQ error info */ 79 STMMAC_STAT(tx_undeflow_irq), 80 STMMAC_STAT(tx_process_stopped_irq), 81 STMMAC_STAT(tx_jabber_irq), 82 STMMAC_STAT(rx_overflow_irq), 83 STMMAC_STAT(rx_buf_unav_irq), 84 STMMAC_STAT(rx_process_stopped_irq), 85 STMMAC_STAT(rx_watchdog_irq), 86 STMMAC_STAT(tx_early_irq), 87 STMMAC_STAT(fatal_bus_error_irq), 88 /* Tx/Rx IRQ Events */ 89 STMMAC_STAT(rx_early_irq), 90 STMMAC_STAT(threshold), 91 STMMAC_STAT(tx_pkt_n), 92 STMMAC_STAT(rx_pkt_n), 93 STMMAC_STAT(normal_irq_n), 94 STMMAC_STAT(rx_normal_irq_n), 95 STMMAC_STAT(napi_poll), 96 STMMAC_STAT(tx_normal_irq_n), 97 STMMAC_STAT(tx_clean), 98 STMMAC_STAT(tx_set_ic_bit), 99 STMMAC_STAT(irq_receive_pmt_irq_n), 100 /* MMC info */ 101 STMMAC_STAT(mmc_tx_irq_n), 102 STMMAC_STAT(mmc_rx_irq_n), 103 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 104 /* EEE */ 105 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 106 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 107 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 108 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 109 STMMAC_STAT(phy_eee_wakeup_error_n), 110 /* Extended RDES status */ 111 STMMAC_STAT(ip_hdr_err), 112 STMMAC_STAT(ip_payload_err), 113 STMMAC_STAT(ip_csum_bypassed), 114 STMMAC_STAT(ipv4_pkt_rcvd), 115 STMMAC_STAT(ipv6_pkt_rcvd), 116 STMMAC_STAT(no_ptp_rx_msg_type_ext), 117 STMMAC_STAT(ptp_rx_msg_type_sync), 118 STMMAC_STAT(ptp_rx_msg_type_follow_up), 119 STMMAC_STAT(ptp_rx_msg_type_delay_req), 120 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 121 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 122 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 123 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 124 STMMAC_STAT(ptp_rx_msg_type_announce), 125 STMMAC_STAT(ptp_rx_msg_type_management), 126 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 127 STMMAC_STAT(ptp_frame_type), 128 STMMAC_STAT(ptp_ver), 129 STMMAC_STAT(timestamp_dropped), 130 STMMAC_STAT(av_pkt_rcvd), 131 STMMAC_STAT(av_tagged_pkt_rcvd), 132 STMMAC_STAT(vlan_tag_priority_val), 133 STMMAC_STAT(l3_filter_match), 134 STMMAC_STAT(l4_filter_match), 135 STMMAC_STAT(l3_l4_filter_no_match), 136 /* PCS */ 137 STMMAC_STAT(irq_pcs_ane_n), 138 STMMAC_STAT(irq_pcs_link_n), 139 STMMAC_STAT(irq_rgmii_n), 140 /* DEBUG */ 141 STMMAC_STAT(mtl_tx_status_fifo_full), 142 STMMAC_STAT(mtl_tx_fifo_not_empty), 143 STMMAC_STAT(mmtl_fifo_ctrl), 144 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 147 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 148 STMMAC_STAT(mac_tx_in_pause), 149 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 150 STMMAC_STAT(mac_tx_frame_ctrl_idle), 151 STMMAC_STAT(mac_tx_frame_ctrl_wait), 152 STMMAC_STAT(mac_tx_frame_ctrl_pause), 153 STMMAC_STAT(mac_gmii_tx_proto_engine), 154 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 155 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 156 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 157 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 158 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 161 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 162 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 163 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 164 STMMAC_STAT(mac_gmii_rx_proto_engine), 165 /* TSO */ 166 STMMAC_STAT(tx_tso_frames), 167 STMMAC_STAT(tx_tso_nfrags), 168 }; 169 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 170 171 /* HW MAC Management counters (if supported) */ 172 #define STMMAC_MMC_STAT(m) \ 173 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \ 174 offsetof(struct stmmac_priv, mmc.m)} 175 176 static const struct stmmac_stats stmmac_mmc[] = { 177 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 178 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 179 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 180 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 181 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 182 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 183 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 184 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 185 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 186 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 187 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 188 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 189 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 190 STMMAC_MMC_STAT(mmc_tx_underflow_error), 191 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 192 STMMAC_MMC_STAT(mmc_tx_multicol_g), 193 STMMAC_MMC_STAT(mmc_tx_deferred), 194 STMMAC_MMC_STAT(mmc_tx_latecol), 195 STMMAC_MMC_STAT(mmc_tx_exesscol), 196 STMMAC_MMC_STAT(mmc_tx_carrier_error), 197 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 198 STMMAC_MMC_STAT(mmc_tx_framecount_g), 199 STMMAC_MMC_STAT(mmc_tx_excessdef), 200 STMMAC_MMC_STAT(mmc_tx_pause_frame), 201 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 202 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 203 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 204 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 205 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 206 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 207 STMMAC_MMC_STAT(mmc_rx_crc_error), 208 STMMAC_MMC_STAT(mmc_rx_align_error), 209 STMMAC_MMC_STAT(mmc_rx_run_error), 210 STMMAC_MMC_STAT(mmc_rx_jabber_error), 211 STMMAC_MMC_STAT(mmc_rx_undersize_g), 212 STMMAC_MMC_STAT(mmc_rx_oversize_g), 213 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 214 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 215 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 216 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 217 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 218 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 219 STMMAC_MMC_STAT(mmc_rx_unicast_g), 220 STMMAC_MMC_STAT(mmc_rx_length_error), 221 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 222 STMMAC_MMC_STAT(mmc_rx_pause_frames), 223 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 224 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 225 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 226 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 227 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 228 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 229 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 230 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 231 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 232 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 233 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 234 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 235 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 236 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 237 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 238 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 239 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 240 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 241 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 242 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 243 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 244 STMMAC_MMC_STAT(mmc_rx_udp_gd), 245 STMMAC_MMC_STAT(mmc_rx_udp_err), 246 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 247 STMMAC_MMC_STAT(mmc_rx_tcp_err), 248 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 249 STMMAC_MMC_STAT(mmc_rx_icmp_err), 250 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 251 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 252 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 253 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 254 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 255 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 256 }; 257 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 258 259 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 260 struct ethtool_drvinfo *info) 261 { 262 struct stmmac_priv *priv = netdev_priv(dev); 263 264 if (priv->plat->has_gmac || priv->plat->has_gmac4) 265 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 266 else 267 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 268 sizeof(info->driver)); 269 270 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 271 } 272 273 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 274 struct ethtool_link_ksettings *cmd) 275 { 276 struct stmmac_priv *priv = netdev_priv(dev); 277 278 if (priv->hw->pcs & STMMAC_PCS_RGMII || 279 priv->hw->pcs & STMMAC_PCS_SGMII) { 280 struct rgmii_adv adv; 281 u32 supported, advertising, lp_advertising; 282 283 if (!priv->xstats.pcs_link) { 284 cmd->base.speed = SPEED_UNKNOWN; 285 cmd->base.duplex = DUPLEX_UNKNOWN; 286 return 0; 287 } 288 cmd->base.duplex = priv->xstats.pcs_duplex; 289 290 cmd->base.speed = priv->xstats.pcs_speed; 291 292 /* Get and convert ADV/LP_ADV from the HW AN registers */ 293 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 294 return -EOPNOTSUPP; /* should never happen indeed */ 295 296 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 297 298 ethtool_convert_link_mode_to_legacy_u32( 299 &supported, cmd->link_modes.supported); 300 ethtool_convert_link_mode_to_legacy_u32( 301 &advertising, cmd->link_modes.advertising); 302 ethtool_convert_link_mode_to_legacy_u32( 303 &lp_advertising, cmd->link_modes.lp_advertising); 304 305 if (adv.pause & STMMAC_PCS_PAUSE) 306 advertising |= ADVERTISED_Pause; 307 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 308 advertising |= ADVERTISED_Asym_Pause; 309 if (adv.lp_pause & STMMAC_PCS_PAUSE) 310 lp_advertising |= ADVERTISED_Pause; 311 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 312 lp_advertising |= ADVERTISED_Asym_Pause; 313 314 /* Reg49[3] always set because ANE is always supported */ 315 cmd->base.autoneg = ADVERTISED_Autoneg; 316 supported |= SUPPORTED_Autoneg; 317 advertising |= ADVERTISED_Autoneg; 318 lp_advertising |= ADVERTISED_Autoneg; 319 320 if (adv.duplex) { 321 supported |= (SUPPORTED_1000baseT_Full | 322 SUPPORTED_100baseT_Full | 323 SUPPORTED_10baseT_Full); 324 advertising |= (ADVERTISED_1000baseT_Full | 325 ADVERTISED_100baseT_Full | 326 ADVERTISED_10baseT_Full); 327 } else { 328 supported |= (SUPPORTED_1000baseT_Half | 329 SUPPORTED_100baseT_Half | 330 SUPPORTED_10baseT_Half); 331 advertising |= (ADVERTISED_1000baseT_Half | 332 ADVERTISED_100baseT_Half | 333 ADVERTISED_10baseT_Half); 334 } 335 if (adv.lp_duplex) 336 lp_advertising |= (ADVERTISED_1000baseT_Full | 337 ADVERTISED_100baseT_Full | 338 ADVERTISED_10baseT_Full); 339 else 340 lp_advertising |= (ADVERTISED_1000baseT_Half | 341 ADVERTISED_100baseT_Half | 342 ADVERTISED_10baseT_Half); 343 cmd->base.port = PORT_OTHER; 344 345 ethtool_convert_legacy_u32_to_link_mode( 346 cmd->link_modes.supported, supported); 347 ethtool_convert_legacy_u32_to_link_mode( 348 cmd->link_modes.advertising, advertising); 349 ethtool_convert_legacy_u32_to_link_mode( 350 cmd->link_modes.lp_advertising, lp_advertising); 351 352 return 0; 353 } 354 355 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 356 } 357 358 static int 359 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 360 const struct ethtool_link_ksettings *cmd) 361 { 362 struct stmmac_priv *priv = netdev_priv(dev); 363 364 if (priv->hw->pcs & STMMAC_PCS_RGMII || 365 priv->hw->pcs & STMMAC_PCS_SGMII) { 366 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 367 368 /* Only support ANE */ 369 if (cmd->base.autoneg != AUTONEG_ENABLE) 370 return -EINVAL; 371 372 mask &= (ADVERTISED_1000baseT_Half | 373 ADVERTISED_1000baseT_Full | 374 ADVERTISED_100baseT_Half | 375 ADVERTISED_100baseT_Full | 376 ADVERTISED_10baseT_Half | 377 ADVERTISED_10baseT_Full); 378 379 mutex_lock(&priv->lock); 380 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 381 mutex_unlock(&priv->lock); 382 383 return 0; 384 } 385 386 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 387 } 388 389 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 390 { 391 struct stmmac_priv *priv = netdev_priv(dev); 392 return priv->msg_enable; 393 } 394 395 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 396 { 397 struct stmmac_priv *priv = netdev_priv(dev); 398 priv->msg_enable = level; 399 400 } 401 402 static int stmmac_check_if_running(struct net_device *dev) 403 { 404 if (!netif_running(dev)) 405 return -EBUSY; 406 return 0; 407 } 408 409 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 410 { 411 return REG_SPACE_SIZE; 412 } 413 414 static void stmmac_ethtool_gregs(struct net_device *dev, 415 struct ethtool_regs *regs, void *space) 416 { 417 u32 *reg_space = (u32 *) space; 418 419 struct stmmac_priv *priv = netdev_priv(dev); 420 421 memset(reg_space, 0x0, REG_SPACE_SIZE); 422 423 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 424 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 425 /* Copy DMA registers to where ethtool expects them */ 426 memcpy(®_space[ETHTOOL_DMA_OFFSET], ®_space[DMA_BUS_MODE / 4], 427 NUM_DWMAC1000_DMA_REGS * 4); 428 } 429 430 static int stmmac_nway_reset(struct net_device *dev) 431 { 432 struct stmmac_priv *priv = netdev_priv(dev); 433 434 return phylink_ethtool_nway_reset(priv->phylink); 435 } 436 437 static void 438 stmmac_get_pauseparam(struct net_device *netdev, 439 struct ethtool_pauseparam *pause) 440 { 441 struct stmmac_priv *priv = netdev_priv(netdev); 442 struct rgmii_adv adv_lp; 443 444 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 445 pause->autoneg = 1; 446 if (!adv_lp.pause) 447 return; 448 } else { 449 phylink_ethtool_get_pauseparam(priv->phylink, pause); 450 } 451 } 452 453 static int 454 stmmac_set_pauseparam(struct net_device *netdev, 455 struct ethtool_pauseparam *pause) 456 { 457 struct stmmac_priv *priv = netdev_priv(netdev); 458 struct rgmii_adv adv_lp; 459 460 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 461 pause->autoneg = 1; 462 if (!adv_lp.pause) 463 return -EOPNOTSUPP; 464 return 0; 465 } else { 466 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 467 } 468 } 469 470 static void stmmac_get_ethtool_stats(struct net_device *dev, 471 struct ethtool_stats *dummy, u64 *data) 472 { 473 struct stmmac_priv *priv = netdev_priv(dev); 474 u32 rx_queues_count = priv->plat->rx_queues_to_use; 475 u32 tx_queues_count = priv->plat->tx_queues_to_use; 476 unsigned long count; 477 int i, j = 0, ret; 478 479 if (priv->dma_cap.asp) { 480 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 481 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 482 &count, NULL)) 483 data[j++] = count; 484 } 485 } 486 487 /* Update the DMA HW counters for dwmac10/100 */ 488 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 489 priv->ioaddr); 490 if (ret) { 491 /* If supported, for new GMAC chips expose the MMC counters */ 492 if (priv->dma_cap.rmon) { 493 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 494 495 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 496 char *p; 497 p = (char *)priv + stmmac_mmc[i].stat_offset; 498 499 data[j++] = (stmmac_mmc[i].sizeof_stat == 500 sizeof(u64)) ? (*(u64 *)p) : 501 (*(u32 *)p); 502 } 503 } 504 if (priv->eee_enabled) { 505 int val = phylink_get_eee_err(priv->phylink); 506 if (val) 507 priv->xstats.phy_eee_wakeup_error_n = val; 508 } 509 510 if (priv->synopsys_id >= DWMAC_CORE_3_50) 511 stmmac_mac_debug(priv, priv->ioaddr, 512 (void *)&priv->xstats, 513 rx_queues_count, tx_queues_count); 514 } 515 for (i = 0; i < STMMAC_STATS_LEN; i++) { 516 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 517 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 518 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 519 } 520 } 521 522 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 523 { 524 struct stmmac_priv *priv = netdev_priv(netdev); 525 int i, len, safety_len = 0; 526 527 switch (sset) { 528 case ETH_SS_STATS: 529 len = STMMAC_STATS_LEN; 530 531 if (priv->dma_cap.rmon) 532 len += STMMAC_MMC_STATS_LEN; 533 if (priv->dma_cap.asp) { 534 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 535 if (!stmmac_safety_feat_dump(priv, 536 &priv->sstats, i, 537 NULL, NULL)) 538 safety_len++; 539 } 540 541 len += safety_len; 542 } 543 544 return len; 545 case ETH_SS_TEST: 546 return stmmac_selftest_get_count(priv); 547 default: 548 return -EOPNOTSUPP; 549 } 550 } 551 552 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 553 { 554 int i; 555 u8 *p = data; 556 struct stmmac_priv *priv = netdev_priv(dev); 557 558 switch (stringset) { 559 case ETH_SS_STATS: 560 if (priv->dma_cap.asp) { 561 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 562 const char *desc; 563 if (!stmmac_safety_feat_dump(priv, 564 &priv->sstats, i, 565 NULL, &desc)) { 566 memcpy(p, desc, ETH_GSTRING_LEN); 567 p += ETH_GSTRING_LEN; 568 } 569 } 570 } 571 if (priv->dma_cap.rmon) 572 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 573 memcpy(p, stmmac_mmc[i].stat_string, 574 ETH_GSTRING_LEN); 575 p += ETH_GSTRING_LEN; 576 } 577 for (i = 0; i < STMMAC_STATS_LEN; i++) { 578 memcpy(p, stmmac_gstrings_stats[i].stat_string, 579 ETH_GSTRING_LEN); 580 p += ETH_GSTRING_LEN; 581 } 582 break; 583 case ETH_SS_TEST: 584 stmmac_selftest_get_strings(priv, p); 585 break; 586 default: 587 WARN_ON(1); 588 break; 589 } 590 } 591 592 /* Currently only support WOL through Magic packet. */ 593 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 594 { 595 struct stmmac_priv *priv = netdev_priv(dev); 596 597 mutex_lock(&priv->lock); 598 if (device_can_wakeup(priv->device)) { 599 wol->supported = WAKE_MAGIC | WAKE_UCAST; 600 wol->wolopts = priv->wolopts; 601 } 602 mutex_unlock(&priv->lock); 603 } 604 605 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 606 { 607 struct stmmac_priv *priv = netdev_priv(dev); 608 u32 support = WAKE_MAGIC | WAKE_UCAST; 609 610 /* By default almost all GMAC devices support the WoL via 611 * magic frame but we can disable it if the HW capability 612 * register shows no support for pmt_magic_frame. */ 613 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 614 wol->wolopts &= ~WAKE_MAGIC; 615 616 if (!device_can_wakeup(priv->device)) 617 return -EINVAL; 618 619 if (wol->wolopts & ~support) 620 return -EINVAL; 621 622 if (wol->wolopts) { 623 pr_info("stmmac: wakeup enable\n"); 624 device_set_wakeup_enable(priv->device, 1); 625 enable_irq_wake(priv->wol_irq); 626 } else { 627 device_set_wakeup_enable(priv->device, 0); 628 disable_irq_wake(priv->wol_irq); 629 } 630 631 mutex_lock(&priv->lock); 632 priv->wolopts = wol->wolopts; 633 mutex_unlock(&priv->lock); 634 635 return 0; 636 } 637 638 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 639 struct ethtool_eee *edata) 640 { 641 struct stmmac_priv *priv = netdev_priv(dev); 642 643 if (!priv->dma_cap.eee) 644 return -EOPNOTSUPP; 645 646 edata->eee_enabled = priv->eee_enabled; 647 edata->eee_active = priv->eee_active; 648 edata->tx_lpi_timer = priv->tx_lpi_timer; 649 650 return phylink_ethtool_get_eee(priv->phylink, edata); 651 } 652 653 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 654 struct ethtool_eee *edata) 655 { 656 struct stmmac_priv *priv = netdev_priv(dev); 657 int ret; 658 659 if (!edata->eee_enabled) { 660 stmmac_disable_eee_mode(priv); 661 } else { 662 /* We are asking for enabling the EEE but it is safe 663 * to verify all by invoking the eee_init function. 664 * In case of failure it will return an error. 665 */ 666 edata->eee_enabled = stmmac_eee_init(priv); 667 if (!edata->eee_enabled) 668 return -EOPNOTSUPP; 669 } 670 671 ret = phylink_ethtool_set_eee(priv->phylink, edata); 672 if (ret) 673 return ret; 674 675 priv->eee_enabled = edata->eee_enabled; 676 priv->tx_lpi_timer = edata->tx_lpi_timer; 677 return 0; 678 } 679 680 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 681 { 682 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 683 684 if (!clk) { 685 clk = priv->plat->clk_ref_rate; 686 if (!clk) 687 return 0; 688 } 689 690 return (usec * (clk / 1000000)) / 256; 691 } 692 693 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 694 { 695 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 696 697 if (!clk) { 698 clk = priv->plat->clk_ref_rate; 699 if (!clk) 700 return 0; 701 } 702 703 return (riwt * 256) / (clk / 1000000); 704 } 705 706 static int stmmac_get_coalesce(struct net_device *dev, 707 struct ethtool_coalesce *ec) 708 { 709 struct stmmac_priv *priv = netdev_priv(dev); 710 711 ec->tx_coalesce_usecs = priv->tx_coal_timer; 712 ec->tx_max_coalesced_frames = priv->tx_coal_frames; 713 714 if (priv->use_riwt) 715 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv); 716 717 return 0; 718 } 719 720 static int stmmac_set_coalesce(struct net_device *dev, 721 struct ethtool_coalesce *ec) 722 { 723 struct stmmac_priv *priv = netdev_priv(dev); 724 u32 rx_cnt = priv->plat->rx_queues_to_use; 725 unsigned int rx_riwt; 726 727 /* Check not supported parameters */ 728 if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) || 729 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) || 730 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) || 731 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) || 732 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) || 733 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) || 734 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) || 735 (ec->rx_max_coalesced_frames_high) || 736 (ec->tx_max_coalesced_frames_irq) || 737 (ec->stats_block_coalesce_usecs) || 738 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval)) 739 return -EOPNOTSUPP; 740 741 if (ec->rx_coalesce_usecs == 0) 742 return -EINVAL; 743 744 if ((ec->tx_coalesce_usecs == 0) && 745 (ec->tx_max_coalesced_frames == 0)) 746 return -EINVAL; 747 748 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 749 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 750 return -EINVAL; 751 752 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 753 754 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 755 return -EINVAL; 756 else if (!priv->use_riwt) 757 return -EOPNOTSUPP; 758 759 /* Only copy relevant parameters, ignore all others. */ 760 priv->tx_coal_frames = ec->tx_max_coalesced_frames; 761 priv->tx_coal_timer = ec->tx_coalesce_usecs; 762 priv->rx_riwt = rx_riwt; 763 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 764 765 return 0; 766 } 767 768 static int stmmac_get_ts_info(struct net_device *dev, 769 struct ethtool_ts_info *info) 770 { 771 struct stmmac_priv *priv = netdev_priv(dev); 772 773 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 774 775 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 776 SOF_TIMESTAMPING_TX_HARDWARE | 777 SOF_TIMESTAMPING_RX_SOFTWARE | 778 SOF_TIMESTAMPING_RX_HARDWARE | 779 SOF_TIMESTAMPING_SOFTWARE | 780 SOF_TIMESTAMPING_RAW_HARDWARE; 781 782 if (priv->ptp_clock) 783 info->phc_index = ptp_clock_index(priv->ptp_clock); 784 785 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 786 787 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 788 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 789 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 790 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 791 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 792 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 793 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 794 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 795 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 796 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 797 (1 << HWTSTAMP_FILTER_ALL)); 798 return 0; 799 } else 800 return ethtool_op_get_ts_info(dev, info); 801 } 802 803 static int stmmac_get_tunable(struct net_device *dev, 804 const struct ethtool_tunable *tuna, void *data) 805 { 806 struct stmmac_priv *priv = netdev_priv(dev); 807 int ret = 0; 808 809 switch (tuna->id) { 810 case ETHTOOL_RX_COPYBREAK: 811 *(u32 *)data = priv->rx_copybreak; 812 break; 813 default: 814 ret = -EINVAL; 815 break; 816 } 817 818 return ret; 819 } 820 821 static int stmmac_set_tunable(struct net_device *dev, 822 const struct ethtool_tunable *tuna, 823 const void *data) 824 { 825 struct stmmac_priv *priv = netdev_priv(dev); 826 int ret = 0; 827 828 switch (tuna->id) { 829 case ETHTOOL_RX_COPYBREAK: 830 priv->rx_copybreak = *(u32 *)data; 831 break; 832 default: 833 ret = -EINVAL; 834 break; 835 } 836 837 return ret; 838 } 839 840 static const struct ethtool_ops stmmac_ethtool_ops = { 841 .begin = stmmac_check_if_running, 842 .get_drvinfo = stmmac_ethtool_getdrvinfo, 843 .get_msglevel = stmmac_ethtool_getmsglevel, 844 .set_msglevel = stmmac_ethtool_setmsglevel, 845 .get_regs = stmmac_ethtool_gregs, 846 .get_regs_len = stmmac_ethtool_get_regs_len, 847 .get_link = ethtool_op_get_link, 848 .nway_reset = stmmac_nway_reset, 849 .get_pauseparam = stmmac_get_pauseparam, 850 .set_pauseparam = stmmac_set_pauseparam, 851 .self_test = stmmac_selftest_run, 852 .get_ethtool_stats = stmmac_get_ethtool_stats, 853 .get_strings = stmmac_get_strings, 854 .get_wol = stmmac_get_wol, 855 .set_wol = stmmac_set_wol, 856 .get_eee = stmmac_ethtool_op_get_eee, 857 .set_eee = stmmac_ethtool_op_set_eee, 858 .get_sset_count = stmmac_get_sset_count, 859 .get_ts_info = stmmac_get_ts_info, 860 .get_coalesce = stmmac_get_coalesce, 861 .set_coalesce = stmmac_set_coalesce, 862 .get_tunable = stmmac_get_tunable, 863 .set_tunable = stmmac_set_tunable, 864 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 865 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 866 }; 867 868 void stmmac_set_ethtool_ops(struct net_device *netdev) 869 { 870 netdev->ethtool_ops = &stmmac_ethtool_ops; 871 } 872