1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 22 #define REG_SPACE_SIZE 0x1060 23 #define MAC100_ETHTOOL_NAME "st_mac100" 24 #define GMAC_ETHTOOL_NAME "st_gmac" 25 26 #define ETHTOOL_DMA_OFFSET 55 27 28 struct stmmac_stats { 29 char stat_string[ETH_GSTRING_LEN]; 30 int sizeof_stat; 31 int stat_offset; 32 }; 33 34 #define STMMAC_STAT(m) \ 35 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \ 36 offsetof(struct stmmac_priv, xstats.m)} 37 38 static const struct stmmac_stats stmmac_gstrings_stats[] = { 39 /* Transmit errors */ 40 STMMAC_STAT(tx_underflow), 41 STMMAC_STAT(tx_carrier), 42 STMMAC_STAT(tx_losscarrier), 43 STMMAC_STAT(vlan_tag), 44 STMMAC_STAT(tx_deferred), 45 STMMAC_STAT(tx_vlan), 46 STMMAC_STAT(tx_jabber), 47 STMMAC_STAT(tx_frame_flushed), 48 STMMAC_STAT(tx_payload_error), 49 STMMAC_STAT(tx_ip_header_error), 50 /* Receive errors */ 51 STMMAC_STAT(rx_desc), 52 STMMAC_STAT(sa_filter_fail), 53 STMMAC_STAT(overflow_error), 54 STMMAC_STAT(ipc_csum_error), 55 STMMAC_STAT(rx_collision), 56 STMMAC_STAT(rx_crc_errors), 57 STMMAC_STAT(dribbling_bit), 58 STMMAC_STAT(rx_length), 59 STMMAC_STAT(rx_mii), 60 STMMAC_STAT(rx_multicast), 61 STMMAC_STAT(rx_gmac_overflow), 62 STMMAC_STAT(rx_watchdog), 63 STMMAC_STAT(da_rx_filter_fail), 64 STMMAC_STAT(sa_rx_filter_fail), 65 STMMAC_STAT(rx_missed_cntr), 66 STMMAC_STAT(rx_overflow_cntr), 67 STMMAC_STAT(rx_vlan), 68 /* Tx/Rx IRQ error info */ 69 STMMAC_STAT(tx_undeflow_irq), 70 STMMAC_STAT(tx_process_stopped_irq), 71 STMMAC_STAT(tx_jabber_irq), 72 STMMAC_STAT(rx_overflow_irq), 73 STMMAC_STAT(rx_buf_unav_irq), 74 STMMAC_STAT(rx_process_stopped_irq), 75 STMMAC_STAT(rx_watchdog_irq), 76 STMMAC_STAT(tx_early_irq), 77 STMMAC_STAT(fatal_bus_error_irq), 78 /* Tx/Rx IRQ Events */ 79 STMMAC_STAT(rx_early_irq), 80 STMMAC_STAT(threshold), 81 STMMAC_STAT(tx_pkt_n), 82 STMMAC_STAT(rx_pkt_n), 83 STMMAC_STAT(normal_irq_n), 84 STMMAC_STAT(rx_normal_irq_n), 85 STMMAC_STAT(napi_poll), 86 STMMAC_STAT(tx_normal_irq_n), 87 STMMAC_STAT(tx_clean), 88 STMMAC_STAT(tx_set_ic_bit), 89 STMMAC_STAT(irq_receive_pmt_irq_n), 90 /* MMC info */ 91 STMMAC_STAT(mmc_tx_irq_n), 92 STMMAC_STAT(mmc_rx_irq_n), 93 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 94 /* EEE */ 95 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 96 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 97 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 98 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 99 STMMAC_STAT(phy_eee_wakeup_error_n), 100 /* Extended RDES status */ 101 STMMAC_STAT(ip_hdr_err), 102 STMMAC_STAT(ip_payload_err), 103 STMMAC_STAT(ip_csum_bypassed), 104 STMMAC_STAT(ipv4_pkt_rcvd), 105 STMMAC_STAT(ipv6_pkt_rcvd), 106 STMMAC_STAT(no_ptp_rx_msg_type_ext), 107 STMMAC_STAT(ptp_rx_msg_type_sync), 108 STMMAC_STAT(ptp_rx_msg_type_follow_up), 109 STMMAC_STAT(ptp_rx_msg_type_delay_req), 110 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 111 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 112 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 113 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 114 STMMAC_STAT(ptp_rx_msg_type_announce), 115 STMMAC_STAT(ptp_rx_msg_type_management), 116 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 117 STMMAC_STAT(ptp_frame_type), 118 STMMAC_STAT(ptp_ver), 119 STMMAC_STAT(timestamp_dropped), 120 STMMAC_STAT(av_pkt_rcvd), 121 STMMAC_STAT(av_tagged_pkt_rcvd), 122 STMMAC_STAT(vlan_tag_priority_val), 123 STMMAC_STAT(l3_filter_match), 124 STMMAC_STAT(l4_filter_match), 125 STMMAC_STAT(l3_l4_filter_no_match), 126 /* PCS */ 127 STMMAC_STAT(irq_pcs_ane_n), 128 STMMAC_STAT(irq_pcs_link_n), 129 STMMAC_STAT(irq_rgmii_n), 130 /* DEBUG */ 131 STMMAC_STAT(mtl_tx_status_fifo_full), 132 STMMAC_STAT(mtl_tx_fifo_not_empty), 133 STMMAC_STAT(mmtl_fifo_ctrl), 134 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 135 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 136 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 138 STMMAC_STAT(mac_tx_in_pause), 139 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 140 STMMAC_STAT(mac_tx_frame_ctrl_idle), 141 STMMAC_STAT(mac_tx_frame_ctrl_wait), 142 STMMAC_STAT(mac_tx_frame_ctrl_pause), 143 STMMAC_STAT(mac_gmii_tx_proto_engine), 144 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 145 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 146 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 148 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 149 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 150 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 152 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 153 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 154 STMMAC_STAT(mac_gmii_rx_proto_engine), 155 /* TSO */ 156 STMMAC_STAT(tx_tso_frames), 157 STMMAC_STAT(tx_tso_nfrags), 158 }; 159 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 160 161 /* HW MAC Management counters (if supported) */ 162 #define STMMAC_MMC_STAT(m) \ 163 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \ 164 offsetof(struct stmmac_priv, mmc.m)} 165 166 static const struct stmmac_stats stmmac_mmc[] = { 167 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 168 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 169 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 170 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 171 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 172 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 173 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 174 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 175 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 176 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 177 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 178 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 179 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 180 STMMAC_MMC_STAT(mmc_tx_underflow_error), 181 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 182 STMMAC_MMC_STAT(mmc_tx_multicol_g), 183 STMMAC_MMC_STAT(mmc_tx_deferred), 184 STMMAC_MMC_STAT(mmc_tx_latecol), 185 STMMAC_MMC_STAT(mmc_tx_exesscol), 186 STMMAC_MMC_STAT(mmc_tx_carrier_error), 187 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 188 STMMAC_MMC_STAT(mmc_tx_framecount_g), 189 STMMAC_MMC_STAT(mmc_tx_excessdef), 190 STMMAC_MMC_STAT(mmc_tx_pause_frame), 191 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 192 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 193 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 194 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 195 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 196 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 197 STMMAC_MMC_STAT(mmc_rx_crc_error), 198 STMMAC_MMC_STAT(mmc_rx_align_error), 199 STMMAC_MMC_STAT(mmc_rx_run_error), 200 STMMAC_MMC_STAT(mmc_rx_jabber_error), 201 STMMAC_MMC_STAT(mmc_rx_undersize_g), 202 STMMAC_MMC_STAT(mmc_rx_oversize_g), 203 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 204 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 205 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 206 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 207 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 208 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 209 STMMAC_MMC_STAT(mmc_rx_unicast_g), 210 STMMAC_MMC_STAT(mmc_rx_length_error), 211 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 212 STMMAC_MMC_STAT(mmc_rx_pause_frames), 213 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 214 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 215 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 216 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 217 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 218 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 219 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 220 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 221 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 222 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 223 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 224 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 225 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 226 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 227 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 228 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 229 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 230 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 231 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 232 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 233 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 234 STMMAC_MMC_STAT(mmc_rx_udp_gd), 235 STMMAC_MMC_STAT(mmc_rx_udp_err), 236 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 237 STMMAC_MMC_STAT(mmc_rx_tcp_err), 238 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 239 STMMAC_MMC_STAT(mmc_rx_icmp_err), 240 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 241 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 242 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 243 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 244 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 245 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 246 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 247 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 248 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 249 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 250 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 251 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 252 }; 253 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 254 255 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 256 struct ethtool_drvinfo *info) 257 { 258 struct stmmac_priv *priv = netdev_priv(dev); 259 260 if (priv->plat->has_gmac || priv->plat->has_gmac4) 261 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 262 else 263 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 264 sizeof(info->driver)); 265 266 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 267 } 268 269 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 270 struct ethtool_link_ksettings *cmd) 271 { 272 struct stmmac_priv *priv = netdev_priv(dev); 273 274 if (priv->hw->pcs & STMMAC_PCS_RGMII || 275 priv->hw->pcs & STMMAC_PCS_SGMII) { 276 struct rgmii_adv adv; 277 u32 supported, advertising, lp_advertising; 278 279 if (!priv->xstats.pcs_link) { 280 cmd->base.speed = SPEED_UNKNOWN; 281 cmd->base.duplex = DUPLEX_UNKNOWN; 282 return 0; 283 } 284 cmd->base.duplex = priv->xstats.pcs_duplex; 285 286 cmd->base.speed = priv->xstats.pcs_speed; 287 288 /* Get and convert ADV/LP_ADV from the HW AN registers */ 289 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 290 return -EOPNOTSUPP; /* should never happen indeed */ 291 292 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 293 294 ethtool_convert_link_mode_to_legacy_u32( 295 &supported, cmd->link_modes.supported); 296 ethtool_convert_link_mode_to_legacy_u32( 297 &advertising, cmd->link_modes.advertising); 298 ethtool_convert_link_mode_to_legacy_u32( 299 &lp_advertising, cmd->link_modes.lp_advertising); 300 301 if (adv.pause & STMMAC_PCS_PAUSE) 302 advertising |= ADVERTISED_Pause; 303 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 304 advertising |= ADVERTISED_Asym_Pause; 305 if (adv.lp_pause & STMMAC_PCS_PAUSE) 306 lp_advertising |= ADVERTISED_Pause; 307 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 308 lp_advertising |= ADVERTISED_Asym_Pause; 309 310 /* Reg49[3] always set because ANE is always supported */ 311 cmd->base.autoneg = ADVERTISED_Autoneg; 312 supported |= SUPPORTED_Autoneg; 313 advertising |= ADVERTISED_Autoneg; 314 lp_advertising |= ADVERTISED_Autoneg; 315 316 if (adv.duplex) { 317 supported |= (SUPPORTED_1000baseT_Full | 318 SUPPORTED_100baseT_Full | 319 SUPPORTED_10baseT_Full); 320 advertising |= (ADVERTISED_1000baseT_Full | 321 ADVERTISED_100baseT_Full | 322 ADVERTISED_10baseT_Full); 323 } else { 324 supported |= (SUPPORTED_1000baseT_Half | 325 SUPPORTED_100baseT_Half | 326 SUPPORTED_10baseT_Half); 327 advertising |= (ADVERTISED_1000baseT_Half | 328 ADVERTISED_100baseT_Half | 329 ADVERTISED_10baseT_Half); 330 } 331 if (adv.lp_duplex) 332 lp_advertising |= (ADVERTISED_1000baseT_Full | 333 ADVERTISED_100baseT_Full | 334 ADVERTISED_10baseT_Full); 335 else 336 lp_advertising |= (ADVERTISED_1000baseT_Half | 337 ADVERTISED_100baseT_Half | 338 ADVERTISED_10baseT_Half); 339 cmd->base.port = PORT_OTHER; 340 341 ethtool_convert_legacy_u32_to_link_mode( 342 cmd->link_modes.supported, supported); 343 ethtool_convert_legacy_u32_to_link_mode( 344 cmd->link_modes.advertising, advertising); 345 ethtool_convert_legacy_u32_to_link_mode( 346 cmd->link_modes.lp_advertising, lp_advertising); 347 348 return 0; 349 } 350 351 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 352 } 353 354 static int 355 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 356 const struct ethtool_link_ksettings *cmd) 357 { 358 struct stmmac_priv *priv = netdev_priv(dev); 359 360 if (priv->hw->pcs & STMMAC_PCS_RGMII || 361 priv->hw->pcs & STMMAC_PCS_SGMII) { 362 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 363 364 /* Only support ANE */ 365 if (cmd->base.autoneg != AUTONEG_ENABLE) 366 return -EINVAL; 367 368 mask &= (ADVERTISED_1000baseT_Half | 369 ADVERTISED_1000baseT_Full | 370 ADVERTISED_100baseT_Half | 371 ADVERTISED_100baseT_Full | 372 ADVERTISED_10baseT_Half | 373 ADVERTISED_10baseT_Full); 374 375 mutex_lock(&priv->lock); 376 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 377 mutex_unlock(&priv->lock); 378 379 return 0; 380 } 381 382 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 383 } 384 385 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 386 { 387 struct stmmac_priv *priv = netdev_priv(dev); 388 return priv->msg_enable; 389 } 390 391 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 392 { 393 struct stmmac_priv *priv = netdev_priv(dev); 394 priv->msg_enable = level; 395 396 } 397 398 static int stmmac_check_if_running(struct net_device *dev) 399 { 400 if (!netif_running(dev)) 401 return -EBUSY; 402 return 0; 403 } 404 405 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 406 { 407 return REG_SPACE_SIZE; 408 } 409 410 static void stmmac_ethtool_gregs(struct net_device *dev, 411 struct ethtool_regs *regs, void *space) 412 { 413 u32 *reg_space = (u32 *) space; 414 415 struct stmmac_priv *priv = netdev_priv(dev); 416 417 memset(reg_space, 0x0, REG_SPACE_SIZE); 418 419 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 420 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 421 /* Copy DMA registers to where ethtool expects them */ 422 memcpy(®_space[ETHTOOL_DMA_OFFSET], ®_space[DMA_BUS_MODE / 4], 423 NUM_DWMAC1000_DMA_REGS * 4); 424 } 425 426 static int stmmac_nway_reset(struct net_device *dev) 427 { 428 struct stmmac_priv *priv = netdev_priv(dev); 429 430 return phylink_ethtool_nway_reset(priv->phylink); 431 } 432 433 static void 434 stmmac_get_pauseparam(struct net_device *netdev, 435 struct ethtool_pauseparam *pause) 436 { 437 struct stmmac_priv *priv = netdev_priv(netdev); 438 struct rgmii_adv adv_lp; 439 440 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 441 pause->autoneg = 1; 442 if (!adv_lp.pause) 443 return; 444 } else { 445 phylink_ethtool_get_pauseparam(priv->phylink, pause); 446 } 447 } 448 449 static int 450 stmmac_set_pauseparam(struct net_device *netdev, 451 struct ethtool_pauseparam *pause) 452 { 453 struct stmmac_priv *priv = netdev_priv(netdev); 454 struct rgmii_adv adv_lp; 455 456 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 457 pause->autoneg = 1; 458 if (!adv_lp.pause) 459 return -EOPNOTSUPP; 460 return 0; 461 } else { 462 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 463 } 464 } 465 466 static void stmmac_get_ethtool_stats(struct net_device *dev, 467 struct ethtool_stats *dummy, u64 *data) 468 { 469 struct stmmac_priv *priv = netdev_priv(dev); 470 u32 rx_queues_count = priv->plat->rx_queues_to_use; 471 u32 tx_queues_count = priv->plat->tx_queues_to_use; 472 unsigned long count; 473 int i, j = 0, ret; 474 475 if (priv->dma_cap.asp) { 476 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 477 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 478 &count, NULL)) 479 data[j++] = count; 480 } 481 } 482 483 /* Update the DMA HW counters for dwmac10/100 */ 484 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 485 priv->ioaddr); 486 if (ret) { 487 /* If supported, for new GMAC chips expose the MMC counters */ 488 if (priv->dma_cap.rmon) { 489 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 490 491 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 492 char *p; 493 p = (char *)priv + stmmac_mmc[i].stat_offset; 494 495 data[j++] = (stmmac_mmc[i].sizeof_stat == 496 sizeof(u64)) ? (*(u64 *)p) : 497 (*(u32 *)p); 498 } 499 } 500 if (priv->eee_enabled) { 501 int val = phylink_get_eee_err(priv->phylink); 502 if (val) 503 priv->xstats.phy_eee_wakeup_error_n = val; 504 } 505 506 if (priv->synopsys_id >= DWMAC_CORE_3_50) 507 stmmac_mac_debug(priv, priv->ioaddr, 508 (void *)&priv->xstats, 509 rx_queues_count, tx_queues_count); 510 } 511 for (i = 0; i < STMMAC_STATS_LEN; i++) { 512 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 513 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 514 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 515 } 516 } 517 518 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 519 { 520 struct stmmac_priv *priv = netdev_priv(netdev); 521 int i, len, safety_len = 0; 522 523 switch (sset) { 524 case ETH_SS_STATS: 525 len = STMMAC_STATS_LEN; 526 527 if (priv->dma_cap.rmon) 528 len += STMMAC_MMC_STATS_LEN; 529 if (priv->dma_cap.asp) { 530 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 531 if (!stmmac_safety_feat_dump(priv, 532 &priv->sstats, i, 533 NULL, NULL)) 534 safety_len++; 535 } 536 537 len += safety_len; 538 } 539 540 return len; 541 case ETH_SS_TEST: 542 return stmmac_selftest_get_count(priv); 543 default: 544 return -EOPNOTSUPP; 545 } 546 } 547 548 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 549 { 550 int i; 551 u8 *p = data; 552 struct stmmac_priv *priv = netdev_priv(dev); 553 554 switch (stringset) { 555 case ETH_SS_STATS: 556 if (priv->dma_cap.asp) { 557 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 558 const char *desc; 559 if (!stmmac_safety_feat_dump(priv, 560 &priv->sstats, i, 561 NULL, &desc)) { 562 memcpy(p, desc, ETH_GSTRING_LEN); 563 p += ETH_GSTRING_LEN; 564 } 565 } 566 } 567 if (priv->dma_cap.rmon) 568 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 569 memcpy(p, stmmac_mmc[i].stat_string, 570 ETH_GSTRING_LEN); 571 p += ETH_GSTRING_LEN; 572 } 573 for (i = 0; i < STMMAC_STATS_LEN; i++) { 574 memcpy(p, stmmac_gstrings_stats[i].stat_string, 575 ETH_GSTRING_LEN); 576 p += ETH_GSTRING_LEN; 577 } 578 break; 579 case ETH_SS_TEST: 580 stmmac_selftest_get_strings(priv, p); 581 break; 582 default: 583 WARN_ON(1); 584 break; 585 } 586 } 587 588 /* Currently only support WOL through Magic packet. */ 589 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 590 { 591 struct stmmac_priv *priv = netdev_priv(dev); 592 593 mutex_lock(&priv->lock); 594 if (device_can_wakeup(priv->device)) { 595 wol->supported = WAKE_MAGIC | WAKE_UCAST; 596 wol->wolopts = priv->wolopts; 597 } 598 mutex_unlock(&priv->lock); 599 } 600 601 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 602 { 603 struct stmmac_priv *priv = netdev_priv(dev); 604 u32 support = WAKE_MAGIC | WAKE_UCAST; 605 606 /* By default almost all GMAC devices support the WoL via 607 * magic frame but we can disable it if the HW capability 608 * register shows no support for pmt_magic_frame. */ 609 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 610 wol->wolopts &= ~WAKE_MAGIC; 611 612 if (!device_can_wakeup(priv->device)) 613 return -EINVAL; 614 615 if (wol->wolopts & ~support) 616 return -EINVAL; 617 618 if (wol->wolopts) { 619 pr_info("stmmac: wakeup enable\n"); 620 device_set_wakeup_enable(priv->device, 1); 621 enable_irq_wake(priv->wol_irq); 622 } else { 623 device_set_wakeup_enable(priv->device, 0); 624 disable_irq_wake(priv->wol_irq); 625 } 626 627 mutex_lock(&priv->lock); 628 priv->wolopts = wol->wolopts; 629 mutex_unlock(&priv->lock); 630 631 return 0; 632 } 633 634 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 635 struct ethtool_eee *edata) 636 { 637 struct stmmac_priv *priv = netdev_priv(dev); 638 639 if (!priv->dma_cap.eee) 640 return -EOPNOTSUPP; 641 642 edata->eee_enabled = priv->eee_enabled; 643 edata->eee_active = priv->eee_active; 644 edata->tx_lpi_timer = priv->tx_lpi_timer; 645 646 return phylink_ethtool_get_eee(priv->phylink, edata); 647 } 648 649 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 650 struct ethtool_eee *edata) 651 { 652 struct stmmac_priv *priv = netdev_priv(dev); 653 int ret; 654 655 if (!edata->eee_enabled) { 656 stmmac_disable_eee_mode(priv); 657 } else { 658 /* We are asking for enabling the EEE but it is safe 659 * to verify all by invoking the eee_init function. 660 * In case of failure it will return an error. 661 */ 662 edata->eee_enabled = stmmac_eee_init(priv); 663 if (!edata->eee_enabled) 664 return -EOPNOTSUPP; 665 } 666 667 ret = phylink_ethtool_set_eee(priv->phylink, edata); 668 if (ret) 669 return ret; 670 671 priv->eee_enabled = edata->eee_enabled; 672 priv->tx_lpi_timer = edata->tx_lpi_timer; 673 return 0; 674 } 675 676 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 677 { 678 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 679 680 if (!clk) { 681 clk = priv->plat->clk_ref_rate; 682 if (!clk) 683 return 0; 684 } 685 686 return (usec * (clk / 1000000)) / 256; 687 } 688 689 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 690 { 691 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 692 693 if (!clk) { 694 clk = priv->plat->clk_ref_rate; 695 if (!clk) 696 return 0; 697 } 698 699 return (riwt * 256) / (clk / 1000000); 700 } 701 702 static int stmmac_get_coalesce(struct net_device *dev, 703 struct ethtool_coalesce *ec) 704 { 705 struct stmmac_priv *priv = netdev_priv(dev); 706 707 ec->tx_coalesce_usecs = priv->tx_coal_timer; 708 ec->tx_max_coalesced_frames = priv->tx_coal_frames; 709 710 if (priv->use_riwt) { 711 ec->rx_max_coalesced_frames = priv->rx_coal_frames; 712 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv); 713 } 714 715 return 0; 716 } 717 718 static int stmmac_set_coalesce(struct net_device *dev, 719 struct ethtool_coalesce *ec) 720 { 721 struct stmmac_priv *priv = netdev_priv(dev); 722 u32 rx_cnt = priv->plat->rx_queues_to_use; 723 unsigned int rx_riwt; 724 725 /* Check not supported parameters */ 726 if ((ec->rx_coalesce_usecs_irq) || 727 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) || 728 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) || 729 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) || 730 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) || 731 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) || 732 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) || 733 (ec->rx_max_coalesced_frames_high) || 734 (ec->tx_max_coalesced_frames_irq) || 735 (ec->stats_block_coalesce_usecs) || 736 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval)) 737 return -EOPNOTSUPP; 738 739 if (ec->rx_coalesce_usecs == 0) 740 return -EINVAL; 741 742 if ((ec->tx_coalesce_usecs == 0) && 743 (ec->tx_max_coalesced_frames == 0)) 744 return -EINVAL; 745 746 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 747 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 748 return -EINVAL; 749 750 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 751 752 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 753 return -EINVAL; 754 else if (!priv->use_riwt) 755 return -EOPNOTSUPP; 756 757 /* Only copy relevant parameters, ignore all others. */ 758 priv->tx_coal_frames = ec->tx_max_coalesced_frames; 759 priv->tx_coal_timer = ec->tx_coalesce_usecs; 760 priv->rx_coal_frames = ec->rx_max_coalesced_frames; 761 priv->rx_riwt = rx_riwt; 762 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 763 764 return 0; 765 } 766 767 static int stmmac_get_rxnfc(struct net_device *dev, 768 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 769 { 770 struct stmmac_priv *priv = netdev_priv(dev); 771 772 switch (rxnfc->cmd) { 773 case ETHTOOL_GRXRINGS: 774 rxnfc->data = priv->plat->rx_queues_to_use; 775 break; 776 default: 777 return -EOPNOTSUPP; 778 } 779 780 return 0; 781 } 782 783 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 784 { 785 struct stmmac_priv *priv = netdev_priv(dev); 786 787 return sizeof(priv->rss.key); 788 } 789 790 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 791 { 792 struct stmmac_priv *priv = netdev_priv(dev); 793 794 return ARRAY_SIZE(priv->rss.table); 795 } 796 797 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 798 u8 *hfunc) 799 { 800 struct stmmac_priv *priv = netdev_priv(dev); 801 int i; 802 803 if (indir) { 804 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 805 indir[i] = priv->rss.table[i]; 806 } 807 808 if (key) 809 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 810 if (hfunc) 811 *hfunc = ETH_RSS_HASH_TOP; 812 813 return 0; 814 } 815 816 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 817 const u8 *key, const u8 hfunc) 818 { 819 struct stmmac_priv *priv = netdev_priv(dev); 820 int i; 821 822 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 823 return -EOPNOTSUPP; 824 825 if (indir) { 826 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 827 priv->rss.table[i] = indir[i]; 828 } 829 830 if (key) 831 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 832 833 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 834 priv->plat->rx_queues_to_use); 835 } 836 837 static int stmmac_get_ts_info(struct net_device *dev, 838 struct ethtool_ts_info *info) 839 { 840 struct stmmac_priv *priv = netdev_priv(dev); 841 842 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 843 844 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 845 SOF_TIMESTAMPING_TX_HARDWARE | 846 SOF_TIMESTAMPING_RX_SOFTWARE | 847 SOF_TIMESTAMPING_RX_HARDWARE | 848 SOF_TIMESTAMPING_SOFTWARE | 849 SOF_TIMESTAMPING_RAW_HARDWARE; 850 851 if (priv->ptp_clock) 852 info->phc_index = ptp_clock_index(priv->ptp_clock); 853 854 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 855 856 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 857 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 858 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 859 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 860 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 861 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 862 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 863 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 864 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 865 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 866 (1 << HWTSTAMP_FILTER_ALL)); 867 return 0; 868 } else 869 return ethtool_op_get_ts_info(dev, info); 870 } 871 872 static int stmmac_get_tunable(struct net_device *dev, 873 const struct ethtool_tunable *tuna, void *data) 874 { 875 struct stmmac_priv *priv = netdev_priv(dev); 876 int ret = 0; 877 878 switch (tuna->id) { 879 case ETHTOOL_RX_COPYBREAK: 880 *(u32 *)data = priv->rx_copybreak; 881 break; 882 default: 883 ret = -EINVAL; 884 break; 885 } 886 887 return ret; 888 } 889 890 static int stmmac_set_tunable(struct net_device *dev, 891 const struct ethtool_tunable *tuna, 892 const void *data) 893 { 894 struct stmmac_priv *priv = netdev_priv(dev); 895 int ret = 0; 896 897 switch (tuna->id) { 898 case ETHTOOL_RX_COPYBREAK: 899 priv->rx_copybreak = *(u32 *)data; 900 break; 901 default: 902 ret = -EINVAL; 903 break; 904 } 905 906 return ret; 907 } 908 909 static const struct ethtool_ops stmmac_ethtool_ops = { 910 .begin = stmmac_check_if_running, 911 .get_drvinfo = stmmac_ethtool_getdrvinfo, 912 .get_msglevel = stmmac_ethtool_getmsglevel, 913 .set_msglevel = stmmac_ethtool_setmsglevel, 914 .get_regs = stmmac_ethtool_gregs, 915 .get_regs_len = stmmac_ethtool_get_regs_len, 916 .get_link = ethtool_op_get_link, 917 .nway_reset = stmmac_nway_reset, 918 .get_pauseparam = stmmac_get_pauseparam, 919 .set_pauseparam = stmmac_set_pauseparam, 920 .self_test = stmmac_selftest_run, 921 .get_ethtool_stats = stmmac_get_ethtool_stats, 922 .get_strings = stmmac_get_strings, 923 .get_wol = stmmac_get_wol, 924 .set_wol = stmmac_set_wol, 925 .get_eee = stmmac_ethtool_op_get_eee, 926 .set_eee = stmmac_ethtool_op_set_eee, 927 .get_sset_count = stmmac_get_sset_count, 928 .get_rxnfc = stmmac_get_rxnfc, 929 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 930 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 931 .get_rxfh = stmmac_get_rxfh, 932 .set_rxfh = stmmac_set_rxfh, 933 .get_ts_info = stmmac_get_ts_info, 934 .get_coalesce = stmmac_get_coalesce, 935 .set_coalesce = stmmac_set_coalesce, 936 .get_tunable = stmmac_get_tunable, 937 .set_tunable = stmmac_set_tunable, 938 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 939 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 940 }; 941 942 void stmmac_set_ethtool_ops(struct net_device *netdev) 943 { 944 netdev->ethtool_ops = &stmmac_ethtool_ops; 945 } 946