1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 14 #include <linux/clk.h> 15 #include <linux/hrtimer.h> 16 #include <linux/if_vlan.h> 17 #include <linux/stmmac.h> 18 #include <linux/phylink.h> 19 #include <linux/pci.h> 20 #include "common.h" 21 #include <linux/ptp_clock_kernel.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/reset.h> 24 #include <net/page_pool/types.h> 25 #include <net/xdp.h> 26 #include <uapi/linux/bpf.h> 27 28 struct stmmac_resources { 29 void __iomem *addr; 30 u8 mac[ETH_ALEN]; 31 int wol_irq; 32 int lpi_irq; 33 int irq; 34 int sfty_irq; 35 int sfty_ce_irq; 36 int sfty_ue_irq; 37 int rx_irq[MTL_MAX_RX_QUEUES]; 38 int tx_irq[MTL_MAX_TX_QUEUES]; 39 }; 40 41 enum stmmac_txbuf_type { 42 STMMAC_TXBUF_T_SKB, 43 STMMAC_TXBUF_T_XDP_TX, 44 STMMAC_TXBUF_T_XDP_NDO, 45 STMMAC_TXBUF_T_XSK_TX, 46 }; 47 48 struct stmmac_tx_info { 49 dma_addr_t buf; 50 bool map_as_page; 51 unsigned len; 52 bool last_segment; 53 bool is_jumbo; 54 enum stmmac_txbuf_type buf_type; 55 struct xsk_tx_metadata_compl xsk_meta; 56 }; 57 58 #define STMMAC_TBS_AVAIL BIT(0) 59 #define STMMAC_TBS_EN BIT(1) 60 61 /* Frequently used values are kept adjacent for cache effect */ 62 struct stmmac_tx_queue { 63 u32 tx_count_frames; 64 int tbs; 65 struct hrtimer txtimer; 66 u32 queue_index; 67 struct stmmac_priv *priv_data; 68 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 69 struct dma_edesc *dma_entx; 70 struct dma_desc *dma_tx; 71 union { 72 struct sk_buff **tx_skbuff; 73 struct xdp_frame **xdpf; 74 }; 75 struct stmmac_tx_info *tx_skbuff_dma; 76 struct xsk_buff_pool *xsk_pool; 77 u32 xsk_frames_done; 78 unsigned int cur_tx; 79 unsigned int dirty_tx; 80 dma_addr_t dma_tx_phy; 81 dma_addr_t tx_tail_addr; 82 u32 mss; 83 }; 84 85 struct stmmac_rx_buffer { 86 union { 87 struct { 88 struct page *page; 89 dma_addr_t addr; 90 __u32 page_offset; 91 }; 92 struct xdp_buff *xdp; 93 }; 94 struct page *sec_page; 95 dma_addr_t sec_addr; 96 }; 97 98 struct stmmac_xdp_buff { 99 struct xdp_buff xdp; 100 struct stmmac_priv *priv; 101 struct dma_desc *desc; 102 struct dma_desc *ndesc; 103 }; 104 105 struct stmmac_metadata_request { 106 struct stmmac_priv *priv; 107 struct dma_desc *tx_desc; 108 bool *set_ic; 109 }; 110 111 struct stmmac_xsk_tx_complete { 112 struct stmmac_priv *priv; 113 struct dma_desc *desc; 114 }; 115 116 struct stmmac_rx_queue { 117 u32 rx_count_frames; 118 u32 queue_index; 119 struct xdp_rxq_info xdp_rxq; 120 struct xsk_buff_pool *xsk_pool; 121 struct page_pool *page_pool; 122 struct stmmac_rx_buffer *buf_pool; 123 struct stmmac_priv *priv_data; 124 struct dma_extended_desc *dma_erx; 125 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 126 unsigned int cur_rx; 127 unsigned int dirty_rx; 128 unsigned int buf_alloc_num; 129 u32 rx_zeroc_thresh; 130 dma_addr_t dma_rx_phy; 131 u32 rx_tail_addr; 132 unsigned int state_saved; 133 struct { 134 struct sk_buff *skb; 135 unsigned int len; 136 unsigned int error; 137 } state; 138 }; 139 140 struct stmmac_channel { 141 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 142 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 143 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp; 144 struct stmmac_priv *priv_data; 145 spinlock_t lock; 146 u32 index; 147 }; 148 149 struct stmmac_fpe_cfg { 150 /* Serialize access to MAC Merge state between ethtool requests 151 * and link state updates. 152 */ 153 spinlock_t lock; 154 155 const struct stmmac_fpe_reg *reg; 156 u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */ 157 158 enum ethtool_mm_verify_status status; 159 struct timer_list verify_timer; 160 bool verify_enabled; 161 int verify_retries; 162 bool pmac_enabled; 163 u32 verify_time; 164 bool tx_enabled; 165 }; 166 167 struct stmmac_tc_entry { 168 bool in_use; 169 bool in_hw; 170 bool is_last; 171 bool is_frag; 172 void *frag_ptr; 173 unsigned int table_pos; 174 u32 handle; 175 u32 prio; 176 struct { 177 u32 match_data; 178 u32 match_en; 179 u8 af:1; 180 u8 rf:1; 181 u8 im:1; 182 u8 nc:1; 183 u8 res1:4; 184 u8 frame_offset; 185 u8 ok_index; 186 u8 dma_ch_no; 187 u32 res2; 188 } __packed val; 189 }; 190 191 #define STMMAC_PPS_MAX 4 192 struct stmmac_pps_cfg { 193 bool available; 194 struct timespec64 start; 195 struct timespec64 period; 196 }; 197 198 struct stmmac_rss { 199 int enable; 200 u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 201 u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 202 }; 203 204 #define STMMAC_FLOW_ACTION_DROP BIT(0) 205 struct stmmac_flow_entry { 206 unsigned long cookie; 207 unsigned long action; 208 u8 ip_proto; 209 int in_use; 210 int idx; 211 int is_l4; 212 }; 213 214 /* Rx Frame Steering */ 215 enum stmmac_rfs_type { 216 STMMAC_RFS_T_VLAN, 217 STMMAC_RFS_T_LLDP, 218 STMMAC_RFS_T_1588, 219 STMMAC_RFS_T_MAX, 220 }; 221 222 struct stmmac_rfs_entry { 223 unsigned long cookie; 224 u16 etype; 225 int in_use; 226 int type; 227 int tc; 228 }; 229 230 struct stmmac_dma_conf { 231 unsigned int dma_buf_sz; 232 233 /* RX Queue */ 234 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 235 unsigned int dma_rx_size; 236 237 /* TX Queue */ 238 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 239 unsigned int dma_tx_size; 240 }; 241 242 #define EST_GCL 1024 243 struct stmmac_est { 244 int enable; 245 u32 btr_reserve[2]; 246 u32 btr_offset[2]; 247 u32 btr[2]; 248 u32 ctr[2]; 249 u32 ter; 250 u32 gcl_unaligned[EST_GCL]; 251 u32 gcl[EST_GCL]; 252 u32 gcl_size; 253 u32 max_sdu[MTL_MAX_TX_QUEUES]; 254 }; 255 256 struct stmmac_priv { 257 /* Frequently used values are kept adjacent for cache effect */ 258 u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; 259 u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; 260 u32 rx_coal_frames[MTL_MAX_TX_QUEUES]; 261 262 int hwts_tx_en; 263 bool tx_path_in_lpi_mode; 264 bool tso; 265 int sph; 266 int sph_cap; 267 u32 sarc_type; 268 269 unsigned int rx_copybreak; 270 u32 rx_riwt[MTL_MAX_TX_QUEUES]; 271 int hwts_rx_en; 272 273 void __iomem *ioaddr; 274 struct net_device *dev; 275 struct device *device; 276 struct mac_device_info *hw; 277 int (*hwif_quirks)(struct stmmac_priv *priv); 278 struct mutex lock; 279 280 struct stmmac_dma_conf dma_conf; 281 282 /* Generic channel for NAPI */ 283 struct stmmac_channel channel[STMMAC_CH_MAX]; 284 285 int speed; 286 unsigned int flow_ctrl; 287 unsigned int pause; 288 struct mii_bus *mii; 289 290 struct phylink_config phylink_config; 291 struct phylink *phylink; 292 293 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 294 struct stmmac_safety_stats sstats; 295 struct plat_stmmacenet_data *plat; 296 /* Protect est parameters */ 297 struct mutex est_lock; 298 struct stmmac_est *est; 299 struct dma_features dma_cap; 300 struct stmmac_counters mmc; 301 int hw_cap_support; 302 int synopsys_id; 303 u32 msg_enable; 304 int wolopts; 305 int wol_irq; 306 bool wol_irq_disabled; 307 int clk_csr; 308 struct timer_list eee_ctrl_timer; 309 int lpi_irq; 310 int eee_enabled; 311 int eee_active; 312 int tx_lpi_timer; 313 int tx_lpi_enabled; 314 int eee_tw_timer; 315 bool eee_sw_timer_en; 316 unsigned int mode; 317 unsigned int chain_mode; 318 int extend_desc; 319 struct hwtstamp_config tstamp_config; 320 struct ptp_clock *ptp_clock; 321 struct ptp_clock_info ptp_clock_ops; 322 unsigned int default_addend; 323 u32 sub_second_inc; 324 u32 systime_flags; 325 u32 adv_ts; 326 int use_riwt; 327 int irq_wake; 328 rwlock_t ptp_lock; 329 /* Protects auxiliary snapshot registers from concurrent access. */ 330 struct mutex aux_ts_lock; 331 wait_queue_head_t tstamp_busy_wait; 332 333 void __iomem *mmcaddr; 334 void __iomem *ptpaddr; 335 void __iomem *estaddr; 336 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 337 int sfty_irq; 338 int sfty_ce_irq; 339 int sfty_ue_irq; 340 int rx_irq[MTL_MAX_RX_QUEUES]; 341 int tx_irq[MTL_MAX_TX_QUEUES]; 342 /*irq name */ 343 char int_name_mac[IFNAMSIZ + 9]; 344 char int_name_wol[IFNAMSIZ + 9]; 345 char int_name_lpi[IFNAMSIZ + 9]; 346 char int_name_sfty[IFNAMSIZ + 10]; 347 char int_name_sfty_ce[IFNAMSIZ + 10]; 348 char int_name_sfty_ue[IFNAMSIZ + 10]; 349 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14]; 350 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; 351 352 #ifdef CONFIG_DEBUG_FS 353 struct dentry *dbgfs_dir; 354 #endif 355 356 unsigned long state; 357 struct workqueue_struct *wq; 358 struct work_struct service_task; 359 360 /* Frame Preemption feature (FPE) */ 361 struct stmmac_fpe_cfg fpe_cfg; 362 363 /* TC Handling */ 364 unsigned int tc_entries_max; 365 unsigned int tc_off_max; 366 struct stmmac_tc_entry *tc_entries; 367 unsigned int flow_entries_max; 368 struct stmmac_flow_entry *flow_entries; 369 unsigned int rfs_entries_max[STMMAC_RFS_T_MAX]; 370 unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX]; 371 unsigned int rfs_entries_total; 372 struct stmmac_rfs_entry *rfs_entries; 373 374 /* Pulse Per Second output */ 375 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 376 377 /* Receive Side Scaling */ 378 struct stmmac_rss rss; 379 380 /* XDP BPF Program */ 381 unsigned long *af_xdp_zc_qps; 382 struct bpf_prog *xdp_prog; 383 }; 384 385 enum stmmac_state { 386 STMMAC_DOWN, 387 STMMAC_RESET_REQUESTED, 388 STMMAC_RESETING, 389 STMMAC_SERVICE_SCHED, 390 }; 391 392 int stmmac_mdio_unregister(struct net_device *ndev); 393 int stmmac_mdio_register(struct net_device *ndev); 394 int stmmac_mdio_reset(struct mii_bus *mii); 395 int stmmac_pcs_setup(struct net_device *ndev); 396 void stmmac_pcs_clean(struct net_device *ndev); 397 void stmmac_set_ethtool_ops(struct net_device *netdev); 398 399 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags); 400 void stmmac_ptp_register(struct stmmac_priv *priv); 401 void stmmac_ptp_unregister(struct stmmac_priv *priv); 402 int stmmac_xdp_open(struct net_device *dev); 403 void stmmac_xdp_release(struct net_device *dev); 404 int stmmac_resume(struct device *dev); 405 int stmmac_suspend(struct device *dev); 406 void stmmac_dvr_remove(struct device *dev); 407 int stmmac_dvr_probe(struct device *device, 408 struct plat_stmmacenet_data *plat_dat, 409 struct stmmac_resources *res); 410 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 411 bool stmmac_eee_init(struct stmmac_priv *priv); 412 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); 413 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); 414 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); 415 416 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) 417 { 418 return !!priv->xdp_prog; 419 } 420 421 static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv) 422 { 423 if (stmmac_xdp_is_enabled(priv)) 424 return XDP_PACKET_HEADROOM; 425 426 return 0; 427 } 428 429 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue); 430 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue); 431 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue); 432 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue); 433 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags); 434 struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time, 435 ktime_t current_time, 436 u64 cycle_time); 437 438 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 439 void stmmac_selftest_run(struct net_device *dev, 440 struct ethtool_test *etest, u64 *buf); 441 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 442 int stmmac_selftest_get_count(struct stmmac_priv *priv); 443 #else 444 static inline void stmmac_selftest_run(struct net_device *dev, 445 struct ethtool_test *etest, u64 *buf) 446 { 447 /* Not enabled */ 448 } 449 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 450 u8 *data) 451 { 452 /* Not enabled */ 453 } 454 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 455 { 456 return -EOPNOTSUPP; 457 } 458 #endif /* CONFIG_STMMAC_SELFTESTS */ 459 460 #endif /* __STMMAC_H__ */ 461