1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 14 #include <linux/clk.h> 15 #include <linux/hrtimer.h> 16 #include <linux/if_vlan.h> 17 #include <linux/stmmac.h> 18 #include <linux/phylink.h> 19 #include <linux/pci.h> 20 #include "common.h" 21 #include <linux/ptp_clock_kernel.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/reset.h> 24 #include <net/page_pool/types.h> 25 #include <net/xdp.h> 26 #include <uapi/linux/bpf.h> 27 28 struct stmmac_pcs; 29 30 struct stmmac_resources { 31 void __iomem *addr; 32 u8 mac[ETH_ALEN]; 33 int wol_irq; 34 int lpi_irq; 35 int irq; 36 int sfty_irq; 37 int sfty_ce_irq; 38 int sfty_ue_irq; 39 int rx_irq[MTL_MAX_RX_QUEUES]; 40 int tx_irq[MTL_MAX_TX_QUEUES]; 41 }; 42 43 enum stmmac_txbuf_type { 44 STMMAC_TXBUF_T_SKB, 45 STMMAC_TXBUF_T_XDP_TX, 46 STMMAC_TXBUF_T_XDP_NDO, 47 STMMAC_TXBUF_T_XSK_TX, 48 }; 49 50 struct stmmac_tx_info { 51 dma_addr_t buf; 52 bool map_as_page; 53 unsigned len; 54 bool last_segment; 55 bool is_jumbo; 56 enum stmmac_txbuf_type buf_type; 57 struct xsk_tx_metadata_compl xsk_meta; 58 }; 59 60 #define STMMAC_TBS_AVAIL BIT(0) 61 #define STMMAC_TBS_EN BIT(1) 62 63 /* Frequently used values are kept adjacent for cache effect */ 64 struct stmmac_tx_queue { 65 u32 tx_count_frames; 66 int tbs; 67 struct hrtimer txtimer; 68 u32 queue_index; 69 struct stmmac_priv *priv_data; 70 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 71 struct dma_edesc *dma_entx; 72 struct dma_desc *dma_tx; 73 union { 74 struct sk_buff **tx_skbuff; 75 struct xdp_frame **xdpf; 76 }; 77 struct stmmac_tx_info *tx_skbuff_dma; 78 struct xsk_buff_pool *xsk_pool; 79 u32 xsk_frames_done; 80 unsigned int cur_tx; 81 unsigned int dirty_tx; 82 dma_addr_t dma_tx_phy; 83 dma_addr_t tx_tail_addr; 84 u32 mss; 85 }; 86 87 struct stmmac_rx_buffer { 88 union { 89 struct { 90 struct page *page; 91 dma_addr_t addr; 92 __u32 page_offset; 93 }; 94 struct xdp_buff *xdp; 95 }; 96 struct page *sec_page; 97 dma_addr_t sec_addr; 98 }; 99 100 struct stmmac_xdp_buff { 101 struct xdp_buff xdp; 102 struct stmmac_priv *priv; 103 struct dma_desc *desc; 104 struct dma_desc *ndesc; 105 }; 106 107 struct stmmac_metadata_request { 108 struct stmmac_priv *priv; 109 struct dma_desc *tx_desc; 110 bool *set_ic; 111 struct dma_edesc *edesc; 112 int tbs; 113 }; 114 115 struct stmmac_xsk_tx_complete { 116 struct stmmac_priv *priv; 117 struct dma_desc *desc; 118 }; 119 120 struct stmmac_rx_queue { 121 u32 rx_count_frames; 122 u32 queue_index; 123 struct xdp_rxq_info xdp_rxq; 124 struct xsk_buff_pool *xsk_pool; 125 struct page_pool *page_pool; 126 struct stmmac_rx_buffer *buf_pool; 127 struct stmmac_priv *priv_data; 128 struct dma_extended_desc *dma_erx; 129 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 130 unsigned int cur_rx; 131 unsigned int dirty_rx; 132 unsigned int buf_alloc_num; 133 unsigned int napi_skb_frag_size; 134 dma_addr_t dma_rx_phy; 135 u32 rx_tail_addr; 136 unsigned int state_saved; 137 struct { 138 struct sk_buff *skb; 139 unsigned int len; 140 unsigned int error; 141 } state; 142 }; 143 144 struct stmmac_channel { 145 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 146 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 147 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp; 148 struct stmmac_priv *priv_data; 149 spinlock_t lock; 150 u32 index; 151 }; 152 153 struct stmmac_fpe_cfg { 154 struct ethtool_mmsv mmsv; 155 const struct stmmac_fpe_reg *reg; 156 u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */ 157 }; 158 159 struct stmmac_tc_entry { 160 bool in_use; 161 bool in_hw; 162 bool is_last; 163 bool is_frag; 164 void *frag_ptr; 165 unsigned int table_pos; 166 u32 handle; 167 u32 prio; 168 struct { 169 u32 match_data; 170 u32 match_en; 171 u8 af:1; 172 u8 rf:1; 173 u8 im:1; 174 u8 nc:1; 175 u8 res1:4; 176 u8 frame_offset; 177 u8 ok_index; 178 u8 dma_ch_no; 179 u32 res2; 180 } __packed val; 181 }; 182 183 #define STMMAC_PPS_MAX 4 184 struct stmmac_pps_cfg { 185 bool available; 186 struct timespec64 start; 187 struct timespec64 period; 188 }; 189 190 struct stmmac_rss { 191 int enable; 192 u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 193 u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 194 }; 195 196 #define STMMAC_FLOW_ACTION_DROP BIT(0) 197 struct stmmac_flow_entry { 198 unsigned long cookie; 199 unsigned long action; 200 u8 ip_proto; 201 int in_use; 202 int idx; 203 int is_l4; 204 }; 205 206 /* Rx Frame Steering */ 207 enum stmmac_rfs_type { 208 STMMAC_RFS_T_VLAN, 209 STMMAC_RFS_T_LLDP, 210 STMMAC_RFS_T_1588, 211 STMMAC_RFS_T_MAX, 212 }; 213 214 struct stmmac_rfs_entry { 215 unsigned long cookie; 216 u16 etype; 217 int in_use; 218 int type; 219 int tc; 220 }; 221 222 struct stmmac_dma_conf { 223 unsigned int dma_buf_sz; 224 225 /* RX Queue */ 226 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 227 unsigned int dma_rx_size; 228 229 /* TX Queue */ 230 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 231 unsigned int dma_tx_size; 232 }; 233 234 #define EST_GCL 1024 235 struct stmmac_est { 236 int enable; 237 u32 btr_reserve[2]; 238 u32 btr_offset[2]; 239 u32 btr[2]; 240 u32 ctr[2]; 241 u32 ter; 242 u32 gcl_unaligned[EST_GCL]; 243 u32 gcl[EST_GCL]; 244 u32 gcl_size; 245 u32 max_sdu[MTL_MAX_TX_QUEUES]; 246 }; 247 248 struct stmmac_priv { 249 /* Frequently used values are kept adjacent for cache effect */ 250 u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; 251 u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; 252 u32 rx_coal_frames[MTL_MAX_RX_QUEUES]; 253 254 int hwts_tx_en; 255 bool tx_path_in_lpi_mode; 256 bool tso; 257 bool sph_active; 258 bool sph_capable; 259 u32 sarc_type; 260 u32 rx_riwt[MTL_MAX_RX_QUEUES]; 261 int hwts_rx_en; 262 bool tsfupdt_coarse; 263 264 void __iomem *ioaddr; 265 struct net_device *dev; 266 struct device *device; 267 struct mac_device_info *hw; 268 int (*hwif_quirks)(struct stmmac_priv *priv); 269 struct mutex lock; 270 271 struct stmmac_dma_conf dma_conf; 272 273 /* Generic channel for NAPI */ 274 struct stmmac_channel channel[STMMAC_CH_MAX]; 275 276 unsigned int pause_time; 277 struct mii_bus *mii; 278 279 struct stmmac_pcs *integrated_pcs; 280 281 struct phylink_config phylink_config; 282 struct phylink *phylink; 283 284 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 285 struct stmmac_safety_stats sstats; 286 struct plat_stmmacenet_data *plat; 287 /* Protect est parameters */ 288 struct mutex est_lock; 289 struct stmmac_est *est; 290 struct dma_features dma_cap; 291 struct stmmac_counters mmc; 292 int hw_cap_support; 293 int synopsys_id; 294 u32 msg_enable; 295 /* Our MAC Wake-on-Lan options */ 296 int wolopts; 297 int wol_irq; 298 u32 gmii_address_bus_config; 299 struct timer_list eee_ctrl_timer; 300 int lpi_irq; 301 u32 tx_lpi_timer; 302 bool tx_lpi_clk_stop; 303 bool eee_enabled; 304 bool eee_active; 305 bool eee_sw_timer_en; 306 unsigned int mode; 307 unsigned int chain_mode; 308 int extend_desc; 309 struct kernel_hwtstamp_config tstamp_config; 310 struct ptp_clock *ptp_clock; 311 struct ptp_clock_info ptp_clock_ops; 312 unsigned int default_addend; 313 u32 sub_second_inc; 314 u32 systime_flags; 315 u32 adv_ts; 316 int use_riwt; 317 int irq_wake; 318 rwlock_t ptp_lock; 319 /* Protects auxiliary snapshot registers from concurrent access. */ 320 struct mutex aux_ts_lock; 321 wait_queue_head_t tstamp_busy_wait; 322 323 void __iomem *mmcaddr; 324 void __iomem *ptpaddr; 325 void __iomem *estaddr; 326 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 327 int sfty_irq; 328 int sfty_ce_irq; 329 int sfty_ue_irq; 330 int rx_irq[MTL_MAX_RX_QUEUES]; 331 int tx_irq[MTL_MAX_TX_QUEUES]; 332 /*irq name */ 333 char int_name_mac[IFNAMSIZ + 9]; 334 char int_name_wol[IFNAMSIZ + 9]; 335 char int_name_lpi[IFNAMSIZ + 9]; 336 char int_name_sfty[IFNAMSIZ + 10]; 337 char int_name_sfty_ce[IFNAMSIZ + 10]; 338 char int_name_sfty_ue[IFNAMSIZ + 10]; 339 char int_name_rx_irq[MTL_MAX_RX_QUEUES][IFNAMSIZ + 14]; 340 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; 341 342 #ifdef CONFIG_DEBUG_FS 343 struct dentry *dbgfs_dir; 344 #endif 345 346 unsigned long state; 347 struct workqueue_struct *wq; 348 struct work_struct service_task; 349 350 /* Frame Preemption feature (FPE) */ 351 struct stmmac_fpe_cfg fpe_cfg; 352 353 /* TC Handling */ 354 unsigned int tc_entries_max; 355 unsigned int tc_off_max; 356 struct stmmac_tc_entry *tc_entries; 357 unsigned int flow_entries_max; 358 struct stmmac_flow_entry *flow_entries; 359 unsigned int rfs_entries_max[STMMAC_RFS_T_MAX]; 360 unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX]; 361 unsigned int rfs_entries_total; 362 struct stmmac_rfs_entry *rfs_entries; 363 364 /* Pulse Per Second output */ 365 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 366 367 /* Receive Side Scaling */ 368 struct stmmac_rss rss; 369 370 /* XDP BPF Program */ 371 unsigned long *af_xdp_zc_qps; 372 struct bpf_prog *xdp_prog; 373 374 struct devlink *devlink; 375 }; 376 377 enum stmmac_state { 378 STMMAC_DOWN, 379 STMMAC_RESET_REQUESTED, 380 STMMAC_RESETING, 381 STMMAC_SERVICE_SCHED, 382 }; 383 384 extern const struct dev_pm_ops stmmac_simple_pm_ops; 385 386 int stmmac_mdio_unregister(struct net_device *ndev); 387 int stmmac_mdio_register(struct net_device *ndev); 388 int stmmac_mdio_reset(struct mii_bus *mii); 389 void stmmac_mdio_lock(struct stmmac_priv *priv); 390 void stmmac_mdio_unlock(struct stmmac_priv *priv); 391 int stmmac_pcs_setup(struct net_device *ndev); 392 void stmmac_pcs_clean(struct net_device *ndev); 393 void stmmac_set_ethtool_ops(struct net_device *netdev); 394 395 void stmmac_ptp_register(struct stmmac_priv *priv); 396 void stmmac_ptp_unregister(struct stmmac_priv *priv); 397 int stmmac_xdp_open(struct net_device *dev); 398 void stmmac_xdp_release(struct net_device *dev); 399 int stmmac_get_phy_intf_sel(phy_interface_t interface); 400 int stmmac_resume(struct device *dev); 401 int stmmac_suspend(struct device *dev); 402 void stmmac_dvr_remove(struct device *dev); 403 int stmmac_dvr_probe(struct device *device, 404 struct plat_stmmacenet_data *plat_dat, 405 struct stmmac_resources *res); 406 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); 407 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); 408 int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 409 phy_interface_t interface, int speed); 410 411 struct plat_stmmacenet_data *stmmac_plat_dat_alloc(struct device *dev); 412 413 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) 414 { 415 return !!priv->xdp_prog; 416 } 417 418 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue); 419 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue); 420 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue); 421 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue); 422 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags); 423 struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time, 424 ktime_t current_time, 425 u64 cycle_time); 426 427 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 428 void stmmac_selftest_run(struct net_device *dev, 429 struct ethtool_test *etest, u64 *buf); 430 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 431 int stmmac_selftest_get_count(struct stmmac_priv *priv); 432 #else 433 static inline void stmmac_selftest_run(struct net_device *dev, 434 struct ethtool_test *etest, u64 *buf) 435 { 436 /* Not enabled */ 437 } 438 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 439 u8 *data) 440 { 441 /* Not enabled */ 442 } 443 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 444 { 445 return -EOPNOTSUPP; 446 } 447 #endif /* CONFIG_STMMAC_SELFTESTS */ 448 449 #endif /* __STMMAC_H__ */ 450