1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 14 #include <linux/clk.h> 15 #include <linux/hrtimer.h> 16 #include <linux/if_vlan.h> 17 #include <linux/stmmac.h> 18 #include <linux/phylink.h> 19 #include <linux/pci.h> 20 #include "common.h" 21 #include <linux/ptp_clock_kernel.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/reset.h> 24 #include <net/page_pool/types.h> 25 #include <net/xdp.h> 26 #include <uapi/linux/bpf.h> 27 28 struct stmmac_resources { 29 void __iomem *addr; 30 u8 mac[ETH_ALEN]; 31 int wol_irq; 32 int lpi_irq; 33 int irq; 34 int sfty_ce_irq; 35 int sfty_ue_irq; 36 int rx_irq[MTL_MAX_RX_QUEUES]; 37 int tx_irq[MTL_MAX_TX_QUEUES]; 38 }; 39 40 enum stmmac_txbuf_type { 41 STMMAC_TXBUF_T_SKB, 42 STMMAC_TXBUF_T_XDP_TX, 43 STMMAC_TXBUF_T_XDP_NDO, 44 STMMAC_TXBUF_T_XSK_TX, 45 }; 46 47 struct stmmac_tx_info { 48 dma_addr_t buf; 49 bool map_as_page; 50 unsigned len; 51 bool last_segment; 52 bool is_jumbo; 53 enum stmmac_txbuf_type buf_type; 54 struct xsk_tx_metadata_compl xsk_meta; 55 }; 56 57 #define STMMAC_TBS_AVAIL BIT(0) 58 #define STMMAC_TBS_EN BIT(1) 59 60 /* Frequently used values are kept adjacent for cache effect */ 61 struct stmmac_tx_queue { 62 u32 tx_count_frames; 63 int tbs; 64 struct hrtimer txtimer; 65 u32 queue_index; 66 struct stmmac_priv *priv_data; 67 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 68 struct dma_edesc *dma_entx; 69 struct dma_desc *dma_tx; 70 union { 71 struct sk_buff **tx_skbuff; 72 struct xdp_frame **xdpf; 73 }; 74 struct stmmac_tx_info *tx_skbuff_dma; 75 struct xsk_buff_pool *xsk_pool; 76 u32 xsk_frames_done; 77 unsigned int cur_tx; 78 unsigned int dirty_tx; 79 dma_addr_t dma_tx_phy; 80 dma_addr_t tx_tail_addr; 81 u32 mss; 82 }; 83 84 struct stmmac_rx_buffer { 85 union { 86 struct { 87 struct page *page; 88 dma_addr_t addr; 89 __u32 page_offset; 90 }; 91 struct xdp_buff *xdp; 92 }; 93 struct page *sec_page; 94 dma_addr_t sec_addr; 95 }; 96 97 struct stmmac_xdp_buff { 98 struct xdp_buff xdp; 99 struct stmmac_priv *priv; 100 struct dma_desc *desc; 101 struct dma_desc *ndesc; 102 }; 103 104 struct stmmac_metadata_request { 105 struct stmmac_priv *priv; 106 struct dma_desc *tx_desc; 107 bool *set_ic; 108 }; 109 110 struct stmmac_xsk_tx_complete { 111 struct stmmac_priv *priv; 112 struct dma_desc *desc; 113 }; 114 115 struct stmmac_rx_queue { 116 u32 rx_count_frames; 117 u32 queue_index; 118 struct xdp_rxq_info xdp_rxq; 119 struct xsk_buff_pool *xsk_pool; 120 struct page_pool *page_pool; 121 struct stmmac_rx_buffer *buf_pool; 122 struct stmmac_priv *priv_data; 123 struct dma_extended_desc *dma_erx; 124 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 125 unsigned int cur_rx; 126 unsigned int dirty_rx; 127 unsigned int buf_alloc_num; 128 u32 rx_zeroc_thresh; 129 dma_addr_t dma_rx_phy; 130 u32 rx_tail_addr; 131 unsigned int state_saved; 132 struct { 133 struct sk_buff *skb; 134 unsigned int len; 135 unsigned int error; 136 } state; 137 }; 138 139 struct stmmac_channel { 140 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 141 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 142 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp; 143 struct stmmac_priv *priv_data; 144 spinlock_t lock; 145 u32 index; 146 }; 147 148 struct stmmac_tc_entry { 149 bool in_use; 150 bool in_hw; 151 bool is_last; 152 bool is_frag; 153 void *frag_ptr; 154 unsigned int table_pos; 155 u32 handle; 156 u32 prio; 157 struct { 158 u32 match_data; 159 u32 match_en; 160 u8 af:1; 161 u8 rf:1; 162 u8 im:1; 163 u8 nc:1; 164 u8 res1:4; 165 u8 frame_offset; 166 u8 ok_index; 167 u8 dma_ch_no; 168 u32 res2; 169 } __packed val; 170 }; 171 172 #define STMMAC_PPS_MAX 4 173 struct stmmac_pps_cfg { 174 bool available; 175 struct timespec64 start; 176 struct timespec64 period; 177 }; 178 179 struct stmmac_rss { 180 int enable; 181 u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 182 u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 183 }; 184 185 #define STMMAC_FLOW_ACTION_DROP BIT(0) 186 struct stmmac_flow_entry { 187 unsigned long cookie; 188 unsigned long action; 189 u8 ip_proto; 190 int in_use; 191 int idx; 192 int is_l4; 193 }; 194 195 /* Rx Frame Steering */ 196 enum stmmac_rfs_type { 197 STMMAC_RFS_T_VLAN, 198 STMMAC_RFS_T_LLDP, 199 STMMAC_RFS_T_1588, 200 STMMAC_RFS_T_MAX, 201 }; 202 203 struct stmmac_rfs_entry { 204 unsigned long cookie; 205 u16 etype; 206 int in_use; 207 int type; 208 int tc; 209 }; 210 211 struct stmmac_dma_conf { 212 unsigned int dma_buf_sz; 213 214 /* RX Queue */ 215 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 216 unsigned int dma_rx_size; 217 218 /* TX Queue */ 219 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 220 unsigned int dma_tx_size; 221 }; 222 223 struct stmmac_priv { 224 /* Frequently used values are kept adjacent for cache effect */ 225 u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; 226 u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; 227 u32 rx_coal_frames[MTL_MAX_TX_QUEUES]; 228 229 int hwts_tx_en; 230 bool tx_path_in_lpi_mode; 231 bool tso; 232 int sph; 233 int sph_cap; 234 u32 sarc_type; 235 236 unsigned int rx_copybreak; 237 u32 rx_riwt[MTL_MAX_TX_QUEUES]; 238 int hwts_rx_en; 239 240 void __iomem *ioaddr; 241 struct net_device *dev; 242 struct device *device; 243 struct mac_device_info *hw; 244 int (*hwif_quirks)(struct stmmac_priv *priv); 245 struct mutex lock; 246 247 struct stmmac_dma_conf dma_conf; 248 249 /* Generic channel for NAPI */ 250 struct stmmac_channel channel[STMMAC_CH_MAX]; 251 252 int speed; 253 unsigned int flow_ctrl; 254 unsigned int pause; 255 struct mii_bus *mii; 256 257 struct phylink_config phylink_config; 258 struct phylink *phylink; 259 260 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 261 struct stmmac_safety_stats sstats; 262 struct plat_stmmacenet_data *plat; 263 struct dma_features dma_cap; 264 struct stmmac_counters mmc; 265 int hw_cap_support; 266 int synopsys_id; 267 u32 msg_enable; 268 int wolopts; 269 int wol_irq; 270 bool wol_irq_disabled; 271 int clk_csr; 272 struct timer_list eee_ctrl_timer; 273 int lpi_irq; 274 int eee_enabled; 275 int eee_active; 276 int tx_lpi_timer; 277 int tx_lpi_enabled; 278 int eee_tw_timer; 279 bool eee_sw_timer_en; 280 unsigned int mode; 281 unsigned int chain_mode; 282 int extend_desc; 283 struct hwtstamp_config tstamp_config; 284 struct ptp_clock *ptp_clock; 285 struct ptp_clock_info ptp_clock_ops; 286 unsigned int default_addend; 287 u32 sub_second_inc; 288 u32 systime_flags; 289 u32 adv_ts; 290 int use_riwt; 291 int irq_wake; 292 rwlock_t ptp_lock; 293 /* Protects auxiliary snapshot registers from concurrent access. */ 294 struct mutex aux_ts_lock; 295 wait_queue_head_t tstamp_busy_wait; 296 297 void __iomem *mmcaddr; 298 void __iomem *ptpaddr; 299 void __iomem *estaddr; 300 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 301 int sfty_ce_irq; 302 int sfty_ue_irq; 303 int rx_irq[MTL_MAX_RX_QUEUES]; 304 int tx_irq[MTL_MAX_TX_QUEUES]; 305 /*irq name */ 306 char int_name_mac[IFNAMSIZ + 9]; 307 char int_name_wol[IFNAMSIZ + 9]; 308 char int_name_lpi[IFNAMSIZ + 9]; 309 char int_name_sfty_ce[IFNAMSIZ + 10]; 310 char int_name_sfty_ue[IFNAMSIZ + 10]; 311 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14]; 312 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; 313 314 #ifdef CONFIG_DEBUG_FS 315 struct dentry *dbgfs_dir; 316 #endif 317 318 unsigned long state; 319 struct workqueue_struct *wq; 320 struct work_struct service_task; 321 322 /* Workqueue for handling FPE hand-shaking */ 323 unsigned long fpe_task_state; 324 struct workqueue_struct *fpe_wq; 325 struct work_struct fpe_task; 326 char wq_name[IFNAMSIZ + 4]; 327 328 /* TC Handling */ 329 unsigned int tc_entries_max; 330 unsigned int tc_off_max; 331 struct stmmac_tc_entry *tc_entries; 332 unsigned int flow_entries_max; 333 struct stmmac_flow_entry *flow_entries; 334 unsigned int rfs_entries_max[STMMAC_RFS_T_MAX]; 335 unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX]; 336 unsigned int rfs_entries_total; 337 struct stmmac_rfs_entry *rfs_entries; 338 339 /* Pulse Per Second output */ 340 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 341 342 /* Receive Side Scaling */ 343 struct stmmac_rss rss; 344 345 /* XDP BPF Program */ 346 unsigned long *af_xdp_zc_qps; 347 struct bpf_prog *xdp_prog; 348 }; 349 350 enum stmmac_state { 351 STMMAC_DOWN, 352 STMMAC_RESET_REQUESTED, 353 STMMAC_RESETING, 354 STMMAC_SERVICE_SCHED, 355 }; 356 357 int stmmac_mdio_unregister(struct net_device *ndev); 358 int stmmac_mdio_register(struct net_device *ndev); 359 int stmmac_mdio_reset(struct mii_bus *mii); 360 int stmmac_xpcs_setup(struct mii_bus *mii); 361 void stmmac_set_ethtool_ops(struct net_device *netdev); 362 363 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags); 364 void stmmac_ptp_register(struct stmmac_priv *priv); 365 void stmmac_ptp_unregister(struct stmmac_priv *priv); 366 int stmmac_xdp_open(struct net_device *dev); 367 void stmmac_xdp_release(struct net_device *dev); 368 int stmmac_resume(struct device *dev); 369 int stmmac_suspend(struct device *dev); 370 void stmmac_dvr_remove(struct device *dev); 371 int stmmac_dvr_probe(struct device *device, 372 struct plat_stmmacenet_data *plat_dat, 373 struct stmmac_resources *res); 374 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 375 bool stmmac_eee_init(struct stmmac_priv *priv); 376 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); 377 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); 378 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); 379 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable); 380 381 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) 382 { 383 return !!priv->xdp_prog; 384 } 385 386 static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv) 387 { 388 if (stmmac_xdp_is_enabled(priv)) 389 return XDP_PACKET_HEADROOM; 390 391 return 0; 392 } 393 394 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue); 395 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue); 396 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue); 397 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue); 398 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags); 399 struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time, 400 ktime_t current_time, 401 u64 cycle_time); 402 403 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 404 void stmmac_selftest_run(struct net_device *dev, 405 struct ethtool_test *etest, u64 *buf); 406 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 407 int stmmac_selftest_get_count(struct stmmac_priv *priv); 408 #else 409 static inline void stmmac_selftest_run(struct net_device *dev, 410 struct ethtool_test *etest, u64 *buf) 411 { 412 /* Not enabled */ 413 } 414 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 415 u8 *data) 416 { 417 /* Not enabled */ 418 } 419 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 420 { 421 return -EOPNOTSUPP; 422 } 423 #endif /* CONFIG_STMMAC_SELFTESTS */ 424 425 #endif /* __STMMAC_H__ */ 426