1 /******************************************************************************* 2 This contains the functions to handle the normal descriptors. 3 4 Copyright (C) 2007-2009 STMicroelectronics Ltd 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 23 *******************************************************************************/ 24 25 #include <linux/stmmac.h> 26 #include "common.h" 27 #include "descs_com.h" 28 29 static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x, 30 struct dma_desc *p, void __iomem *ioaddr) 31 { 32 int ret = 0; 33 struct net_device_stats *stats = (struct net_device_stats *)data; 34 35 if (unlikely(p->des01.tx.error_summary)) { 36 if (unlikely(p->des01.tx.underflow_error)) { 37 x->tx_underflow++; 38 stats->tx_fifo_errors++; 39 } 40 if (unlikely(p->des01.tx.no_carrier)) { 41 x->tx_carrier++; 42 stats->tx_carrier_errors++; 43 } 44 if (unlikely(p->des01.tx.loss_carrier)) { 45 x->tx_losscarrier++; 46 stats->tx_carrier_errors++; 47 } 48 if (unlikely((p->des01.tx.excessive_deferral) || 49 (p->des01.tx.excessive_collisions) || 50 (p->des01.tx.late_collision))) 51 stats->collisions += p->des01.tx.collision_count; 52 ret = -1; 53 } 54 55 if (p->des01.etx.vlan_frame) 56 x->tx_vlan++; 57 58 if (unlikely(p->des01.tx.deferred)) 59 x->tx_deferred++; 60 61 return ret; 62 } 63 64 static int ndesc_get_tx_len(struct dma_desc *p) 65 { 66 return p->des01.tx.buffer1_size; 67 } 68 69 /* This function verifies if each incoming frame has some errors 70 * and, if required, updates the multicast statistics. 71 * In case of success, it returns good_frame because the GMAC device 72 * is supposed to be able to compute the csum in HW. */ 73 static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x, 74 struct dma_desc *p) 75 { 76 int ret = good_frame; 77 struct net_device_stats *stats = (struct net_device_stats *)data; 78 79 if (unlikely(p->des01.rx.last_descriptor == 0)) { 80 pr_warn("%s: Oversized frame spanned multiple buffers\n", 81 __func__); 82 stats->rx_length_errors++; 83 return discard_frame; 84 } 85 86 if (unlikely(p->des01.rx.error_summary)) { 87 if (unlikely(p->des01.rx.descriptor_error)) 88 x->rx_desc++; 89 if (unlikely(p->des01.rx.sa_filter_fail)) 90 x->sa_filter_fail++; 91 if (unlikely(p->des01.rx.overflow_error)) 92 x->overflow_error++; 93 if (unlikely(p->des01.rx.ipc_csum_error)) 94 x->ipc_csum_error++; 95 if (unlikely(p->des01.rx.collision)) { 96 x->rx_collision++; 97 stats->collisions++; 98 } 99 if (unlikely(p->des01.rx.crc_error)) { 100 x->rx_crc++; 101 stats->rx_crc_errors++; 102 } 103 ret = discard_frame; 104 } 105 if (unlikely(p->des01.rx.dribbling)) 106 x->dribbling_bit++; 107 108 if (unlikely(p->des01.rx.length_error)) { 109 x->rx_length++; 110 ret = discard_frame; 111 } 112 if (unlikely(p->des01.rx.mii_error)) { 113 x->rx_mii++; 114 ret = discard_frame; 115 } 116 #ifdef STMMAC_VLAN_TAG_USED 117 if (p->des01.rx.vlan_tag) 118 x->vlan_tag++; 119 #endif 120 return ret; 121 } 122 123 static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode, 124 int end) 125 { 126 p->des01.all_flags = 0; 127 p->des01.rx.own = 1; 128 p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1; 129 130 if (mode == STMMAC_CHAIN_MODE) 131 ndesc_rx_set_on_chain(p, end); 132 else 133 ndesc_rx_set_on_ring(p, end); 134 135 if (disable_rx_ic) 136 p->des01.rx.disable_ic = 1; 137 } 138 139 static void ndesc_init_tx_desc(struct dma_desc *p, int mode, int end) 140 { 141 p->des01.all_flags = 0; 142 if (mode == STMMAC_CHAIN_MODE) 143 ndesc_tx_set_on_chain(p, end); 144 else 145 ndesc_tx_set_on_ring(p, end); 146 } 147 148 static int ndesc_get_tx_owner(struct dma_desc *p) 149 { 150 return p->des01.tx.own; 151 } 152 153 static int ndesc_get_rx_owner(struct dma_desc *p) 154 { 155 return p->des01.rx.own; 156 } 157 158 static void ndesc_set_tx_owner(struct dma_desc *p) 159 { 160 p->des01.tx.own = 1; 161 } 162 163 static void ndesc_set_rx_owner(struct dma_desc *p) 164 { 165 p->des01.rx.own = 1; 166 } 167 168 static int ndesc_get_tx_ls(struct dma_desc *p) 169 { 170 return p->des01.tx.last_segment; 171 } 172 173 static void ndesc_release_tx_desc(struct dma_desc *p, int mode) 174 { 175 int ter = p->des01.tx.end_ring; 176 177 memset(p, 0, offsetof(struct dma_desc, des2)); 178 if (mode == STMMAC_CHAIN_MODE) 179 ndesc_end_tx_desc_on_chain(p, ter); 180 else 181 ndesc_end_tx_desc_on_ring(p, ter); 182 } 183 184 static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 185 int csum_flag, int mode) 186 { 187 p->des01.tx.first_segment = is_fs; 188 if (mode == STMMAC_CHAIN_MODE) 189 norm_set_tx_desc_len_on_chain(p, len); 190 else 191 norm_set_tx_desc_len_on_ring(p, len); 192 193 if (likely(csum_flag)) 194 p->des01.tx.checksum_insertion = cic_full; 195 } 196 197 static void ndesc_clear_tx_ic(struct dma_desc *p) 198 { 199 p->des01.tx.interrupt = 0; 200 } 201 202 static void ndesc_close_tx_desc(struct dma_desc *p) 203 { 204 p->des01.tx.last_segment = 1; 205 p->des01.tx.interrupt = 1; 206 } 207 208 static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type) 209 { 210 /* The type-1 checksum offload engines append the checksum at 211 * the end of frame and the two bytes of checksum are added in 212 * the length. 213 * Adjust for that in the framelen for type-1 checksum offload 214 * engines. */ 215 if (rx_coe_type == STMMAC_RX_COE_TYPE1) 216 return p->des01.rx.frame_length - 2; 217 else 218 return p->des01.rx.frame_length; 219 } 220 221 static void ndesc_enable_tx_timestamp(struct dma_desc *p) 222 { 223 p->des01.tx.time_stamp_enable = 1; 224 } 225 226 static int ndesc_get_tx_timestamp_status(struct dma_desc *p) 227 { 228 return p->des01.tx.time_stamp_status; 229 } 230 231 static u64 ndesc_get_timestamp(void *desc, u32 ats) 232 { 233 struct dma_desc *p = (struct dma_desc *)desc; 234 u64 ns; 235 236 ns = p->des2; 237 /* convert high/sec time stamp value to nanosecond */ 238 ns += p->des3 * 1000000000ULL; 239 240 return ns; 241 } 242 243 static int ndesc_get_rx_timestamp_status(void *desc, u32 ats) 244 { 245 struct dma_desc *p = (struct dma_desc *)desc; 246 247 if ((p->des2 == 0xffffffff) && (p->des3 == 0xffffffff)) 248 /* timestamp is corrupted, hence don't store it */ 249 return 0; 250 else 251 return 1; 252 } 253 254 const struct stmmac_desc_ops ndesc_ops = { 255 .tx_status = ndesc_get_tx_status, 256 .rx_status = ndesc_get_rx_status, 257 .get_tx_len = ndesc_get_tx_len, 258 .init_rx_desc = ndesc_init_rx_desc, 259 .init_tx_desc = ndesc_init_tx_desc, 260 .get_tx_owner = ndesc_get_tx_owner, 261 .get_rx_owner = ndesc_get_rx_owner, 262 .release_tx_desc = ndesc_release_tx_desc, 263 .prepare_tx_desc = ndesc_prepare_tx_desc, 264 .clear_tx_ic = ndesc_clear_tx_ic, 265 .close_tx_desc = ndesc_close_tx_desc, 266 .get_tx_ls = ndesc_get_tx_ls, 267 .set_tx_owner = ndesc_set_tx_owner, 268 .set_rx_owner = ndesc_set_rx_owner, 269 .get_rx_frame_len = ndesc_get_rx_frame_len, 270 .enable_tx_timestamp = ndesc_enable_tx_timestamp, 271 .get_tx_timestamp_status = ndesc_get_tx_timestamp_status, 272 .get_timestamp = ndesc_get_timestamp, 273 .get_rx_timestamp_status = ndesc_get_rx_timestamp_status, 274 }; 275