1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac XGMAC support. 5 */ 6 7 #include <linux/iopoll.h> 8 #include "stmmac.h" 9 #include "dwxgmac2.h" 10 11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) 12 { 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); 14 15 /* DMA SW reset */ 16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); 17 18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, 19 !(value & XGMAC_SWR), 0, 100000); 20 } 21 22 static void dwxgmac2_dma_init(void __iomem *ioaddr, 23 struct stmmac_dma_cfg *dma_cfg, int atds) 24 { 25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 26 27 if (dma_cfg->aal) 28 value |= XGMAC_AAL; 29 30 if (dma_cfg->eame) 31 value |= XGMAC_EAME; 32 33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 34 } 35 36 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, 37 struct stmmac_dma_cfg *dma_cfg, u32 chan) 38 { 39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 40 41 if (dma_cfg->pblx8) 42 value |= XGMAC_PBLx8; 43 44 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 45 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 46 } 47 48 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, 49 struct stmmac_dma_cfg *dma_cfg, 50 dma_addr_t phy, u32 chan) 51 { 52 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 53 u32 value; 54 55 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 56 value &= ~XGMAC_RxPBL; 57 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; 58 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 59 60 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); 61 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); 62 } 63 64 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr, 65 struct stmmac_dma_cfg *dma_cfg, 66 dma_addr_t phy, u32 chan) 67 { 68 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 69 u32 value; 70 71 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 72 value &= ~XGMAC_TxPBL; 73 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL; 74 value |= XGMAC_OSP; 75 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 76 77 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); 78 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); 79 } 80 81 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 82 { 83 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 84 int i; 85 86 if (axi->axi_lpi_en) 87 value |= XGMAC_EN_LPI; 88 if (axi->axi_xit_frm) 89 value |= XGMAC_LPI_XIT_PKT; 90 91 value &= ~XGMAC_WR_OSR_LMT; 92 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) & 93 XGMAC_WR_OSR_LMT; 94 95 value &= ~XGMAC_RD_OSR_LMT; 96 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) & 97 XGMAC_RD_OSR_LMT; 98 99 if (!axi->axi_fb) 100 value |= XGMAC_UNDEF; 101 102 value &= ~XGMAC_BLEN; 103 for (i = 0; i < AXI_BLEN; i++) { 104 switch (axi->axi_blen[i]) { 105 case 256: 106 value |= XGMAC_BLEN256; 107 break; 108 case 128: 109 value |= XGMAC_BLEN128; 110 break; 111 case 64: 112 value |= XGMAC_BLEN64; 113 break; 114 case 32: 115 value |= XGMAC_BLEN32; 116 break; 117 case 16: 118 value |= XGMAC_BLEN16; 119 break; 120 case 8: 121 value |= XGMAC_BLEN8; 122 break; 123 case 4: 124 value |= XGMAC_BLEN4; 125 break; 126 } 127 } 128 129 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 130 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL); 131 writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL); 132 } 133 134 static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space) 135 { 136 int i; 137 138 for (i = (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++) 139 reg_space[i] = readl(ioaddr + i * 4); 140 } 141 142 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, 143 u32 channel, int fifosz, u8 qmode) 144 { 145 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); 146 unsigned int rqs = fifosz / 256 - 1; 147 148 if (mode == SF_DMA_MODE) { 149 value |= XGMAC_RSF; 150 } else { 151 value &= ~XGMAC_RSF; 152 value &= ~XGMAC_RTC; 153 154 if (mode <= 64) 155 value |= 0x0 << XGMAC_RTC_SHIFT; 156 else if (mode <= 96) 157 value |= 0x2 << XGMAC_RTC_SHIFT; 158 else 159 value |= 0x3 << XGMAC_RTC_SHIFT; 160 } 161 162 value &= ~XGMAC_RQS; 163 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; 164 165 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 166 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); 167 unsigned int rfd, rfa; 168 169 value |= XGMAC_EHFC; 170 171 /* Set Threshold for Activating Flow Control to min 2 frames, 172 * i.e. 1500 * 2 = 3000 bytes. 173 * 174 * Set Threshold for Deactivating Flow Control to min 1 frame, 175 * i.e. 1500 bytes. 176 */ 177 switch (fifosz) { 178 case 4096: 179 /* This violates the above formula because of FIFO size 180 * limit therefore overflow may occur in spite of this. 181 */ 182 rfd = 0x03; /* Full-2.5K */ 183 rfa = 0x01; /* Full-1.5K */ 184 break; 185 186 case 8192: 187 rfd = 0x06; /* Full-4K */ 188 rfa = 0x0a; /* Full-6K */ 189 break; 190 191 case 16384: 192 rfd = 0x06; /* Full-4K */ 193 rfa = 0x12; /* Full-10K */ 194 break; 195 196 default: 197 rfd = 0x06; /* Full-4K */ 198 rfa = 0x1e; /* Full-16K */ 199 break; 200 } 201 202 flow &= ~XGMAC_RFD; 203 flow |= rfd << XGMAC_RFD_SHIFT; 204 205 flow &= ~XGMAC_RFA; 206 flow |= rfa << XGMAC_RFA_SHIFT; 207 208 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); 209 } 210 211 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); 212 213 /* Enable MTL RX overflow */ 214 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); 215 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); 216 } 217 218 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode, 219 u32 channel, int fifosz, u8 qmode) 220 { 221 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 222 unsigned int tqs = fifosz / 256 - 1; 223 224 if (mode == SF_DMA_MODE) { 225 value |= XGMAC_TSF; 226 } else { 227 value &= ~XGMAC_TSF; 228 value &= ~XGMAC_TTC; 229 230 if (mode <= 64) 231 value |= 0x0 << XGMAC_TTC_SHIFT; 232 else if (mode <= 96) 233 value |= 0x2 << XGMAC_TTC_SHIFT; 234 else if (mode <= 128) 235 value |= 0x3 << XGMAC_TTC_SHIFT; 236 else if (mode <= 192) 237 value |= 0x4 << XGMAC_TTC_SHIFT; 238 else if (mode <= 256) 239 value |= 0x5 << XGMAC_TTC_SHIFT; 240 else if (mode <= 384) 241 value |= 0x6 << XGMAC_TTC_SHIFT; 242 else 243 value |= 0x7 << XGMAC_TTC_SHIFT; 244 } 245 246 /* Use static TC to Queue mapping */ 247 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP; 248 249 value &= ~XGMAC_TXQEN; 250 if (qmode != MTL_QUEUE_AVB) 251 value |= 0x2 << XGMAC_TXQEN_SHIFT; 252 else 253 value |= 0x1 << XGMAC_TXQEN_SHIFT; 254 255 value &= ~XGMAC_TQS; 256 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS; 257 258 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 259 } 260 261 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan) 262 { 263 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 264 } 265 266 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan) 267 { 268 writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 269 } 270 271 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan) 272 { 273 u32 value; 274 275 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 276 value |= XGMAC_TXST; 277 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 278 279 value = readl(ioaddr + XGMAC_TX_CONFIG); 280 value |= XGMAC_CONFIG_TE; 281 writel(value, ioaddr + XGMAC_TX_CONFIG); 282 } 283 284 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan) 285 { 286 u32 value; 287 288 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 289 value &= ~XGMAC_TXST; 290 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 291 292 value = readl(ioaddr + XGMAC_TX_CONFIG); 293 value &= ~XGMAC_CONFIG_TE; 294 writel(value, ioaddr + XGMAC_TX_CONFIG); 295 } 296 297 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan) 298 { 299 u32 value; 300 301 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 302 value |= XGMAC_RXST; 303 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 304 305 value = readl(ioaddr + XGMAC_RX_CONFIG); 306 value |= XGMAC_CONFIG_RE; 307 writel(value, ioaddr + XGMAC_RX_CONFIG); 308 } 309 310 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan) 311 { 312 u32 value; 313 314 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 315 value &= ~XGMAC_RXST; 316 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 317 } 318 319 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr, 320 struct stmmac_extra_stats *x, u32 chan) 321 { 322 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan)); 323 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 324 int ret = 0; 325 326 /* ABNORMAL interrupts */ 327 if (unlikely(intr_status & XGMAC_AIS)) { 328 if (unlikely(intr_status & XGMAC_RBU)) { 329 x->rx_buf_unav_irq++; 330 ret |= handle_rx; 331 } 332 if (unlikely(intr_status & XGMAC_TPS)) { 333 x->tx_process_stopped_irq++; 334 ret |= tx_hard_error; 335 } 336 if (unlikely(intr_status & XGMAC_FBE)) { 337 x->fatal_bus_error_irq++; 338 ret |= tx_hard_error; 339 } 340 } 341 342 /* TX/RX NORMAL interrupts */ 343 if (likely(intr_status & XGMAC_NIS)) { 344 x->normal_irq_n++; 345 346 if (likely(intr_status & XGMAC_RI)) { 347 x->rx_normal_irq_n++; 348 ret |= handle_rx; 349 } 350 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { 351 x->tx_normal_irq_n++; 352 ret |= handle_tx; 353 } 354 } 355 356 /* Clear interrupts */ 357 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); 358 359 return ret; 360 } 361 362 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr, 363 struct dma_features *dma_cap) 364 { 365 u32 hw_cap; 366 367 /* MAC HW feature 0 */ 368 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0); 369 dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27; 370 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16; 371 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14; 372 dma_cap->eee = (hw_cap & XGMAC_HWFEAT_EEESEL) >> 13; 373 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12; 374 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11; 375 dma_cap->av &= !((hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10); 376 dma_cap->arpoffsel = (hw_cap & XGMAC_HWFEAT_ARPOFFSEL) >> 9; 377 dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8; 378 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7; 379 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6; 380 dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4; 381 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; 382 383 /* MAC HW feature 1 */ 384 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1); 385 dma_cap->l3l4fnum = (hw_cap & XGMAC_HWFEAT_L3L4FNUM) >> 27; 386 dma_cap->hash_tb_sz = (hw_cap & XGMAC_HWFEAT_HASHTBLSZ) >> 24; 387 dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20; 388 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18; 389 dma_cap->sphen = (hw_cap & XGMAC_HWFEAT_SPHEN) >> 17; 390 391 dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14; 392 switch (dma_cap->addr64) { 393 case 0: 394 dma_cap->addr64 = 32; 395 break; 396 case 1: 397 dma_cap->addr64 = 40; 398 break; 399 case 2: 400 dma_cap->addr64 = 48; 401 break; 402 default: 403 dma_cap->addr64 = 32; 404 break; 405 } 406 407 dma_cap->tx_fifo_size = 408 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6); 409 dma_cap->rx_fifo_size = 410 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0); 411 412 /* MAC HW feature 2 */ 413 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2); 414 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24; 415 dma_cap->number_tx_channel = 416 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1; 417 dma_cap->number_rx_channel = 418 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1; 419 dma_cap->number_tx_queues = 420 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1; 421 dma_cap->number_rx_queues = 422 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1; 423 424 /* MAC HW feature 3 */ 425 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3); 426 dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14; 427 dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13; 428 dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11; 429 dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9; 430 dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3; 431 } 432 433 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan) 434 { 435 u32 i; 436 437 for (i = 0; i < nchan; i++) 438 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i)); 439 } 440 441 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 442 { 443 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan)); 444 } 445 446 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 447 { 448 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan)); 449 } 450 451 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) 452 { 453 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan)); 454 } 455 456 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) 457 { 458 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan)); 459 } 460 461 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 462 { 463 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 464 465 if (en) 466 value |= XGMAC_TSE; 467 else 468 value &= ~XGMAC_TSE; 469 470 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 471 } 472 473 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 474 { 475 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 476 u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL); 477 478 value &= ~XGMAC_TXQEN; 479 if (qmode != MTL_QUEUE_AVB) { 480 value |= 0x2 << XGMAC_TXQEN_SHIFT; 481 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel)); 482 } else { 483 value |= 0x1 << XGMAC_TXQEN_SHIFT; 484 writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL); 485 } 486 487 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 488 } 489 490 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 491 { 492 u32 value; 493 494 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 495 value |= bfsize << 1; 496 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 497 } 498 499 static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan) 500 { 501 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); 502 503 value &= ~XGMAC_CONFIG_HDSMS; 504 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ 505 writel(value, ioaddr + XGMAC_RX_CONFIG); 506 507 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 508 if (en) 509 value |= XGMAC_SPH; 510 else 511 value &= ~XGMAC_SPH; 512 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 513 } 514 515 const struct stmmac_dma_ops dwxgmac210_dma_ops = { 516 .reset = dwxgmac2_dma_reset, 517 .init = dwxgmac2_dma_init, 518 .init_chan = dwxgmac2_dma_init_chan, 519 .init_rx_chan = dwxgmac2_dma_init_rx_chan, 520 .init_tx_chan = dwxgmac2_dma_init_tx_chan, 521 .axi = dwxgmac2_dma_axi, 522 .dump_regs = dwxgmac2_dma_dump_regs, 523 .dma_rx_mode = dwxgmac2_dma_rx_mode, 524 .dma_tx_mode = dwxgmac2_dma_tx_mode, 525 .enable_dma_irq = dwxgmac2_enable_dma_irq, 526 .disable_dma_irq = dwxgmac2_disable_dma_irq, 527 .start_tx = dwxgmac2_dma_start_tx, 528 .stop_tx = dwxgmac2_dma_stop_tx, 529 .start_rx = dwxgmac2_dma_start_rx, 530 .stop_rx = dwxgmac2_dma_stop_rx, 531 .dma_interrupt = dwxgmac2_dma_interrupt, 532 .get_hw_feature = dwxgmac2_get_hw_feature, 533 .rx_watchdog = dwxgmac2_rx_watchdog, 534 .set_rx_ring_len = dwxgmac2_set_rx_ring_len, 535 .set_tx_ring_len = dwxgmac2_set_tx_ring_len, 536 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr, 537 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr, 538 .enable_tso = dwxgmac2_enable_tso, 539 .qmode = dwxgmac2_qmode, 540 .set_bfsize = dwxgmac2_set_bfsize, 541 .enable_sph = dwxgmac2_enable_sph, 542 }; 543