1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac XGMAC support. 5 */ 6 7 #include <linux/stmmac.h> 8 #include "common.h" 9 #include "dwxgmac2.h" 10 11 static int dwxgmac2_get_tx_status(void *data, struct stmmac_extra_stats *x, 12 struct dma_desc *p, void __iomem *ioaddr) 13 { 14 unsigned int tdes3 = le32_to_cpu(p->des3); 15 int ret = tx_done; 16 17 if (unlikely(tdes3 & XGMAC_TDES3_OWN)) 18 return tx_dma_own; 19 if (likely(!(tdes3 & XGMAC_TDES3_LD))) 20 return tx_not_ls; 21 22 return ret; 23 } 24 25 static int dwxgmac2_get_rx_status(void *data, struct stmmac_extra_stats *x, 26 struct dma_desc *p) 27 { 28 unsigned int rdes3 = le32_to_cpu(p->des3); 29 30 if (unlikely(rdes3 & XGMAC_RDES3_OWN)) 31 return dma_own; 32 if (unlikely(rdes3 & XGMAC_RDES3_CTXT)) 33 return discard_frame; 34 if (likely(!(rdes3 & XGMAC_RDES3_LD))) 35 return rx_not_ls; 36 if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD))) 37 return discard_frame; 38 39 return good_frame; 40 } 41 42 static int dwxgmac2_get_tx_len(struct dma_desc *p) 43 { 44 return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L); 45 } 46 47 static int dwxgmac2_get_tx_owner(struct dma_desc *p) 48 { 49 return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0; 50 } 51 52 static void dwxgmac2_set_tx_owner(struct dma_desc *p) 53 { 54 p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN); 55 } 56 57 static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic) 58 { 59 p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN); 60 61 if (!disable_rx_ic) 62 p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC); 63 } 64 65 static int dwxgmac2_get_tx_ls(struct dma_desc *p) 66 { 67 return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0; 68 } 69 70 static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe) 71 { 72 return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL); 73 } 74 75 static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p) 76 { 77 p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE); 78 } 79 80 static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p) 81 { 82 return 0; /* Not supported */ 83 } 84 85 static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts) 86 { 87 struct dma_desc *p = (struct dma_desc *)desc; 88 u64 ns = 0; 89 90 ns += le32_to_cpu(p->des1) * 1000000000ULL; 91 ns += le32_to_cpu(p->des0); 92 93 *ts = ns; 94 } 95 96 static int dwxgmac2_rx_check_timestamp(void *desc) 97 { 98 struct dma_desc *p = (struct dma_desc *)desc; 99 unsigned int rdes3 = le32_to_cpu(p->des3); 100 bool desc_valid, ts_valid; 101 102 dma_rmb(); 103 104 desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT); 105 ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA); 106 107 if (likely(desc_valid && ts_valid)) { 108 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff)) 109 return -EINVAL; 110 return 0; 111 } 112 113 return -EINVAL; 114 } 115 116 static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc, 117 u32 ats) 118 { 119 struct dma_desc *p = (struct dma_desc *)desc; 120 unsigned int rdes3 = le32_to_cpu(p->des3); 121 int ret = -EBUSY; 122 123 if (likely(rdes3 & XGMAC_RDES3_CDA)) 124 ret = dwxgmac2_rx_check_timestamp(next_desc); 125 126 return !ret; 127 } 128 129 static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic, 130 int mode, int end, int bfsize) 131 { 132 dwxgmac2_set_rx_owner(p, disable_rx_ic); 133 } 134 135 static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end) 136 { 137 p->des0 = 0; 138 p->des1 = 0; 139 p->des2 = 0; 140 p->des3 = 0; 141 } 142 143 static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 144 bool csum_flag, int mode, bool tx_own, 145 bool ls, unsigned int tot_pkt_len) 146 { 147 unsigned int tdes3 = le32_to_cpu(p->des3); 148 149 p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L); 150 151 tdes3 |= tot_pkt_len & XGMAC_TDES3_FL; 152 if (is_fs) 153 tdes3 |= XGMAC_TDES3_FD; 154 else 155 tdes3 &= ~XGMAC_TDES3_FD; 156 157 if (csum_flag) 158 tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT; 159 else 160 tdes3 &= ~XGMAC_TDES3_CIC; 161 162 if (ls) 163 tdes3 |= XGMAC_TDES3_LD; 164 else 165 tdes3 &= ~XGMAC_TDES3_LD; 166 167 /* Finally set the OWN bit. Later the DMA will start! */ 168 if (tx_own) 169 tdes3 |= XGMAC_TDES3_OWN; 170 171 if (is_fs && tx_own) 172 /* When the own bit, for the first frame, has to be set, all 173 * descriptors for the same frame has to be set before, to 174 * avoid race condition. 175 */ 176 dma_wmb(); 177 178 p->des3 = cpu_to_le32(tdes3); 179 } 180 181 static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs, 182 int len1, int len2, bool tx_own, 183 bool ls, unsigned int tcphdrlen, 184 unsigned int tcppayloadlen) 185 { 186 unsigned int tdes3 = le32_to_cpu(p->des3); 187 188 if (len1) 189 p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L); 190 if (len2) 191 p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) & 192 XGMAC_TDES2_B2L); 193 if (is_fs) { 194 tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE; 195 tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) & 196 XGMAC_TDES3_THL; 197 tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL; 198 } else { 199 tdes3 &= ~XGMAC_TDES3_FD; 200 } 201 202 if (ls) 203 tdes3 |= XGMAC_TDES3_LD; 204 else 205 tdes3 &= ~XGMAC_TDES3_LD; 206 207 /* Finally set the OWN bit. Later the DMA will start! */ 208 if (tx_own) 209 tdes3 |= XGMAC_TDES3_OWN; 210 211 if (is_fs && tx_own) 212 /* When the own bit, for the first frame, has to be set, all 213 * descriptors for the same frame has to be set before, to 214 * avoid race condition. 215 */ 216 dma_wmb(); 217 218 p->des3 = cpu_to_le32(tdes3); 219 } 220 221 static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode) 222 { 223 p->des0 = 0; 224 p->des1 = 0; 225 p->des2 = 0; 226 p->des3 = 0; 227 } 228 229 static void dwxgmac2_set_tx_ic(struct dma_desc *p) 230 { 231 p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC); 232 } 233 234 static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss) 235 { 236 p->des0 = 0; 237 p->des1 = 0; 238 p->des2 = cpu_to_le32(mss); 239 p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV); 240 } 241 242 static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr) 243 { 244 p->des0 = cpu_to_le32(lower_32_bits(addr)); 245 p->des1 = cpu_to_le32(upper_32_bits(addr)); 246 } 247 248 static void dwxgmac2_clear(struct dma_desc *p) 249 { 250 p->des0 = 0; 251 p->des1 = 0; 252 p->des2 = 0; 253 p->des3 = 0; 254 } 255 256 static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash, 257 enum pkt_hash_types *type) 258 { 259 unsigned int rdes3 = le32_to_cpu(p->des3); 260 u32 ptype; 261 262 if (rdes3 & XGMAC_RDES3_RSV) { 263 ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT; 264 265 switch (ptype) { 266 case XGMAC_L34T_IP4TCP: 267 case XGMAC_L34T_IP4UDP: 268 case XGMAC_L34T_IP6TCP: 269 case XGMAC_L34T_IP6UDP: 270 *type = PKT_HASH_TYPE_L4; 271 break; 272 default: 273 *type = PKT_HASH_TYPE_L3; 274 break; 275 } 276 277 *hash = le32_to_cpu(p->des1); 278 return 0; 279 } 280 281 return -EINVAL; 282 } 283 284 static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len) 285 { 286 if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T) 287 *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; 288 } 289 290 static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid) 291 { 292 p->des2 = cpu_to_le32(lower_32_bits(addr)); 293 p->des3 = cpu_to_le32(upper_32_bits(addr)); 294 } 295 296 static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type) 297 { 298 sarc_type <<= XGMAC_TDES3_SAIC_SHIFT; 299 300 p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC); 301 } 302 303 static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag, 304 u32 inner_type) 305 { 306 p->des0 = 0; 307 p->des1 = 0; 308 p->des2 = 0; 309 p->des3 = 0; 310 311 /* Inner VLAN */ 312 if (inner_type) { 313 u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT; 314 315 des &= XGMAC_TDES2_IVT; 316 p->des2 = cpu_to_le32(des); 317 318 des = inner_type << XGMAC_TDES3_IVTIR_SHIFT; 319 des &= XGMAC_TDES3_IVTIR; 320 p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV); 321 } 322 323 /* Outer VLAN */ 324 p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT); 325 p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV); 326 327 p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT); 328 } 329 330 static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type) 331 { 332 type <<= XGMAC_TDES2_VTIR_SHIFT; 333 p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR); 334 } 335 336 static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec) 337 { 338 p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV); 339 p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT); 340 p->des6 = 0; 341 p->des7 = 0; 342 } 343 344 const struct stmmac_desc_ops dwxgmac210_desc_ops = { 345 .tx_status = dwxgmac2_get_tx_status, 346 .rx_status = dwxgmac2_get_rx_status, 347 .get_tx_len = dwxgmac2_get_tx_len, 348 .get_tx_owner = dwxgmac2_get_tx_owner, 349 .set_tx_owner = dwxgmac2_set_tx_owner, 350 .set_rx_owner = dwxgmac2_set_rx_owner, 351 .get_tx_ls = dwxgmac2_get_tx_ls, 352 .get_rx_frame_len = dwxgmac2_get_rx_frame_len, 353 .enable_tx_timestamp = dwxgmac2_enable_tx_timestamp, 354 .get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status, 355 .get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status, 356 .get_timestamp = dwxgmac2_get_timestamp, 357 .set_tx_ic = dwxgmac2_set_tx_ic, 358 .prepare_tx_desc = dwxgmac2_prepare_tx_desc, 359 .prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc, 360 .release_tx_desc = dwxgmac2_release_tx_desc, 361 .init_rx_desc = dwxgmac2_init_rx_desc, 362 .init_tx_desc = dwxgmac2_init_tx_desc, 363 .set_mss = dwxgmac2_set_mss, 364 .set_addr = dwxgmac2_set_addr, 365 .clear = dwxgmac2_clear, 366 .get_rx_hash = dwxgmac2_get_rx_hash, 367 .get_rx_header_len = dwxgmac2_get_rx_header_len, 368 .set_sec_addr = dwxgmac2_set_sec_addr, 369 .set_sarc = dwxgmac2_set_sarc, 370 .set_vlan_tag = dwxgmac2_set_vlan_tag, 371 .set_vlan = dwxgmac2_set_vlan, 372 .set_tbs = dwxgmac2_set_tbs, 373 }; 374