1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include "common.h" 12 #include "dwmac_dma.h" 13 14 #define GMAC_HI_REG_AE 0x80000000 15 16 int dwmac_dma_reset(void __iomem *ioaddr) 17 { 18 u32 value = readl(ioaddr + DMA_BUS_MODE); 19 20 /* DMA SW reset */ 21 value |= DMA_BUS_MODE_SFT_RESET; 22 writel(value, ioaddr + DMA_BUS_MODE); 23 24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 25 !(value & DMA_BUS_MODE_SFT_RESET), 26 10000, 200000); 27 } 28 29 /* CSR1 enables the transmit DMA to check for new descriptor */ 30 void dwmac_enable_dma_transmission(void __iomem *ioaddr) 31 { 32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 33 } 34 35 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 36 u32 chan, bool rx, bool tx) 37 { 38 u32 value = readl(ioaddr + DMA_INTR_ENA); 39 40 if (rx) 41 value |= DMA_INTR_DEFAULT_RX; 42 if (tx) 43 value |= DMA_INTR_DEFAULT_TX; 44 45 writel(value, ioaddr + DMA_INTR_ENA); 46 } 47 48 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 49 u32 chan, bool rx, bool tx) 50 { 51 u32 value = readl(ioaddr + DMA_INTR_ENA); 52 53 if (rx) 54 value &= ~DMA_INTR_DEFAULT_RX; 55 if (tx) 56 value &= ~DMA_INTR_DEFAULT_TX; 57 58 writel(value, ioaddr + DMA_INTR_ENA); 59 } 60 61 void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 62 u32 chan) 63 { 64 u32 value = readl(ioaddr + DMA_CONTROL); 65 value |= DMA_CONTROL_ST; 66 writel(value, ioaddr + DMA_CONTROL); 67 } 68 69 void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) 70 { 71 u32 value = readl(ioaddr + DMA_CONTROL); 72 value &= ~DMA_CONTROL_ST; 73 writel(value, ioaddr + DMA_CONTROL); 74 } 75 76 void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 77 u32 chan) 78 { 79 u32 value = readl(ioaddr + DMA_CONTROL); 80 value |= DMA_CONTROL_SR; 81 writel(value, ioaddr + DMA_CONTROL); 82 } 83 84 void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) 85 { 86 u32 value = readl(ioaddr + DMA_CONTROL); 87 value &= ~DMA_CONTROL_SR; 88 writel(value, ioaddr + DMA_CONTROL); 89 } 90 91 #ifdef DWMAC_DMA_DEBUG 92 static void show_tx_process_state(unsigned int status) 93 { 94 unsigned int state; 95 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 96 97 switch (state) { 98 case 0: 99 pr_debug("- TX (Stopped): Reset or Stop command\n"); 100 break; 101 case 1: 102 pr_debug("- TX (Running): Fetching the Tx desc\n"); 103 break; 104 case 2: 105 pr_debug("- TX (Running): Waiting for end of tx\n"); 106 break; 107 case 3: 108 pr_debug("- TX (Running): Reading the data " 109 "and queuing the data into the Tx buf\n"); 110 break; 111 case 6: 112 pr_debug("- TX (Suspended): Tx Buff Underflow " 113 "or an unavailable Transmit descriptor\n"); 114 break; 115 case 7: 116 pr_debug("- TX (Running): Closing Tx descriptor\n"); 117 break; 118 default: 119 break; 120 } 121 } 122 123 static void show_rx_process_state(unsigned int status) 124 { 125 unsigned int state; 126 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 127 128 switch (state) { 129 case 0: 130 pr_debug("- RX (Stopped): Reset or Stop command\n"); 131 break; 132 case 1: 133 pr_debug("- RX (Running): Fetching the Rx desc\n"); 134 break; 135 case 2: 136 pr_debug("- RX (Running): Checking for end of pkt\n"); 137 break; 138 case 3: 139 pr_debug("- RX (Running): Waiting for Rx pkt\n"); 140 break; 141 case 4: 142 pr_debug("- RX (Suspended): Unavailable Rx buf\n"); 143 break; 144 case 5: 145 pr_debug("- RX (Running): Closing Rx descriptor\n"); 146 break; 147 case 6: 148 pr_debug("- RX(Running): Flushing the current frame" 149 " from the Rx buf\n"); 150 break; 151 case 7: 152 pr_debug("- RX (Running): Queuing the Rx frame" 153 " from the Rx buf into memory\n"); 154 break; 155 default: 156 break; 157 } 158 } 159 #endif 160 161 int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, 162 struct stmmac_extra_stats *x, u32 chan, u32 dir) 163 { 164 int ret = 0; 165 /* read the status register (CSR5) */ 166 u32 intr_status = readl(ioaddr + DMA_STATUS); 167 168 #ifdef DWMAC_DMA_DEBUG 169 /* Enable it to monitor DMA rx/tx status in case of critical problems */ 170 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status); 171 show_tx_process_state(intr_status); 172 show_rx_process_state(intr_status); 173 #endif 174 175 if (dir == DMA_DIR_RX) 176 intr_status &= DMA_STATUS_MSK_RX; 177 else if (dir == DMA_DIR_TX) 178 intr_status &= DMA_STATUS_MSK_TX; 179 180 /* ABNORMAL interrupts */ 181 if (unlikely(intr_status & DMA_STATUS_AIS)) { 182 if (unlikely(intr_status & DMA_STATUS_UNF)) { 183 ret = tx_hard_error_bump_tc; 184 x->tx_undeflow_irq++; 185 } 186 if (unlikely(intr_status & DMA_STATUS_TJT)) 187 x->tx_jabber_irq++; 188 189 if (unlikely(intr_status & DMA_STATUS_OVF)) 190 x->rx_overflow_irq++; 191 192 if (unlikely(intr_status & DMA_STATUS_RU)) 193 x->rx_buf_unav_irq++; 194 if (unlikely(intr_status & DMA_STATUS_RPS)) 195 x->rx_process_stopped_irq++; 196 if (unlikely(intr_status & DMA_STATUS_RWT)) 197 x->rx_watchdog_irq++; 198 if (unlikely(intr_status & DMA_STATUS_ETI)) 199 x->tx_early_irq++; 200 if (unlikely(intr_status & DMA_STATUS_TPS)) { 201 x->tx_process_stopped_irq++; 202 ret = tx_hard_error; 203 } 204 if (unlikely(intr_status & DMA_STATUS_FBI)) { 205 x->fatal_bus_error_irq++; 206 ret = tx_hard_error; 207 } 208 } 209 /* TX/RX NORMAL interrupts */ 210 if (likely(intr_status & DMA_STATUS_NIS)) { 211 x->normal_irq_n++; 212 if (likely(intr_status & DMA_STATUS_RI)) { 213 u32 value = readl(ioaddr + DMA_INTR_ENA); 214 /* to schedule NAPI on real RIE event. */ 215 if (likely(value & DMA_INTR_ENA_RIE)) { 216 x->rx_normal_irq_n++; 217 ret |= handle_rx; 218 } 219 } 220 if (likely(intr_status & DMA_STATUS_TI)) { 221 x->tx_normal_irq_n++; 222 ret |= handle_tx; 223 } 224 if (unlikely(intr_status & DMA_STATUS_ERI)) 225 x->rx_early_irq++; 226 } 227 /* Optional hardware blocks, interrupts should be disabled */ 228 if (unlikely(intr_status & 229 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 230 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 231 232 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 233 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 234 235 return ret; 236 } 237 238 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) 239 { 240 u32 csr6 = readl(ioaddr + DMA_CONTROL); 241 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 242 243 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 244 } 245 246 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 247 unsigned int high, unsigned int low) 248 { 249 unsigned long data; 250 251 data = (addr[5] << 8) | addr[4]; 252 /* For MAC Addr registers we have to set the Address Enable (AE) 253 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 254 * is RO. 255 */ 256 writel(data | GMAC_HI_REG_AE, ioaddr + high); 257 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 258 writel(data, ioaddr + low); 259 } 260 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr); 261 262 /* Enable disable MAC RX/TX */ 263 void stmmac_set_mac(void __iomem *ioaddr, bool enable) 264 { 265 u32 old_val, value; 266 267 old_val = readl(ioaddr + MAC_CTRL_REG); 268 value = old_val; 269 270 if (enable) 271 value |= MAC_ENABLE_RX | MAC_ENABLE_TX; 272 else 273 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); 274 275 if (value != old_val) 276 writel(value, ioaddr + MAC_CTRL_REG); 277 } 278 279 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 280 unsigned int high, unsigned int low) 281 { 282 unsigned int hi_addr, lo_addr; 283 284 /* Read the MAC address from the hardware */ 285 hi_addr = readl(ioaddr + high); 286 lo_addr = readl(ioaddr + low); 287 288 /* Extract the MAC address from the high and low words */ 289 addr[0] = lo_addr & 0xff; 290 addr[1] = (lo_addr >> 8) & 0xff; 291 addr[2] = (lo_addr >> 16) & 0xff; 292 addr[3] = (lo_addr >> 24) & 0xff; 293 addr[4] = hi_addr & 0xff; 294 addr[5] = (hi_addr >> 8) & 0xff; 295 } 296 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr); 297