1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include "common.h" 12 #include "dwmac_dma.h" 13 #include "stmmac.h" 14 15 #define GMAC_HI_REG_AE 0x80000000 16 17 int dwmac_dma_reset(void __iomem *ioaddr) 18 { 19 u32 value = readl(ioaddr + DMA_BUS_MODE); 20 21 /* DMA SW reset */ 22 value |= DMA_BUS_MODE_SFT_RESET; 23 writel(value, ioaddr + DMA_BUS_MODE); 24 25 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 26 !(value & DMA_BUS_MODE_SFT_RESET), 27 10000, 200000); 28 } 29 30 /* CSR1 enables the transmit DMA to check for new descriptor */ 31 void dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan) 32 { 33 writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan)); 34 } 35 36 void dwmac_enable_dma_reception(void __iomem *ioaddr, u32 chan) 37 { 38 writel(1, ioaddr + DMA_CHAN_RCV_POLL_DEMAND(chan)); 39 } 40 41 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 42 u32 chan, bool rx, bool tx) 43 { 44 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); 45 46 if (rx) 47 value |= DMA_INTR_DEFAULT_RX; 48 if (tx) 49 value |= DMA_INTR_DEFAULT_TX; 50 51 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); 52 } 53 54 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 55 u32 chan, bool rx, bool tx) 56 { 57 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); 58 59 if (rx) 60 value &= ~DMA_INTR_DEFAULT_RX; 61 if (tx) 62 value &= ~DMA_INTR_DEFAULT_TX; 63 64 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); 65 } 66 67 void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 68 u32 chan) 69 { 70 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 71 value |= DMA_CONTROL_ST; 72 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 73 } 74 75 void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) 76 { 77 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 78 value &= ~DMA_CONTROL_ST; 79 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 80 } 81 82 void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 83 u32 chan) 84 { 85 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 86 value |= DMA_CONTROL_SR; 87 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 88 } 89 90 void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) 91 { 92 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 93 value &= ~DMA_CONTROL_SR; 94 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 95 } 96 97 #ifdef DWMAC_DMA_DEBUG 98 static void show_tx_process_state(unsigned int status) 99 { 100 unsigned int state; 101 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 102 103 switch (state) { 104 case 0: 105 pr_debug("- TX (Stopped): Reset or Stop command\n"); 106 break; 107 case 1: 108 pr_debug("- TX (Running): Fetching the Tx desc\n"); 109 break; 110 case 2: 111 pr_debug("- TX (Running): Waiting for end of tx\n"); 112 break; 113 case 3: 114 pr_debug("- TX (Running): Reading the data " 115 "and queuing the data into the Tx buf\n"); 116 break; 117 case 6: 118 pr_debug("- TX (Suspended): Tx Buff Underflow " 119 "or an unavailable Transmit descriptor\n"); 120 break; 121 case 7: 122 pr_debug("- TX (Running): Closing Tx descriptor\n"); 123 break; 124 default: 125 break; 126 } 127 } 128 129 static void show_rx_process_state(unsigned int status) 130 { 131 unsigned int state; 132 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 133 134 switch (state) { 135 case 0: 136 pr_debug("- RX (Stopped): Reset or Stop command\n"); 137 break; 138 case 1: 139 pr_debug("- RX (Running): Fetching the Rx desc\n"); 140 break; 141 case 2: 142 pr_debug("- RX (Running): Checking for end of pkt\n"); 143 break; 144 case 3: 145 pr_debug("- RX (Running): Waiting for Rx pkt\n"); 146 break; 147 case 4: 148 pr_debug("- RX (Suspended): Unavailable Rx buf\n"); 149 break; 150 case 5: 151 pr_debug("- RX (Running): Closing Rx descriptor\n"); 152 break; 153 case 6: 154 pr_debug("- RX(Running): Flushing the current frame" 155 " from the Rx buf\n"); 156 break; 157 case 7: 158 pr_debug("- RX (Running): Queuing the Rx frame" 159 " from the Rx buf into memory\n"); 160 break; 161 default: 162 break; 163 } 164 } 165 #endif 166 167 int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, 168 struct stmmac_extra_stats *x, u32 chan, u32 dir) 169 { 170 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats); 171 int ret = 0; 172 /* read the status register (CSR5) */ 173 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); 174 175 #ifdef DWMAC_DMA_DEBUG 176 /* Enable it to monitor DMA rx/tx status in case of critical problems */ 177 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status); 178 show_tx_process_state(intr_status); 179 show_rx_process_state(intr_status); 180 #endif 181 182 if (dir == DMA_DIR_RX) 183 intr_status &= DMA_STATUS_MSK_RX; 184 else if (dir == DMA_DIR_TX) 185 intr_status &= DMA_STATUS_MSK_TX; 186 187 /* ABNORMAL interrupts */ 188 if (unlikely(intr_status & DMA_STATUS_AIS)) { 189 if (unlikely(intr_status & DMA_STATUS_UNF)) { 190 ret = tx_hard_error_bump_tc; 191 x->tx_undeflow_irq++; 192 } 193 if (unlikely(intr_status & DMA_STATUS_TJT)) 194 x->tx_jabber_irq++; 195 196 if (unlikely(intr_status & DMA_STATUS_OVF)) 197 x->rx_overflow_irq++; 198 199 if (unlikely(intr_status & DMA_STATUS_RU)) 200 x->rx_buf_unav_irq++; 201 if (unlikely(intr_status & DMA_STATUS_RPS)) 202 x->rx_process_stopped_irq++; 203 if (unlikely(intr_status & DMA_STATUS_RWT)) 204 x->rx_watchdog_irq++; 205 if (unlikely(intr_status & DMA_STATUS_ETI)) 206 x->tx_early_irq++; 207 if (unlikely(intr_status & DMA_STATUS_TPS)) { 208 x->tx_process_stopped_irq++; 209 ret = tx_hard_error; 210 } 211 if (unlikely(intr_status & DMA_STATUS_FBI)) { 212 x->fatal_bus_error_irq++; 213 ret = tx_hard_error; 214 } 215 } 216 /* TX/RX NORMAL interrupts */ 217 if (likely(intr_status & DMA_STATUS_NIS)) { 218 if (likely(intr_status & DMA_STATUS_RI)) { 219 u32 value = readl(ioaddr + DMA_INTR_ENA); 220 /* to schedule NAPI on real RIE event. */ 221 if (likely(value & DMA_INTR_ENA_RIE)) { 222 u64_stats_update_begin(&stats->syncp); 223 u64_stats_inc(&stats->rx_normal_irq_n[chan]); 224 u64_stats_update_end(&stats->syncp); 225 ret |= handle_rx; 226 } 227 } 228 if (likely(intr_status & DMA_STATUS_TI)) { 229 u64_stats_update_begin(&stats->syncp); 230 u64_stats_inc(&stats->tx_normal_irq_n[chan]); 231 u64_stats_update_end(&stats->syncp); 232 ret |= handle_tx; 233 } 234 if (unlikely(intr_status & DMA_STATUS_ERI)) 235 x->rx_early_irq++; 236 } 237 /* Optional hardware blocks, interrupts should be disabled */ 238 if (unlikely(intr_status & 239 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 240 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 241 242 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 243 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 244 245 return ret; 246 } 247 248 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) 249 { 250 u32 csr6 = readl(ioaddr + DMA_CONTROL); 251 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 252 253 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 254 } 255 256 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 257 unsigned int high, unsigned int low) 258 { 259 u32 data; 260 261 data = (addr[5] << 8) | addr[4]; 262 /* For MAC Addr registers we have to set the Address Enable (AE) 263 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 264 * is RO. 265 */ 266 writel(data | GMAC_HI_REG_AE, ioaddr + high); 267 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 268 writel(data, ioaddr + low); 269 } 270 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr); 271 272 /* Enable disable MAC RX/TX */ 273 void stmmac_set_mac(void __iomem *ioaddr, bool enable) 274 { 275 u32 old_val, value; 276 277 old_val = readl(ioaddr + MAC_CTRL_REG); 278 value = old_val; 279 280 if (enable) 281 value |= MAC_ENABLE_RX | MAC_ENABLE_TX; 282 else 283 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); 284 285 if (value != old_val) 286 writel(value, ioaddr + MAC_CTRL_REG); 287 } 288 289 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 290 unsigned int high, unsigned int low) 291 { 292 unsigned int hi_addr, lo_addr; 293 294 /* Read the MAC address from the hardware */ 295 hi_addr = readl(ioaddr + high); 296 lo_addr = readl(ioaddr + low); 297 298 /* Extract the MAC address from the high and low words */ 299 addr[0] = lo_addr & 0xff; 300 addr[1] = (lo_addr >> 8) & 0xff; 301 addr[2] = (lo_addr >> 16) & 0xff; 302 addr[3] = (lo_addr >> 24) & 0xff; 303 addr[4] = hi_addr & 0xff; 304 addr[5] = (hi_addr >> 8) & 0xff; 305 } 306 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr); 307