1 /******************************************************************************* 2 DWMAC DMA Header file. 3 4 Copyright (C) 2007-2009 STMicroelectronics Ltd 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 23 *******************************************************************************/ 24 25 #ifndef __DWMAC_DMA_H__ 26 #define __DWMAC_DMA_H__ 27 28 /* DMA CRS Control and Status Register Mapping */ 29 #define DMA_BUS_MODE 0x00001000 /* Bus Mode */ 30 #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */ 31 #define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */ 32 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */ 33 #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */ 34 #define DMA_STATUS 0x00001014 /* Status Register */ 35 #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */ 36 #define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */ 37 #define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */ 38 /* Rx watchdog register */ 39 #define DMA_RX_WATCHDOG 0x00001024 40 /* AXI Bus Mode */ 41 #define DMA_AXI_BUS_MODE 0x00001028 42 #define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */ 43 #define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */ 44 #define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */ 45 46 /* DMA Control register defines */ 47 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ 48 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ 49 50 /* DMA Normal interrupt */ 51 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */ 52 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ 53 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */ 54 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */ 55 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */ 56 57 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \ 58 DMA_INTR_ENA_TIE) 59 60 /* DMA Abnormal interrupt */ 61 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */ 62 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */ 63 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */ 64 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */ 65 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */ 66 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */ 67 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */ 68 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */ 69 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */ 70 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */ 71 72 #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \ 73 DMA_INTR_ENA_UNE) 74 75 /* DMA default interrupt mask */ 76 #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) 77 78 /* DMA Status register defines */ 79 #define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */ 80 #define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */ 81 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ 82 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ 83 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ 84 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ 85 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ 86 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ 87 #define DMA_STATUS_TS_SHIFT 20 88 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ 89 #define DMA_STATUS_RS_SHIFT 17 90 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ 91 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ 92 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ 93 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ 94 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ 95 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ 96 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ 97 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ 98 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ 99 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ 100 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ 101 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ 102 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */ 103 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ 104 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 105 #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */ 106 107 void dwmac_enable_dma_transmission(void __iomem *ioaddr); 108 void dwmac_enable_dma_irq(void __iomem *ioaddr); 109 void dwmac_disable_dma_irq(void __iomem *ioaddr); 110 void dwmac_dma_start_tx(void __iomem *ioaddr); 111 void dwmac_dma_stop_tx(void __iomem *ioaddr); 112 void dwmac_dma_start_rx(void __iomem *ioaddr); 113 void dwmac_dma_stop_rx(void __iomem *ioaddr); 114 int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x); 115 116 #endif /* __DWMAC_DMA_H__ */ 117