1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 // Copyright (c) 2017 Synopsys, Inc. and/or its affiliates. 3 // stmmac Support for 5.xx Ethernet QoS cores 4 5 #ifndef __DWMAC5_H__ 6 #define __DWMAC5_H__ 7 8 #define MAC_DPP_FSM_INT_STATUS 0x00000140 9 #define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144 10 #define MAC_FSM_CONTROL 0x00000148 11 #define PRTYEN BIT(1) 12 #define TMOUTEN BIT(0) 13 14 #define MAC_FPE_CTRL_STS 0x00000234 15 #define EFPE BIT(0) 16 17 #define MAC_PPS_CONTROL 0x00000b70 18 #define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1) 19 #define PPS_MINIDX(x) ((x) * 8) 20 #define PPSx_MASK(x) GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x)) 21 #define MCGRENx(x) BIT(PPS_MAXIDX(x)) 22 #define TRGTMODSELx(x, val) \ 23 GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \ 24 ((val) << (PPS_MAXIDX(x) - 2)) 25 #define PPSCMDx(x, val) \ 26 GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \ 27 ((val) << PPS_MINIDX(x)) 28 #define PPSEN0 BIT(4) 29 #define MAC_PPSx_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10)) 30 #define MAC_PPSx_TARGET_TIME_NSEC(x) (0x00000b84 + ((x) * 0x10)) 31 #define TRGTBUSY0 BIT(31) 32 #define TTSL0 GENMASK(30, 0) 33 #define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10)) 34 #define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10)) 35 36 #define MTL_EST_CONTROL 0x00000c50 37 #define PTOV GENMASK(31, 24) 38 #define PTOV_SHIFT 24 39 #define SSWL BIT(1) 40 #define EEST BIT(0) 41 42 #define MTL_EST_STATUS 0x00000c58 43 #define BTRL GENMASK(11, 8) 44 #define BTRL_SHIFT 8 45 #define BTRL_MAX (0xF << BTRL_SHIFT) 46 #define SWOL BIT(7) 47 #define SWOL_SHIFT 7 48 #define CGCE BIT(4) 49 #define HLBS BIT(3) 50 #define HLBF BIT(2) 51 #define BTRE BIT(1) 52 #define SWLC BIT(0) 53 54 #define MTL_EST_SCH_ERR 0x00000c60 55 #define MTL_EST_FRM_SZ_ERR 0x00000c64 56 #define MTL_EST_FRM_SZ_CAP 0x00000c68 57 #define SZ_CAP_HBFS_MASK GENMASK(14, 0) 58 #define SZ_CAP_HBFQ_SHIFT 16 59 #define SZ_CAP_HBFQ_MASK(_val) ({ typeof(_val) (val) = (_val); \ 60 ((val) > 4 ? GENMASK(18, 16) : \ 61 (val) > 2 ? GENMASK(17, 16) : \ 62 BIT(16)); }) 63 64 #define MTL_EST_INT_EN 0x00000c70 65 #define IECGCE CGCE 66 #define IEHS HLBS 67 #define IEHF HLBF 68 #define IEBE BTRE 69 #define IECC SWLC 70 71 #define MTL_EST_GCL_CONTROL 0x00000c80 72 #define BTR_LOW 0x0 73 #define BTR_HIGH 0x1 74 #define CTR_LOW 0x2 75 #define CTR_HIGH 0x3 76 #define TER 0x4 77 #define LLR 0x5 78 #define ADDR_SHIFT 8 79 #define GCRR BIT(2) 80 #define SRWO BIT(0) 81 #define MTL_EST_GCL_DATA 0x00000c84 82 83 #define MTL_RXP_CONTROL_STATUS 0x00000ca0 84 #define RXPI BIT(31) 85 #define NPE GENMASK(23, 16) 86 #define NVE GENMASK(7, 0) 87 #define MTL_RXP_IACC_CTRL_STATUS 0x00000cb0 88 #define STARTBUSY BIT(31) 89 #define RXPEIEC GENMASK(22, 21) 90 #define RXPEIEE BIT(20) 91 #define WRRDN BIT(16) 92 #define ADDR GENMASK(15, 0) 93 #define MTL_RXP_IACC_DATA 0x00000cb4 94 #define MTL_ECC_CONTROL 0x00000cc0 95 #define TSOEE BIT(4) 96 #define MRXPEE BIT(3) 97 #define MESTEE BIT(2) 98 #define MRXEE BIT(1) 99 #define MTXEE BIT(0) 100 101 #define MTL_SAFETY_INT_STATUS 0x00000cc4 102 #define MCSIS BIT(31) 103 #define MEUIS BIT(1) 104 #define MECIS BIT(0) 105 #define MTL_ECC_INT_ENABLE 0x00000cc8 106 #define RPCEIE BIT(12) 107 #define ECEIE BIT(8) 108 #define RXCEIE BIT(4) 109 #define TXCEIE BIT(0) 110 #define MTL_ECC_INT_STATUS 0x00000ccc 111 #define MTL_DPP_CONTROL 0x00000ce0 112 #define EPSI BIT(2) 113 #define OPE BIT(1) 114 #define EDPP BIT(0) 115 116 #define DMA_SAFETY_INT_STATUS 0x00001080 117 #define MSUIS BIT(29) 118 #define MSCIS BIT(28) 119 #define DEUIS BIT(1) 120 #define DECIS BIT(0) 121 #define DMA_ECC_INT_ENABLE 0x00001084 122 #define TCEIE BIT(0) 123 #define DMA_ECC_INT_STATUS 0x00001088 124 125 /* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */ 126 #define GMAC_RXQ_CTRL4 0x00000094 127 #define GMAC_RXQCTRL_VFFQ_MASK GENMASK(19, 17) 128 #define GMAC_RXQCTRL_VFFQ_SHIFT 17 129 #define GMAC_RXQCTRL_VFFQE BIT(16) 130 131 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp); 132 int dwmac5_safety_feat_irq_status(struct net_device *ndev, 133 void __iomem *ioaddr, unsigned int asp, 134 struct stmmac_safety_stats *stats); 135 int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats, 136 int index, unsigned long *count, const char **desc); 137 int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, 138 unsigned int count); 139 int dwmac5_flex_pps_config(void __iomem *ioaddr, int index, 140 struct stmmac_pps_cfg *cfg, bool enable, 141 u32 sub_second_inc, u32 systime_flags); 142 int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, 143 unsigned int ptp_rate); 144 void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev, 145 struct stmmac_extra_stats *x, u32 txqcnt); 146 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, 147 bool enable); 148 149 #endif /* __DWMAC5_H__ */ 150