1 /* 2 * Copyright (C) 2007-2015 STMicroelectronics Ltd 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * Author: Alexandre Torgue <alexandre.torgue@st.com> 9 */ 10 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include "common.h" 14 #include "dwmac4_dma.h" 15 #include "dwmac4.h" 16 17 int dwmac4_dma_reset(void __iomem *ioaddr) 18 { 19 u32 value = readl(ioaddr + DMA_BUS_MODE); 20 int limit; 21 22 /* DMA SW reset */ 23 value |= DMA_BUS_MODE_SFT_RESET; 24 writel(value, ioaddr + DMA_BUS_MODE); 25 limit = 10; 26 while (limit--) { 27 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 28 break; 29 mdelay(10); 30 } 31 32 if (limit < 0) 33 return -EBUSY; 34 35 return 0; 36 } 37 38 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) 39 { 40 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(chan)); 41 } 42 43 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) 44 { 45 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(chan)); 46 } 47 48 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan) 49 { 50 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 51 52 value |= DMA_CONTROL_ST; 53 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 54 55 value = readl(ioaddr + GMAC_CONFIG); 56 value |= GMAC_CONFIG_TE; 57 writel(value, ioaddr + GMAC_CONFIG); 58 } 59 60 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan) 61 { 62 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 63 64 value &= ~DMA_CONTROL_ST; 65 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 66 67 value = readl(ioaddr + GMAC_CONFIG); 68 value &= ~GMAC_CONFIG_TE; 69 writel(value, ioaddr + GMAC_CONFIG); 70 } 71 72 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan) 73 { 74 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 75 76 value |= DMA_CONTROL_SR; 77 78 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 79 80 value = readl(ioaddr + GMAC_CONFIG); 81 value |= GMAC_CONFIG_RE; 82 writel(value, ioaddr + GMAC_CONFIG); 83 } 84 85 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan) 86 { 87 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 88 89 value &= ~DMA_CONTROL_SR; 90 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 91 } 92 93 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 94 { 95 writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(chan)); 96 } 97 98 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 99 { 100 writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(chan)); 101 } 102 103 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan) 104 { 105 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + 106 DMA_CHAN_INTR_ENA(chan)); 107 } 108 109 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan) 110 { 111 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10, 112 ioaddr + DMA_CHAN_INTR_ENA(chan)); 113 } 114 115 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan) 116 { 117 writel(0, ioaddr + DMA_CHAN_INTR_ENA(chan)); 118 } 119 120 int dwmac4_dma_interrupt(void __iomem *ioaddr, 121 struct stmmac_extra_stats *x, u32 chan) 122 { 123 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); 124 u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); 125 int ret = 0; 126 127 /* ABNORMAL interrupts */ 128 if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) { 129 if (unlikely(intr_status & DMA_CHAN_STATUS_RBU)) 130 x->rx_buf_unav_irq++; 131 if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) 132 x->rx_process_stopped_irq++; 133 if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) 134 x->rx_watchdog_irq++; 135 if (unlikely(intr_status & DMA_CHAN_STATUS_ETI)) 136 x->tx_early_irq++; 137 if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) { 138 x->tx_process_stopped_irq++; 139 ret = tx_hard_error; 140 } 141 if (unlikely(intr_status & DMA_CHAN_STATUS_FBE)) { 142 x->fatal_bus_error_irq++; 143 ret = tx_hard_error; 144 } 145 } 146 /* TX/RX NORMAL interrupts */ 147 if (likely(intr_status & DMA_CHAN_STATUS_NIS)) { 148 x->normal_irq_n++; 149 if (likely(intr_status & DMA_CHAN_STATUS_RI)) { 150 x->rx_normal_irq_n++; 151 ret |= handle_rx; 152 } 153 if (likely(intr_status & (DMA_CHAN_STATUS_TI | 154 DMA_CHAN_STATUS_TBU))) { 155 x->tx_normal_irq_n++; 156 ret |= handle_tx; 157 } 158 if (unlikely(intr_status & DMA_CHAN_STATUS_ERI)) 159 x->rx_early_irq++; 160 } 161 162 writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan)); 163 return ret; 164 } 165 166 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 167 unsigned int high, unsigned int low) 168 { 169 unsigned long data; 170 171 data = (addr[5] << 8) | addr[4]; 172 /* For MAC Addr registers se have to set the Address Enable (AE) 173 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 174 * is RO. 175 */ 176 data |= (STMMAC_CHAN0 << GMAC_HI_DCS_SHIFT); 177 writel(data | GMAC_HI_REG_AE, ioaddr + high); 178 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 179 writel(data, ioaddr + low); 180 } 181 182 /* Enable disable MAC RX/TX */ 183 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable) 184 { 185 u32 value = readl(ioaddr + GMAC_CONFIG); 186 187 if (enable) 188 value |= GMAC_CONFIG_RE | GMAC_CONFIG_TE; 189 else 190 value &= ~(GMAC_CONFIG_TE | GMAC_CONFIG_RE); 191 192 writel(value, ioaddr + GMAC_CONFIG); 193 } 194 195 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 196 unsigned int high, unsigned int low) 197 { 198 unsigned int hi_addr, lo_addr; 199 200 /* Read the MAC address from the hardware */ 201 hi_addr = readl(ioaddr + high); 202 lo_addr = readl(ioaddr + low); 203 204 /* Extract the MAC address from the high and low words */ 205 addr[0] = lo_addr & 0xff; 206 addr[1] = (lo_addr >> 8) & 0xff; 207 addr[2] = (lo_addr >> 16) & 0xff; 208 addr[3] = (lo_addr >> 24) & 0xff; 209 addr[4] = hi_addr & 0xff; 210 addr[5] = (hi_addr >> 8) & 0xff; 211 } 212