1 /* 2 * DWMAC4 DMA Header file. 3 * 4 * 5 * Copyright (C) 2007-2015 STMicroelectronics Ltd 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * Author: Alexandre Torgue <alexandre.torgue@st.com> 12 */ 13 14 #ifndef __DWMAC4_DMA_H__ 15 #define __DWMAC4_DMA_H__ 16 17 /* Define the max channel number used for tx (also rx). 18 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX 19 */ 20 #define DMA_CHANNEL_NB_MAX 1 21 22 #define DMA_BUS_MODE 0x00001000 23 #define DMA_SYS_BUS_MODE 0x00001004 24 #define DMA_STATUS 0x00001008 25 #define DMA_DEBUG_STATUS_0 0x0000100c 26 #define DMA_DEBUG_STATUS_1 0x00001010 27 #define DMA_DEBUG_STATUS_2 0x00001014 28 #define DMA_AXI_BUS_MODE 0x00001028 29 30 /* DMA Bus Mode bitmap */ 31 #define DMA_BUS_MODE_SFT_RESET BIT(0) 32 33 /* DMA SYS Bus Mode bitmap */ 34 #define DMA_BUS_MODE_SPH BIT(24) 35 #define DMA_BUS_MODE_PBL BIT(16) 36 #define DMA_BUS_MODE_PBL_SHIFT 16 37 #define DMA_BUS_MODE_RPBL_SHIFT 16 38 #define DMA_BUS_MODE_MB BIT(14) 39 #define DMA_BUS_MODE_FB BIT(0) 40 41 /* DMA Interrupt top status */ 42 #define DMA_STATUS_MAC BIT(17) 43 #define DMA_STATUS_MTL BIT(16) 44 #define DMA_STATUS_CHAN7 BIT(7) 45 #define DMA_STATUS_CHAN6 BIT(6) 46 #define DMA_STATUS_CHAN5 BIT(5) 47 #define DMA_STATUS_CHAN4 BIT(4) 48 #define DMA_STATUS_CHAN3 BIT(3) 49 #define DMA_STATUS_CHAN2 BIT(2) 50 #define DMA_STATUS_CHAN1 BIT(1) 51 #define DMA_STATUS_CHAN0 BIT(0) 52 53 /* DMA debug status bitmap */ 54 #define DMA_DEBUG_STATUS_TS_MASK 0xf 55 #define DMA_DEBUG_STATUS_RS_MASK 0xf 56 57 /* DMA AXI bitmap */ 58 #define DMA_AXI_EN_LPI BIT(31) 59 #define DMA_AXI_LPI_XIT_FRM BIT(30) 60 #define DMA_AXI_WR_OSR_LMT GENMASK(27, 24) 61 #define DMA_AXI_WR_OSR_LMT_SHIFT 24 62 #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16) 63 #define DMA_AXI_RD_OSR_LMT_SHIFT 16 64 65 #define DMA_AXI_OSR_MAX 0xf 66 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \ 67 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT)) 68 69 #define DMA_SYS_BUS_MB BIT(14) 70 #define DMA_AXI_1KBBE BIT(13) 71 #define DMA_SYS_BUS_AAL BIT(12) 72 #define DMA_AXI_BLEN256 BIT(7) 73 #define DMA_AXI_BLEN128 BIT(6) 74 #define DMA_AXI_BLEN64 BIT(5) 75 #define DMA_AXI_BLEN32 BIT(4) 76 #define DMA_AXI_BLEN16 BIT(3) 77 #define DMA_AXI_BLEN8 BIT(2) 78 #define DMA_AXI_BLEN4 BIT(1) 79 #define DMA_SYS_BUS_FB BIT(0) 80 81 #define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \ 82 DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \ 83 DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \ 84 DMA_AXI_BLEN4) 85 86 #define DMA_AXI_BURST_LEN_MASK 0x000000FE 87 88 /* Following DMA defines are chanels oriented */ 89 #define DMA_CHAN_BASE_ADDR 0x00001100 90 #define DMA_CHAN_BASE_OFFSET 0x80 91 #define DMA_CHANX_BASE_ADDR(x) (DMA_CHAN_BASE_ADDR + \ 92 (x * DMA_CHAN_BASE_OFFSET)) 93 #define DMA_CHAN_REG_NUMBER 17 94 95 #define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x) 96 #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) 97 #define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8) 98 #define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14) 99 #define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c) 100 #define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20) 101 #define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28) 102 #define DMA_CHAN_TX_RING_LEN(x) (DMA_CHANX_BASE_ADDR(x) + 0x2c) 103 #define DMA_CHAN_RX_RING_LEN(x) (DMA_CHANX_BASE_ADDR(x) + 0x30) 104 #define DMA_CHAN_INTR_ENA(x) (DMA_CHANX_BASE_ADDR(x) + 0x34) 105 #define DMA_CHAN_RX_WATCHDOG(x) (DMA_CHANX_BASE_ADDR(x) + 0x38) 106 #define DMA_CHAN_SLOT_CTRL_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x3c) 107 #define DMA_CHAN_CUR_TX_DESC(x) (DMA_CHANX_BASE_ADDR(x) + 0x44) 108 #define DMA_CHAN_CUR_RX_DESC(x) (DMA_CHANX_BASE_ADDR(x) + 0x4c) 109 #define DMA_CHAN_CUR_TX_BUF_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x54) 110 #define DMA_CHAN_CUR_RX_BUF_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x5c) 111 #define DMA_CHAN_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x60) 112 113 /* DMA Control X */ 114 #define DMA_CONTROL_MSS_MASK GENMASK(13, 0) 115 116 /* DMA Tx Channel X Control register defines */ 117 #define DMA_CONTROL_TSE BIT(12) 118 #define DMA_CONTROL_OSP BIT(4) 119 #define DMA_CONTROL_ST BIT(0) 120 121 /* DMA Rx Channel X Control register defines */ 122 #define DMA_CONTROL_SR BIT(0) 123 124 /* Interrupt status per channel */ 125 #define DMA_CHAN_STATUS_REB GENMASK(21, 19) 126 #define DMA_CHAN_STATUS_REB_SHIFT 19 127 #define DMA_CHAN_STATUS_TEB GENMASK(18, 16) 128 #define DMA_CHAN_STATUS_TEB_SHIFT 16 129 #define DMA_CHAN_STATUS_NIS BIT(15) 130 #define DMA_CHAN_STATUS_AIS BIT(14) 131 #define DMA_CHAN_STATUS_CDE BIT(13) 132 #define DMA_CHAN_STATUS_FBE BIT(12) 133 #define DMA_CHAN_STATUS_ERI BIT(11) 134 #define DMA_CHAN_STATUS_ETI BIT(10) 135 #define DMA_CHAN_STATUS_RWT BIT(9) 136 #define DMA_CHAN_STATUS_RPS BIT(8) 137 #define DMA_CHAN_STATUS_RBU BIT(7) 138 #define DMA_CHAN_STATUS_RI BIT(6) 139 #define DMA_CHAN_STATUS_TBU BIT(2) 140 #define DMA_CHAN_STATUS_TPS BIT(1) 141 #define DMA_CHAN_STATUS_TI BIT(0) 142 143 /* Interrupt enable bits per channel */ 144 #define DMA_CHAN_INTR_ENA_NIE BIT(16) 145 #define DMA_CHAN_INTR_ENA_AIE BIT(15) 146 #define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15) 147 #define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14) 148 #define DMA_CHAN_INTR_ENA_CDE BIT(13) 149 #define DMA_CHAN_INTR_ENA_FBE BIT(12) 150 #define DMA_CHAN_INTR_ENA_ERE BIT(11) 151 #define DMA_CHAN_INTR_ENA_ETE BIT(10) 152 #define DMA_CHAN_INTR_ENA_RWE BIT(9) 153 #define DMA_CHAN_INTR_ENA_RSE BIT(8) 154 #define DMA_CHAN_INTR_ENA_RBUE BIT(7) 155 #define DMA_CHAN_INTR_ENA_RIE BIT(6) 156 #define DMA_CHAN_INTR_ENA_TBUE BIT(2) 157 #define DMA_CHAN_INTR_ENA_TSE BIT(1) 158 #define DMA_CHAN_INTR_ENA_TIE BIT(0) 159 160 #define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \ 161 DMA_CHAN_INTR_ENA_RIE | \ 162 DMA_CHAN_INTR_ENA_TIE) 163 164 #define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \ 165 DMA_CHAN_INTR_ENA_FBE) 166 /* DMA default interrupt mask for 4.00 */ 167 #define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \ 168 DMA_CHAN_INTR_ABNORMAL) 169 170 #define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \ 171 DMA_CHAN_INTR_ENA_RIE | \ 172 DMA_CHAN_INTR_ENA_TIE) 173 174 #define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \ 175 DMA_CHAN_INTR_ENA_FBE) 176 /* DMA default interrupt mask for 4.10a */ 177 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \ 178 DMA_CHAN_INTR_ABNORMAL_4_10) 179 180 /* channel 0 specific fields */ 181 #define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12) 182 #define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12 183 #define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8) 184 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8 185 186 int dwmac4_dma_reset(void __iomem *ioaddr); 187 void dwmac4_enable_dma_transmission(void __iomem *ioaddr, u32 tail_ptr); 188 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan); 189 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan); 190 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan); 191 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan); 192 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan); 193 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan); 194 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan); 195 int dwmac4_dma_interrupt(void __iomem *ioaddr, 196 struct stmmac_extra_stats *x, u32 chan); 197 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan); 198 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan); 199 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan); 200 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan); 201 202 #endif /* __DWMAC4_DMA_H__ */ 203