1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 DMA Header file. 4 * 5 * Copyright (C) 2007-2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_DMA_H__ 11 #define __DWMAC4_DMA_H__ 12 13 /* Define the max channel number used for tx (also rx). 14 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX 15 */ 16 #define DMA_CHANNEL_NB_MAX 1 17 18 #define DMA_BUS_MODE 0x00001000 19 20 #define DMA_BUS_MODE_DCHE BIT(19) 21 #define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16) 22 #define DMA_BUS_MODE_INTM_MODE1 0x1 23 #define DMA_BUS_MODE_SFT_RESET BIT(0) 24 25 #define DMA_SYS_BUS_MODE 0x00001004 26 27 #define DMA_BUS_MODE_MB BIT(14) 28 #define DMA_BUS_MODE_FB BIT(0) 29 30 #define DMA_STATUS 0x00001008 31 32 #define DMA_AXI_BUS_MODE 0x00001028 33 34 #define DMA_AXI_EN_LPI BIT(31) 35 #define DMA_AXI_LPI_XIT_FRM BIT(30) 36 #define DMA_AXI_WR_OSR_LMT GENMASK(27, 24) 37 #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16) 38 39 #define DMA_SYS_BUS_MB BIT(14) 40 #define DMA_SYS_BUS_AAL DMA_AXI_AAL 41 #define DMA_SYS_BUS_EAME BIT(11) 42 #define DMA_SYS_BUS_FB BIT(0) 43 44 #define DMA_TBS_CTRL 0x00001050 45 46 #define DMA_TBS_FTOS GENMASK(31, 8) 47 #define DMA_TBS_FTOV BIT(0) 48 #define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV) 49 50 /* Following DMA defines are channel-oriented */ 51 #define DMA_CHAN_BASE_ADDR 0x00001100 52 #define DMA_CHAN_BASE_OFFSET 0x80 53 54 static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs, 55 const u32 x) 56 { 57 u32 addr; 58 59 if (addrs) 60 addr = addrs->dma_chan + (x * addrs->dma_chan_offset); 61 else 62 addr = DMA_CHAN_BASE_ADDR + (x * DMA_CHAN_BASE_OFFSET); 63 64 return addr; 65 } 66 67 #define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x) 68 69 #define DMA_CHAN_CTRL_PBLX8 BIT(16) 70 #define DMA_CONTROL_SPH BIT(24) 71 72 #define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4) 73 74 #define DMA_CONTROL_EDSE BIT(28) 75 #define DMA_CHAN_TX_CTRL_TXPBL_MASK GENMASK(21, 16) 76 #define DMA_CONTROL_TSE BIT(12) 77 #define DMA_CONTROL_OSP BIT(4) 78 #define DMA_CONTROL_ST BIT(0) 79 80 #define DMA_CHAN_RX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x8) 81 82 #define DMA_CHAN_RX_CTRL_RXPBL_MASK GENMASK(21, 16) 83 #define DMA_RBSZ_MASK GENMASK(14, 1) 84 #define DMA_CONTROL_SR BIT(0) 85 86 #define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x10) 87 #define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14) 88 #define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x18) 89 #define DMA_CHAN_RX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x1c) 90 #define DMA_CHAN_TX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x20) 91 #define DMA_CHAN_RX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x28) 92 #define DMA_CHAN_TX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x2c) 93 #define DMA_CHAN_RX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x30) 94 95 #define DMA_CHAN_INTR_ENA(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x34) 96 97 #define DMA_CHAN_INTR_ENA_NIE BIT(16) 98 #define DMA_CHAN_INTR_ENA_AIE BIT(15) 99 #define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15) 100 #define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14) 101 #define DMA_CHAN_INTR_ENA_FBE BIT(12) 102 #define DMA_CHAN_INTR_ENA_RIE BIT(6) 103 #define DMA_CHAN_INTR_ENA_TIE BIT(0) 104 105 #define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \ 106 DMA_CHAN_INTR_ENA_RIE | \ 107 DMA_CHAN_INTR_ENA_TIE) 108 109 #define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \ 110 DMA_CHAN_INTR_ENA_FBE) 111 /* DMA default interrupt mask for 4.00 */ 112 #define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \ 113 DMA_CHAN_INTR_ABNORMAL) 114 #define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE) 115 #define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE) 116 117 #define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \ 118 DMA_CHAN_INTR_ENA_RIE | \ 119 DMA_CHAN_INTR_ENA_TIE) 120 121 #define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \ 122 DMA_CHAN_INTR_ENA_FBE) 123 /* DMA default interrupt mask for 4.10a */ 124 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \ 125 DMA_CHAN_INTR_ABNORMAL_4_10) 126 #define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE) 127 #define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE) 128 129 #define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38) 130 #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c) 131 #define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44) 132 #define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c) 133 #define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x50) 134 #define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x54) 135 #define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x58) 136 #define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c) 137 #define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60) 138 139 /* Interrupt status per channel */ 140 #define DMA_CHAN_STATUS_REB GENMASK(21, 19) 141 #define DMA_CHAN_STATUS_NIS BIT(15) 142 #define DMA_CHAN_STATUS_AIS BIT(14) 143 #define DMA_CHAN_STATUS_CDE BIT(13) 144 #define DMA_CHAN_STATUS_FBE BIT(12) 145 #define DMA_CHAN_STATUS_ERI BIT(11) 146 #define DMA_CHAN_STATUS_ETI BIT(10) 147 #define DMA_CHAN_STATUS_RWT BIT(9) 148 #define DMA_CHAN_STATUS_RPS BIT(8) 149 #define DMA_CHAN_STATUS_RBU BIT(7) 150 #define DMA_CHAN_STATUS_RI BIT(6) 151 #define DMA_CHAN_STATUS_TBU BIT(2) 152 #define DMA_CHAN_STATUS_TPS BIT(1) 153 #define DMA_CHAN_STATUS_TI BIT(0) 154 155 #define DMA_CHAN_STATUS_MSK_COMMON (DMA_CHAN_STATUS_NIS | \ 156 DMA_CHAN_STATUS_AIS | \ 157 DMA_CHAN_STATUS_CDE | \ 158 DMA_CHAN_STATUS_FBE) 159 160 #define DMA_CHAN_STATUS_MSK_RX (DMA_CHAN_STATUS_REB | \ 161 DMA_CHAN_STATUS_ERI | \ 162 DMA_CHAN_STATUS_RWT | \ 163 DMA_CHAN_STATUS_RPS | \ 164 DMA_CHAN_STATUS_RBU | \ 165 DMA_CHAN_STATUS_RI | \ 166 DMA_CHAN_STATUS_MSK_COMMON) 167 168 #define DMA_CHAN_STATUS_MSK_TX (DMA_CHAN_STATUS_ETI | \ 169 DMA_CHAN_STATUS_TBU | \ 170 DMA_CHAN_STATUS_TPS | \ 171 DMA_CHAN_STATUS_TI | \ 172 DMA_CHAN_STATUS_MSK_COMMON) 173 174 int dwmac4_dma_reset(void __iomem *ioaddr); 175 void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 176 u32 chan, bool rx, bool tx); 177 void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 178 u32 chan, bool rx, bool tx); 179 void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 180 u32 chan, bool rx, bool tx); 181 void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 182 u32 chan, bool rx, bool tx); 183 void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 184 u32 chan); 185 void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 186 u32 chan); 187 void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 188 u32 chan); 189 void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 190 u32 chan); 191 int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, 192 struct stmmac_extra_stats *x, u32 chan, u32 dir); 193 void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, 194 u32 len, u32 chan); 195 void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, 196 u32 len, u32 chan); 197 void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, 198 u32 tail_ptr, u32 chan); 199 void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, 200 u32 tail_ptr, u32 chan); 201 202 #endif /* __DWMAC4_DMA_H__ */ 203