1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 4 * DWC Ether MAC version 4.xx has been used for developing this code. 5 * 6 * This contains the functions to handle the dma. 7 * 8 * Copyright (C) 2015 STMicroelectronics Ltd 9 * 10 * Author: Alexandre Torgue <alexandre.torgue@st.com> 11 */ 12 13 #include <linux/io.h> 14 #include "dwmac4.h" 15 #include "dwmac4_dma.h" 16 #include "stmmac.h" 17 18 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 19 { 20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 21 22 pr_info("dwmac4: Master AXI performs %s burst length\n", 23 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 24 25 if (axi->axi_lpi_en) 26 value |= DMA_AXI_EN_LPI; 27 if (axi->axi_xit_frm) 28 value |= DMA_AXI_LPI_XIT_FRM; 29 30 value &= ~DMA_AXI_WR_OSR_LMT; 31 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 32 DMA_AXI_WR_OSR_LMT_SHIFT; 33 34 value &= ~DMA_AXI_RD_OSR_LMT; 35 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 36 DMA_AXI_RD_OSR_LMT_SHIFT; 37 38 /* Depending on the UNDEF bit the Master AXI will perform any burst 39 * length according to the BLEN programmed (by default all BLEN are 40 * set). Note that the UNDEF bit is readonly, and is the inverse of 41 * Bus Mode bit 16. 42 */ 43 value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval; 44 45 writel(value, ioaddr + DMA_SYS_BUS_MODE); 46 } 47 48 static void dwmac4_dma_init_rx_chan(struct stmmac_priv *priv, 49 void __iomem *ioaddr, 50 struct stmmac_dma_cfg *dma_cfg, 51 dma_addr_t dma_rx_phy, u32 chan) 52 { 53 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 54 u32 value; 55 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 56 57 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); 58 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 59 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); 60 61 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 62 writel(upper_32_bits(dma_rx_phy), 63 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, chan)); 64 65 writel(lower_32_bits(dma_rx_phy), 66 ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, chan)); 67 } 68 69 static void dwmac4_dma_init_tx_chan(struct stmmac_priv *priv, 70 void __iomem *ioaddr, 71 struct stmmac_dma_cfg *dma_cfg, 72 dma_addr_t dma_tx_phy, u32 chan) 73 { 74 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 75 u32 value; 76 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 77 78 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 79 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 80 81 /* Enable OSP to get best performance */ 82 value |= DMA_CONTROL_OSP; 83 84 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 85 86 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 87 writel(upper_32_bits(dma_tx_phy), 88 ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, chan)); 89 90 writel(lower_32_bits(dma_tx_phy), 91 ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, chan)); 92 } 93 94 static void dwmac4_dma_init_channel(struct stmmac_priv *priv, 95 void __iomem *ioaddr, 96 struct stmmac_dma_cfg *dma_cfg, u32 chan) 97 { 98 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 99 u32 value; 100 101 /* common channel control register config */ 102 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 103 if (dma_cfg->pblx8) 104 value = value | DMA_BUS_MODE_PBL; 105 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 106 107 /* Mask interrupts by writing to CSR7 */ 108 writel(DMA_CHAN_INTR_DEFAULT_MASK, 109 ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan)); 110 } 111 112 static void dwmac410_dma_init_channel(struct stmmac_priv *priv, 113 void __iomem *ioaddr, 114 struct stmmac_dma_cfg *dma_cfg, u32 chan) 115 { 116 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 117 u32 value; 118 119 /* common channel control register config */ 120 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 121 if (dma_cfg->pblx8) 122 value = value | DMA_BUS_MODE_PBL; 123 124 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 125 126 /* Mask interrupts by writing to CSR7 */ 127 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10, 128 ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan)); 129 } 130 131 static void dwmac4_dma_init(void __iomem *ioaddr, 132 struct stmmac_dma_cfg *dma_cfg) 133 { 134 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 135 136 /* Set the Fixed burst mode */ 137 if (dma_cfg->fixed_burst) 138 value |= DMA_SYS_BUS_FB; 139 140 /* Mixed Burst has no effect when fb is set */ 141 if (dma_cfg->mixed_burst) 142 value |= DMA_SYS_BUS_MB; 143 144 if (dma_cfg->aal) 145 value |= DMA_SYS_BUS_AAL; 146 147 if (dma_cfg->eame) 148 value |= DMA_SYS_BUS_EAME; 149 150 writel(value, ioaddr + DMA_SYS_BUS_MODE); 151 152 value = readl(ioaddr + DMA_BUS_MODE); 153 154 if (dma_cfg->multi_msi_en) { 155 value &= ~DMA_BUS_MODE_INTM_MASK; 156 value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT); 157 } 158 159 if (dma_cfg->dche) 160 value |= DMA_BUS_MODE_DCHE; 161 162 writel(value, ioaddr + DMA_BUS_MODE); 163 164 } 165 166 static void _dwmac4_dump_dma_regs(struct stmmac_priv *priv, 167 void __iomem *ioaddr, u32 channel, 168 u32 *reg_space) 169 { 170 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 171 const struct dwmac4_addrs *default_addrs = NULL; 172 173 /* Purposely save the registers in the "normal" layout, regardless of 174 * platform modifications, to keep reg_space size constant 175 */ 176 reg_space[DMA_CHAN_CONTROL(default_addrs, channel) / 4] = 177 readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel)); 178 reg_space[DMA_CHAN_TX_CONTROL(default_addrs, channel) / 4] = 179 readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel)); 180 reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] = 181 readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel)); 182 reg_space[DMA_CHAN_TX_BASE_ADDR_HI(default_addrs, channel) / 4] = 183 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel)); 184 reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] = 185 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel)); 186 reg_space[DMA_CHAN_RX_BASE_ADDR_HI(default_addrs, channel) / 4] = 187 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel)); 188 reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] = 189 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel)); 190 reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] = 191 readl(ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, channel)); 192 reg_space[DMA_CHAN_RX_END_ADDR(default_addrs, channel) / 4] = 193 readl(ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, channel)); 194 reg_space[DMA_CHAN_TX_RING_LEN(default_addrs, channel) / 4] = 195 readl(ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, channel)); 196 reg_space[DMA_CHAN_RX_RING_LEN(default_addrs, channel) / 4] = 197 readl(ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, channel)); 198 reg_space[DMA_CHAN_INTR_ENA(default_addrs, channel) / 4] = 199 readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel)); 200 reg_space[DMA_CHAN_RX_WATCHDOG(default_addrs, channel) / 4] = 201 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, channel)); 202 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(default_addrs, channel) / 4] = 203 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(dwmac4_addrs, channel)); 204 reg_space[DMA_CHAN_CUR_TX_DESC(default_addrs, channel) / 4] = 205 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel)); 206 reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] = 207 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel)); 208 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR_HI(default_addrs, channel) / 4] = 209 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel)); 210 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] = 211 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel)); 212 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR_HI(default_addrs, channel) / 4] = 213 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel)); 214 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] = 215 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel)); 216 reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] = 217 readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, channel)); 218 } 219 220 static void dwmac4_dump_dma_regs(struct stmmac_priv *priv, void __iomem *ioaddr, 221 u32 *reg_space) 222 { 223 int i; 224 225 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 226 _dwmac4_dump_dma_regs(priv, ioaddr, i, reg_space); 227 } 228 229 static void dwmac4_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr, 230 u32 riwt, u32 queue) 231 { 232 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 233 234 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue)); 235 } 236 237 static void dwmac4_dma_rx_chan_op_mode(struct stmmac_priv *priv, 238 void __iomem *ioaddr, int mode, 239 u32 channel, int fifosz, u8 qmode) 240 { 241 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 242 unsigned int rqs = fifosz / 256 - 1; 243 u32 mtl_rx_op; 244 245 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel)); 246 247 mtl_rx_op |= MTL_OP_MODE_DIS_TCP_EF; 248 249 if (mode == SF_DMA_MODE) { 250 pr_debug("GMAC: enable RX store and forward mode\n"); 251 mtl_rx_op |= MTL_OP_MODE_RSF; 252 } else { 253 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 254 mtl_rx_op &= ~MTL_OP_MODE_RSF; 255 mtl_rx_op &= ~MTL_OP_MODE_RTC_MASK; 256 if (mode <= 32) 257 mtl_rx_op |= MTL_OP_MODE_RTC_32; 258 else if (mode <= 64) 259 mtl_rx_op |= MTL_OP_MODE_RTC_64; 260 else if (mode <= 96) 261 mtl_rx_op |= MTL_OP_MODE_RTC_96; 262 else 263 mtl_rx_op |= MTL_OP_MODE_RTC_128; 264 } 265 266 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 267 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 268 269 /* Enable flow control only if each channel gets 4 KiB or more FIFO and 270 * only if channel is not an AVB channel. 271 */ 272 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 273 unsigned int rfd, rfa; 274 275 mtl_rx_op |= MTL_OP_MODE_EHFC; 276 277 /* Set Threshold for Activating Flow Control to min 2 frames, 278 * i.e. 1500 * 2 = 3000 bytes. 279 * 280 * Set Threshold for Deactivating Flow Control to min 1 frame, 281 * i.e. 1500 bytes. 282 */ 283 switch (fifosz) { 284 case 4096: 285 /* This violates the above formula because of FIFO size 286 * limit therefore overflow may occur in spite of this. 287 */ 288 rfd = 0x03; /* Full-2.5K */ 289 rfa = 0x01; /* Full-1.5K */ 290 break; 291 292 default: 293 rfd = 0x07; /* Full-4.5K */ 294 rfa = 0x04; /* Full-3K */ 295 break; 296 } 297 298 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 299 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 300 301 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 302 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 303 } 304 305 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel)); 306 } 307 308 static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv, 309 void __iomem *ioaddr, int mode, 310 u32 channel, int fifosz, u8 qmode) 311 { 312 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 313 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, 314 channel)); 315 unsigned int tqs = fifosz / 256 - 1; 316 317 if (mode == SF_DMA_MODE) { 318 pr_debug("GMAC: enable TX store and forward mode\n"); 319 /* Transmit COE type 2 cannot be done in cut-through mode. */ 320 mtl_tx_op |= MTL_OP_MODE_TSF; 321 } else { 322 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 323 mtl_tx_op &= ~MTL_OP_MODE_TSF; 324 mtl_tx_op &= ~MTL_OP_MODE_TTC_MASK; 325 /* Set the transmit threshold */ 326 if (mode <= 32) 327 mtl_tx_op |= MTL_OP_MODE_TTC_32; 328 else if (mode <= 64) 329 mtl_tx_op |= MTL_OP_MODE_TTC_64; 330 else if (mode <= 96) 331 mtl_tx_op |= MTL_OP_MODE_TTC_96; 332 else if (mode <= 128) 333 mtl_tx_op |= MTL_OP_MODE_TTC_128; 334 else if (mode <= 192) 335 mtl_tx_op |= MTL_OP_MODE_TTC_192; 336 else if (mode <= 256) 337 mtl_tx_op |= MTL_OP_MODE_TTC_256; 338 else if (mode <= 384) 339 mtl_tx_op |= MTL_OP_MODE_TTC_384; 340 else 341 mtl_tx_op |= MTL_OP_MODE_TTC_512; 342 } 343 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 344 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 345 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 346 * with reset values: TXQEN off, TQS 256 bytes. 347 * 348 * TXQEN must be written for multi-channel operation and TQS must 349 * reflect the available fifo size per queue (total fifo size / number 350 * of enabled queues). 351 */ 352 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 353 if (qmode != MTL_QUEUE_AVB) 354 mtl_tx_op |= MTL_OP_MODE_TXQEN; 355 else 356 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 357 mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 358 mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 359 360 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel)); 361 } 362 363 static int dwmac4_get_hw_feature(void __iomem *ioaddr, 364 struct dma_features *dma_cap) 365 { 366 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 367 368 /* MAC HW feature0 */ 369 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 370 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 371 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 372 dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 373 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 374 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 375 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 376 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 377 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 378 /* MMC */ 379 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 380 /* IEEE 1588-2008 */ 381 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 382 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 383 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 384 /* TX and RX csum */ 385 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 386 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 387 dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27; 388 dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9; 389 390 /* MAC HW feature1 */ 391 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 392 dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27; 393 dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; 394 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 395 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 396 dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17; 397 398 dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; 399 switch (dma_cap->addr64) { 400 case 0: 401 dma_cap->addr64 = 32; 402 break; 403 case 1: 404 dma_cap->addr64 = 40; 405 break; 406 case 2: 407 dma_cap->addr64 = 48; 408 break; 409 default: 410 dma_cap->addr64 = 32; 411 break; 412 } 413 414 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 415 * shifting and store the sizes in bytes. 416 */ 417 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 418 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 419 /* MAC HW feature2 */ 420 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 421 /* TX and RX number of channels */ 422 dma_cap->number_rx_channel = 423 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 424 dma_cap->number_tx_channel = 425 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 426 /* TX and RX number of queues */ 427 dma_cap->number_rx_queues = 428 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 429 dma_cap->number_tx_queues = 430 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 431 /* PPS output */ 432 dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 433 434 /* IEEE 1588-2002 */ 435 dma_cap->time_stamp = 0; 436 /* Number of Auxiliary Snapshot Inputs */ 437 dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28; 438 439 /* MAC HW feature3 */ 440 hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 441 442 /* 5.10 Features */ 443 dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 444 dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27; 445 dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26; 446 dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20; 447 dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17; 448 dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16; 449 dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 450 dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 451 dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 452 dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5; 453 454 return 0; 455 } 456 457 /* Enable/disable TSO feature and set MSS */ 458 static void dwmac4_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr, 459 bool en, u32 chan) 460 { 461 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 462 u32 value; 463 464 if (en) { 465 /* enable TSO */ 466 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 467 writel(value | DMA_CONTROL_TSE, 468 ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 469 } else { 470 /* enable TSO */ 471 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 472 writel(value & ~DMA_CONTROL_TSE, 473 ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 474 } 475 } 476 477 static void dwmac4_qmode(struct stmmac_priv *priv, void __iomem *ioaddr, 478 u32 channel, u8 qmode) 479 { 480 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 481 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, 482 channel)); 483 484 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 485 if (qmode != MTL_QUEUE_AVB) 486 mtl_tx_op |= MTL_OP_MODE_TXQEN; 487 else 488 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 489 490 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel)); 491 } 492 493 static void dwmac4_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr, 494 int bfsize, u32 chan) 495 { 496 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 497 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); 498 499 value &= ~DMA_RBSZ_MASK; 500 value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; 501 502 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); 503 } 504 505 static void dwmac4_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr, 506 bool en, u32 chan) 507 { 508 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 509 u32 value = readl(ioaddr + GMAC_EXT_CONFIG); 510 511 value &= ~GMAC_CONFIG_HDSMS; 512 value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ 513 writel(value, ioaddr + GMAC_EXT_CONFIG); 514 515 value = readl(ioaddr + GMAC_EXT_CFG1); 516 value |= GMAC_CONFIG1_SPLM(1); /* Split mode set to L2OFST */ 517 value |= GMAC_CONFIG1_SAVE_EN; /* Enable Split AV mode */ 518 writel(value, ioaddr + GMAC_EXT_CFG1); 519 520 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 521 if (en) 522 value |= DMA_CONTROL_SPH; 523 else 524 value &= ~DMA_CONTROL_SPH; 525 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 526 } 527 528 static int dwmac4_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr, 529 bool en, u32 chan) 530 { 531 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 532 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 533 534 if (en) 535 value |= DMA_CONTROL_EDSE; 536 else 537 value &= ~DMA_CONTROL_EDSE; 538 539 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 540 541 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, 542 chan)) & DMA_CONTROL_EDSE; 543 if (en && !value) 544 return -EIO; 545 546 writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL); 547 return 0; 548 } 549 550 const struct stmmac_dma_ops dwmac4_dma_ops = { 551 .reset = dwmac4_dma_reset, 552 .init = dwmac4_dma_init, 553 .init_chan = dwmac4_dma_init_channel, 554 .init_rx_chan = dwmac4_dma_init_rx_chan, 555 .init_tx_chan = dwmac4_dma_init_tx_chan, 556 .axi = dwmac4_dma_axi, 557 .dump_regs = dwmac4_dump_dma_regs, 558 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 559 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 560 .enable_dma_irq = dwmac4_enable_dma_irq, 561 .disable_dma_irq = dwmac4_disable_dma_irq, 562 .start_tx = dwmac4_dma_start_tx, 563 .stop_tx = dwmac4_dma_stop_tx, 564 .start_rx = dwmac4_dma_start_rx, 565 .stop_rx = dwmac4_dma_stop_rx, 566 .dma_interrupt = dwmac4_dma_interrupt, 567 .get_hw_feature = dwmac4_get_hw_feature, 568 .rx_watchdog = dwmac4_rx_watchdog, 569 .set_rx_ring_len = dwmac4_set_rx_ring_len, 570 .set_tx_ring_len = dwmac4_set_tx_ring_len, 571 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 572 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 573 .enable_tso = dwmac4_enable_tso, 574 .qmode = dwmac4_qmode, 575 .set_bfsize = dwmac4_set_bfsize, 576 .enable_sph = dwmac4_enable_sph, 577 }; 578 579 const struct stmmac_dma_ops dwmac410_dma_ops = { 580 .reset = dwmac4_dma_reset, 581 .init = dwmac4_dma_init, 582 .init_chan = dwmac410_dma_init_channel, 583 .init_rx_chan = dwmac4_dma_init_rx_chan, 584 .init_tx_chan = dwmac4_dma_init_tx_chan, 585 .axi = dwmac4_dma_axi, 586 .dump_regs = dwmac4_dump_dma_regs, 587 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 588 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 589 .enable_dma_irq = dwmac410_enable_dma_irq, 590 .disable_dma_irq = dwmac4_disable_dma_irq, 591 .start_tx = dwmac4_dma_start_tx, 592 .stop_tx = dwmac4_dma_stop_tx, 593 .start_rx = dwmac4_dma_start_rx, 594 .stop_rx = dwmac4_dma_stop_rx, 595 .dma_interrupt = dwmac4_dma_interrupt, 596 .get_hw_feature = dwmac4_get_hw_feature, 597 .rx_watchdog = dwmac4_rx_watchdog, 598 .set_rx_ring_len = dwmac4_set_rx_ring_len, 599 .set_tx_ring_len = dwmac4_set_tx_ring_len, 600 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 601 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 602 .enable_tso = dwmac4_enable_tso, 603 .qmode = dwmac4_qmode, 604 .set_bfsize = dwmac4_set_bfsize, 605 .enable_sph = dwmac4_enable_sph, 606 .enable_tbs = dwmac4_enable_tbs, 607 }; 608