1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This contains the functions to handle the descriptors for DesignWare databook 4 * 4.xx. 5 * 6 * Copyright (C) 2015 STMicroelectronics Ltd 7 * 8 * Author: Alexandre Torgue <alexandre.torgue@st.com> 9 */ 10 11 #include <linux/stmmac.h> 12 #include "common.h" 13 #include "dwmac4.h" 14 #include "dwmac4_descs.h" 15 16 static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x, 17 struct dma_desc *p, 18 void __iomem *ioaddr) 19 { 20 unsigned int tdes3; 21 int ret = tx_done; 22 23 tdes3 = le32_to_cpu(p->des3); 24 25 /* Get tx owner first */ 26 if (unlikely(tdes3 & TDES3_OWN)) 27 return tx_dma_own; 28 29 /* Verify tx error by looking at the last segment. */ 30 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR))) 31 return tx_not_ls; 32 33 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) { 34 ret = tx_err; 35 36 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT)) 37 x->tx_jabber++; 38 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED)) 39 x->tx_frame_flushed++; 40 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) { 41 x->tx_losscarrier++; 42 } 43 if (unlikely(tdes3 & TDES3_NO_CARRIER)) { 44 x->tx_carrier++; 45 } 46 if (unlikely((tdes3 & TDES3_LATE_COLLISION) || 47 (tdes3 & TDES3_EXCESSIVE_COLLISION))) 48 x->tx_collision += 49 (tdes3 & TDES3_COLLISION_COUNT_MASK) 50 >> TDES3_COLLISION_COUNT_SHIFT; 51 52 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL)) 53 x->tx_deferred++; 54 55 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) { 56 x->tx_underflow++; 57 ret |= tx_err_bump_tc; 58 } 59 60 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR)) 61 x->tx_ip_header_error++; 62 63 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR)) 64 x->tx_payload_error++; 65 } 66 67 if (unlikely(tdes3 & TDES3_DEFERRED)) 68 x->tx_deferred++; 69 70 return ret; 71 } 72 73 static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x, 74 struct dma_desc *p) 75 { 76 unsigned int rdes1 = le32_to_cpu(p->des1); 77 unsigned int rdes2 = le32_to_cpu(p->des2); 78 unsigned int rdes3 = le32_to_cpu(p->des3); 79 int message_type; 80 int ret = good_frame; 81 82 if (unlikely(rdes3 & RDES3_OWN)) 83 return dma_own; 84 85 if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR)) 86 return discard_frame; 87 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR))) 88 return rx_not_ls; 89 90 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) { 91 if (unlikely(rdes3 & RDES3_GIANT_PACKET)) 92 x->rx_length++; 93 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR)) 94 x->rx_gmac_overflow++; 95 96 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG)) 97 x->rx_watchdog++; 98 99 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR)) 100 x->rx_mii++; 101 102 if (unlikely(rdes3 & RDES3_CRC_ERROR)) 103 x->rx_crc_errors++; 104 105 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR)) 106 x->dribbling_bit++; 107 108 ret = discard_frame; 109 } 110 111 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8; 112 113 if (rdes1 & RDES1_IP_HDR_ERROR) 114 x->ip_hdr_err++; 115 if (rdes1 & RDES1_IP_CSUM_BYPASSED) 116 x->ip_csum_bypassed++; 117 if (rdes1 & RDES1_IPV4_HEADER) 118 x->ipv4_pkt_rcvd++; 119 if (rdes1 & RDES1_IPV6_HEADER) 120 x->ipv6_pkt_rcvd++; 121 122 if (message_type == RDES_EXT_NO_PTP) 123 x->no_ptp_rx_msg_type_ext++; 124 else if (message_type == RDES_EXT_SYNC) 125 x->ptp_rx_msg_type_sync++; 126 else if (message_type == RDES_EXT_FOLLOW_UP) 127 x->ptp_rx_msg_type_follow_up++; 128 else if (message_type == RDES_EXT_DELAY_REQ) 129 x->ptp_rx_msg_type_delay_req++; 130 else if (message_type == RDES_EXT_DELAY_RESP) 131 x->ptp_rx_msg_type_delay_resp++; 132 else if (message_type == RDES_EXT_PDELAY_REQ) 133 x->ptp_rx_msg_type_pdelay_req++; 134 else if (message_type == RDES_EXT_PDELAY_RESP) 135 x->ptp_rx_msg_type_pdelay_resp++; 136 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP) 137 x->ptp_rx_msg_type_pdelay_follow_up++; 138 else if (message_type == RDES_PTP_ANNOUNCE) 139 x->ptp_rx_msg_type_announce++; 140 else if (message_type == RDES_PTP_MANAGEMENT) 141 x->ptp_rx_msg_type_management++; 142 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE) 143 x->ptp_rx_msg_pkt_reserved_type++; 144 145 if (rdes1 & RDES1_PTP_PACKET_TYPE) 146 x->ptp_frame_type++; 147 if (rdes1 & RDES1_PTP_VER) 148 x->ptp_ver++; 149 if (rdes1 & RDES1_TIMESTAMP_DROPPED) 150 x->timestamp_dropped++; 151 152 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) { 153 x->sa_rx_filter_fail++; 154 ret = discard_frame; 155 } 156 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) { 157 x->da_rx_filter_fail++; 158 ret = discard_frame; 159 } 160 161 if (rdes2 & RDES2_L3_FILTER_MATCH) 162 x->l3_filter_match++; 163 if (rdes2 & RDES2_L4_FILTER_MATCH) 164 x->l4_filter_match++; 165 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK) 166 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT) 167 x->l3_l4_filter_no_match++; 168 169 return ret; 170 } 171 172 static int dwmac4_rd_get_tx_len(struct dma_desc *p) 173 { 174 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK); 175 } 176 177 static int dwmac4_get_tx_owner(struct dma_desc *p) 178 { 179 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT; 180 } 181 182 static void dwmac4_set_tx_owner(struct dma_desc *p) 183 { 184 p->des3 |= cpu_to_le32(TDES3_OWN); 185 } 186 187 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic) 188 { 189 p->des3 |= cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR); 190 191 if (!disable_rx_ic) 192 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN); 193 } 194 195 static int dwmac4_get_tx_ls(struct dma_desc *p) 196 { 197 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR) 198 >> TDES3_LAST_DESCRIPTOR_SHIFT; 199 } 200 201 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe) 202 { 203 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK); 204 } 205 206 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p) 207 { 208 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE); 209 } 210 211 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p) 212 { 213 /* Context type from W/B descriptor must be zero */ 214 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE) 215 return 0; 216 217 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */ 218 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS) 219 return 1; 220 221 return 0; 222 } 223 224 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts) 225 { 226 struct dma_desc *p = (struct dma_desc *)desc; 227 u64 ns; 228 229 ns = le32_to_cpu(p->des0); 230 /* convert high/sec time stamp value to nanosecond */ 231 ns += le32_to_cpu(p->des1) * 1000000000ULL; 232 233 *ts = ns; 234 } 235 236 static int dwmac4_rx_check_timestamp(void *desc) 237 { 238 struct dma_desc *p = (struct dma_desc *)desc; 239 unsigned int rdes0 = le32_to_cpu(p->des0); 240 unsigned int rdes1 = le32_to_cpu(p->des1); 241 unsigned int rdes3 = le32_to_cpu(p->des3); 242 u32 own, ctxt; 243 int ret = 1; 244 245 own = rdes3 & RDES3_OWN; 246 ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR) 247 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT); 248 249 if (likely(!own && ctxt)) { 250 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff)) 251 /* Corrupted value */ 252 ret = -EINVAL; 253 else 254 /* A valid Timestamp is ready to be read */ 255 ret = 0; 256 } 257 258 /* Timestamp not ready */ 259 return ret; 260 } 261 262 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc, 263 u32 ats) 264 { 265 struct dma_desc *p = (struct dma_desc *)desc; 266 int ret = -EINVAL; 267 268 /* Get the status from normal w/b descriptor */ 269 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) { 270 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) { 271 int i = 0; 272 273 /* Check if timestamp is OK from context descriptor */ 274 do { 275 ret = dwmac4_rx_check_timestamp(next_desc); 276 if (ret < 0) 277 goto exit; 278 i++; 279 280 } while ((ret == 1) && (i < 10)); 281 282 if (i == 10) 283 ret = -EBUSY; 284 } 285 } 286 exit: 287 if (likely(ret == 0)) 288 return 1; 289 290 return 0; 291 } 292 293 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic, 294 int mode, int end, int bfsize) 295 { 296 dwmac4_set_rx_owner(p, disable_rx_ic); 297 } 298 299 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end) 300 { 301 p->des0 = 0; 302 p->des1 = 0; 303 p->des2 = 0; 304 p->des3 = 0; 305 } 306 307 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 308 bool csum_flag, int mode, bool tx_own, 309 bool ls, unsigned int tot_pkt_len) 310 { 311 unsigned int tdes3 = le32_to_cpu(p->des3); 312 313 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK); 314 315 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK; 316 if (is_fs) 317 tdes3 |= TDES3_FIRST_DESCRIPTOR; 318 else 319 tdes3 &= ~TDES3_FIRST_DESCRIPTOR; 320 321 if (likely(csum_flag)) 322 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT); 323 else 324 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT); 325 326 if (ls) 327 tdes3 |= TDES3_LAST_DESCRIPTOR; 328 else 329 tdes3 &= ~TDES3_LAST_DESCRIPTOR; 330 331 /* Finally set the OWN bit. Later the DMA will start! */ 332 if (tx_own) 333 tdes3 |= TDES3_OWN; 334 335 if (is_fs && tx_own) 336 /* When the own bit, for the first frame, has to be set, all 337 * descriptors for the same frame has to be set before, to 338 * avoid race condition. 339 */ 340 dma_wmb(); 341 342 p->des3 = cpu_to_le32(tdes3); 343 } 344 345 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs, 346 int len1, int len2, bool tx_own, 347 bool ls, unsigned int tcphdrlen, 348 unsigned int tcppayloadlen) 349 { 350 unsigned int tdes3 = le32_to_cpu(p->des3); 351 352 if (len1) 353 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK)); 354 355 if (len2) 356 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT) 357 & TDES2_BUFFER2_SIZE_MASK); 358 359 if (is_fs) { 360 tdes3 |= TDES3_FIRST_DESCRIPTOR | 361 TDES3_TCP_SEGMENTATION_ENABLE | 362 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) & 363 TDES3_SLOT_NUMBER_MASK) | 364 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK)); 365 } else { 366 tdes3 &= ~TDES3_FIRST_DESCRIPTOR; 367 } 368 369 if (ls) 370 tdes3 |= TDES3_LAST_DESCRIPTOR; 371 else 372 tdes3 &= ~TDES3_LAST_DESCRIPTOR; 373 374 /* Finally set the OWN bit. Later the DMA will start! */ 375 if (tx_own) 376 tdes3 |= TDES3_OWN; 377 378 if (is_fs && tx_own) 379 /* When the own bit, for the first frame, has to be set, all 380 * descriptors for the same frame has to be set before, to 381 * avoid race condition. 382 */ 383 dma_wmb(); 384 385 p->des3 = cpu_to_le32(tdes3); 386 } 387 388 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode) 389 { 390 p->des0 = 0; 391 p->des1 = 0; 392 p->des2 = 0; 393 p->des3 = 0; 394 } 395 396 static void dwmac4_rd_set_tx_ic(struct dma_desc *p) 397 { 398 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION); 399 } 400 401 static void dwmac4_display_ring(void *head, unsigned int size, bool rx, 402 dma_addr_t dma_rx_phy, unsigned int desc_size) 403 { 404 dma_addr_t dma_addr; 405 int i; 406 407 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX"); 408 409 if (desc_size == sizeof(struct dma_desc)) { 410 struct dma_desc *p = (struct dma_desc *)head; 411 412 for (i = 0; i < size; i++) { 413 dma_addr = dma_rx_phy + i * sizeof(*p); 414 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 415 i, &dma_addr, 416 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 417 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 418 p++; 419 } 420 } else if (desc_size == sizeof(struct dma_extended_desc)) { 421 struct dma_extended_desc *extp = (struct dma_extended_desc *)head; 422 423 for (i = 0; i < size; i++) { 424 dma_addr = dma_rx_phy + i * sizeof(*extp); 425 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 426 i, &dma_addr, 427 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1), 428 le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3), 429 le32_to_cpu(extp->des4), le32_to_cpu(extp->des5), 430 le32_to_cpu(extp->des6), le32_to_cpu(extp->des7)); 431 extp++; 432 } 433 } else if (desc_size == sizeof(struct dma_edesc)) { 434 struct dma_edesc *ep = (struct dma_edesc *)head; 435 436 for (i = 0; i < size; i++) { 437 dma_addr = dma_rx_phy + i * sizeof(*ep); 438 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 439 i, &dma_addr, 440 le32_to_cpu(ep->des4), le32_to_cpu(ep->des5), 441 le32_to_cpu(ep->des6), le32_to_cpu(ep->des7), 442 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1), 443 le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3)); 444 ep++; 445 } 446 } else { 447 pr_err("unsupported descriptor!"); 448 } 449 } 450 451 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss) 452 { 453 p->des0 = 0; 454 p->des1 = 0; 455 p->des2 = cpu_to_le32(mss); 456 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV); 457 } 458 459 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr) 460 { 461 p->des0 = cpu_to_le32(lower_32_bits(addr)); 462 p->des1 = cpu_to_le32(upper_32_bits(addr)); 463 } 464 465 static void dwmac4_clear(struct dma_desc *p) 466 { 467 p->des0 = 0; 468 p->des1 = 0; 469 p->des2 = 0; 470 p->des3 = 0; 471 } 472 473 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type) 474 { 475 sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT; 476 477 p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK); 478 } 479 480 static int set_16kib_bfsize(int mtu) 481 { 482 int ret = 0; 483 484 if (unlikely(mtu >= BUF_SIZE_8KiB)) 485 ret = BUF_SIZE_16KiB; 486 return ret; 487 } 488 489 static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag, 490 u32 inner_type) 491 { 492 p->des0 = 0; 493 p->des1 = 0; 494 p->des2 = 0; 495 p->des3 = 0; 496 497 /* Inner VLAN */ 498 if (inner_type) { 499 u32 des = inner_tag << TDES2_IVT_SHIFT; 500 501 des &= TDES2_IVT_MASK; 502 p->des2 = cpu_to_le32(des); 503 504 des = inner_type << TDES3_IVTIR_SHIFT; 505 des &= TDES3_IVTIR_MASK; 506 p->des3 = cpu_to_le32(des | TDES3_IVLTV); 507 } 508 509 /* Outer VLAN */ 510 p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG); 511 p->des3 |= cpu_to_le32(TDES3_VLTV); 512 513 p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE); 514 } 515 516 static void dwmac4_set_vlan(struct dma_desc *p, u32 type) 517 { 518 type <<= TDES2_VLAN_TAG_SHIFT; 519 p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK); 520 } 521 522 static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len) 523 { 524 *len = le32_to_cpu(p->des2) & RDES2_HL; 525 } 526 527 static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid) 528 { 529 p->des2 = cpu_to_le32(lower_32_bits(addr)); 530 p->des3 = cpu_to_le32(upper_32_bits(addr)); 531 532 if (buf2_valid) 533 p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR); 534 else 535 p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR); 536 } 537 538 static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec) 539 { 540 p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV); 541 p->des5 = cpu_to_le32(nsec & TDES5_LT); 542 p->des6 = 0; 543 p->des7 = 0; 544 } 545 546 const struct stmmac_desc_ops dwmac4_desc_ops = { 547 .tx_status = dwmac4_wrback_get_tx_status, 548 .rx_status = dwmac4_wrback_get_rx_status, 549 .get_tx_len = dwmac4_rd_get_tx_len, 550 .get_tx_owner = dwmac4_get_tx_owner, 551 .set_tx_owner = dwmac4_set_tx_owner, 552 .set_rx_owner = dwmac4_set_rx_owner, 553 .get_tx_ls = dwmac4_get_tx_ls, 554 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len, 555 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp, 556 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status, 557 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status, 558 .get_timestamp = dwmac4_get_timestamp, 559 .set_tx_ic = dwmac4_rd_set_tx_ic, 560 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc, 561 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc, 562 .release_tx_desc = dwmac4_release_tx_desc, 563 .init_rx_desc = dwmac4_rd_init_rx_desc, 564 .init_tx_desc = dwmac4_rd_init_tx_desc, 565 .display_ring = dwmac4_display_ring, 566 .set_mss = dwmac4_set_mss_ctxt, 567 .set_addr = dwmac4_set_addr, 568 .clear = dwmac4_clear, 569 .set_sarc = dwmac4_set_sarc, 570 .set_vlan_tag = dwmac4_set_vlan_tag, 571 .set_vlan = dwmac4_set_vlan, 572 .get_rx_header_len = dwmac4_get_rx_header_len, 573 .set_sec_addr = dwmac4_set_sec_addr, 574 .set_tbs = dwmac4_set_tbs, 575 }; 576 577 const struct stmmac_mode_ops dwmac4_ring_mode_ops = { 578 .set_16kib_bfsize = set_16kib_bfsize, 579 }; 580