1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 Header file. 4 * 5 * Copyright (C) 2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_H__ 11 #define __DWMAC4_H__ 12 13 #include "common.h" 14 15 /* MAC registers */ 16 #define GMAC_CONFIG 0x00000000 17 #define GMAC_EXT_CONFIG 0x00000004 18 #define GMAC_PACKET_FILTER 0x00000008 19 #define GMAC_HASH_TAB(x) (0x10 + (x) * 4) 20 #define GMAC_VLAN_TAG 0x00000050 21 #define GMAC_VLAN_TAG_DATA 0x00000054 22 #define GMAC_VLAN_HASH_TABLE 0x00000058 23 #define GMAC_RX_FLOW_CTRL 0x00000090 24 #define GMAC_VLAN_INCL 0x00000060 25 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 26 #define GMAC_TXQ_PRTY_MAP0 0x98 27 #define GMAC_TXQ_PRTY_MAP1 0x9C 28 #define GMAC_RXQ_CTRL0 0x000000a0 29 #define GMAC_RXQ_CTRL1 0x000000a4 30 #define GMAC_RXQ_CTRL2 0x000000a8 31 #define GMAC_RXQ_CTRL3 0x000000ac 32 #define GMAC_INT_STATUS 0x000000b0 33 #define GMAC_INT_EN 0x000000b4 34 #define GMAC_PCS_BASE 0x000000e0 35 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 36 #define GMAC_PMT 0x000000c0 37 #define GMAC_DEBUG 0x00000114 38 #define GMAC_HW_FEATURE0 0x0000011c 39 #define GMAC_HW_FEATURE1 0x00000120 40 #define GMAC_HW_FEATURE2 0x00000124 41 #define GMAC_HW_FEATURE3 0x00000128 42 #define GMAC_MDIO_ADDR 0x00000200 43 #define GMAC_MDIO_DATA 0x00000204 44 #define GMAC_GPIO_STATUS 0x0000020C 45 #define GMAC_ARP_ADDR 0x00000210 46 #define GMAC_EXT_CFG1 0x00000238 47 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 48 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 49 #define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30) 50 #define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30) 51 #define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30) 52 #define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30) 53 #define GMAC_TIMESTAMP_STATUS 0x00000b20 54 55 /* RX Queues Routing */ 56 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 57 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0 58 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 59 #define GMAC_RXQCTRL_PTPQ_SHIFT 4 60 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 61 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 62 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 63 #define GMAC_RXQCTRL_UPQ_SHIFT 12 64 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 65 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16 66 #define GMAC_RXQCTRL_MCBCQEN BIT(20) 67 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 68 #define GMAC_RXQCTRL_TACPQE BIT(21) 69 #define GMAC_RXQCTRL_TACPQE_SHIFT 21 70 #define GMAC_RXQCTRL_FPRQ GENMASK(26, 24) 71 72 /* MAC Packet Filtering */ 73 #define GMAC_PACKET_FILTER_PR BIT(0) 74 #define GMAC_PACKET_FILTER_HMC BIT(2) 75 #define GMAC_PACKET_FILTER_PM BIT(4) 76 #define GMAC_PACKET_FILTER_PCF BIT(7) 77 #define GMAC_PACKET_FILTER_HPF BIT(10) 78 #define GMAC_PACKET_FILTER_VTFE BIT(16) 79 #define GMAC_PACKET_FILTER_IPFE BIT(20) 80 #define GMAC_PACKET_FILTER_RA BIT(31) 81 82 #define GMAC_MAX_PERFECT_ADDRESSES 128 83 84 /* MAC VLAN */ 85 #define GMAC_VLAN_EDVLP BIT(26) 86 #define GMAC_VLAN_VTHM BIT(25) 87 #define GMAC_VLAN_DOVLTC BIT(20) 88 #define GMAC_VLAN_ESVL BIT(18) 89 #define GMAC_VLAN_ETV BIT(16) 90 #define GMAC_VLAN_VID GENMASK(15, 0) 91 #define GMAC_VLAN_VLTI BIT(20) 92 #define GMAC_VLAN_CSVL BIT(19) 93 #define GMAC_VLAN_VLC GENMASK(17, 16) 94 #define GMAC_VLAN_VLC_SHIFT 16 95 #define GMAC_VLAN_VLHT GENMASK(15, 0) 96 97 /* MAC VLAN Tag */ 98 #define GMAC_VLAN_TAG_VID GENMASK(15, 0) 99 #define GMAC_VLAN_TAG_ETV BIT(16) 100 101 /* MAC VLAN Tag Control */ 102 #define GMAC_VLAN_TAG_CTRL_OB BIT(0) 103 #define GMAC_VLAN_TAG_CTRL_CT BIT(1) 104 #define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2) 105 #define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2 106 #define GMAC_VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21) 107 #define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT 21 108 #define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24) 109 110 #define GMAC_VLAN_TAG_STRIP_NONE (0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 111 #define GMAC_VLAN_TAG_STRIP_PASS (0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 112 #define GMAC_VLAN_TAG_STRIP_FAIL (0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 113 #define GMAC_VLAN_TAG_STRIP_ALL (0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 114 115 /* MAC VLAN Tag Data/Filter */ 116 #define GMAC_VLAN_TAG_DATA_VID GENMASK(15, 0) 117 #define GMAC_VLAN_TAG_DATA_VEN BIT(16) 118 #define GMAC_VLAN_TAG_DATA_ETV BIT(17) 119 120 /* MAC RX Queue Enable */ 121 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 122 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 123 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 124 125 /* MAC Flow Control RX */ 126 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 127 128 /* RX Queues Priorities */ 129 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 130 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 131 132 /* TX Queues Priorities */ 133 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 134 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 135 136 /* MAC Flow Control TX */ 137 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 138 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 139 140 /* MAC Interrupt bitmap*/ 141 #define GMAC_INT_RGSMIIS BIT(0) 142 #define GMAC_INT_PCS_LINK BIT(1) 143 #define GMAC_INT_PCS_ANE BIT(2) 144 #define GMAC_INT_PCS_PHYIS BIT(3) 145 #define GMAC_INT_PMT_EN BIT(4) 146 #define GMAC_INT_LPI_EN BIT(5) 147 #define GMAC_INT_TSIE BIT(12) 148 149 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 150 GMAC_INT_PCS_ANE) 151 152 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \ 153 GMAC_INT_TSIE) 154 155 enum dwmac4_irq_status { 156 time_stamp_irq = 0x00001000, 157 mmc_rx_csum_offload_irq = 0x00000800, 158 mmc_tx_irq = 0x00000400, 159 mmc_rx_irq = 0x00000200, 160 mmc_irq = 0x00000100, 161 lpi_irq = 0x00000020, 162 pmt_irq = 0x00000010, 163 }; 164 165 /* MAC PMT bitmap */ 166 enum power_event { 167 pointer_reset = 0x80000000, 168 global_unicast = 0x00000200, 169 wake_up_rx_frame = 0x00000040, 170 magic_frame = 0x00000020, 171 wake_up_frame_en = 0x00000004, 172 magic_pkt_en = 0x00000002, 173 power_down = 0x00000001, 174 }; 175 176 /* Energy Efficient Ethernet (EEE) for GMAC4 177 * 178 * LPI status, timer and control register offset 179 * For LPI control and status bit definitions, see common.h. 180 */ 181 #define GMAC4_LPI_CTRL_STATUS 0xd0 182 #define GMAC4_LPI_TIMER_CTRL 0xd4 183 #define GMAC4_LPI_ENTRY_TIMER 0xd8 184 #define GMAC4_MAC_ONEUS_TIC_COUNTER 0xdc 185 186 /* MAC Debug bitmap */ 187 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 188 #define GMAC_DEBUG_TFCSTS_SHIFT 17 189 #define GMAC_DEBUG_TFCSTS_IDLE 0 190 #define GMAC_DEBUG_TFCSTS_WAIT 1 191 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 192 #define GMAC_DEBUG_TFCSTS_XFER 3 193 #define GMAC_DEBUG_TPESTS BIT(16) 194 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 195 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 196 #define GMAC_DEBUG_RPESTS BIT(0) 197 198 /* MAC config */ 199 #define GMAC_CONFIG_ARPEN BIT(31) 200 #define GMAC_CONFIG_SARC GENMASK(30, 28) 201 #define GMAC_CONFIG_SARC_SHIFT 28 202 #define GMAC_CONFIG_IPC BIT(27) 203 #define GMAC_CONFIG_IPG GENMASK(26, 24) 204 #define GMAC_CONFIG_IPG_SHIFT 24 205 #define GMAC_CONFIG_2K BIT(22) 206 #define GMAC_CONFIG_ACS BIT(20) 207 #define GMAC_CONFIG_BE BIT(18) 208 #define GMAC_CONFIG_JD BIT(17) 209 #define GMAC_CONFIG_JE BIT(16) 210 #define GMAC_CONFIG_PS BIT(15) 211 #define GMAC_CONFIG_FES BIT(14) 212 #define GMAC_CONFIG_FES_SHIFT 14 213 #define GMAC_CONFIG_DM BIT(13) 214 #define GMAC_CONFIG_LM BIT(12) 215 #define GMAC_CONFIG_DCRS BIT(9) 216 #define GMAC_CONFIG_TE BIT(1) 217 #define GMAC_CONFIG_RE BIT(0) 218 219 /* MAC extended config */ 220 #define GMAC_CONFIG_EIPG GENMASK(29, 25) 221 #define GMAC_CONFIG_EIPG_SHIFT 25 222 #define GMAC_CONFIG_EIPG_EN BIT(24) 223 #define GMAC_CONFIG_HDSMS GENMASK(22, 20) 224 #define GMAC_CONFIG_HDSMS_SHIFT 20 225 #define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT) 226 227 /* MAC HW features0 bitmap */ 228 #define GMAC_HW_FEAT_SAVLANINS BIT(27) 229 #define GMAC_HW_FEAT_ADDMAC BIT(18) 230 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 231 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 232 #define GMAC_HW_FEAT_EEESEL BIT(13) 233 #define GMAC_HW_FEAT_TSSEL BIT(12) 234 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9) 235 #define GMAC_HW_FEAT_MMCSEL BIT(8) 236 #define GMAC_HW_FEAT_MGKSEL BIT(7) 237 #define GMAC_HW_FEAT_RWKSEL BIT(6) 238 #define GMAC_HW_FEAT_SMASEL BIT(5) 239 #define GMAC_HW_FEAT_VLHASH BIT(4) 240 #define GMAC_HW_FEAT_PCSSEL BIT(3) 241 #define GMAC_HW_FEAT_HDSEL BIT(2) 242 #define GMAC_HW_FEAT_GMIISEL BIT(1) 243 #define GMAC_HW_FEAT_MIISEL BIT(0) 244 245 /* MAC HW features1 bitmap */ 246 #define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27) 247 #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) 248 #define GMAC_HW_FEAT_AVSEL BIT(20) 249 #define GMAC_HW_TSOEN BIT(18) 250 #define GMAC_HW_FEAT_SPHEN BIT(17) 251 #define GMAC_HW_ADDR64 GENMASK(15, 14) 252 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 253 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 254 255 /* MAC HW features2 bitmap */ 256 #define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28) 257 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24) 258 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 259 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 260 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 261 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 262 263 /* MAC HW features3 bitmap */ 264 #define GMAC_HW_FEAT_ASP GENMASK(29, 28) 265 #define GMAC_HW_FEAT_TBSSEL BIT(27) 266 #define GMAC_HW_FEAT_FPESEL BIT(26) 267 #define GMAC_HW_FEAT_ESTWID GENMASK(21, 20) 268 #define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17) 269 #define GMAC_HW_FEAT_ESTSEL BIT(16) 270 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13) 271 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11) 272 #define GMAC_HW_FEAT_FRPSEL BIT(10) 273 #define GMAC_HW_FEAT_DVLAN BIT(5) 274 #define GMAC_HW_FEAT_NRVF GENMASK(2, 0) 275 276 /* MAC extended config 1 */ 277 #define GMAC_CONFIG1_SAVE_EN BIT(24) 278 #define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v) 279 280 /* GMAC GPIO Status reg */ 281 #define GMAC_GPO0 BIT(16) 282 #define GMAC_GPO1 BIT(17) 283 #define GMAC_GPO2 BIT(18) 284 #define GMAC_GPO3 BIT(19) 285 286 /* MAC HW ADDR regs */ 287 #define GMAC_HI_DCS GENMASK(18, 16) 288 #define GMAC_HI_DCS_SHIFT 16 289 #define GMAC_HI_REG_AE BIT(31) 290 291 /* L3/L4 Filters regs */ 292 #define GMAC_L4DPIM0 BIT(21) 293 #define GMAC_L4DPM0 BIT(20) 294 #define GMAC_L4SPIM0 BIT(19) 295 #define GMAC_L4SPM0 BIT(18) 296 #define GMAC_L4PEN0 BIT(16) 297 #define GMAC_L3DAIM0 BIT(5) 298 #define GMAC_L3DAM0 BIT(4) 299 #define GMAC_L3SAIM0 BIT(3) 300 #define GMAC_L3SAM0 BIT(2) 301 #define GMAC_L3PEN0 BIT(0) 302 #define GMAC_L4DP0 GENMASK(31, 16) 303 #define GMAC_L4DP0_SHIFT 16 304 #define GMAC_L4SP0 GENMASK(15, 0) 305 306 /* MAC Timestamp Status */ 307 #define GMAC_TIMESTAMP_AUXTSTRIG BIT(2) 308 #define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25) 309 #define GMAC_TIMESTAMP_ATSNS_SHIFT 25 310 311 /* MTL registers */ 312 #define MTL_OPERATION_MODE 0x00000c00 313 #define MTL_FRPE BIT(15) 314 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 315 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 316 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 317 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 318 #define MTL_OPERATION_SCHALG_SP (0x3 << 5) 319 #define MTL_OPERATION_RAA BIT(2) 320 #define MTL_OPERATION_RAA_SP (0x0 << 2) 321 #define MTL_OPERATION_RAA_WSP (0x1 << 2) 322 323 #define MTL_INT_STATUS 0x00000c20 324 #define MTL_INT_QX(x) BIT(x) 325 326 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 327 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 328 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x)) 329 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 330 331 #define MTL_CHAN_BASE_ADDR 0x00000d00 332 #define MTL_CHAN_BASE_OFFSET 0x40 333 334 static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs, 335 const u32 x) 336 { 337 u32 addr; 338 339 if (addrs) 340 addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset); 341 else 342 addr = MTL_CHAN_BASE_ADDR + (x * MTL_CHAN_BASE_OFFSET); 343 344 return addr; 345 } 346 347 #define MTL_CHAN_TX_OP_MODE(addrs, x) mtl_chanx_base_addr(addrs, x) 348 #define MTL_CHAN_TX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x8) 349 #define MTL_CHAN_INT_CTRL(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x2c) 350 #define MTL_CHAN_RX_OP_MODE(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x30) 351 #define MTL_CHAN_RX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x38) 352 353 #define MTL_OP_MODE_RSF BIT(5) 354 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 355 #define MTL_OP_MODE_TXQEN_AV BIT(2) 356 #define MTL_OP_MODE_TXQEN BIT(3) 357 #define MTL_OP_MODE_TSF BIT(1) 358 359 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 360 #define MTL_OP_MODE_TQS_SHIFT 16 361 362 #define MTL_OP_MODE_TTC_MASK 0x70 363 #define MTL_OP_MODE_TTC_SHIFT 4 364 365 #define MTL_OP_MODE_TTC_32 0 366 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 367 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 368 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 369 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 370 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 371 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 372 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 373 374 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 375 #define MTL_OP_MODE_RQS_SHIFT 20 376 377 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 378 #define MTL_OP_MODE_RFD_SHIFT 14 379 380 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 381 #define MTL_OP_MODE_RFA_SHIFT 8 382 383 #define MTL_OP_MODE_EHFC BIT(7) 384 385 #define MTL_OP_MODE_RTC_MASK GENMASK(1, 0) 386 #define MTL_OP_MODE_RTC_SHIFT 0 387 388 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 389 #define MTL_OP_MODE_RTC_64 0 390 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 391 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 392 393 /* MTL ETS Control register */ 394 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 395 #define MTL_ETS_CTRL_BASE_OFFSET 0x40 396 397 static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs, 398 const u32 x) 399 { 400 u32 addr; 401 402 if (addrs) 403 addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset); 404 else 405 addr = MTL_ETS_CTRL_BASE_ADDR + (x * MTL_ETS_CTRL_BASE_OFFSET); 406 407 return addr; 408 } 409 410 #define MTL_ETS_CTRL_CC BIT(3) 411 #define MTL_ETS_CTRL_AVALG BIT(2) 412 413 /* MTL Queue Quantum Weight */ 414 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 415 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 416 417 static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs, 418 const u32 x) 419 { 420 u32 addr; 421 422 if (addrs) 423 addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset); 424 else 425 addr = MTL_TXQ_WEIGHT_BASE_ADDR + (x * MTL_TXQ_WEIGHT_BASE_OFFSET); 426 427 return addr; 428 } 429 430 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 431 432 /* MTL sendSlopeCredit register */ 433 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 434 #define MTL_SEND_SLP_CRED_OFFSET 0x40 435 436 static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs, 437 const u32 x) 438 { 439 u32 addr; 440 441 if (addrs) 442 addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset); 443 else 444 addr = MTL_SEND_SLP_CRED_BASE_ADDR + (x * MTL_SEND_SLP_CRED_OFFSET); 445 446 return addr; 447 } 448 449 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 450 451 /* MTL hiCredit register */ 452 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 453 #define MTL_HIGH_CRED_OFFSET 0x40 454 455 static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs, 456 const u32 x) 457 { 458 u32 addr; 459 460 if (addrs) 461 addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset); 462 else 463 addr = MTL_HIGH_CRED_BASE_ADDR + (x * MTL_HIGH_CRED_OFFSET); 464 465 return addr; 466 } 467 468 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 469 470 /* MTL loCredit register */ 471 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24 472 #define MTL_LOW_CRED_OFFSET 0x40 473 474 static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs, 475 const u32 x) 476 { 477 u32 addr; 478 479 if (addrs) 480 addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset); 481 else 482 addr = MTL_LOW_CRED_BASE_ADDR + (x * MTL_LOW_CRED_OFFSET); 483 484 return addr; 485 } 486 487 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 488 489 /* MTL debug */ 490 #define MTL_DEBUG_TXSTSFSTS BIT(5) 491 #define MTL_DEBUG_TXFSTS BIT(4) 492 #define MTL_DEBUG_TWCSTS BIT(3) 493 494 /* MTL debug: Tx FIFO Read Controller Status */ 495 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 496 #define MTL_DEBUG_TRCSTS_SHIFT 1 497 #define MTL_DEBUG_TRCSTS_IDLE 0 498 #define MTL_DEBUG_TRCSTS_READ 1 499 #define MTL_DEBUG_TRCSTS_TXW 2 500 #define MTL_DEBUG_TRCSTS_WRITE 3 501 #define MTL_DEBUG_TXPAUSED BIT(0) 502 503 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 504 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 505 #define MTL_DEBUG_RXFSTS_SHIFT 4 506 #define MTL_DEBUG_RXFSTS_EMPTY 0 507 #define MTL_DEBUG_RXFSTS_BT 1 508 #define MTL_DEBUG_RXFSTS_AT 2 509 #define MTL_DEBUG_RXFSTS_FULL 3 510 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 511 #define MTL_DEBUG_RRCSTS_SHIFT 1 512 #define MTL_DEBUG_RRCSTS_IDLE 0 513 #define MTL_DEBUG_RRCSTS_RDATA 1 514 #define MTL_DEBUG_RRCSTS_RSTAT 2 515 #define MTL_DEBUG_RRCSTS_FLUSH 3 516 #define MTL_DEBUG_RWCSTS BIT(0) 517 518 /* MTL interrupt */ 519 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 520 #define MTL_RX_OVERFLOW_INT BIT(16) 521 522 /* Default operating mode of the MAC */ 523 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 524 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \ 525 GMAC_CONFIG_JE) 526 527 /* To dump the core regs excluding the Address Registers */ 528 #define GMAC_REG_NUM 132 529 530 /* MTL debug */ 531 #define MTL_DEBUG_TXSTSFSTS BIT(5) 532 #define MTL_DEBUG_TXFSTS BIT(4) 533 #define MTL_DEBUG_TWCSTS BIT(3) 534 535 /* MTL debug: Tx FIFO Read Controller Status */ 536 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 537 #define MTL_DEBUG_TRCSTS_SHIFT 1 538 #define MTL_DEBUG_TRCSTS_IDLE 0 539 #define MTL_DEBUG_TRCSTS_READ 1 540 #define MTL_DEBUG_TRCSTS_TXW 2 541 #define MTL_DEBUG_TRCSTS_WRITE 3 542 #define MTL_DEBUG_TXPAUSED BIT(0) 543 544 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 545 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 546 #define MTL_DEBUG_RXFSTS_SHIFT 4 547 #define MTL_DEBUG_RXFSTS_EMPTY 0 548 #define MTL_DEBUG_RXFSTS_BT 1 549 #define MTL_DEBUG_RXFSTS_AT 2 550 #define MTL_DEBUG_RXFSTS_FULL 3 551 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 552 #define MTL_DEBUG_RRCSTS_SHIFT 1 553 #define MTL_DEBUG_RRCSTS_IDLE 0 554 #define MTL_DEBUG_RRCSTS_RDATA 1 555 #define MTL_DEBUG_RRCSTS_RSTAT 2 556 #define MTL_DEBUG_RRCSTS_FLUSH 3 557 #define MTL_DEBUG_RWCSTS BIT(0) 558 559 /* SGMII/RGMII status register */ 560 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 561 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 562 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 563 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 564 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 565 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 566 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 567 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 568 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 569 /* LNKSPEED */ 570 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 571 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 572 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 573 574 extern const struct stmmac_dma_ops dwmac4_dma_ops; 575 extern const struct stmmac_dma_ops dwmac410_dma_ops; 576 #endif /* __DWMAC4_H__ */ 577