1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 Header file. 4 * 5 * Copyright (C) 2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_H__ 11 #define __DWMAC4_H__ 12 13 #include "common.h" 14 15 /* MAC registers */ 16 #define GMAC_CONFIG 0x00000000 17 #define GMAC_EXT_CONFIG 0x00000004 18 #define GMAC_PACKET_FILTER 0x00000008 19 #define GMAC_HASH_TAB(x) (0x10 + (x) * 4) 20 #define GMAC_RX_FLOW_CTRL 0x00000090 21 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 22 #define GMAC_TXQ_PRTY_MAP0 0x98 23 #define GMAC_TXQ_PRTY_MAP1 0x9C 24 #define GMAC_RXQ_CTRL0 0x000000a0 25 #define GMAC_RXQ_CTRL1 0x000000a4 26 #define GMAC_RXQ_CTRL2 0x000000a8 27 #define GMAC_RXQ_CTRL3 0x000000ac 28 #define GMAC_INT_STATUS 0x000000b0 29 #define GMAC_INT_EN 0x000000b4 30 #define GMAC_PCS_BASE 0x000000e0 31 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 32 #define GMAC_PMT 0x000000c0 33 #define GMAC_DEBUG 0x00000114 34 #define GMAC_HW_FEATURE0 0x0000011c 35 #define GMAC_HW_FEATURE1 0x00000120 36 #define GMAC_HW_FEATURE2 0x00000124 37 #define GMAC_HW_FEATURE3 0x00000128 38 #define GMAC_MDIO_ADDR 0x00000200 39 #define GMAC_MDIO_DATA 0x00000204 40 #define GMAC_GPIO_STATUS 0x0000020C 41 #define GMAC_ARP_ADDR 0x00000210 42 #define GMAC_EXT_CFG1 0x00000238 43 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 44 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 45 #define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30) 46 #define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30) 47 #define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30) 48 #define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30) 49 #define GMAC_TIMESTAMP_STATUS 0x00000b20 50 51 /* RX Queues Routing */ 52 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 53 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0 54 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 55 #define GMAC_RXQCTRL_PTPQ_SHIFT 4 56 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 57 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 58 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 59 #define GMAC_RXQCTRL_UPQ_SHIFT 12 60 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 61 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16 62 #define GMAC_RXQCTRL_MCBCQEN BIT(20) 63 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 64 #define GMAC_RXQCTRL_TACPQE BIT(21) 65 #define GMAC_RXQCTRL_TACPQE_SHIFT 21 66 #define GMAC_RXQCTRL_FPRQ GENMASK(26, 24) 67 68 /* MAC Packet Filtering */ 69 #define GMAC_PACKET_FILTER_PR BIT(0) 70 #define GMAC_PACKET_FILTER_HMC BIT(2) 71 #define GMAC_PACKET_FILTER_PM BIT(4) 72 #define GMAC_PACKET_FILTER_PCF BIT(7) 73 #define GMAC_PACKET_FILTER_HPF BIT(10) 74 #define GMAC_PACKET_FILTER_VTFE BIT(16) 75 #define GMAC_PACKET_FILTER_IPFE BIT(20) 76 #define GMAC_PACKET_FILTER_RA BIT(31) 77 78 #define GMAC_MAX_PERFECT_ADDRESSES 128 79 80 /* MAC RX Queue Enable */ 81 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 82 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 83 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 84 85 /* MAC Flow Control RX */ 86 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 87 88 /* RX Queues Priorities */ 89 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 90 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 91 92 /* TX Queues Priorities */ 93 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 94 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 95 96 /* MAC Flow Control TX */ 97 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 98 #define GMAC_TX_FLOW_CTRL_PT_MASK GENMASK(31, 16) 99 100 /* MAC Interrupt bitmap*/ 101 #define GMAC_INT_RGSMIIS BIT(0) 102 #define GMAC_INT_PCS_LINK BIT(1) 103 #define GMAC_INT_PCS_ANE BIT(2) 104 #define GMAC_INT_PCS_PHYIS BIT(3) 105 #define GMAC_INT_PMT_EN BIT(4) 106 #define GMAC_INT_LPI_EN BIT(5) 107 #define GMAC_INT_TSIE BIT(12) 108 109 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \ 110 GMAC_INT_TSIE) 111 112 enum dwmac4_irq_status { 113 time_stamp_irq = 0x00001000, 114 mmc_rx_csum_offload_irq = 0x00000800, 115 mmc_tx_irq = 0x00000400, 116 mmc_rx_irq = 0x00000200, 117 mmc_irq = 0x00000100, 118 lpi_irq = 0x00000020, 119 pmt_irq = 0x00000010, 120 }; 121 122 /* MAC PMT bitmap */ 123 enum power_event { 124 pointer_reset = 0x80000000, 125 global_unicast = 0x00000200, 126 wake_up_rx_frame = 0x00000040, 127 magic_frame = 0x00000020, 128 wake_up_frame_en = 0x00000004, 129 magic_pkt_en = 0x00000002, 130 power_down = 0x00000001, 131 }; 132 133 /* Energy Efficient Ethernet (EEE) for GMAC4 134 * 135 * LPI status, timer and control register offset 136 * For LPI control and status bit definitions, see common.h. 137 */ 138 #define GMAC4_LPI_CTRL_STATUS 0xd0 139 #define GMAC4_LPI_TIMER_CTRL 0xd4 140 #define GMAC4_LPI_ENTRY_TIMER 0xd8 141 #define GMAC4_MAC_ONEUS_TIC_COUNTER 0xdc 142 143 /* MAC Debug bitmap */ 144 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 145 #define GMAC_DEBUG_TFCSTS_IDLE 0 146 #define GMAC_DEBUG_TFCSTS_WAIT 1 147 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 148 #define GMAC_DEBUG_TFCSTS_XFER 3 149 #define GMAC_DEBUG_TPESTS BIT(16) 150 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 151 #define GMAC_DEBUG_RPESTS BIT(0) 152 153 /* MAC config */ 154 #define GMAC_CONFIG_ARPEN BIT(31) 155 #define GMAC_CONFIG_SARC GENMASK(30, 28) 156 #define GMAC_CONFIG_IPC BIT(27) 157 #define GMAC_CONFIG_IPG GENMASK(26, 24) 158 #define GMAC_CONFIG_2K BIT(22) 159 #define GMAC_CONFIG_ACS BIT(20) 160 #define GMAC_CONFIG_BE BIT(18) 161 #define GMAC_CONFIG_JD BIT(17) 162 #define GMAC_CONFIG_JE BIT(16) 163 #define GMAC_CONFIG_PS BIT(15) 164 #define GMAC_CONFIG_FES BIT(14) 165 #define GMAC_CONFIG_DM BIT(13) 166 #define GMAC_CONFIG_LM BIT(12) 167 #define GMAC_CONFIG_DCRS BIT(9) 168 #define GMAC_CONFIG_TE BIT(1) 169 #define GMAC_CONFIG_RE BIT(0) 170 171 /* MAC extended config */ 172 #define GMAC_CONFIG_EIPG GENMASK(29, 25) 173 #define GMAC_CONFIG_EIPG_EN BIT(24) 174 #define GMAC_CONFIG_HDSMS GENMASK(22, 20) 175 #define GMAC_CONFIG_HDSMS_256 FIELD_PREP_CONST(GMAC_CONFIG_HDSMS, 0x2) 176 177 /* MAC HW features0 bitmap */ 178 #define GMAC_HW_FEAT_SAVLANINS BIT(27) 179 #define GMAC_HW_FEAT_ADDMAC BIT(18) 180 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 181 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 182 #define GMAC_HW_FEAT_EEESEL BIT(13) 183 #define GMAC_HW_FEAT_TSSEL BIT(12) 184 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9) 185 #define GMAC_HW_FEAT_MMCSEL BIT(8) 186 #define GMAC_HW_FEAT_MGKSEL BIT(7) 187 #define GMAC_HW_FEAT_RWKSEL BIT(6) 188 #define GMAC_HW_FEAT_SMASEL BIT(5) 189 #define GMAC_HW_FEAT_VLHASH BIT(4) 190 #define GMAC_HW_FEAT_PCSSEL BIT(3) 191 #define GMAC_HW_FEAT_HDSEL BIT(2) 192 #define GMAC_HW_FEAT_GMIISEL BIT(1) 193 #define GMAC_HW_FEAT_MIISEL BIT(0) 194 195 /* MAC HW features1 bitmap */ 196 #define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27) 197 #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) 198 #define GMAC_HW_FEAT_AVSEL BIT(20) 199 #define GMAC_HW_TSOEN BIT(18) 200 #define GMAC_HW_FEAT_SPHEN BIT(17) 201 #define GMAC_HW_ADDR64 GENMASK(15, 14) 202 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 203 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 204 205 /* MAC HW features2 bitmap */ 206 #define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28) 207 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24) 208 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 209 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 210 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 211 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 212 213 /* MAC HW features3 bitmap */ 214 #define GMAC_HW_FEAT_ASP GENMASK(29, 28) 215 #define GMAC_HW_FEAT_TBSSEL BIT(27) 216 #define GMAC_HW_FEAT_FPESEL BIT(26) 217 #define GMAC_HW_FEAT_ESTWID GENMASK(21, 20) 218 #define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17) 219 #define GMAC_HW_FEAT_ESTSEL BIT(16) 220 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13) 221 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11) 222 #define GMAC_HW_FEAT_FRPSEL BIT(10) 223 #define GMAC_HW_FEAT_DVLAN BIT(5) 224 #define GMAC_HW_FEAT_NRVF GENMASK(2, 0) 225 226 /* MAC extended config 1 */ 227 #define GMAC_CONFIG1_SAVE_EN BIT(24) 228 #define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v) 229 230 /* GMAC GPIO Status reg */ 231 #define GMAC_GPO0 BIT(16) 232 #define GMAC_GPO1 BIT(17) 233 #define GMAC_GPO2 BIT(18) 234 #define GMAC_GPO3 BIT(19) 235 236 /* MAC HW ADDR regs */ 237 #define GMAC_HI_DCS GENMASK(18, 16) 238 #define GMAC_HI_REG_AE BIT(31) 239 240 /* L3/L4 Filters regs */ 241 #define GMAC_L4DPIM0 BIT(21) 242 #define GMAC_L4DPM0 BIT(20) 243 #define GMAC_L4SPIM0 BIT(19) 244 #define GMAC_L4SPM0 BIT(18) 245 #define GMAC_L4PEN0 BIT(16) 246 #define GMAC_L3DAIM0 BIT(5) 247 #define GMAC_L3DAM0 BIT(4) 248 #define GMAC_L3SAIM0 BIT(3) 249 #define GMAC_L3SAM0 BIT(2) 250 #define GMAC_L3PEN0 BIT(0) 251 #define GMAC_L4DP0 GENMASK(31, 16) 252 #define GMAC_L4SP0 GENMASK(15, 0) 253 254 /* MAC Timestamp Status */ 255 #define GMAC_TIMESTAMP_AUXTSTRIG BIT(2) 256 #define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25) 257 #define GMAC_TIMESTAMP_ATSNS_SHIFT 25 258 259 /* MTL registers */ 260 #define MTL_OPERATION_MODE 0x00000c00 261 #define MTL_FRPE BIT(15) 262 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 263 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 264 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 265 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 266 #define MTL_OPERATION_SCHALG_SP (0x3 << 5) 267 #define MTL_OPERATION_RAA BIT(2) 268 #define MTL_OPERATION_RAA_SP (0x0 << 2) 269 #define MTL_OPERATION_RAA_WSP (0x1 << 2) 270 271 #define MTL_INT_STATUS 0x00000c20 272 #define MTL_INT_QX(x) BIT(x) 273 274 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 275 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 276 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x)) 277 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 278 279 #define MTL_CHAN_BASE_ADDR 0x00000d00 280 #define MTL_CHAN_BASE_OFFSET 0x40 281 282 static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs, 283 const u32 x) 284 { 285 u32 addr; 286 287 if (addrs) 288 addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset); 289 else 290 addr = MTL_CHAN_BASE_ADDR + (x * MTL_CHAN_BASE_OFFSET); 291 292 return addr; 293 } 294 295 #define MTL_CHAN_TX_OP_MODE(addrs, x) mtl_chanx_base_addr(addrs, x) 296 #define MTL_CHAN_TX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x8) 297 #define MTL_CHAN_INT_CTRL(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x2c) 298 #define MTL_CHAN_RX_OP_MODE(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x30) 299 #define MTL_CHAN_RX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x38) 300 301 #define MTL_OP_MODE_RSF BIT(5) 302 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 303 #define MTL_OP_MODE_TXQEN_AV BIT(2) 304 #define MTL_OP_MODE_TXQEN BIT(3) 305 #define MTL_OP_MODE_TSF BIT(1) 306 307 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 308 309 #define MTL_OP_MODE_TTC_MASK GENMASK(6, 4) 310 #define MTL_OP_MODE_TTC_32 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 0) 311 #define MTL_OP_MODE_TTC_64 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 1) 312 #define MTL_OP_MODE_TTC_96 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 2) 313 #define MTL_OP_MODE_TTC_128 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 3) 314 #define MTL_OP_MODE_TTC_192 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 4) 315 #define MTL_OP_MODE_TTC_256 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 5) 316 #define MTL_OP_MODE_TTC_384 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 6) 317 #define MTL_OP_MODE_TTC_512 FIELD_PREP(MTL_OP_MODE_TTC_MASK, 7) 318 319 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 320 321 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 322 323 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 324 325 #define MTL_OP_MODE_EHFC BIT(7) 326 #define MTL_OP_MODE_DIS_TCP_EF BIT(6) 327 328 #define MTL_OP_MODE_RTC_MASK GENMASK(1, 0) 329 330 #define MTL_OP_MODE_RTC_32 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 1) 331 #define MTL_OP_MODE_RTC_64 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 0) 332 #define MTL_OP_MODE_RTC_96 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 2) 333 #define MTL_OP_MODE_RTC_128 FIELD_PREP(MTL_OP_MODE_RTC_MASK, 3) 334 335 /* MTL ETS Control register */ 336 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 337 #define MTL_ETS_CTRL_BASE_OFFSET 0x40 338 339 static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs, 340 const u32 x) 341 { 342 u32 addr; 343 344 if (addrs) 345 addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset); 346 else 347 addr = MTL_ETS_CTRL_BASE_ADDR + (x * MTL_ETS_CTRL_BASE_OFFSET); 348 349 return addr; 350 } 351 352 #define MTL_ETS_CTRL_CC BIT(3) 353 #define MTL_ETS_CTRL_AVALG BIT(2) 354 355 /* MTL Queue Quantum Weight */ 356 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 357 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 358 359 static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs, 360 const u32 x) 361 { 362 u32 addr; 363 364 if (addrs) 365 addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset); 366 else 367 addr = MTL_TXQ_WEIGHT_BASE_ADDR + (x * MTL_TXQ_WEIGHT_BASE_OFFSET); 368 369 return addr; 370 } 371 372 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 373 374 /* MTL sendSlopeCredit register */ 375 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 376 #define MTL_SEND_SLP_CRED_OFFSET 0x40 377 378 static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs, 379 const u32 x) 380 { 381 u32 addr; 382 383 if (addrs) 384 addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset); 385 else 386 addr = MTL_SEND_SLP_CRED_BASE_ADDR + (x * MTL_SEND_SLP_CRED_OFFSET); 387 388 return addr; 389 } 390 391 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 392 393 /* MTL hiCredit register */ 394 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 395 #define MTL_HIGH_CRED_OFFSET 0x40 396 397 static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs, 398 const u32 x) 399 { 400 u32 addr; 401 402 if (addrs) 403 addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset); 404 else 405 addr = MTL_HIGH_CRED_BASE_ADDR + (x * MTL_HIGH_CRED_OFFSET); 406 407 return addr; 408 } 409 410 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 411 412 /* MTL loCredit register */ 413 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24 414 #define MTL_LOW_CRED_OFFSET 0x40 415 416 static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs, 417 const u32 x) 418 { 419 u32 addr; 420 421 if (addrs) 422 addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset); 423 else 424 addr = MTL_LOW_CRED_BASE_ADDR + (x * MTL_LOW_CRED_OFFSET); 425 426 return addr; 427 } 428 429 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 430 431 /* MTL debug */ 432 #define MTL_DEBUG_TXSTSFSTS BIT(5) 433 #define MTL_DEBUG_TXFSTS BIT(4) 434 #define MTL_DEBUG_TWCSTS BIT(3) 435 436 /* MTL debug: Tx FIFO Read Controller Status */ 437 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 438 #define MTL_DEBUG_TRCSTS_IDLE 0 439 #define MTL_DEBUG_TRCSTS_READ 1 440 #define MTL_DEBUG_TRCSTS_TXW 2 441 #define MTL_DEBUG_TRCSTS_WRITE 3 442 #define MTL_DEBUG_TXPAUSED BIT(0) 443 444 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 445 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 446 #define MTL_DEBUG_RXFSTS_EMPTY 0 447 #define MTL_DEBUG_RXFSTS_BT 1 448 #define MTL_DEBUG_RXFSTS_AT 2 449 #define MTL_DEBUG_RXFSTS_FULL 3 450 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 451 #define MTL_DEBUG_RRCSTS_IDLE 0 452 #define MTL_DEBUG_RRCSTS_RDATA 1 453 #define MTL_DEBUG_RRCSTS_RSTAT 2 454 #define MTL_DEBUG_RRCSTS_FLUSH 3 455 #define MTL_DEBUG_RWCSTS BIT(0) 456 457 /* MTL interrupt */ 458 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 459 #define MTL_RX_OVERFLOW_INT BIT(16) 460 461 /* Default operating mode of the MAC */ 462 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 463 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \ 464 GMAC_CONFIG_JE) 465 466 /* To dump the core regs excluding the Address Registers */ 467 #define GMAC_REG_NUM 132 468 469 /* SGMII/RGMII status register */ 470 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 471 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 472 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 473 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 474 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 475 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 476 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 477 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 478 /* LNKSPEED */ 479 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 480 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 481 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 482 483 extern const struct stmmac_dma_ops dwmac4_dma_ops; 484 extern const struct stmmac_dma_ops dwmac410_dma_ops; 485 #endif /* __DWMAC4_H__ */ 486