1 /******************************************************************************* 2 This is the driver for the MAC 10/100 on-chip Ethernet controller 3 currently tested on all the ST boards based on STb7109 and stx7200 SoCs. 4 5 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing 6 this code. 7 8 This contains the functions to handle the dma. 9 10 Copyright (C) 2007-2009 STMicroelectronics Ltd 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms and conditions of the GNU General Public License, 14 version 2, as published by the Free Software Foundation. 15 16 This program is distributed in the hope it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 more details. 20 21 The full GNU General Public License is included in this distribution in 22 the file called "COPYING". 23 24 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 25 *******************************************************************************/ 26 27 #include <asm/io.h> 28 #include "dwmac100.h" 29 #include "dwmac_dma.h" 30 31 static void dwmac100_dma_init(void __iomem *ioaddr, 32 struct stmmac_dma_cfg *dma_cfg, int atds) 33 { 34 /* Enable Application Access by writing to DMA CSR0 */ 35 writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT), 36 ioaddr + DMA_BUS_MODE); 37 38 /* Mask interrupts by writing to CSR7 */ 39 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 40 } 41 42 static void dwmac100_dma_init_rx(void __iomem *ioaddr, 43 struct stmmac_dma_cfg *dma_cfg, 44 u32 dma_rx_phy, u32 chan) 45 { 46 /* RX descriptor base addr lists must be written into DMA CSR3 */ 47 writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR); 48 } 49 50 static void dwmac100_dma_init_tx(void __iomem *ioaddr, 51 struct stmmac_dma_cfg *dma_cfg, 52 u32 dma_tx_phy, u32 chan) 53 { 54 /* TX descriptor base addr lists must be written into DMA CSR4 */ 55 writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR); 56 } 57 58 /* Store and Forward capability is not used at all. 59 * 60 * The transmit threshold can be programmed by setting the TTC bits in the DMA 61 * control register. 62 */ 63 static void dwmac100_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 64 u32 channel, int fifosz, u8 qmode) 65 { 66 u32 csr6 = readl(ioaddr + DMA_CONTROL); 67 68 if (mode <= 32) 69 csr6 |= DMA_CONTROL_TTC_32; 70 else if (mode <= 64) 71 csr6 |= DMA_CONTROL_TTC_64; 72 else 73 csr6 |= DMA_CONTROL_TTC_128; 74 75 writel(csr6, ioaddr + DMA_CONTROL); 76 } 77 78 static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 79 { 80 int i; 81 82 for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++) 83 reg_space[DMA_BUS_MODE / 4 + i] = 84 readl(ioaddr + DMA_BUS_MODE + i * 4); 85 86 reg_space[DMA_CUR_TX_BUF_ADDR / 4] = 87 readl(ioaddr + DMA_CUR_TX_BUF_ADDR); 88 reg_space[DMA_CUR_RX_BUF_ADDR / 4] = 89 readl(ioaddr + DMA_CUR_RX_BUF_ADDR); 90 } 91 92 /* DMA controller has two counters to track the number of the missed frames. */ 93 static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 94 void __iomem *ioaddr) 95 { 96 struct net_device_stats *stats = (struct net_device_stats *)data; 97 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); 98 99 if (unlikely(csr8)) { 100 if (csr8 & DMA_MISSED_FRAME_OVE) { 101 stats->rx_over_errors += 0x800; 102 x->rx_overflow_cntr += 0x800; 103 } else { 104 unsigned int ove_cntr; 105 ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17); 106 stats->rx_over_errors += ove_cntr; 107 x->rx_overflow_cntr += ove_cntr; 108 } 109 110 if (csr8 & DMA_MISSED_FRAME_OVE_M) { 111 stats->rx_missed_errors += 0xffff; 112 x->rx_missed_cntr += 0xffff; 113 } else { 114 unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR); 115 stats->rx_missed_errors += miss_f; 116 x->rx_missed_cntr += miss_f; 117 } 118 } 119 } 120 121 const struct stmmac_dma_ops dwmac100_dma_ops = { 122 .reset = dwmac_dma_reset, 123 .init = dwmac100_dma_init, 124 .init_rx_chan = dwmac100_dma_init_rx, 125 .init_tx_chan = dwmac100_dma_init_tx, 126 .dump_regs = dwmac100_dump_dma_regs, 127 .dma_tx_mode = dwmac100_dma_operation_mode_tx, 128 .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr, 129 .enable_dma_transmission = dwmac_enable_dma_transmission, 130 .enable_dma_irq = dwmac_enable_dma_irq, 131 .disable_dma_irq = dwmac_disable_dma_irq, 132 .start_tx = dwmac_dma_start_tx, 133 .stop_tx = dwmac_dma_stop_tx, 134 .start_rx = dwmac_dma_start_rx, 135 .stop_rx = dwmac_dma_stop_rx, 136 .dma_interrupt = dwmac_dma_interrupt, 137 }; 138