1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the MAC 10/100 on-chip Ethernet controller 4 currently tested on all the ST boards based on STb7109 and stx7200 SoCs. 5 6 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing 7 this code. 8 9 This contains the functions to handle the dma. 10 11 Copyright (C) 2007-2009 STMicroelectronics Ltd 12 13 14 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 15 *******************************************************************************/ 16 17 #include <linux/io.h> 18 #include "dwmac100.h" 19 #include "dwmac_dma.h" 20 21 static void dwmac100_dma_init(void __iomem *ioaddr, 22 struct stmmac_dma_cfg *dma_cfg) 23 { 24 /* Enable Application Access by writing to DMA CSR0 */ 25 writel(DMA_BUS_MODE_DEFAULT | 26 FIELD_PREP(DMA_BUS_MODE_PBL_MASK, dma_cfg->pbl), 27 ioaddr + DMA_BUS_MODE); 28 29 /* Mask interrupts by writing to CSR7 */ 30 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 31 } 32 33 static void dwmac100_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 34 struct stmmac_dma_cfg *dma_cfg, 35 dma_addr_t dma_rx_phy, u32 chan) 36 { 37 /* RX descriptor base addr lists must be written into DMA CSR3 */ 38 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); 39 } 40 41 static void dwmac100_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 42 struct stmmac_dma_cfg *dma_cfg, 43 dma_addr_t dma_tx_phy, u32 chan) 44 { 45 /* TX descriptor base addr lists must be written into DMA CSR4 */ 46 writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); 47 } 48 49 /* Store and Forward capability is not used at all. 50 * 51 * The transmit threshold can be programmed by setting the TTC bits in the DMA 52 * control register. 53 */ 54 static void dwmac100_dma_operation_mode_tx(struct stmmac_priv *priv, 55 void __iomem *ioaddr, int mode, 56 u32 channel, int fifosz, u8 qmode) 57 { 58 u32 csr6 = readl(ioaddr + DMA_CONTROL); 59 60 if (mode <= 32) 61 csr6 |= DMA_CONTROL_TTC_32; 62 else if (mode <= 64) 63 csr6 |= DMA_CONTROL_TTC_64; 64 else 65 csr6 |= DMA_CONTROL_TTC_128; 66 67 writel(csr6, ioaddr + DMA_CONTROL); 68 } 69 70 static void dwmac100_dump_dma_regs(struct stmmac_priv *priv, 71 void __iomem *ioaddr, u32 *reg_space) 72 { 73 int i; 74 75 for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++) 76 reg_space[DMA_BUS_MODE / 4 + i] = 77 readl(ioaddr + DMA_BUS_MODE + i * 4); 78 79 reg_space[DMA_CUR_TX_BUF_ADDR / 4] = 80 readl(ioaddr + DMA_CUR_TX_BUF_ADDR); 81 reg_space[DMA_CUR_RX_BUF_ADDR / 4] = 82 readl(ioaddr + DMA_CUR_RX_BUF_ADDR); 83 } 84 85 /* DMA controller has two counters to track the number of the missed frames. */ 86 static void dwmac100_dma_diagnostic_fr(struct stmmac_extra_stats *x, 87 void __iomem *ioaddr) 88 { 89 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); 90 91 if (unlikely(csr8)) { 92 if (csr8 & DMA_MISSED_FRAME_OVE) { 93 x->rx_overflow_cntr += 0x800; 94 } else { 95 unsigned int ove_cntr; 96 ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17); 97 x->rx_overflow_cntr += ove_cntr; 98 } 99 100 if (csr8 & DMA_MISSED_FRAME_OVE_M) { 101 x->rx_missed_cntr += 0xffff; 102 } else { 103 unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR); 104 x->rx_missed_cntr += miss_f; 105 } 106 } 107 } 108 109 const struct stmmac_dma_ops dwmac100_dma_ops = { 110 .reset = dwmac_dma_reset, 111 .init = dwmac100_dma_init, 112 .init_rx_chan = dwmac100_dma_init_rx, 113 .init_tx_chan = dwmac100_dma_init_tx, 114 .dump_regs = dwmac100_dump_dma_regs, 115 .dma_tx_mode = dwmac100_dma_operation_mode_tx, 116 .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr, 117 .enable_dma_transmission = dwmac_enable_dma_transmission, 118 .enable_dma_irq = dwmac_enable_dma_irq, 119 .disable_dma_irq = dwmac_disable_dma_irq, 120 .start_tx = dwmac_dma_start_tx, 121 .stop_tx = dwmac_dma_stop_tx, 122 .start_rx = dwmac_dma_start_rx, 123 .stop_rx = dwmac_dma_stop_rx, 124 .dma_interrupt = dwmac_dma_interrupt, 125 }; 126