1 /******************************************************************************* 2 This is the driver for the MAC 10/100 on-chip Ethernet controller 3 currently tested on all the ST boards based on STb7109 and stx7200 SoCs. 4 5 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing 6 this code. 7 8 This contains the functions to handle the dma. 9 10 Copyright (C) 2007-2009 STMicroelectronics Ltd 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms and conditions of the GNU General Public License, 14 version 2, as published by the Free Software Foundation. 15 16 This program is distributed in the hope it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 more details. 20 21 You should have received a copy of the GNU General Public License along with 22 this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 24 25 The full GNU General Public License is included in this distribution in 26 the file called "COPYING". 27 28 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 29 *******************************************************************************/ 30 31 #include <asm/io.h> 32 #include "dwmac100.h" 33 #include "dwmac_dma.h" 34 35 static void dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, 36 int aal, u32 dma_tx, u32 dma_rx, int atds) 37 { 38 /* Enable Application Access by writing to DMA CSR0 */ 39 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), 40 ioaddr + DMA_BUS_MODE); 41 42 /* Mask interrupts by writing to CSR7 */ 43 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 44 45 /* RX/TX descriptor base addr lists must be written into 46 * DMA CSR3 and CSR4, respectively 47 */ 48 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); 49 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); 50 } 51 52 /* Store and Forward capability is not used at all. 53 * 54 * The transmit threshold can be programmed by setting the TTC bits in the DMA 55 * control register. 56 */ 57 static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode, 58 int rxmode, int rxfifosz) 59 { 60 u32 csr6 = readl(ioaddr + DMA_CONTROL); 61 62 if (txmode <= 32) 63 csr6 |= DMA_CONTROL_TTC_32; 64 else if (txmode <= 64) 65 csr6 |= DMA_CONTROL_TTC_64; 66 else 67 csr6 |= DMA_CONTROL_TTC_128; 68 69 writel(csr6, ioaddr + DMA_CONTROL); 70 } 71 72 static void dwmac100_dump_dma_regs(void __iomem *ioaddr) 73 { 74 int i; 75 76 pr_debug("DWMAC 100 DMA CSR\n"); 77 for (i = 0; i < 9; i++) 78 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i, 79 (DMA_BUS_MODE + i * 4), 80 readl(ioaddr + DMA_BUS_MODE + i * 4)); 81 82 pr_debug("\tCSR20 (0x%x): 0x%08x, CSR21 (0x%x): 0x%08x\n", 83 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR), 84 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR)); 85 } 86 87 /* DMA controller has two counters to track the number of the missed frames. */ 88 static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 89 void __iomem *ioaddr) 90 { 91 struct net_device_stats *stats = (struct net_device_stats *)data; 92 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); 93 94 if (unlikely(csr8)) { 95 if (csr8 & DMA_MISSED_FRAME_OVE) { 96 stats->rx_over_errors += 0x800; 97 x->rx_overflow_cntr += 0x800; 98 } else { 99 unsigned int ove_cntr; 100 ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17); 101 stats->rx_over_errors += ove_cntr; 102 x->rx_overflow_cntr += ove_cntr; 103 } 104 105 if (csr8 & DMA_MISSED_FRAME_OVE_M) { 106 stats->rx_missed_errors += 0xffff; 107 x->rx_missed_cntr += 0xffff; 108 } else { 109 unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR); 110 stats->rx_missed_errors += miss_f; 111 x->rx_missed_cntr += miss_f; 112 } 113 } 114 } 115 116 const struct stmmac_dma_ops dwmac100_dma_ops = { 117 .reset = dwmac_dma_reset, 118 .init = dwmac100_dma_init, 119 .dump_regs = dwmac100_dump_dma_regs, 120 .dma_mode = dwmac100_dma_operation_mode, 121 .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr, 122 .enable_dma_transmission = dwmac_enable_dma_transmission, 123 .enable_dma_irq = dwmac_enable_dma_irq, 124 .disable_dma_irq = dwmac_disable_dma_irq, 125 .start_tx = dwmac_dma_start_tx, 126 .stop_tx = dwmac_dma_stop_tx, 127 .start_rx = dwmac_dma_start_rx, 128 .stop_rx = dwmac_dma_stop_rx, 129 .dma_interrupt = dwmac_dma_interrupt, 130 }; 131