1 /******************************************************************************* 2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for 4 developing this code. 5 6 This contains the functions to handle the dma. 7 8 Copyright (C) 2007-2009 STMicroelectronics Ltd 9 10 This program is free software; you can redistribute it and/or modify it 11 under the terms and conditions of the GNU General Public License, 12 version 2, as published by the Free Software Foundation. 13 14 This program is distributed in the hope it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 more details. 18 19 You should have received a copy of the GNU General Public License along with 20 this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 22 23 The full GNU General Public License is included in this distribution in 24 the file called "COPYING". 25 26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 27 *******************************************************************************/ 28 29 #include <asm/io.h> 30 #include "dwmac1000.h" 31 #include "dwmac_dma.h" 32 33 static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, 34 int mb, int burst_len, u32 dma_tx, u32 dma_rx) 35 { 36 u32 value = readl(ioaddr + DMA_BUS_MODE); 37 int limit; 38 39 /* DMA SW reset */ 40 value |= DMA_BUS_MODE_SFT_RESET; 41 writel(value, ioaddr + DMA_BUS_MODE); 42 limit = 10; 43 while (limit--) { 44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 45 break; 46 mdelay(10); 47 } 48 if (limit < 0) 49 return -EBUSY; 50 51 /* 52 * Set the DMA PBL (Programmable Burst Length) mode 53 * Before stmmac core 3.50 this mode bit was 4xPBL, and 54 * post 3.5 mode bit acts as 8*PBL. 55 * For core rev < 3.5, when the core is set for 4xPBL mode, the 56 * DMA transfers the data in 4, 8, 16, 32, 64 & 128 beats 57 * depending on pbl value. 58 * For core rev > 3.5, when the core is set for 8xPBL mode, the 59 * DMA transfers the data in 8, 16, 32, 64, 128 & 256 beats 60 * depending on pbl value. 61 */ 62 value = DMA_BUS_MODE_PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) | 63 (pbl << DMA_BUS_MODE_RPBL_SHIFT)); 64 65 /* Set the Fixed burst mode */ 66 if (fb) 67 value |= DMA_BUS_MODE_FB; 68 69 /* Mixed Burst has no effect when fb is set */ 70 if (mb) 71 value |= DMA_BUS_MODE_MB; 72 73 #ifdef CONFIG_STMMAC_DA 74 value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */ 75 #endif 76 writel(value, ioaddr + DMA_BUS_MODE); 77 78 /* In case of GMAC AXI configuration, program the DMA_AXI_BUS_MODE 79 * for supported bursts. 80 * 81 * Note: This is applicable only for revision GMACv3.61a. For 82 * older version this register is reserved and shall have no 83 * effect. 84 * 85 * Note: 86 * For Fixed Burst Mode: if we directly write 0xFF to this 87 * register using the configurations pass from platform code, 88 * this would ensure that all bursts supported by core are set 89 * and those which are not supported would remain ineffective. 90 * 91 * For Non Fixed Burst Mode: provide the maximum value of the 92 * burst length. Any burst equal or below the provided burst 93 * length would be allowed to perform. */ 94 writel(burst_len, ioaddr + DMA_AXI_BUS_MODE); 95 96 /* Mask interrupts by writing to CSR7 */ 97 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 98 99 /* The base address of the RX/TX descriptor lists must be written into 100 * DMA CSR3 and CSR4, respectively. */ 101 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); 102 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); 103 104 return 0; 105 } 106 107 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode, 108 int rxmode) 109 { 110 u32 csr6 = readl(ioaddr + DMA_CONTROL); 111 112 if (txmode == SF_DMA_MODE) { 113 CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n"); 114 /* Transmit COE type 2 cannot be done in cut-through mode. */ 115 csr6 |= DMA_CONTROL_TSF; 116 /* Operating on second frame increase the performance 117 * especially when transmit store-and-forward is used.*/ 118 csr6 |= DMA_CONTROL_OSF; 119 } else { 120 CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode" 121 " (threshold = %d)\n", txmode); 122 csr6 &= ~DMA_CONTROL_TSF; 123 csr6 &= DMA_CONTROL_TC_TX_MASK; 124 /* Set the transmit threshold */ 125 if (txmode <= 32) 126 csr6 |= DMA_CONTROL_TTC_32; 127 else if (txmode <= 64) 128 csr6 |= DMA_CONTROL_TTC_64; 129 else if (txmode <= 128) 130 csr6 |= DMA_CONTROL_TTC_128; 131 else if (txmode <= 192) 132 csr6 |= DMA_CONTROL_TTC_192; 133 else 134 csr6 |= DMA_CONTROL_TTC_256; 135 } 136 137 if (rxmode == SF_DMA_MODE) { 138 CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n"); 139 csr6 |= DMA_CONTROL_RSF; 140 } else { 141 CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode" 142 " (threshold = %d)\n", rxmode); 143 csr6 &= ~DMA_CONTROL_RSF; 144 csr6 &= DMA_CONTROL_TC_RX_MASK; 145 if (rxmode <= 32) 146 csr6 |= DMA_CONTROL_RTC_32; 147 else if (rxmode <= 64) 148 csr6 |= DMA_CONTROL_RTC_64; 149 else if (rxmode <= 96) 150 csr6 |= DMA_CONTROL_RTC_96; 151 else 152 csr6 |= DMA_CONTROL_RTC_128; 153 } 154 155 writel(csr6, ioaddr + DMA_CONTROL); 156 } 157 158 static void dwmac1000_dump_dma_regs(void __iomem *ioaddr) 159 { 160 int i; 161 pr_info(" DMA registers\n"); 162 for (i = 0; i < 22; i++) { 163 if ((i < 9) || (i > 17)) { 164 int offset = i * 4; 165 pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i, 166 (DMA_BUS_MODE + offset), 167 readl(ioaddr + DMA_BUS_MODE + offset)); 168 } 169 } 170 } 171 172 static unsigned int dwmac1000_get_hw_feature(void __iomem *ioaddr) 173 { 174 return readl(ioaddr + DMA_HW_FEATURE); 175 } 176 177 static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt) 178 { 179 writel(riwt, ioaddr + DMA_RX_WATCHDOG); 180 } 181 182 const struct stmmac_dma_ops dwmac1000_dma_ops = { 183 .init = dwmac1000_dma_init, 184 .dump_regs = dwmac1000_dump_dma_regs, 185 .dma_mode = dwmac1000_dma_operation_mode, 186 .enable_dma_transmission = dwmac_enable_dma_transmission, 187 .enable_dma_irq = dwmac_enable_dma_irq, 188 .disable_dma_irq = dwmac_disable_dma_irq, 189 .start_tx = dwmac_dma_start_tx, 190 .stop_tx = dwmac_dma_stop_tx, 191 .start_rx = dwmac_dma_start_rx, 192 .stop_rx = dwmac_dma_stop_rx, 193 .dma_interrupt = dwmac_dma_interrupt, 194 .get_hw_feature = dwmac1000_get_hw_feature, 195 .rx_watchdog = dwmac1000_rx_watchdog, 196 }; 197