1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 #ifndef __DWMAC1000_H__ 9 #define __DWMAC1000_H__ 10 11 #include <linux/phy.h> 12 #include "common.h" 13 14 #define GMAC_CONTROL 0x00000000 /* Configuration */ 15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 16 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 17 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ 18 #define GMAC_MII_ADDR 0x00000010 /* MII Address */ 19 #define GMAC_MII_DATA 0x00000014 /* MII Data */ 20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ 21 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ 22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */ 23 24 #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 25 #define GMAC_INT_STATUS_MMCRIS BIT(5) 26 #define GMAC_INT_STATUS_MMCTIS BIT(6) 27 #define GMAC_INT_STATUS_MMCCSUM BIT(7) 28 #define GMAC_INT_STATUS_LPIIS BIT(10) 29 30 /* interrupt mask register */ 31 #define GMAC_INT_MASK 0x0000003c 32 #define GMAC_INT_DISABLE_RGMII BIT(0) 33 #define GMAC_INT_DISABLE_PCSLINK BIT(1) 34 #define GMAC_INT_DISABLE_PCSAN BIT(2) 35 #define GMAC_INT_DISABLE_PMT BIT(3) 36 #define GMAC_INT_DISABLE_TIMESTAMP BIT(9) 37 #define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_RGMII | \ 38 GMAC_INT_DISABLE_PCSLINK | \ 39 GMAC_INT_DISABLE_PCSAN | \ 40 GMAC_INT_DISABLE_TIMESTAMP) 41 42 /* PMT Control and Status */ 43 #define GMAC_PMT 0x0000002c 44 enum power_event { 45 pointer_reset = 0x80000000, 46 global_unicast = 0x00000200, 47 wake_up_rx_frame = 0x00000040, 48 magic_frame = 0x00000020, 49 wake_up_frame_en = 0x00000004, 50 magic_pkt_en = 0x00000002, 51 power_down = 0x00000001, 52 }; 53 54 /* Energy Efficient Ethernet (EEE) 55 * 56 * LPI status, timer and control register offset 57 * For LPI control and status bit definitions, see common.h. 58 */ 59 #define LPI_CTRL_STATUS 0x0030 60 #define LPI_TIMER_CTRL 0x0034 61 62 /* GMAC HW ADDR regs */ 63 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \ 64 0x00000040 + (reg * 8)) 65 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \ 66 0x00000044 + (reg * 8)) 67 #define GMAC_MAX_PERFECT_ADDRESSES 1 68 69 #define GMAC_PCS_BASE 0x000000c0 /* PCS register base */ 70 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */ 71 72 /* SGMII/RGMII status register */ 73 #define GMAC_RGSMIIIS_LNKMODE BIT(0) 74 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1) 75 #define GMAC_RGSMIIIS_LNKSTS BIT(3) 76 #define GMAC_RGSMIIIS_JABTO BIT(4) 77 #define GMAC_RGSMIIIS_FALSECARDET BIT(5) 78 #define GMAC_RGSMIIIS_SMIDRXS BIT(16) 79 /* LNKMOD */ 80 #define GMAC_RGSMIIIS_LNKMOD_MASK 0x1 81 /* LNKSPEED */ 82 #define GMAC_RGSMIIIS_SPEED_125 0x2 83 #define GMAC_RGSMIIIS_SPEED_25 0x1 84 #define GMAC_RGSMIIIS_SPEED_2_5 0x0 85 86 /* GMAC Configuration defines */ 87 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */ 88 #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 89 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 90 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 91 enum inter_frame_gap { 92 GMAC_CONTROL_IFG_88 = 0x00040000, 93 GMAC_CONTROL_IFG_80 = 0x00020000, 94 GMAC_CONTROL_IFG_40 = 0x000e0000, 95 }; 96 #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */ 97 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ 98 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ 99 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 100 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ 101 #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 102 103 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | \ 104 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS) 105 106 /* GMAC Frame Filter defines */ 107 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 108 #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 109 #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 110 #define GMAC_FRAME_FILTER_PCF 0x00000080 /* Pass Control frames */ 111 #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 112 #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 113 /* GMAC FLOW CTRL defines */ 114 #define GMAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */ 115 #define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */ 116 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 117 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 118 119 /* DEBUG Register defines */ 120 /* MTL TxStatus FIFO */ 121 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */ 122 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */ 123 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */ 124 /* MTL Tx FIFO Read Controller Status */ 125 #define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20) 126 #define GMAC_DEBUG_TRCSTS_READ 1 127 #define GMAC_DEBUG_TRCSTS_TXW 2 128 #define GMAC_DEBUG_TRCSTS_WRITE 3 129 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */ 130 /* MAC Transmit Frame Controller Status */ 131 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 132 #define GMAC_DEBUG_TFCSTS_WAIT 1 133 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 134 #define GMAC_DEBUG_TFCSTS_XFER 3 135 /* MAC GMII or MII Transmit Protocol Engine Status */ 136 #define GMAC_DEBUG_TPESTS BIT(16) 137 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */ 138 #define GMAC_DEBUG_RXFSTS_EMPTY 0 139 #define GMAC_DEBUG_RXFSTS_BT 1 140 #define GMAC_DEBUG_RXFSTS_AT 2 141 #define GMAC_DEBUG_RXFSTS_FULL 3 142 #define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */ 143 #define GMAC_DEBUG_RRCSTS_IDLE 0 144 #define GMAC_DEBUG_RRCSTS_RDATA 1 145 #define GMAC_DEBUG_RRCSTS_RSTAT 2 146 #define GMAC_DEBUG_RRCSTS_FLUSH 3 147 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */ 148 /* MAC Receive Frame Controller FIFO Status */ 149 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 150 /* MAC GMII or MII Receive Protocol Engine Status */ 151 #define GMAC_DEBUG_RPESTS BIT(0) 152 153 /*--- DMA BLOCK defines ---*/ 154 /* DMA Bus Mode register defines */ 155 /* Programmable burst length (passed through platform)*/ 156 #define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */ 157 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 158 159 enum rx_tx_priority_ratio { 160 double_ratio = 0x00004000, /* 2:1 */ 161 triple_ratio = 0x00008000, /* 3:1 */ 162 quadruple_ratio = 0x0000c000, /* 4:1 */ 163 }; 164 165 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 166 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */ 167 #define DMA_BUS_MODE_RPBL_MASK GENMASK(22, 17) /* Rx-Programmable Burst Len */ 168 #define DMA_BUS_MODE_USP 0x00800000 169 #define DMA_BUS_MODE_MAXPBL 0x01000000 170 #define DMA_BUS_MODE_AAL 0x02000000 171 172 /* DMA CRS Control and Status Register Mapping */ 173 174 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ 175 /* Disable Drop TCP/IP csum error */ 176 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ 177 #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ 178 /* Threshold for Activating the FC */ 179 enum rfa { 180 act_full_minus_1 = 0x00800000, 181 act_full_minus_2 = 0x00800200, 182 act_full_minus_3 = 0x00800400, 183 act_full_minus_4 = 0x00800600, 184 }; 185 /* Threshold for Deactivating the FC */ 186 enum rfd { 187 deac_full_minus_1 = 0x00400000, 188 deac_full_minus_2 = 0x00400800, 189 deac_full_minus_3 = 0x00401000, 190 deac_full_minus_4 = 0x00401800, 191 }; 192 #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ 193 194 enum ttc_control { 195 DMA_CONTROL_TTC_64 = 0x00000000, 196 DMA_CONTROL_TTC_128 = 0x00004000, 197 DMA_CONTROL_TTC_192 = 0x00008000, 198 DMA_CONTROL_TTC_256 = 0x0000c000, 199 DMA_CONTROL_TTC_40 = 0x00010000, 200 DMA_CONTROL_TTC_32 = 0x00014000, 201 DMA_CONTROL_TTC_24 = 0x00018000, 202 DMA_CONTROL_TTC_16 = 0x0001c000, 203 }; 204 #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff 205 206 #define DMA_CONTROL_EFC 0x00000100 207 208 /* Receive flow control activation field 209 * RFA field in DMA control register, bits 23,10:9 210 */ 211 #define DMA_CONTROL_RFA_MASK 0x00800600 212 213 /* Receive flow control deactivation field 214 * RFD field in DMA control register, bits 22,12:11 215 */ 216 #define DMA_CONTROL_RFD_MASK 0x00401800 217 218 /* RFD and RFA fields are encoded as follows 219 * 220 * Bit Field 221 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled) 222 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled) 223 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled) 224 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled) 225 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled) 226 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled) 227 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled) 228 * 1,11 - Reserved 229 * 230 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work, 231 * but packet throughput performance may not be as expected. 232 * 233 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame 234 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause 235 * Description). 236 * 237 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6), 238 * is set to 0. This allows pause frames with a quanta of 0 to be sent 239 * as an XOFF message to the link peer. 240 */ 241 242 #define RFA_FULL_MINUS_1K 0x00000000 243 244 #define RFD_FULL_MINUS_2K 0x00000800 245 246 enum rtc_control { 247 DMA_CONTROL_RTC_64 = 0x00000000, 248 DMA_CONTROL_RTC_32 = 0x00000008, 249 DMA_CONTROL_RTC_96 = 0x00000010, 250 DMA_CONTROL_RTC_128 = 0x00000018, 251 }; 252 #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 253 254 #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ 255 256 /* MMC registers offset */ 257 #define GMAC_EXTHASH_BASE 0x500 258 259 /* PTP and timestamping registers */ 260 261 #define GMAC3_X_ATSNS GENMASK(29, 25) 262 263 #define GMAC_PTP_TCR_ATSFC BIT(24) 264 #define GMAC_PTP_TCR_ATSEN0 BIT(25) 265 266 #define GMAC3_X_TIMESTAMP_STATUS 0x28 267 #define GMAC_PTP_ATNR 0x30 268 #define GMAC_PTP_ATSR 0x34 269 270 extern const struct stmmac_dma_ops dwmac1000_dma_ops; 271 #endif /* __DWMAC1000_H__ */ 272