1 /******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 You should have received a copy of the GNU General Public License along with 14 this program; if not, write to the Free Software Foundation, Inc., 15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 17 The full GNU General Public License is included in this distribution in 18 the file called "COPYING". 19 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 21 *******************************************************************************/ 22 #ifndef __DWMAC1000_H__ 23 #define __DWMAC1000_H__ 24 25 #include <linux/phy.h> 26 #include "common.h" 27 28 #define GMAC_CONTROL 0x00000000 /* Configuration */ 29 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 30 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 31 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ 32 #define GMAC_MII_ADDR 0x00000010 /* MII Address */ 33 #define GMAC_MII_DATA 0x00000014 /* MII Data */ 34 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ 35 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ 36 #define GMAC_VERSION 0x00000020 /* GMAC CORE Version */ 37 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */ 38 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 39 40 #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 41 enum dwmac1000_irq_status { 42 lpiis_irq = 0x400, 43 time_stamp_irq = 0x0200, 44 mmc_rx_csum_offload_irq = 0x0080, 45 mmc_tx_irq = 0x0040, 46 mmc_rx_irq = 0x0020, 47 mmc_irq = 0x0010, 48 pmt_irq = 0x0008, 49 pcs_ane_irq = 0x0004, 50 pcs_link_irq = 0x0002, 51 rgmii_irq = 0x0001, 52 }; 53 #define GMAC_INT_MASK 0x0000003c /* interrupt mask register */ 54 55 /* PMT Control and Status */ 56 #define GMAC_PMT 0x0000002c 57 enum power_event { 58 pointer_reset = 0x80000000, 59 global_unicast = 0x00000200, 60 wake_up_rx_frame = 0x00000040, 61 magic_frame = 0x00000020, 62 wake_up_frame_en = 0x00000004, 63 magic_pkt_en = 0x00000002, 64 power_down = 0x00000001, 65 }; 66 67 /* Energy Efficient Ethernet (EEE) 68 * 69 * LPI status, timer and control register offset 70 */ 71 #define LPI_CTRL_STATUS 0x0030 72 #define LPI_TIMER_CTRL 0x0034 73 74 /* LPI control and status defines */ 75 #define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */ 76 #define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */ 77 #define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */ 78 #define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */ 79 #define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */ 80 #define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */ 81 #define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */ 82 #define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */ 83 #define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */ 84 #define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */ 85 86 /* GMAC HW ADDR regs */ 87 #define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ 88 (reg * 8)) 89 #define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ 90 (reg * 8)) 91 #define GMAC_MAX_PERFECT_ADDRESSES 1 92 93 /* PCS registers (AN/TBI/SGMII/RGMII) offset */ 94 #define GMAC_AN_CTRL 0x000000c0 /* AN control */ 95 #define GMAC_AN_STATUS 0x000000c4 /* AN status */ 96 #define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */ 97 #define GMAC_ANE_LPA 0x000000cc /* Auto-Neg. link partener ability */ 98 #define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */ 99 #define GMAC_TBI 0x000000d4 /* TBI extend status */ 100 #define GMAC_S_R_GMII 0x000000d8 /* SGMII RGMII status */ 101 102 /* AN Configuration defines */ 103 #define GMAC_AN_CTRL_RAN 0x00000200 /* Restart Auto-Negotiation */ 104 #define GMAC_AN_CTRL_ANE 0x00001000 /* Auto-Negotiation Enable */ 105 #define GMAC_AN_CTRL_ELE 0x00004000 /* External Loopback Enable */ 106 #define GMAC_AN_CTRL_ECD 0x00010000 /* Enable Comma Detect */ 107 #define GMAC_AN_CTRL_LR 0x00020000 /* Lock to Reference */ 108 #define GMAC_AN_CTRL_SGMRAL 0x00040000 /* SGMII RAL Control */ 109 110 /* AN Status defines */ 111 #define GMAC_AN_STATUS_LS 0x00000004 /* Link Status 0:down 1:up */ 112 #define GMAC_AN_STATUS_ANA 0x00000008 /* Auto-Negotiation Ability */ 113 #define GMAC_AN_STATUS_ANC 0x00000020 /* Auto-Negotiation Complete */ 114 #define GMAC_AN_STATUS_ES 0x00000100 /* Extended Status */ 115 116 /* Register 54 (SGMII/RGMII status register) */ 117 #define GMAC_S_R_GMII_LINK 0x8 118 #define GMAC_S_R_GMII_SPEED 0x5 119 #define GMAC_S_R_GMII_SPEED_SHIFT 0x1 120 #define GMAC_S_R_GMII_MODE 0x1 121 #define GMAC_S_R_GMII_SPEED_125 2 122 #define GMAC_S_R_GMII_SPEED_25 1 123 124 /* Common ADV and LPA defines */ 125 #define GMAC_ANE_FD (1 << 5) 126 #define GMAC_ANE_HD (1 << 6) 127 #define GMAC_ANE_PSE (3 << 7) 128 #define GMAC_ANE_PSE_SHIFT 7 129 130 /* GMAC Configuration defines */ 131 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */ 132 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ 133 #define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */ 134 #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 135 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 136 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 137 enum inter_frame_gap { 138 GMAC_CONTROL_IFG_88 = 0x00040000, 139 GMAC_CONTROL_IFG_80 = 0x00020000, 140 GMAC_CONTROL_IFG_40 = 0x000e0000, 141 }; 142 #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */ 143 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ 144 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ 145 #define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */ 146 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 147 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ 148 #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 149 #define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */ 150 #define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */ 151 #define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */ 152 #define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */ 153 #define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 154 #define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 155 156 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \ 157 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS) 158 159 /* GMAC Frame Filter defines */ 160 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 161 #define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 162 #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 163 #define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 164 #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 165 #define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 166 #define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 167 #define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 168 #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 169 #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 170 /* GMII ADDR defines */ 171 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ 172 #define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ 173 /* GMAC FLOW CTRL defines */ 174 #define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 175 #define GMAC_FLOW_CTRL_PT_SHIFT 16 176 #define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */ 177 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 178 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 179 #define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 180 181 /* DEBUG Register defines */ 182 /* MTL TxStatus FIFO */ 183 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */ 184 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */ 185 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */ 186 /* MTL Tx FIFO Read Controller Status */ 187 #define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20) 188 #define GMAC_DEBUG_TRCSTS_SHIFT 20 189 #define GMAC_DEBUG_TRCSTS_IDLE 0 190 #define GMAC_DEBUG_TRCSTS_READ 1 191 #define GMAC_DEBUG_TRCSTS_TXW 2 192 #define GMAC_DEBUG_TRCSTS_WRITE 3 193 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */ 194 /* MAC Transmit Frame Controller Status */ 195 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 196 #define GMAC_DEBUG_TFCSTS_SHIFT 17 197 #define GMAC_DEBUG_TFCSTS_IDLE 0 198 #define GMAC_DEBUG_TFCSTS_WAIT 1 199 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 200 #define GMAC_DEBUG_TFCSTS_XFER 3 201 /* MAC GMII or MII Transmit Protocol Engine Status */ 202 #define GMAC_DEBUG_TPESTS BIT(16) 203 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */ 204 #define GMAC_DEBUG_RXFSTS_SHIFT 8 205 #define GMAC_DEBUG_RXFSTS_EMPTY 0 206 #define GMAC_DEBUG_RXFSTS_BT 1 207 #define GMAC_DEBUG_RXFSTS_AT 2 208 #define GMAC_DEBUG_RXFSTS_FULL 3 209 #define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */ 210 #define GMAC_DEBUG_RRCSTS_SHIFT 5 211 #define GMAC_DEBUG_RRCSTS_IDLE 0 212 #define GMAC_DEBUG_RRCSTS_RDATA 1 213 #define GMAC_DEBUG_RRCSTS_RSTAT 2 214 #define GMAC_DEBUG_RRCSTS_FLUSH 3 215 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */ 216 /* MAC Receive Frame Controller FIFO Status */ 217 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 218 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 219 /* MAC GMII or MII Receive Protocol Engine Status */ 220 #define GMAC_DEBUG_RPESTS BIT(0) 221 222 /*--- DMA BLOCK defines ---*/ 223 /* DMA Bus Mode register defines */ 224 #define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */ 225 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 226 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 227 /* Programmable burst length (passed thorugh platform)*/ 228 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 229 #define DMA_BUS_MODE_PBL_SHIFT 8 230 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 231 232 enum rx_tx_priority_ratio { 233 double_ratio = 0x00004000, /* 2:1 */ 234 triple_ratio = 0x00008000, /* 3:1 */ 235 quadruple_ratio = 0x0000c000, /* 4:1 */ 236 }; 237 238 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 239 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */ 240 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ 241 #define DMA_BUS_MODE_RPBL_SHIFT 17 242 #define DMA_BUS_MODE_USP 0x00800000 243 #define DMA_BUS_MODE_MAXPBL 0x01000000 244 #define DMA_BUS_MODE_AAL 0x02000000 245 246 /* DMA CRS Control and Status Register Mapping */ 247 #define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */ 248 #define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */ 249 /* DMA Bus Mode register defines */ 250 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 251 #define DMA_BUS_PR_RATIO_SHIFT 14 252 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 253 254 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ 255 /* Disable Drop TCP/IP csum error */ 256 #define DMA_CONTROL_DT 0x04000000 257 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ 258 #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ 259 /* Threshold for Activating the FC */ 260 enum rfa { 261 act_full_minus_1 = 0x00800000, 262 act_full_minus_2 = 0x00800200, 263 act_full_minus_3 = 0x00800400, 264 act_full_minus_4 = 0x00800600, 265 }; 266 /* Threshold for Deactivating the FC */ 267 enum rfd { 268 deac_full_minus_1 = 0x00400000, 269 deac_full_minus_2 = 0x00400800, 270 deac_full_minus_3 = 0x00401000, 271 deac_full_minus_4 = 0x00401800, 272 }; 273 #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ 274 275 enum ttc_control { 276 DMA_CONTROL_TTC_64 = 0x00000000, 277 DMA_CONTROL_TTC_128 = 0x00004000, 278 DMA_CONTROL_TTC_192 = 0x00008000, 279 DMA_CONTROL_TTC_256 = 0x0000c000, 280 DMA_CONTROL_TTC_40 = 0x00010000, 281 DMA_CONTROL_TTC_32 = 0x00014000, 282 DMA_CONTROL_TTC_24 = 0x00018000, 283 DMA_CONTROL_TTC_16 = 0x0001c000, 284 }; 285 #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff 286 287 #define DMA_CONTROL_EFC 0x00000100 288 #define DMA_CONTROL_FEF 0x00000080 289 #define DMA_CONTROL_FUF 0x00000040 290 291 /* Receive flow control activation field 292 * RFA field in DMA control register, bits 23,10:9 293 */ 294 #define DMA_CONTROL_RFA_MASK 0x00800600 295 296 /* Receive flow control deactivation field 297 * RFD field in DMA control register, bits 22,12:11 298 */ 299 #define DMA_CONTROL_RFD_MASK 0x00401800 300 301 /* RFD and RFA fields are encoded as follows 302 * 303 * Bit Field 304 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled) 305 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled) 306 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled) 307 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled) 308 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled) 309 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled) 310 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled) 311 * 1,11 - Reserved 312 * 313 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work, 314 * but packet throughput performance may not be as expected. 315 * 316 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame 317 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause 318 * Description). 319 * 320 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6), 321 * is set to 0. This allows pause frames with a quanta of 0 to be sent 322 * as an XOFF message to the link peer. 323 */ 324 325 #define RFA_FULL_MINUS_1K 0x00000000 326 #define RFA_FULL_MINUS_2K 0x00000200 327 #define RFA_FULL_MINUS_3K 0x00000400 328 #define RFA_FULL_MINUS_4K 0x00000600 329 #define RFA_FULL_MINUS_5K 0x00800000 330 #define RFA_FULL_MINUS_6K 0x00800200 331 #define RFA_FULL_MINUS_7K 0x00800400 332 333 #define RFD_FULL_MINUS_1K 0x00000000 334 #define RFD_FULL_MINUS_2K 0x00000800 335 #define RFD_FULL_MINUS_3K 0x00001000 336 #define RFD_FULL_MINUS_4K 0x00001800 337 #define RFD_FULL_MINUS_5K 0x00400000 338 #define RFD_FULL_MINUS_6K 0x00400800 339 #define RFD_FULL_MINUS_7K 0x00401000 340 341 enum rtc_control { 342 DMA_CONTROL_RTC_64 = 0x00000000, 343 DMA_CONTROL_RTC_32 = 0x00000008, 344 DMA_CONTROL_RTC_96 = 0x00000010, 345 DMA_CONTROL_RTC_128 = 0x00000018, 346 }; 347 #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 348 349 #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ 350 351 /* MMC registers offset */ 352 #define GMAC_MMC_CTRL 0x100 353 #define GMAC_MMC_RX_INTR 0x104 354 #define GMAC_MMC_TX_INTR 0x108 355 #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 356 #define GMAC_EXTHASH_BASE 0x500 357 358 extern const struct stmmac_dma_ops dwmac1000_dma_ops; 359 #endif /* __DWMAC1000_H__ */ 360