1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 MAC 10/100 Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __DWMAC100_H__ 12 #define __DWMAC100_H__ 13 14 #include <linux/phy.h> 15 #include "common.h" 16 17 /*---------------------------------------------------------------------------- 18 * MAC BLOCK defines 19 *---------------------------------------------------------------------------*/ 20 /* MAC CSR offset */ 21 #define MAC_CONTROL 0x00000000 /* MAC Control */ 22 #define MAC_ADDR_HIGH 0x00000004 /* MAC Address High */ 23 #define MAC_ADDR_LOW 0x00000008 /* MAC Address Low */ 24 #define MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */ 25 #define MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */ 26 #define MAC_MII_ADDR 0x00000014 /* MII Address */ 27 #define MAC_MII_DATA 0x00000018 /* MII Data */ 28 #define MAC_FLOW_CTRL 0x0000001c /* Flow Control */ 29 #define MAC_VLAN1 0x00000020 /* VLAN1 Tag */ 30 #define MAC_VLAN2 0x00000024 /* VLAN2 Tag */ 31 32 /* MAC CTRL defines */ 33 #define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */ 34 #define MAC_CONTROL_PS 0x08000000 /* Port Select */ 35 #define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */ 36 #define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */ 37 #define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */ 38 #define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */ 39 #define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */ 40 #define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */ 41 #define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */ 42 43 #define MAC_CORE_INIT (MAC_CONTROL_HBD) 44 45 /* MAC FLOW CTRL defines */ 46 #define MAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */ 47 #define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */ 48 49 /*---------------------------------------------------------------------------- 50 * DMA BLOCK defines 51 *---------------------------------------------------------------------------*/ 52 53 /* DMA Bus Mode register defines */ 54 #define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */ 55 #define DMA_BUS_MODE_DEFAULT 0x00000000 56 57 /* Transmit Threshold Control */ 58 enum ttc_control { 59 DMA_CONTROL_TTC_DEFAULT = 0x00000000, /* Threshold is 32 DWORDS */ 60 DMA_CONTROL_TTC_64 = 0x00004000, /* Threshold is 64 DWORDS */ 61 DMA_CONTROL_TTC_128 = 0x00008000, /* Threshold is 128 DWORDS */ 62 DMA_CONTROL_TTC_256 = 0x0000c000, /* Threshold is 256 DWORDS */ 63 DMA_CONTROL_TTC_18 = 0x00400000, /* Threshold is 18 DWORDS */ 64 DMA_CONTROL_TTC_24 = 0x00404000, /* Threshold is 24 DWORDS */ 65 DMA_CONTROL_TTC_32 = 0x00408000, /* Threshold is 32 DWORDS */ 66 DMA_CONTROL_TTC_40 = 0x0040c000, /* Threshold is 40 DWORDS */ 67 DMA_CONTROL_SE = 0x00000008, /* Stop On Empty */ 68 DMA_CONTROL_OSF = 0x00000004, /* Operate On 2nd Frame */ 69 }; 70 71 /* STMAC110 DMA Missed Frame Counter register defines */ 72 #define DMA_MISSED_FRAME_OVE 0x10000000 /* FIFO Overflow Overflow */ 73 #define DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000 /* Overflow Frame Counter */ 74 #define DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */ 75 #define DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */ 76 77 extern const struct stmmac_dma_ops dwmac100_dma_ops; 78 79 #endif /* __DWMAC100_H__ */ 80