1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/platform_device.h> 3 #include <linux/of.h> 4 #include <linux/module.h> 5 #include <linux/stmmac.h> 6 #include <linux/clk.h> 7 8 #include "stmmac_platform.h" 9 10 static const char *const mgbe_clks[] = { 11 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac" 12 }; 13 14 struct tegra_mgbe { 15 struct device *dev; 16 17 struct clk_bulk_data *clks; 18 19 struct reset_control *rst_mac; 20 struct reset_control *rst_pcs; 21 22 void __iomem *hv; 23 void __iomem *regs; 24 void __iomem *xpcs; 25 26 struct mii_bus *mii; 27 }; 28 29 #define XPCS_WRAP_UPHY_RX_CONTROL 0x801c 30 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31) 31 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10) 32 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9) 33 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8) 34 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6)) 35 #define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5) 36 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4) 37 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0) 38 #define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020 39 #define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0) 40 #define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2) 41 #define XPCS_WRAP_UPHY_STATUS 0x8044 42 #define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0) 43 #define XPCS_WRAP_IRQ_STATUS 0x8050 44 #define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6) 45 46 #define XPCS_REG_ADDR_SHIFT 10 47 #define XPCS_REG_ADDR_MASK 0x1fff 48 #define XPCS_ADDR 0x3fc 49 50 #define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704 51 #define MAC_SBD_INTR BIT(2) 52 #define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 53 #define MGBE_SID 0x6 54 55 static int __maybe_unused tegra_mgbe_suspend(struct device *dev) 56 { 57 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev); 58 int err; 59 60 err = stmmac_suspend(dev); 61 if (err) 62 return err; 63 64 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); 65 66 return reset_control_assert(mgbe->rst_mac); 67 } 68 69 static int __maybe_unused tegra_mgbe_resume(struct device *dev) 70 { 71 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev); 72 u32 value; 73 int err; 74 75 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); 76 if (err < 0) 77 return err; 78 79 err = reset_control_deassert(mgbe->rst_mac); 80 if (err < 0) 81 return err; 82 83 /* Enable common interrupt at wrapper level */ 84 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); 85 86 /* Program SID */ 87 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); 88 89 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); 90 if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) { 91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); 92 value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN; 93 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); 94 } 95 96 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, 97 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0, 98 500, 500 * 2000); 99 if (err < 0) { 100 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); 101 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); 102 return err; 103 } 104 105 err = stmmac_resume(dev); 106 if (err < 0) 107 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); 108 109 return err; 110 } 111 112 static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_data) 113 { 114 struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data; 115 u32 value; 116 int err; 117 118 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 119 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD; 120 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 121 122 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 123 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ; 124 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 125 126 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 127 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ; 128 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 129 130 usleep_range(10, 20); /* 50ns min delay needed as per HW design */ 131 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 132 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP; 133 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 134 135 usleep_range(10, 20); /* 500ns min delay needed as per HW design */ 136 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 137 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN; 138 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 139 140 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value, 141 (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0, 142 1000, 1000 * 2000); 143 if (err < 0) { 144 dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n"); 145 return err; 146 } 147 148 usleep_range(10, 20); /* 50ns min delay needed as per HW design */ 149 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 150 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN; 151 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 152 153 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 154 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; 155 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 156 157 usleep_range(10, 20); /* 50ns min delay needed as per HW design */ 158 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 159 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; 160 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 161 162 usleep_range(10, 20); /* 50ns min delay needed as per HW design */ 163 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 164 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; 165 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 166 167 msleep(30); /* 30ms delay needed as per HW design */ 168 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 169 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; 170 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 171 172 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, 173 value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS, 174 500, 500 * 2000); 175 if (err < 0) { 176 dev_err(mgbe->dev, "timeout waiting for link to become ready\n"); 177 return err; 178 } 179 180 /* clear status */ 181 writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS); 182 183 return 0; 184 } 185 186 static void mgbe_uphy_lane_bringup_serdes_down(struct net_device *ndev, void *mgbe_data) 187 { 188 struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data; 189 u32 value; 190 191 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 192 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD; 193 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 194 195 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 196 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN; 197 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 198 199 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 200 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP; 201 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 202 203 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 204 value |= XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ; 205 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 206 207 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 208 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ; 209 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); 210 } 211 212 static int tegra_mgbe_probe(struct platform_device *pdev) 213 { 214 struct plat_stmmacenet_data *plat; 215 struct stmmac_resources res; 216 struct tegra_mgbe *mgbe; 217 int irq, err, i; 218 u32 value; 219 220 mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL); 221 if (!mgbe) 222 return -ENOMEM; 223 224 mgbe->dev = &pdev->dev; 225 226 memset(&res, 0, sizeof(res)); 227 228 irq = platform_get_irq(pdev, 0); 229 if (irq < 0) 230 return irq; 231 232 mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); 233 if (IS_ERR(mgbe->hv)) 234 return PTR_ERR(mgbe->hv); 235 236 mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac"); 237 if (IS_ERR(mgbe->regs)) 238 return PTR_ERR(mgbe->regs); 239 240 mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs"); 241 if (IS_ERR(mgbe->xpcs)) 242 return PTR_ERR(mgbe->xpcs); 243 244 res.addr = mgbe->regs; 245 res.irq = irq; 246 247 mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks), 248 sizeof(*mgbe->clks), GFP_KERNEL); 249 if (!mgbe->clks) 250 return -ENOMEM; 251 252 for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++) 253 mgbe->clks[i].id = mgbe_clks[i]; 254 255 err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks); 256 if (err < 0) 257 return err; 258 259 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); 260 if (err < 0) 261 return err; 262 263 /* Perform MAC reset */ 264 mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac"); 265 if (IS_ERR(mgbe->rst_mac)) { 266 err = PTR_ERR(mgbe->rst_mac); 267 goto disable_clks; 268 } 269 270 err = reset_control_assert(mgbe->rst_mac); 271 if (err < 0) 272 goto disable_clks; 273 274 usleep_range(2000, 4000); 275 276 err = reset_control_deassert(mgbe->rst_mac); 277 if (err < 0) 278 goto disable_clks; 279 280 /* Perform PCS reset */ 281 mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs"); 282 if (IS_ERR(mgbe->rst_pcs)) { 283 err = PTR_ERR(mgbe->rst_pcs); 284 goto disable_clks; 285 } 286 287 err = reset_control_assert(mgbe->rst_pcs); 288 if (err < 0) 289 goto disable_clks; 290 291 usleep_range(2000, 4000); 292 293 err = reset_control_deassert(mgbe->rst_pcs); 294 if (err < 0) 295 goto disable_clks; 296 297 plat = devm_stmmac_probe_config_dt(pdev, res.mac); 298 if (IS_ERR(plat)) { 299 err = PTR_ERR(plat); 300 goto disable_clks; 301 } 302 303 plat->has_xgmac = 1; 304 plat->flags |= STMMAC_FLAG_TSO_EN; 305 plat->pmt = 1; 306 plat->bsp_priv = mgbe; 307 308 if (!plat->mdio_node) 309 plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 310 311 if (!plat->mdio_bus_data) { 312 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data), 313 GFP_KERNEL); 314 if (!plat->mdio_bus_data) { 315 err = -ENOMEM; 316 goto disable_clks; 317 } 318 } 319 320 plat->mdio_bus_data->needs_reset = true; 321 322 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); 323 if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) { 324 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); 325 value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN; 326 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); 327 } 328 329 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, 330 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0, 331 500, 500 * 2000); 332 if (err < 0) { 333 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); 334 goto disable_clks; 335 } 336 337 plat->serdes_powerup = mgbe_uphy_lane_bringup_serdes_up; 338 plat->serdes_powerdown = mgbe_uphy_lane_bringup_serdes_down; 339 340 /* Tx FIFO Size - 128KB */ 341 plat->tx_fifo_size = 131072; 342 /* Rx FIFO Size - 192KB */ 343 plat->rx_fifo_size = 196608; 344 345 /* Enable common interrupt at wrapper level */ 346 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); 347 348 /* Program SID */ 349 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); 350 351 plat->flags |= STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP; 352 353 err = stmmac_dvr_probe(&pdev->dev, plat, &res); 354 if (err < 0) 355 goto disable_clks; 356 357 return 0; 358 359 disable_clks: 360 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); 361 362 return err; 363 } 364 365 static void tegra_mgbe_remove(struct platform_device *pdev) 366 { 367 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev); 368 369 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); 370 371 stmmac_pltfr_remove(pdev); 372 } 373 374 static const struct of_device_id tegra_mgbe_match[] = { 375 { .compatible = "nvidia,tegra234-mgbe", }, 376 { } 377 }; 378 MODULE_DEVICE_TABLE(of, tegra_mgbe_match); 379 380 static SIMPLE_DEV_PM_OPS(tegra_mgbe_pm_ops, tegra_mgbe_suspend, tegra_mgbe_resume); 381 382 static struct platform_driver tegra_mgbe_driver = { 383 .probe = tegra_mgbe_probe, 384 .remove_new = tegra_mgbe_remove, 385 .driver = { 386 .name = "tegra-mgbe", 387 .pm = &tegra_mgbe_pm_ops, 388 .of_match_table = tegra_mgbe_match, 389 }, 390 }; 391 module_platform_driver(tegra_mgbe_driver); 392 393 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 394 MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver"); 395 MODULE_LICENSE("GPL"); 396