1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/of_platform.h> 18 #include <linux/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/regmap.h> 23 #include <linux/stmmac.h> 24 25 #include "stmmac.h" 26 #include "stmmac_platform.h" 27 28 /* General notes on dwmac-sun8i: 29 * Locking: no locking is necessary in this file because all necessary locking 30 * is done in the "stmmac files" 31 */ 32 33 /* struct emac_variant - Describe dwmac-sun8i hardware variant 34 * @default_syscon_value: The default value of the EMAC register in syscon 35 * This value is used for disabling properly EMAC 36 * and used as a good starting value in case of the 37 * boot process(uboot) leave some stuff. 38 * @syscon_field reg_field for the syscon's gmac register 39 * @soc_has_internal_phy: Does the MAC embed an internal PHY 40 * @support_mii: Does the MAC handle MII 41 * @support_rmii: Does the MAC handle RMII 42 * @support_rgmii: Does the MAC handle RGMII 43 * 44 * @rx_delay_max: Maximum raw value for RX delay chain 45 * @tx_delay_max: Maximum raw value for TX delay chain 46 * These two also indicate the bitmask for 47 * the RX and TX delay chain registers. A 48 * value of zero indicates this is not supported. 49 */ 50 struct emac_variant { 51 u32 default_syscon_value; 52 const struct reg_field *syscon_field; 53 bool soc_has_internal_phy; 54 bool support_mii; 55 bool support_rmii; 56 bool support_rgmii; 57 u8 rx_delay_max; 58 u8 tx_delay_max; 59 }; 60 61 /* struct sunxi_priv_data - hold all sunxi private data 62 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 63 * @regulator: reference to the optional regulator 64 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 65 * @variant: reference to the current board variant 66 * @regmap: regmap for using the syscon 67 * @internal_phy_powered: Does the internal PHY is enabled 68 * @use_internal_phy: Is the internal PHY selected for use 69 * @mux_handle: Internal pointer used by mdio-mux lib 70 */ 71 struct sunxi_priv_data { 72 struct clk *ephy_clk; 73 struct regulator *regulator; 74 struct reset_control *rst_ephy; 75 const struct emac_variant *variant; 76 struct regmap_field *regmap_field; 77 bool internal_phy_powered; 78 bool use_internal_phy; 79 void *mux_handle; 80 }; 81 82 /* EMAC clock register @ 0x30 in the "system control" address range */ 83 static const struct reg_field sun8i_syscon_reg_field = { 84 .reg = 0x30, 85 .lsb = 0, 86 .msb = 31, 87 }; 88 89 /* EMAC clock register @ 0x164 in the CCU address range */ 90 static const struct reg_field sun8i_ccu_reg_field = { 91 .reg = 0x164, 92 .lsb = 0, 93 .msb = 31, 94 }; 95 96 static const struct emac_variant emac_variant_h3 = { 97 .default_syscon_value = 0x58000, 98 .syscon_field = &sun8i_syscon_reg_field, 99 .soc_has_internal_phy = true, 100 .support_mii = true, 101 .support_rmii = true, 102 .support_rgmii = true, 103 .rx_delay_max = 31, 104 .tx_delay_max = 7, 105 }; 106 107 static const struct emac_variant emac_variant_v3s = { 108 .default_syscon_value = 0x38000, 109 .syscon_field = &sun8i_syscon_reg_field, 110 .soc_has_internal_phy = true, 111 .support_mii = true 112 }; 113 114 static const struct emac_variant emac_variant_a83t = { 115 .default_syscon_value = 0, 116 .syscon_field = &sun8i_syscon_reg_field, 117 .soc_has_internal_phy = false, 118 .support_mii = true, 119 .support_rgmii = true, 120 .rx_delay_max = 31, 121 .tx_delay_max = 7, 122 }; 123 124 static const struct emac_variant emac_variant_r40 = { 125 .default_syscon_value = 0, 126 .syscon_field = &sun8i_ccu_reg_field, 127 .support_mii = true, 128 .support_rgmii = true, 129 .rx_delay_max = 7, 130 }; 131 132 static const struct emac_variant emac_variant_a64 = { 133 .default_syscon_value = 0, 134 .syscon_field = &sun8i_syscon_reg_field, 135 .soc_has_internal_phy = false, 136 .support_mii = true, 137 .support_rmii = true, 138 .support_rgmii = true, 139 .rx_delay_max = 31, 140 .tx_delay_max = 7, 141 }; 142 143 static const struct emac_variant emac_variant_h6 = { 144 .default_syscon_value = 0x50000, 145 .syscon_field = &sun8i_syscon_reg_field, 146 /* The "Internal PHY" of H6 is not on the die. It's on the 147 * co-packaged AC200 chip instead. 148 */ 149 .soc_has_internal_phy = false, 150 .support_mii = true, 151 .support_rmii = true, 152 .support_rgmii = true, 153 .rx_delay_max = 31, 154 .tx_delay_max = 7, 155 }; 156 157 #define EMAC_BASIC_CTL0 0x00 158 #define EMAC_BASIC_CTL1 0x04 159 #define EMAC_INT_STA 0x08 160 #define EMAC_INT_EN 0x0C 161 #define EMAC_TX_CTL0 0x10 162 #define EMAC_TX_CTL1 0x14 163 #define EMAC_TX_FLOW_CTL 0x1C 164 #define EMAC_TX_DESC_LIST 0x20 165 #define EMAC_RX_CTL0 0x24 166 #define EMAC_RX_CTL1 0x28 167 #define EMAC_RX_DESC_LIST 0x34 168 #define EMAC_RX_FRM_FLT 0x38 169 #define EMAC_MDIO_CMD 0x48 170 #define EMAC_MDIO_DATA 0x4C 171 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 172 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 173 #define EMAC_TX_DMA_STA 0xB0 174 #define EMAC_TX_CUR_DESC 0xB4 175 #define EMAC_TX_CUR_BUF 0xB8 176 #define EMAC_RX_DMA_STA 0xC0 177 #define EMAC_RX_CUR_DESC 0xC4 178 #define EMAC_RX_CUR_BUF 0xC8 179 180 /* Use in EMAC_BASIC_CTL0 */ 181 #define EMAC_DUPLEX_FULL BIT(0) 182 #define EMAC_LOOPBACK BIT(1) 183 #define EMAC_SPEED_1000 0 184 #define EMAC_SPEED_100 (0x03 << 2) 185 #define EMAC_SPEED_10 (0x02 << 2) 186 187 /* Use in EMAC_BASIC_CTL1 */ 188 #define EMAC_BURSTLEN_SHIFT 24 189 190 /* Used in EMAC_RX_FRM_FLT */ 191 #define EMAC_FRM_FLT_RXALL BIT(0) 192 #define EMAC_FRM_FLT_CTL BIT(13) 193 #define EMAC_FRM_FLT_MULTICAST BIT(16) 194 195 /* Used in RX_CTL1*/ 196 #define EMAC_RX_MD BIT(1) 197 #define EMAC_RX_TH_MASK GENMASK(5, 4) 198 #define EMAC_RX_TH_32 0 199 #define EMAC_RX_TH_64 (0x1 << 4) 200 #define EMAC_RX_TH_96 (0x2 << 4) 201 #define EMAC_RX_TH_128 (0x3 << 4) 202 #define EMAC_RX_DMA_EN BIT(30) 203 #define EMAC_RX_DMA_START BIT(31) 204 205 /* Used in TX_CTL1*/ 206 #define EMAC_TX_MD BIT(1) 207 #define EMAC_TX_NEXT_FRM BIT(2) 208 #define EMAC_TX_TH_MASK GENMASK(10, 8) 209 #define EMAC_TX_TH_64 0 210 #define EMAC_TX_TH_128 (0x1 << 8) 211 #define EMAC_TX_TH_192 (0x2 << 8) 212 #define EMAC_TX_TH_256 (0x3 << 8) 213 #define EMAC_TX_DMA_EN BIT(30) 214 #define EMAC_TX_DMA_START BIT(31) 215 216 /* Used in RX_CTL0 */ 217 #define EMAC_RX_RECEIVER_EN BIT(31) 218 #define EMAC_RX_DO_CRC BIT(27) 219 #define EMAC_RX_FLOW_CTL_EN BIT(16) 220 221 /* Used in TX_CTL0 */ 222 #define EMAC_TX_TRANSMITTER_EN BIT(31) 223 224 /* Used in EMAC_TX_FLOW_CTL */ 225 #define EMAC_TX_FLOW_CTL_EN BIT(0) 226 227 /* Used in EMAC_INT_STA */ 228 #define EMAC_TX_INT BIT(0) 229 #define EMAC_TX_DMA_STOP_INT BIT(1) 230 #define EMAC_TX_BUF_UA_INT BIT(2) 231 #define EMAC_TX_TIMEOUT_INT BIT(3) 232 #define EMAC_TX_UNDERFLOW_INT BIT(4) 233 #define EMAC_TX_EARLY_INT BIT(5) 234 #define EMAC_RX_INT BIT(8) 235 #define EMAC_RX_BUF_UA_INT BIT(9) 236 #define EMAC_RX_DMA_STOP_INT BIT(10) 237 #define EMAC_RX_TIMEOUT_INT BIT(11) 238 #define EMAC_RX_OVERFLOW_INT BIT(12) 239 #define EMAC_RX_EARLY_INT BIT(13) 240 #define EMAC_RGMII_STA_INT BIT(16) 241 242 #define EMAC_INT_MSK_COMMON EMAC_RGMII_STA_INT 243 #define EMAC_INT_MSK_TX (EMAC_TX_INT | \ 244 EMAC_TX_DMA_STOP_INT | \ 245 EMAC_TX_BUF_UA_INT | \ 246 EMAC_TX_TIMEOUT_INT | \ 247 EMAC_TX_UNDERFLOW_INT | \ 248 EMAC_TX_EARLY_INT |\ 249 EMAC_INT_MSK_COMMON) 250 #define EMAC_INT_MSK_RX (EMAC_RX_INT | \ 251 EMAC_RX_BUF_UA_INT | \ 252 EMAC_RX_DMA_STOP_INT | \ 253 EMAC_RX_TIMEOUT_INT | \ 254 EMAC_RX_OVERFLOW_INT | \ 255 EMAC_RX_EARLY_INT | \ 256 EMAC_INT_MSK_COMMON) 257 258 #define MAC_ADDR_TYPE_DST BIT(31) 259 260 /* H3 specific bits for EPHY */ 261 #define H3_EPHY_ADDR_SHIFT 20 262 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 263 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 264 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 265 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 266 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 267 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 268 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 269 270 /* H3/A64 specific bits */ 271 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 272 273 /* Generic system control EMAC_CLK bits */ 274 #define SYSCON_ETXDC_SHIFT 10 275 #define SYSCON_ERXDC_SHIFT 5 276 /* EMAC PHY Interface Type */ 277 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 278 #define SYSCON_ETCS_MASK GENMASK(1, 0) 279 #define SYSCON_ETCS_MII 0x0 280 #define SYSCON_ETCS_EXT_GMII 0x1 281 #define SYSCON_ETCS_INT_GMII 0x2 282 283 /* sun8i_dwmac_dma_reset() - reset the EMAC 284 * Called from stmmac via stmmac_dma_ops->reset 285 */ 286 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 287 { 288 writel(0, ioaddr + EMAC_RX_CTL1); 289 writel(0, ioaddr + EMAC_TX_CTL1); 290 writel(0, ioaddr + EMAC_RX_FRM_FLT); 291 writel(0, ioaddr + EMAC_RX_DESC_LIST); 292 writel(0, ioaddr + EMAC_TX_DESC_LIST); 293 writel(0, ioaddr + EMAC_INT_EN); 294 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 295 return 0; 296 } 297 298 /* sun8i_dwmac_dma_init() - initialize the EMAC 299 * Called from stmmac via stmmac_dma_ops->init 300 */ 301 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 302 struct stmmac_dma_cfg *dma_cfg, int atds) 303 { 304 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 305 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 306 } 307 308 static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv, 309 void __iomem *ioaddr, 310 struct stmmac_dma_cfg *dma_cfg, 311 dma_addr_t dma_rx_phy, u32 chan) 312 { 313 /* Write RX descriptors address */ 314 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 315 } 316 317 static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv, 318 void __iomem *ioaddr, 319 struct stmmac_dma_cfg *dma_cfg, 320 dma_addr_t dma_tx_phy, u32 chan) 321 { 322 /* Write TX descriptors address */ 323 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 324 } 325 326 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 327 * Called from stmmac_dma_ops->dump_regs 328 * Used for ethtool 329 */ 330 static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv, 331 void __iomem *ioaddr, u32 *reg_space) 332 { 333 int i; 334 335 for (i = 0; i < 0xC8; i += 4) { 336 if (i == 0x32 || i == 0x3C) 337 continue; 338 reg_space[i / 4] = readl(ioaddr + i); 339 } 340 } 341 342 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 343 * Called from stmmac_ops->dump_regs 344 * Used for ethtool 345 */ 346 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 347 u32 *reg_space) 348 { 349 int i; 350 void __iomem *ioaddr = hw->pcsr; 351 352 for (i = 0; i < 0xC8; i += 4) { 353 if (i == 0x32 || i == 0x3C) 354 continue; 355 reg_space[i / 4] = readl(ioaddr + i); 356 } 357 } 358 359 static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv, 360 void __iomem *ioaddr, u32 chan, 361 bool rx, bool tx) 362 { 363 u32 value = readl(ioaddr + EMAC_INT_EN); 364 365 if (rx) 366 value |= EMAC_RX_INT; 367 if (tx) 368 value |= EMAC_TX_INT; 369 370 writel(value, ioaddr + EMAC_INT_EN); 371 } 372 373 static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv, 374 void __iomem *ioaddr, u32 chan, 375 bool rx, bool tx) 376 { 377 u32 value = readl(ioaddr + EMAC_INT_EN); 378 379 if (rx) 380 value &= ~EMAC_RX_INT; 381 if (tx) 382 value &= ~EMAC_TX_INT; 383 384 writel(value, ioaddr + EMAC_INT_EN); 385 } 386 387 static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv, 388 void __iomem *ioaddr, u32 chan) 389 { 390 u32 v; 391 392 v = readl(ioaddr + EMAC_TX_CTL1); 393 v |= EMAC_TX_DMA_START; 394 v |= EMAC_TX_DMA_EN; 395 writel(v, ioaddr + EMAC_TX_CTL1); 396 } 397 398 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 399 { 400 u32 v; 401 402 v = readl(ioaddr + EMAC_TX_CTL1); 403 v |= EMAC_TX_DMA_START; 404 v |= EMAC_TX_DMA_EN; 405 writel(v, ioaddr + EMAC_TX_CTL1); 406 } 407 408 static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv, 409 void __iomem *ioaddr, u32 chan) 410 { 411 u32 v; 412 413 v = readl(ioaddr + EMAC_TX_CTL1); 414 v &= ~EMAC_TX_DMA_EN; 415 writel(v, ioaddr + EMAC_TX_CTL1); 416 } 417 418 static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv, 419 void __iomem *ioaddr, u32 chan) 420 { 421 u32 v; 422 423 v = readl(ioaddr + EMAC_RX_CTL1); 424 v |= EMAC_RX_DMA_START; 425 v |= EMAC_RX_DMA_EN; 426 writel(v, ioaddr + EMAC_RX_CTL1); 427 } 428 429 static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv, 430 void __iomem *ioaddr, u32 chan) 431 { 432 u32 v; 433 434 v = readl(ioaddr + EMAC_RX_CTL1); 435 v &= ~EMAC_RX_DMA_EN; 436 writel(v, ioaddr + EMAC_RX_CTL1); 437 } 438 439 static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv, 440 void __iomem *ioaddr, 441 struct stmmac_extra_stats *x, u32 chan, 442 u32 dir) 443 { 444 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[chan]; 445 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan]; 446 int ret = 0; 447 u32 v; 448 449 v = readl(ioaddr + EMAC_INT_STA); 450 451 if (dir == DMA_DIR_RX) 452 v &= EMAC_INT_MSK_RX; 453 else if (dir == DMA_DIR_TX) 454 v &= EMAC_INT_MSK_TX; 455 456 if (v & EMAC_TX_INT) { 457 ret |= handle_tx; 458 u64_stats_update_begin(&txq_stats->syncp); 459 txq_stats->tx_normal_irq_n++; 460 u64_stats_update_end(&txq_stats->syncp); 461 } 462 463 if (v & EMAC_TX_DMA_STOP_INT) 464 x->tx_process_stopped_irq++; 465 466 if (v & EMAC_TX_BUF_UA_INT) 467 x->tx_process_stopped_irq++; 468 469 if (v & EMAC_TX_TIMEOUT_INT) 470 ret |= tx_hard_error; 471 472 if (v & EMAC_TX_UNDERFLOW_INT) { 473 ret |= tx_hard_error; 474 x->tx_undeflow_irq++; 475 } 476 477 if (v & EMAC_TX_EARLY_INT) 478 x->tx_early_irq++; 479 480 if (v & EMAC_RX_INT) { 481 ret |= handle_rx; 482 u64_stats_update_begin(&rxq_stats->syncp); 483 rxq_stats->rx_normal_irq_n++; 484 u64_stats_update_end(&rxq_stats->syncp); 485 } 486 487 if (v & EMAC_RX_BUF_UA_INT) 488 x->rx_buf_unav_irq++; 489 490 if (v & EMAC_RX_DMA_STOP_INT) 491 x->rx_process_stopped_irq++; 492 493 if (v & EMAC_RX_TIMEOUT_INT) 494 ret |= tx_hard_error; 495 496 if (v & EMAC_RX_OVERFLOW_INT) { 497 ret |= tx_hard_error; 498 x->rx_overflow_irq++; 499 } 500 501 if (v & EMAC_RX_EARLY_INT) 502 x->rx_early_irq++; 503 504 if (v & EMAC_RGMII_STA_INT) 505 x->irq_rgmii_n++; 506 507 writel(v, ioaddr + EMAC_INT_STA); 508 509 return ret; 510 } 511 512 static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv, 513 void __iomem *ioaddr, int mode, 514 u32 channel, int fifosz, u8 qmode) 515 { 516 u32 v; 517 518 v = readl(ioaddr + EMAC_RX_CTL1); 519 if (mode == SF_DMA_MODE) { 520 v |= EMAC_RX_MD; 521 } else { 522 v &= ~EMAC_RX_MD; 523 v &= ~EMAC_RX_TH_MASK; 524 if (mode < 32) 525 v |= EMAC_RX_TH_32; 526 else if (mode < 64) 527 v |= EMAC_RX_TH_64; 528 else if (mode < 96) 529 v |= EMAC_RX_TH_96; 530 else if (mode < 128) 531 v |= EMAC_RX_TH_128; 532 } 533 writel(v, ioaddr + EMAC_RX_CTL1); 534 } 535 536 static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv, 537 void __iomem *ioaddr, int mode, 538 u32 channel, int fifosz, u8 qmode) 539 { 540 u32 v; 541 542 v = readl(ioaddr + EMAC_TX_CTL1); 543 if (mode == SF_DMA_MODE) { 544 v |= EMAC_TX_MD; 545 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 546 * comment is 547 * "Operating on second frame increase the performance 548 * especially when transmit store-and-forward is used." 549 */ 550 v |= EMAC_TX_NEXT_FRM; 551 } else { 552 v &= ~EMAC_TX_MD; 553 v &= ~EMAC_TX_TH_MASK; 554 if (mode < 64) 555 v |= EMAC_TX_TH_64; 556 else if (mode < 128) 557 v |= EMAC_TX_TH_128; 558 else if (mode < 192) 559 v |= EMAC_TX_TH_192; 560 else if (mode < 256) 561 v |= EMAC_TX_TH_256; 562 } 563 writel(v, ioaddr + EMAC_TX_CTL1); 564 } 565 566 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 567 .reset = sun8i_dwmac_dma_reset, 568 .init = sun8i_dwmac_dma_init, 569 .init_rx_chan = sun8i_dwmac_dma_init_rx, 570 .init_tx_chan = sun8i_dwmac_dma_init_tx, 571 .dump_regs = sun8i_dwmac_dump_regs, 572 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 573 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 574 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 575 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 576 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 577 .start_tx = sun8i_dwmac_dma_start_tx, 578 .stop_tx = sun8i_dwmac_dma_stop_tx, 579 .start_rx = sun8i_dwmac_dma_start_rx, 580 .stop_rx = sun8i_dwmac_dma_stop_rx, 581 .dma_interrupt = sun8i_dwmac_dma_interrupt, 582 }; 583 584 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); 585 586 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 587 { 588 struct net_device *ndev = platform_get_drvdata(pdev); 589 struct sunxi_priv_data *gmac = priv; 590 int ret; 591 592 if (gmac->regulator) { 593 ret = regulator_enable(gmac->regulator); 594 if (ret) { 595 dev_err(&pdev->dev, "Fail to enable regulator\n"); 596 return ret; 597 } 598 } 599 600 if (gmac->use_internal_phy) { 601 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); 602 if (ret) 603 goto err_disable_regulator; 604 } 605 606 return 0; 607 608 err_disable_regulator: 609 if (gmac->regulator) 610 regulator_disable(gmac->regulator); 611 612 return ret; 613 } 614 615 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 616 struct net_device *dev) 617 { 618 void __iomem *ioaddr = hw->pcsr; 619 u32 v; 620 621 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 622 writel(v, ioaddr + EMAC_BASIC_CTL1); 623 } 624 625 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 626 { 627 u32 t, r; 628 629 t = readl(ioaddr + EMAC_TX_CTL0); 630 r = readl(ioaddr + EMAC_RX_CTL0); 631 if (enable) { 632 t |= EMAC_TX_TRANSMITTER_EN; 633 r |= EMAC_RX_RECEIVER_EN; 634 } else { 635 t &= ~EMAC_TX_TRANSMITTER_EN; 636 r &= ~EMAC_RX_RECEIVER_EN; 637 } 638 writel(t, ioaddr + EMAC_TX_CTL0); 639 writel(r, ioaddr + EMAC_RX_CTL0); 640 } 641 642 /* Set MAC address at slot reg_n 643 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 644 * If addr is NULL, clear the slot 645 */ 646 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 647 const unsigned char *addr, 648 unsigned int reg_n) 649 { 650 void __iomem *ioaddr = hw->pcsr; 651 u32 v; 652 653 if (!addr) { 654 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 655 return; 656 } 657 658 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 659 EMAC_MACADDR_LO(reg_n)); 660 if (reg_n > 0) { 661 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 662 v |= MAC_ADDR_TYPE_DST; 663 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 664 } 665 } 666 667 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 668 unsigned char *addr, 669 unsigned int reg_n) 670 { 671 void __iomem *ioaddr = hw->pcsr; 672 673 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 674 EMAC_MACADDR_LO(reg_n)); 675 } 676 677 /* caution this function must return non 0 to work */ 678 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 679 { 680 void __iomem *ioaddr = hw->pcsr; 681 u32 v; 682 683 v = readl(ioaddr + EMAC_RX_CTL0); 684 v |= EMAC_RX_DO_CRC; 685 writel(v, ioaddr + EMAC_RX_CTL0); 686 687 return 1; 688 } 689 690 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 691 struct net_device *dev) 692 { 693 void __iomem *ioaddr = hw->pcsr; 694 u32 v; 695 int i = 1; 696 struct netdev_hw_addr *ha; 697 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 698 699 v = EMAC_FRM_FLT_CTL; 700 701 if (dev->flags & IFF_PROMISC) { 702 v = EMAC_FRM_FLT_RXALL; 703 } else if (dev->flags & IFF_ALLMULTI) { 704 v |= EMAC_FRM_FLT_MULTICAST; 705 } else if (macaddrs <= hw->unicast_filter_entries) { 706 if (!netdev_mc_empty(dev)) { 707 netdev_for_each_mc_addr(ha, dev) { 708 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 709 i++; 710 } 711 } 712 if (!netdev_uc_empty(dev)) { 713 netdev_for_each_uc_addr(ha, dev) { 714 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 715 i++; 716 } 717 } 718 } else { 719 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 720 netdev_info(dev, "Too many address, switching to promiscuous\n"); 721 v = EMAC_FRM_FLT_RXALL; 722 } 723 724 /* Disable unused address filter slots */ 725 while (i < hw->unicast_filter_entries) 726 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 727 728 writel(v, ioaddr + EMAC_RX_FRM_FLT); 729 } 730 731 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 732 unsigned int duplex, unsigned int fc, 733 unsigned int pause_time, u32 tx_cnt) 734 { 735 void __iomem *ioaddr = hw->pcsr; 736 u32 v; 737 738 v = readl(ioaddr + EMAC_RX_CTL0); 739 if (fc == FLOW_AUTO) 740 v |= EMAC_RX_FLOW_CTL_EN; 741 else 742 v &= ~EMAC_RX_FLOW_CTL_EN; 743 writel(v, ioaddr + EMAC_RX_CTL0); 744 745 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 746 if (fc == FLOW_AUTO) 747 v |= EMAC_TX_FLOW_CTL_EN; 748 else 749 v &= ~EMAC_TX_FLOW_CTL_EN; 750 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 751 } 752 753 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 754 { 755 u32 v; 756 int err; 757 758 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 759 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 760 761 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 762 * need more if no cable plugged. 100ms seems OK 763 */ 764 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 765 !(v & 0x01), 100, 100000); 766 767 if (err) { 768 dev_err(priv->device, "EMAC reset timeout\n"); 769 return err; 770 } 771 return 0; 772 } 773 774 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 775 static int get_ephy_nodes(struct stmmac_priv *priv) 776 { 777 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 778 struct device_node *mdio_mux, *iphynode; 779 struct device_node *mdio_internal; 780 int ret; 781 782 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 783 if (!mdio_mux) { 784 dev_err(priv->device, "Cannot get mdio-mux node\n"); 785 return -ENODEV; 786 } 787 788 mdio_internal = of_get_compatible_child(mdio_mux, 789 "allwinner,sun8i-h3-mdio-internal"); 790 of_node_put(mdio_mux); 791 if (!mdio_internal) { 792 dev_err(priv->device, "Cannot get internal_mdio node\n"); 793 return -ENODEV; 794 } 795 796 /* Seek for internal PHY */ 797 for_each_child_of_node(mdio_internal, iphynode) { 798 gmac->ephy_clk = of_clk_get(iphynode, 0); 799 if (IS_ERR(gmac->ephy_clk)) 800 continue; 801 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 802 if (IS_ERR(gmac->rst_ephy)) { 803 ret = PTR_ERR(gmac->rst_ephy); 804 if (ret == -EPROBE_DEFER) { 805 of_node_put(iphynode); 806 of_node_put(mdio_internal); 807 return ret; 808 } 809 continue; 810 } 811 dev_info(priv->device, "Found internal PHY node\n"); 812 of_node_put(iphynode); 813 of_node_put(mdio_internal); 814 return 0; 815 } 816 817 of_node_put(mdio_internal); 818 return -ENODEV; 819 } 820 821 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 822 { 823 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 824 int ret; 825 826 if (gmac->internal_phy_powered) { 827 dev_warn(priv->device, "Internal PHY already powered\n"); 828 return 0; 829 } 830 831 dev_info(priv->device, "Powering internal PHY\n"); 832 ret = clk_prepare_enable(gmac->ephy_clk); 833 if (ret) { 834 dev_err(priv->device, "Cannot enable internal PHY\n"); 835 return ret; 836 } 837 838 /* Make sure the EPHY is properly reseted, as U-Boot may leave 839 * it at deasserted state, and thus it may fail to reset EMAC. 840 * 841 * This assumes the driver has exclusive access to the EPHY reset. 842 */ 843 ret = reset_control_reset(gmac->rst_ephy); 844 if (ret) { 845 dev_err(priv->device, "Cannot reset internal PHY\n"); 846 clk_disable_unprepare(gmac->ephy_clk); 847 return ret; 848 } 849 850 gmac->internal_phy_powered = true; 851 852 return 0; 853 } 854 855 static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 856 { 857 if (!gmac->internal_phy_powered) 858 return; 859 860 clk_disable_unprepare(gmac->ephy_clk); 861 reset_control_assert(gmac->rst_ephy); 862 gmac->internal_phy_powered = false; 863 } 864 865 /* MDIO multiplexing switch function 866 * This function is called by the mdio-mux layer when it thinks the mdio bus 867 * multiplexer needs to switch. 868 * 'current_child' is the current value of the mux register 869 * 'desired_child' is the value of the 'reg' property of the target child MDIO 870 * node. 871 * The first time this function is called, current_child == -1. 872 * If current_child == desired_child, then the mux is already set to the 873 * correct bus. 874 */ 875 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 876 void *data) 877 { 878 struct stmmac_priv *priv = data; 879 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 880 u32 reg, val; 881 int ret = 0; 882 883 if (current_child ^ desired_child) { 884 regmap_field_read(gmac->regmap_field, ®); 885 switch (desired_child) { 886 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 887 dev_info(priv->device, "Switch mux to internal PHY"); 888 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 889 gmac->use_internal_phy = true; 890 break; 891 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 892 dev_info(priv->device, "Switch mux to external PHY"); 893 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 894 gmac->use_internal_phy = false; 895 break; 896 default: 897 dev_err(priv->device, "Invalid child ID %x\n", 898 desired_child); 899 return -EINVAL; 900 } 901 regmap_field_write(gmac->regmap_field, val); 902 if (gmac->use_internal_phy) { 903 ret = sun8i_dwmac_power_internal_phy(priv); 904 if (ret) 905 return ret; 906 } else { 907 sun8i_dwmac_unpower_internal_phy(gmac); 908 } 909 /* After changing syscon value, the MAC need reset or it will 910 * use the last value (and so the last PHY set). 911 */ 912 ret = sun8i_dwmac_reset(priv); 913 } 914 return ret; 915 } 916 917 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 918 { 919 int ret; 920 struct device_node *mdio_mux; 921 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 922 923 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 924 if (!mdio_mux) 925 return -ENODEV; 926 927 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 928 &gmac->mux_handle, priv, priv->mii); 929 of_node_put(mdio_mux); 930 return ret; 931 } 932 933 static int sun8i_dwmac_set_syscon(struct device *dev, 934 struct plat_stmmacenet_data *plat) 935 { 936 struct sunxi_priv_data *gmac = plat->bsp_priv; 937 struct device_node *node = dev->of_node; 938 int ret; 939 u32 reg, val; 940 941 ret = regmap_field_read(gmac->regmap_field, &val); 942 if (ret) { 943 dev_err(dev, "Fail to read from regmap field.\n"); 944 return ret; 945 } 946 947 reg = gmac->variant->default_syscon_value; 948 if (reg != val) 949 dev_warn(dev, 950 "Current syscon value is not the default %x (expect %x)\n", 951 val, reg); 952 953 if (gmac->variant->soc_has_internal_phy) { 954 if (of_property_read_bool(node, "allwinner,leds-active-low")) 955 reg |= H3_EPHY_LED_POL; 956 else 957 reg &= ~H3_EPHY_LED_POL; 958 959 /* Force EPHY xtal frequency to 24MHz. */ 960 reg |= H3_EPHY_CLK_SEL; 961 962 ret = of_mdio_parse_addr(dev, plat->phy_node); 963 if (ret < 0) { 964 dev_err(dev, "Could not parse MDIO addr\n"); 965 return ret; 966 } 967 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 968 * address. No need to mask it again. 969 */ 970 reg |= 1 << H3_EPHY_ADDR_SHIFT; 971 } else { 972 /* For SoCs without internal PHY the PHY selection bit should be 973 * set to 0 (external PHY). 974 */ 975 reg &= ~H3_EPHY_SELECT; 976 } 977 978 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 979 if (val % 100) { 980 dev_err(dev, "tx-delay must be a multiple of 100\n"); 981 return -EINVAL; 982 } 983 val /= 100; 984 dev_dbg(dev, "set tx-delay to %x\n", val); 985 if (val <= gmac->variant->tx_delay_max) { 986 reg &= ~(gmac->variant->tx_delay_max << 987 SYSCON_ETXDC_SHIFT); 988 reg |= (val << SYSCON_ETXDC_SHIFT); 989 } else { 990 dev_err(dev, "Invalid TX clock delay: %d\n", 991 val); 992 return -EINVAL; 993 } 994 } 995 996 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 997 if (val % 100) { 998 dev_err(dev, "rx-delay must be a multiple of 100\n"); 999 return -EINVAL; 1000 } 1001 val /= 100; 1002 dev_dbg(dev, "set rx-delay to %x\n", val); 1003 if (val <= gmac->variant->rx_delay_max) { 1004 reg &= ~(gmac->variant->rx_delay_max << 1005 SYSCON_ERXDC_SHIFT); 1006 reg |= (val << SYSCON_ERXDC_SHIFT); 1007 } else { 1008 dev_err(dev, "Invalid RX clock delay: %d\n", 1009 val); 1010 return -EINVAL; 1011 } 1012 } 1013 1014 /* Clear interface mode bits */ 1015 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 1016 if (gmac->variant->support_rmii) 1017 reg &= ~SYSCON_RMII_EN; 1018 1019 switch (plat->mac_interface) { 1020 case PHY_INTERFACE_MODE_MII: 1021 /* default */ 1022 break; 1023 case PHY_INTERFACE_MODE_RGMII: 1024 case PHY_INTERFACE_MODE_RGMII_ID: 1025 case PHY_INTERFACE_MODE_RGMII_RXID: 1026 case PHY_INTERFACE_MODE_RGMII_TXID: 1027 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 1028 break; 1029 case PHY_INTERFACE_MODE_RMII: 1030 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 1031 break; 1032 default: 1033 dev_err(dev, "Unsupported interface mode: %s", 1034 phy_modes(plat->mac_interface)); 1035 return -EINVAL; 1036 } 1037 1038 regmap_field_write(gmac->regmap_field, reg); 1039 1040 return 0; 1041 } 1042 1043 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 1044 { 1045 u32 reg = gmac->variant->default_syscon_value; 1046 1047 regmap_field_write(gmac->regmap_field, reg); 1048 } 1049 1050 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 1051 { 1052 struct sunxi_priv_data *gmac = priv; 1053 1054 if (gmac->variant->soc_has_internal_phy) 1055 sun8i_dwmac_unpower_internal_phy(gmac); 1056 1057 if (gmac->regulator) 1058 regulator_disable(gmac->regulator); 1059 } 1060 1061 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1062 { 1063 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1064 1065 if (enable) 1066 value |= EMAC_LOOPBACK; 1067 else 1068 value &= ~EMAC_LOOPBACK; 1069 1070 writel(value, ioaddr + EMAC_BASIC_CTL0); 1071 } 1072 1073 static const struct stmmac_ops sun8i_dwmac_ops = { 1074 .core_init = sun8i_dwmac_core_init, 1075 .set_mac = sun8i_dwmac_set_mac, 1076 .dump_regs = sun8i_dwmac_dump_mac_regs, 1077 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1078 .set_filter = sun8i_dwmac_set_filter, 1079 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1080 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1081 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1082 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1083 }; 1084 1085 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1086 { 1087 struct mac_device_info *mac; 1088 struct stmmac_priv *priv = ppriv; 1089 1090 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1091 if (!mac) 1092 return NULL; 1093 1094 mac->pcsr = priv->ioaddr; 1095 mac->mac = &sun8i_dwmac_ops; 1096 mac->dma = &sun8i_dwmac_dma_ops; 1097 1098 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1099 1100 /* The loopback bit seems to be re-set when link change 1101 * Simply mask it each time 1102 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1103 */ 1104 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1105 mac->link.speed10 = EMAC_SPEED_10; 1106 mac->link.speed100 = EMAC_SPEED_100; 1107 mac->link.speed1000 = EMAC_SPEED_1000; 1108 mac->link.duplex = EMAC_DUPLEX_FULL; 1109 mac->mii.addr = EMAC_MDIO_CMD; 1110 mac->mii.data = EMAC_MDIO_DATA; 1111 mac->mii.reg_shift = 4; 1112 mac->mii.reg_mask = GENMASK(8, 4); 1113 mac->mii.addr_shift = 12; 1114 mac->mii.addr_mask = GENMASK(16, 12); 1115 mac->mii.clk_csr_shift = 20; 1116 mac->mii.clk_csr_mask = GENMASK(22, 20); 1117 mac->unicast_filter_entries = 8; 1118 1119 /* Synopsys Id is not available */ 1120 priv->synopsys_id = 0; 1121 1122 return mac; 1123 } 1124 1125 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1126 { 1127 struct device_node *syscon_node; 1128 struct platform_device *syscon_pdev; 1129 struct regmap *regmap = NULL; 1130 1131 syscon_node = of_parse_phandle(node, "syscon", 0); 1132 if (!syscon_node) 1133 return ERR_PTR(-ENODEV); 1134 1135 syscon_pdev = of_find_device_by_node(syscon_node); 1136 if (!syscon_pdev) { 1137 /* platform device might not be probed yet */ 1138 regmap = ERR_PTR(-EPROBE_DEFER); 1139 goto out_put_node; 1140 } 1141 1142 /* If no regmap is found then the other device driver is at fault */ 1143 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1144 if (!regmap) 1145 regmap = ERR_PTR(-EINVAL); 1146 1147 platform_device_put(syscon_pdev); 1148 out_put_node: 1149 of_node_put(syscon_node); 1150 return regmap; 1151 } 1152 1153 static int sun8i_dwmac_probe(struct platform_device *pdev) 1154 { 1155 struct plat_stmmacenet_data *plat_dat; 1156 struct stmmac_resources stmmac_res; 1157 struct sunxi_priv_data *gmac; 1158 struct device *dev = &pdev->dev; 1159 phy_interface_t interface; 1160 int ret; 1161 struct stmmac_priv *priv; 1162 struct net_device *ndev; 1163 struct regmap *regmap; 1164 1165 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1166 if (ret) 1167 return ret; 1168 1169 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1170 if (!gmac) 1171 return -ENOMEM; 1172 1173 gmac->variant = of_device_get_match_data(&pdev->dev); 1174 if (!gmac->variant) { 1175 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1176 return -EINVAL; 1177 } 1178 1179 /* Optional regulator for PHY */ 1180 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1181 if (IS_ERR(gmac->regulator)) { 1182 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1183 return -EPROBE_DEFER; 1184 dev_info(dev, "No regulator found\n"); 1185 gmac->regulator = NULL; 1186 } 1187 1188 /* The "GMAC clock control" register might be located in the 1189 * CCU address range (on the R40), or the system control address 1190 * range (on most other sun8i and later SoCs). 1191 * 1192 * The former controls most if not all clocks in the SoC. The 1193 * latter has an SoC identification register, and on some SoCs, 1194 * controls to map device specific SRAM to either the intended 1195 * peripheral, or the CPU address space. 1196 * 1197 * In either case, there should be a coordinated and restricted 1198 * method of accessing the register needed here. This is done by 1199 * having the device export a custom regmap, instead of a generic 1200 * syscon, which grants all access to all registers. 1201 * 1202 * To support old device trees, we fall back to using the syscon 1203 * interface if possible. 1204 */ 1205 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1206 if (IS_ERR(regmap)) 1207 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1208 "syscon"); 1209 if (IS_ERR(regmap)) { 1210 ret = PTR_ERR(regmap); 1211 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1212 return ret; 1213 } 1214 1215 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1216 *gmac->variant->syscon_field); 1217 if (IS_ERR(gmac->regmap_field)) { 1218 ret = PTR_ERR(gmac->regmap_field); 1219 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1220 return ret; 1221 } 1222 1223 ret = of_get_phy_mode(dev->of_node, &interface); 1224 if (ret) 1225 return -EINVAL; 1226 1227 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 1228 if (IS_ERR(plat_dat)) 1229 return PTR_ERR(plat_dat); 1230 1231 /* platform data specifying hardware features and callbacks. 1232 * hardware features were copied from Allwinner drivers. 1233 */ 1234 plat_dat->mac_interface = interface; 1235 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1236 plat_dat->tx_coe = 1; 1237 plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I; 1238 plat_dat->bsp_priv = gmac; 1239 plat_dat->init = sun8i_dwmac_init; 1240 plat_dat->exit = sun8i_dwmac_exit; 1241 plat_dat->setup = sun8i_dwmac_setup; 1242 plat_dat->tx_fifo_size = 4096; 1243 plat_dat->rx_fifo_size = 16384; 1244 1245 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); 1246 if (ret) 1247 goto dwmac_deconfig; 1248 1249 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1250 if (ret) 1251 goto dwmac_syscon; 1252 1253 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1254 if (ret) 1255 goto dwmac_exit; 1256 1257 ndev = dev_get_drvdata(&pdev->dev); 1258 priv = netdev_priv(ndev); 1259 1260 /* the MAC is runtime suspended after stmmac_dvr_probe(), so we 1261 * need to ensure the MAC resume back before other operations such 1262 * as reset. 1263 */ 1264 pm_runtime_get_sync(&pdev->dev); 1265 1266 /* The mux must be registered after parent MDIO 1267 * so after stmmac_dvr_probe() 1268 */ 1269 if (gmac->variant->soc_has_internal_phy) { 1270 ret = get_ephy_nodes(priv); 1271 if (ret) 1272 goto dwmac_remove; 1273 ret = sun8i_dwmac_register_mdio_mux(priv); 1274 if (ret) { 1275 dev_err(&pdev->dev, "Failed to register mux\n"); 1276 goto dwmac_mux; 1277 } 1278 } else { 1279 ret = sun8i_dwmac_reset(priv); 1280 if (ret) 1281 goto dwmac_remove; 1282 } 1283 1284 pm_runtime_put(&pdev->dev); 1285 1286 return 0; 1287 1288 dwmac_mux: 1289 reset_control_put(gmac->rst_ephy); 1290 clk_put(gmac->ephy_clk); 1291 dwmac_remove: 1292 pm_runtime_put_noidle(&pdev->dev); 1293 stmmac_dvr_remove(&pdev->dev); 1294 dwmac_exit: 1295 sun8i_dwmac_exit(pdev, gmac); 1296 dwmac_syscon: 1297 sun8i_dwmac_unset_syscon(gmac); 1298 dwmac_deconfig: 1299 stmmac_remove_config_dt(pdev, plat_dat); 1300 1301 return ret; 1302 } 1303 1304 static void sun8i_dwmac_remove(struct platform_device *pdev) 1305 { 1306 struct net_device *ndev = platform_get_drvdata(pdev); 1307 struct stmmac_priv *priv = netdev_priv(ndev); 1308 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1309 1310 if (gmac->variant->soc_has_internal_phy) { 1311 mdio_mux_uninit(gmac->mux_handle); 1312 sun8i_dwmac_unpower_internal_phy(gmac); 1313 reset_control_put(gmac->rst_ephy); 1314 clk_put(gmac->ephy_clk); 1315 } 1316 1317 stmmac_pltfr_remove(pdev); 1318 sun8i_dwmac_unset_syscon(gmac); 1319 } 1320 1321 static void sun8i_dwmac_shutdown(struct platform_device *pdev) 1322 { 1323 struct net_device *ndev = platform_get_drvdata(pdev); 1324 struct stmmac_priv *priv = netdev_priv(ndev); 1325 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1326 1327 sun8i_dwmac_exit(pdev, gmac); 1328 } 1329 1330 static const struct of_device_id sun8i_dwmac_match[] = { 1331 { .compatible = "allwinner,sun8i-h3-emac", 1332 .data = &emac_variant_h3 }, 1333 { .compatible = "allwinner,sun8i-v3s-emac", 1334 .data = &emac_variant_v3s }, 1335 { .compatible = "allwinner,sun8i-a83t-emac", 1336 .data = &emac_variant_a83t }, 1337 { .compatible = "allwinner,sun8i-r40-gmac", 1338 .data = &emac_variant_r40 }, 1339 { .compatible = "allwinner,sun50i-a64-emac", 1340 .data = &emac_variant_a64 }, 1341 { .compatible = "allwinner,sun50i-h6-emac", 1342 .data = &emac_variant_h6 }, 1343 { } 1344 }; 1345 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1346 1347 static struct platform_driver sun8i_dwmac_driver = { 1348 .probe = sun8i_dwmac_probe, 1349 .remove_new = sun8i_dwmac_remove, 1350 .shutdown = sun8i_dwmac_shutdown, 1351 .driver = { 1352 .name = "dwmac-sun8i", 1353 .pm = &stmmac_pltfr_pm_ops, 1354 .of_match_table = sun8i_dwmac_match, 1355 }, 1356 }; 1357 module_platform_driver(sun8i_dwmac_driver); 1358 1359 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1360 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1361 MODULE_LICENSE("GPL"); 1362