1 /* 2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 3 * 4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/mdio-mux.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/phy.h> 27 #include <linux/platform_device.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/regmap.h> 30 #include <linux/stmmac.h> 31 32 #include "stmmac.h" 33 #include "stmmac_platform.h" 34 35 /* General notes on dwmac-sun8i: 36 * Locking: no locking is necessary in this file because all necessary locking 37 * is done in the "stmmac files" 38 */ 39 40 /* struct emac_variant - Descrive dwmac-sun8i hardware variant 41 * @default_syscon_value: The default value of the EMAC register in syscon 42 * This value is used for disabling properly EMAC 43 * and used as a good starting value in case of the 44 * boot process(uboot) leave some stuff. 45 * @syscon_field reg_field for the syscon's gmac register 46 * @soc_has_internal_phy: Does the MAC embed an internal PHY 47 * @support_mii: Does the MAC handle MII 48 * @support_rmii: Does the MAC handle RMII 49 * @support_rgmii: Does the MAC handle RGMII 50 * 51 * @rx_delay_max: Maximum raw value for RX delay chain 52 * @tx_delay_max: Maximum raw value for TX delay chain 53 * These two also indicate the bitmask for 54 * the RX and TX delay chain registers. A 55 * value of zero indicates this is not supported. 56 */ 57 struct emac_variant { 58 u32 default_syscon_value; 59 const struct reg_field *syscon_field; 60 bool soc_has_internal_phy; 61 bool support_mii; 62 bool support_rmii; 63 bool support_rgmii; 64 u8 rx_delay_max; 65 u8 tx_delay_max; 66 }; 67 68 /* struct sunxi_priv_data - hold all sunxi private data 69 * @tx_clk: reference to MAC TX clock 70 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 71 * @regulator: reference to the optional regulator 72 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 73 * @variant: reference to the current board variant 74 * @regmap: regmap for using the syscon 75 * @internal_phy_powered: Does the internal PHY is enabled 76 * @mux_handle: Internal pointer used by mdio-mux lib 77 */ 78 struct sunxi_priv_data { 79 struct clk *tx_clk; 80 struct clk *ephy_clk; 81 struct regulator *regulator; 82 struct reset_control *rst_ephy; 83 const struct emac_variant *variant; 84 struct regmap_field *regmap_field; 85 bool internal_phy_powered; 86 void *mux_handle; 87 }; 88 89 /* EMAC clock register @ 0x30 in the "system control" address range */ 90 static const struct reg_field sun8i_syscon_reg_field = { 91 .reg = 0x30, 92 .lsb = 0, 93 .msb = 31, 94 }; 95 96 /* EMAC clock register @ 0x164 in the CCU address range */ 97 static const struct reg_field sun8i_ccu_reg_field = { 98 .reg = 0x164, 99 .lsb = 0, 100 .msb = 31, 101 }; 102 103 static const struct emac_variant emac_variant_h3 = { 104 .default_syscon_value = 0x58000, 105 .syscon_field = &sun8i_syscon_reg_field, 106 .soc_has_internal_phy = true, 107 .support_mii = true, 108 .support_rmii = true, 109 .support_rgmii = true, 110 .rx_delay_max = 31, 111 .tx_delay_max = 7, 112 }; 113 114 static const struct emac_variant emac_variant_v3s = { 115 .default_syscon_value = 0x38000, 116 .syscon_field = &sun8i_syscon_reg_field, 117 .soc_has_internal_phy = true, 118 .support_mii = true 119 }; 120 121 static const struct emac_variant emac_variant_a83t = { 122 .default_syscon_value = 0, 123 .syscon_field = &sun8i_syscon_reg_field, 124 .soc_has_internal_phy = false, 125 .support_mii = true, 126 .support_rgmii = true, 127 .rx_delay_max = 31, 128 .tx_delay_max = 7, 129 }; 130 131 static const struct emac_variant emac_variant_r40 = { 132 .default_syscon_value = 0, 133 .syscon_field = &sun8i_ccu_reg_field, 134 .support_mii = true, 135 .support_rgmii = true, 136 .rx_delay_max = 7, 137 }; 138 139 static const struct emac_variant emac_variant_a64 = { 140 .default_syscon_value = 0, 141 .syscon_field = &sun8i_syscon_reg_field, 142 .soc_has_internal_phy = false, 143 .support_mii = true, 144 .support_rmii = true, 145 .support_rgmii = true, 146 .rx_delay_max = 31, 147 .tx_delay_max = 7, 148 }; 149 150 #define EMAC_BASIC_CTL0 0x00 151 #define EMAC_BASIC_CTL1 0x04 152 #define EMAC_INT_STA 0x08 153 #define EMAC_INT_EN 0x0C 154 #define EMAC_TX_CTL0 0x10 155 #define EMAC_TX_CTL1 0x14 156 #define EMAC_TX_FLOW_CTL 0x1C 157 #define EMAC_TX_DESC_LIST 0x20 158 #define EMAC_RX_CTL0 0x24 159 #define EMAC_RX_CTL1 0x28 160 #define EMAC_RX_DESC_LIST 0x34 161 #define EMAC_RX_FRM_FLT 0x38 162 #define EMAC_MDIO_CMD 0x48 163 #define EMAC_MDIO_DATA 0x4C 164 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 165 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 166 #define EMAC_TX_DMA_STA 0xB0 167 #define EMAC_TX_CUR_DESC 0xB4 168 #define EMAC_TX_CUR_BUF 0xB8 169 #define EMAC_RX_DMA_STA 0xC0 170 #define EMAC_RX_CUR_DESC 0xC4 171 #define EMAC_RX_CUR_BUF 0xC8 172 173 /* Use in EMAC_BASIC_CTL0 */ 174 #define EMAC_DUPLEX_FULL BIT(0) 175 #define EMAC_LOOPBACK BIT(1) 176 #define EMAC_SPEED_1000 0 177 #define EMAC_SPEED_100 (0x03 << 2) 178 #define EMAC_SPEED_10 (0x02 << 2) 179 180 /* Use in EMAC_BASIC_CTL1 */ 181 #define EMAC_BURSTLEN_SHIFT 24 182 183 /* Used in EMAC_RX_FRM_FLT */ 184 #define EMAC_FRM_FLT_RXALL BIT(0) 185 #define EMAC_FRM_FLT_CTL BIT(13) 186 #define EMAC_FRM_FLT_MULTICAST BIT(16) 187 188 /* Used in RX_CTL1*/ 189 #define EMAC_RX_MD BIT(1) 190 #define EMAC_RX_TH_MASK GENMASK(4, 5) 191 #define EMAC_RX_TH_32 0 192 #define EMAC_RX_TH_64 (0x1 << 4) 193 #define EMAC_RX_TH_96 (0x2 << 4) 194 #define EMAC_RX_TH_128 (0x3 << 4) 195 #define EMAC_RX_DMA_EN BIT(30) 196 #define EMAC_RX_DMA_START BIT(31) 197 198 /* Used in TX_CTL1*/ 199 #define EMAC_TX_MD BIT(1) 200 #define EMAC_TX_NEXT_FRM BIT(2) 201 #define EMAC_TX_TH_MASK GENMASK(8, 10) 202 #define EMAC_TX_TH_64 0 203 #define EMAC_TX_TH_128 (0x1 << 8) 204 #define EMAC_TX_TH_192 (0x2 << 8) 205 #define EMAC_TX_TH_256 (0x3 << 8) 206 #define EMAC_TX_DMA_EN BIT(30) 207 #define EMAC_TX_DMA_START BIT(31) 208 209 /* Used in RX_CTL0 */ 210 #define EMAC_RX_RECEIVER_EN BIT(31) 211 #define EMAC_RX_DO_CRC BIT(27) 212 #define EMAC_RX_FLOW_CTL_EN BIT(16) 213 214 /* Used in TX_CTL0 */ 215 #define EMAC_TX_TRANSMITTER_EN BIT(31) 216 217 /* Used in EMAC_TX_FLOW_CTL */ 218 #define EMAC_TX_FLOW_CTL_EN BIT(0) 219 220 /* Used in EMAC_INT_STA */ 221 #define EMAC_TX_INT BIT(0) 222 #define EMAC_TX_DMA_STOP_INT BIT(1) 223 #define EMAC_TX_BUF_UA_INT BIT(2) 224 #define EMAC_TX_TIMEOUT_INT BIT(3) 225 #define EMAC_TX_UNDERFLOW_INT BIT(4) 226 #define EMAC_TX_EARLY_INT BIT(5) 227 #define EMAC_RX_INT BIT(8) 228 #define EMAC_RX_BUF_UA_INT BIT(9) 229 #define EMAC_RX_DMA_STOP_INT BIT(10) 230 #define EMAC_RX_TIMEOUT_INT BIT(11) 231 #define EMAC_RX_OVERFLOW_INT BIT(12) 232 #define EMAC_RX_EARLY_INT BIT(13) 233 #define EMAC_RGMII_STA_INT BIT(16) 234 235 #define MAC_ADDR_TYPE_DST BIT(31) 236 237 /* H3 specific bits for EPHY */ 238 #define H3_EPHY_ADDR_SHIFT 20 239 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 240 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 241 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 242 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 243 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 244 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 245 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 246 247 /* H3/A64 specific bits */ 248 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 249 250 /* Generic system control EMAC_CLK bits */ 251 #define SYSCON_ETXDC_SHIFT 10 252 #define SYSCON_ERXDC_SHIFT 5 253 /* EMAC PHY Interface Type */ 254 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 255 #define SYSCON_ETCS_MASK GENMASK(1, 0) 256 #define SYSCON_ETCS_MII 0x0 257 #define SYSCON_ETCS_EXT_GMII 0x1 258 #define SYSCON_ETCS_INT_GMII 0x2 259 260 /* sun8i_dwmac_dma_reset() - reset the EMAC 261 * Called from stmmac via stmmac_dma_ops->reset 262 */ 263 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 264 { 265 writel(0, ioaddr + EMAC_RX_CTL1); 266 writel(0, ioaddr + EMAC_TX_CTL1); 267 writel(0, ioaddr + EMAC_RX_FRM_FLT); 268 writel(0, ioaddr + EMAC_RX_DESC_LIST); 269 writel(0, ioaddr + EMAC_TX_DESC_LIST); 270 writel(0, ioaddr + EMAC_INT_EN); 271 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 272 return 0; 273 } 274 275 /* sun8i_dwmac_dma_init() - initialize the EMAC 276 * Called from stmmac via stmmac_dma_ops->init 277 */ 278 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 279 struct stmmac_dma_cfg *dma_cfg, 280 u32 dma_tx, u32 dma_rx, int atds) 281 { 282 /* Write TX and RX descriptors address */ 283 writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST); 284 writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST); 285 286 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 287 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 288 } 289 290 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 291 * Called from stmmac_dma_ops->dump_regs 292 * Used for ethtool 293 */ 294 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 295 { 296 int i; 297 298 for (i = 0; i < 0xC8; i += 4) { 299 if (i == 0x32 || i == 0x3C) 300 continue; 301 reg_space[i / 4] = readl(ioaddr + i); 302 } 303 } 304 305 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 306 * Called from stmmac_ops->dump_regs 307 * Used for ethtool 308 */ 309 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 310 u32 *reg_space) 311 { 312 int i; 313 void __iomem *ioaddr = hw->pcsr; 314 315 for (i = 0; i < 0xC8; i += 4) { 316 if (i == 0x32 || i == 0x3C) 317 continue; 318 reg_space[i / 4] = readl(ioaddr + i); 319 } 320 } 321 322 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) 323 { 324 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 325 } 326 327 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 328 { 329 writel(0, ioaddr + EMAC_INT_EN); 330 } 331 332 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 333 { 334 u32 v; 335 336 v = readl(ioaddr + EMAC_TX_CTL1); 337 v |= EMAC_TX_DMA_START; 338 v |= EMAC_TX_DMA_EN; 339 writel(v, ioaddr + EMAC_TX_CTL1); 340 } 341 342 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 343 { 344 u32 v; 345 346 v = readl(ioaddr + EMAC_TX_CTL1); 347 v |= EMAC_TX_DMA_START; 348 v |= EMAC_TX_DMA_EN; 349 writel(v, ioaddr + EMAC_TX_CTL1); 350 } 351 352 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 353 { 354 u32 v; 355 356 v = readl(ioaddr + EMAC_TX_CTL1); 357 v &= ~EMAC_TX_DMA_EN; 358 writel(v, ioaddr + EMAC_TX_CTL1); 359 } 360 361 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 362 { 363 u32 v; 364 365 v = readl(ioaddr + EMAC_RX_CTL1); 366 v |= EMAC_RX_DMA_START; 367 v |= EMAC_RX_DMA_EN; 368 writel(v, ioaddr + EMAC_RX_CTL1); 369 } 370 371 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 372 { 373 u32 v; 374 375 v = readl(ioaddr + EMAC_RX_CTL1); 376 v &= ~EMAC_RX_DMA_EN; 377 writel(v, ioaddr + EMAC_RX_CTL1); 378 } 379 380 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 381 struct stmmac_extra_stats *x, u32 chan) 382 { 383 u32 v; 384 int ret = 0; 385 386 v = readl(ioaddr + EMAC_INT_STA); 387 388 if (v & EMAC_TX_INT) { 389 ret |= handle_tx; 390 x->tx_normal_irq_n++; 391 } 392 393 if (v & EMAC_TX_DMA_STOP_INT) 394 x->tx_process_stopped_irq++; 395 396 if (v & EMAC_TX_BUF_UA_INT) 397 x->tx_process_stopped_irq++; 398 399 if (v & EMAC_TX_TIMEOUT_INT) 400 ret |= tx_hard_error; 401 402 if (v & EMAC_TX_UNDERFLOW_INT) { 403 ret |= tx_hard_error; 404 x->tx_undeflow_irq++; 405 } 406 407 if (v & EMAC_TX_EARLY_INT) 408 x->tx_early_irq++; 409 410 if (v & EMAC_RX_INT) { 411 ret |= handle_rx; 412 x->rx_normal_irq_n++; 413 } 414 415 if (v & EMAC_RX_BUF_UA_INT) 416 x->rx_buf_unav_irq++; 417 418 if (v & EMAC_RX_DMA_STOP_INT) 419 x->rx_process_stopped_irq++; 420 421 if (v & EMAC_RX_TIMEOUT_INT) 422 ret |= tx_hard_error; 423 424 if (v & EMAC_RX_OVERFLOW_INT) { 425 ret |= tx_hard_error; 426 x->rx_overflow_irq++; 427 } 428 429 if (v & EMAC_RX_EARLY_INT) 430 x->rx_early_irq++; 431 432 if (v & EMAC_RGMII_STA_INT) 433 x->irq_rgmii_n++; 434 435 writel(v, ioaddr + EMAC_INT_STA); 436 437 return ret; 438 } 439 440 static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode, 441 int rxmode, int rxfifosz) 442 { 443 u32 v; 444 445 v = readl(ioaddr + EMAC_TX_CTL1); 446 if (txmode == SF_DMA_MODE) { 447 v |= EMAC_TX_MD; 448 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 449 * comment is 450 * "Operating on second frame increase the performance 451 * especially when transmit store-and-forward is used." 452 */ 453 v |= EMAC_TX_NEXT_FRM; 454 } else { 455 v &= ~EMAC_TX_MD; 456 v &= ~EMAC_TX_TH_MASK; 457 if (txmode < 64) 458 v |= EMAC_TX_TH_64; 459 else if (txmode < 128) 460 v |= EMAC_TX_TH_128; 461 else if (txmode < 192) 462 v |= EMAC_TX_TH_192; 463 else if (txmode < 256) 464 v |= EMAC_TX_TH_256; 465 } 466 writel(v, ioaddr + EMAC_TX_CTL1); 467 468 v = readl(ioaddr + EMAC_RX_CTL1); 469 if (rxmode == SF_DMA_MODE) { 470 v |= EMAC_RX_MD; 471 } else { 472 v &= ~EMAC_RX_MD; 473 v &= ~EMAC_RX_TH_MASK; 474 if (rxmode < 32) 475 v |= EMAC_RX_TH_32; 476 else if (rxmode < 64) 477 v |= EMAC_RX_TH_64; 478 else if (rxmode < 96) 479 v |= EMAC_RX_TH_96; 480 else if (rxmode < 128) 481 v |= EMAC_RX_TH_128; 482 } 483 writel(v, ioaddr + EMAC_RX_CTL1); 484 } 485 486 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 487 .reset = sun8i_dwmac_dma_reset, 488 .init = sun8i_dwmac_dma_init, 489 .dump_regs = sun8i_dwmac_dump_regs, 490 .dma_mode = sun8i_dwmac_dma_operation_mode, 491 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 492 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 493 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 494 .start_tx = sun8i_dwmac_dma_start_tx, 495 .stop_tx = sun8i_dwmac_dma_stop_tx, 496 .start_rx = sun8i_dwmac_dma_start_rx, 497 .stop_rx = sun8i_dwmac_dma_stop_rx, 498 .dma_interrupt = sun8i_dwmac_dma_interrupt, 499 }; 500 501 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 502 { 503 struct sunxi_priv_data *gmac = priv; 504 int ret; 505 506 if (gmac->regulator) { 507 ret = regulator_enable(gmac->regulator); 508 if (ret) { 509 dev_err(&pdev->dev, "Fail to enable regulator\n"); 510 return ret; 511 } 512 } 513 514 ret = clk_prepare_enable(gmac->tx_clk); 515 if (ret) { 516 if (gmac->regulator) 517 regulator_disable(gmac->regulator); 518 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 519 return ret; 520 } 521 522 return 0; 523 } 524 525 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 526 struct net_device *dev) 527 { 528 void __iomem *ioaddr = hw->pcsr; 529 u32 v; 530 531 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 532 writel(v, ioaddr + EMAC_BASIC_CTL1); 533 } 534 535 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 536 { 537 u32 t, r; 538 539 t = readl(ioaddr + EMAC_TX_CTL0); 540 r = readl(ioaddr + EMAC_RX_CTL0); 541 if (enable) { 542 t |= EMAC_TX_TRANSMITTER_EN; 543 r |= EMAC_RX_RECEIVER_EN; 544 } else { 545 t &= ~EMAC_TX_TRANSMITTER_EN; 546 r &= ~EMAC_RX_RECEIVER_EN; 547 } 548 writel(t, ioaddr + EMAC_TX_CTL0); 549 writel(r, ioaddr + EMAC_RX_CTL0); 550 } 551 552 /* Set MAC address at slot reg_n 553 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 554 * If addr is NULL, clear the slot 555 */ 556 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 557 unsigned char *addr, 558 unsigned int reg_n) 559 { 560 void __iomem *ioaddr = hw->pcsr; 561 u32 v; 562 563 if (!addr) { 564 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 565 return; 566 } 567 568 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 569 EMAC_MACADDR_LO(reg_n)); 570 if (reg_n > 0) { 571 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 572 v |= MAC_ADDR_TYPE_DST; 573 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 574 } 575 } 576 577 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 578 unsigned char *addr, 579 unsigned int reg_n) 580 { 581 void __iomem *ioaddr = hw->pcsr; 582 583 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 584 EMAC_MACADDR_LO(reg_n)); 585 } 586 587 /* caution this function must return non 0 to work */ 588 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 589 { 590 void __iomem *ioaddr = hw->pcsr; 591 u32 v; 592 593 v = readl(ioaddr + EMAC_RX_CTL0); 594 v |= EMAC_RX_DO_CRC; 595 writel(v, ioaddr + EMAC_RX_CTL0); 596 597 return 1; 598 } 599 600 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 601 struct net_device *dev) 602 { 603 void __iomem *ioaddr = hw->pcsr; 604 u32 v; 605 int i = 1; 606 struct netdev_hw_addr *ha; 607 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 608 609 v = EMAC_FRM_FLT_CTL; 610 611 if (dev->flags & IFF_PROMISC) { 612 v = EMAC_FRM_FLT_RXALL; 613 } else if (dev->flags & IFF_ALLMULTI) { 614 v |= EMAC_FRM_FLT_MULTICAST; 615 } else if (macaddrs <= hw->unicast_filter_entries) { 616 if (!netdev_mc_empty(dev)) { 617 netdev_for_each_mc_addr(ha, dev) { 618 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 619 i++; 620 } 621 } 622 if (!netdev_uc_empty(dev)) { 623 netdev_for_each_uc_addr(ha, dev) { 624 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 625 i++; 626 } 627 } 628 } else { 629 netdev_info(dev, "Too many address, switching to promiscuous\n"); 630 v = EMAC_FRM_FLT_RXALL; 631 } 632 633 /* Disable unused address filter slots */ 634 while (i < hw->unicast_filter_entries) 635 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 636 637 writel(v, ioaddr + EMAC_RX_FRM_FLT); 638 } 639 640 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 641 unsigned int duplex, unsigned int fc, 642 unsigned int pause_time, u32 tx_cnt) 643 { 644 void __iomem *ioaddr = hw->pcsr; 645 u32 v; 646 647 v = readl(ioaddr + EMAC_RX_CTL0); 648 if (fc == FLOW_AUTO) 649 v |= EMAC_RX_FLOW_CTL_EN; 650 else 651 v &= ~EMAC_RX_FLOW_CTL_EN; 652 writel(v, ioaddr + EMAC_RX_CTL0); 653 654 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 655 if (fc == FLOW_AUTO) 656 v |= EMAC_TX_FLOW_CTL_EN; 657 else 658 v &= ~EMAC_TX_FLOW_CTL_EN; 659 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 660 } 661 662 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 663 { 664 u32 v; 665 int err; 666 667 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 668 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 669 670 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 671 * need more if no cable plugged. 100ms seems OK 672 */ 673 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 674 !(v & 0x01), 100, 100000); 675 676 if (err) { 677 dev_err(priv->device, "EMAC reset timeout\n"); 678 return -EFAULT; 679 } 680 return 0; 681 } 682 683 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 684 static int get_ephy_nodes(struct stmmac_priv *priv) 685 { 686 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 687 struct device_node *mdio_mux, *iphynode; 688 struct device_node *mdio_internal; 689 int ret; 690 691 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 692 if (!mdio_mux) { 693 dev_err(priv->device, "Cannot get mdio-mux node\n"); 694 return -ENODEV; 695 } 696 697 mdio_internal = of_find_compatible_node(mdio_mux, NULL, 698 "allwinner,sun8i-h3-mdio-internal"); 699 if (!mdio_internal) { 700 dev_err(priv->device, "Cannot get internal_mdio node\n"); 701 return -ENODEV; 702 } 703 704 /* Seek for internal PHY */ 705 for_each_child_of_node(mdio_internal, iphynode) { 706 gmac->ephy_clk = of_clk_get(iphynode, 0); 707 if (IS_ERR(gmac->ephy_clk)) 708 continue; 709 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 710 if (IS_ERR(gmac->rst_ephy)) { 711 ret = PTR_ERR(gmac->rst_ephy); 712 if (ret == -EPROBE_DEFER) 713 return ret; 714 continue; 715 } 716 dev_info(priv->device, "Found internal PHY node\n"); 717 return 0; 718 } 719 return -ENODEV; 720 } 721 722 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 723 { 724 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 725 int ret; 726 727 if (gmac->internal_phy_powered) { 728 dev_warn(priv->device, "Internal PHY already powered\n"); 729 return 0; 730 } 731 732 dev_info(priv->device, "Powering internal PHY\n"); 733 ret = clk_prepare_enable(gmac->ephy_clk); 734 if (ret) { 735 dev_err(priv->device, "Cannot enable internal PHY\n"); 736 return ret; 737 } 738 739 /* Make sure the EPHY is properly reseted, as U-Boot may leave 740 * it at deasserted state, and thus it may fail to reset EMAC. 741 */ 742 reset_control_assert(gmac->rst_ephy); 743 744 ret = reset_control_deassert(gmac->rst_ephy); 745 if (ret) { 746 dev_err(priv->device, "Cannot deassert internal phy\n"); 747 clk_disable_unprepare(gmac->ephy_clk); 748 return ret; 749 } 750 751 gmac->internal_phy_powered = true; 752 753 return 0; 754 } 755 756 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 757 { 758 if (!gmac->internal_phy_powered) 759 return 0; 760 761 clk_disable_unprepare(gmac->ephy_clk); 762 reset_control_assert(gmac->rst_ephy); 763 gmac->internal_phy_powered = false; 764 return 0; 765 } 766 767 /* MDIO multiplexing switch function 768 * This function is called by the mdio-mux layer when it thinks the mdio bus 769 * multiplexer needs to switch. 770 * 'current_child' is the current value of the mux register 771 * 'desired_child' is the value of the 'reg' property of the target child MDIO 772 * node. 773 * The first time this function is called, current_child == -1. 774 * If current_child == desired_child, then the mux is already set to the 775 * correct bus. 776 */ 777 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 778 void *data) 779 { 780 struct stmmac_priv *priv = data; 781 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 782 u32 reg, val; 783 int ret = 0; 784 bool need_power_ephy = false; 785 786 if (current_child ^ desired_child) { 787 regmap_field_read(gmac->regmap_field, ®); 788 switch (desired_child) { 789 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 790 dev_info(priv->device, "Switch mux to internal PHY"); 791 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 792 793 need_power_ephy = true; 794 break; 795 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 796 dev_info(priv->device, "Switch mux to external PHY"); 797 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 798 need_power_ephy = false; 799 break; 800 default: 801 dev_err(priv->device, "Invalid child ID %x\n", 802 desired_child); 803 return -EINVAL; 804 } 805 regmap_field_write(gmac->regmap_field, val); 806 if (need_power_ephy) { 807 ret = sun8i_dwmac_power_internal_phy(priv); 808 if (ret) 809 return ret; 810 } else { 811 sun8i_dwmac_unpower_internal_phy(gmac); 812 } 813 /* After changing syscon value, the MAC need reset or it will 814 * use the last value (and so the last PHY set). 815 */ 816 ret = sun8i_dwmac_reset(priv); 817 } 818 return ret; 819 } 820 821 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 822 { 823 int ret; 824 struct device_node *mdio_mux; 825 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 826 827 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 828 if (!mdio_mux) 829 return -ENODEV; 830 831 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 832 &gmac->mux_handle, priv, priv->mii); 833 return ret; 834 } 835 836 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 837 { 838 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 839 struct device_node *node = priv->device->of_node; 840 int ret; 841 u32 reg, val; 842 843 regmap_field_read(gmac->regmap_field, &val); 844 reg = gmac->variant->default_syscon_value; 845 if (reg != val) 846 dev_warn(priv->device, 847 "Current syscon value is not the default %x (expect %x)\n", 848 val, reg); 849 850 if (gmac->variant->soc_has_internal_phy) { 851 if (of_property_read_bool(node, "allwinner,leds-active-low")) 852 reg |= H3_EPHY_LED_POL; 853 else 854 reg &= ~H3_EPHY_LED_POL; 855 856 /* Force EPHY xtal frequency to 24MHz. */ 857 reg |= H3_EPHY_CLK_SEL; 858 859 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 860 if (ret < 0) { 861 dev_err(priv->device, "Could not parse MDIO addr\n"); 862 return ret; 863 } 864 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 865 * address. No need to mask it again. 866 */ 867 reg |= 1 << H3_EPHY_ADDR_SHIFT; 868 } 869 870 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 871 if (val % 100) { 872 dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 873 return -EINVAL; 874 } 875 val /= 100; 876 dev_dbg(priv->device, "set tx-delay to %x\n", val); 877 if (val <= gmac->variant->tx_delay_max) { 878 reg &= ~(gmac->variant->tx_delay_max << 879 SYSCON_ETXDC_SHIFT); 880 reg |= (val << SYSCON_ETXDC_SHIFT); 881 } else { 882 dev_err(priv->device, "Invalid TX clock delay: %d\n", 883 val); 884 return -EINVAL; 885 } 886 } 887 888 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 889 if (val % 100) { 890 dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 891 return -EINVAL; 892 } 893 val /= 100; 894 dev_dbg(priv->device, "set rx-delay to %x\n", val); 895 if (val <= gmac->variant->rx_delay_max) { 896 reg &= ~(gmac->variant->rx_delay_max << 897 SYSCON_ERXDC_SHIFT); 898 reg |= (val << SYSCON_ERXDC_SHIFT); 899 } else { 900 dev_err(priv->device, "Invalid RX clock delay: %d\n", 901 val); 902 return -EINVAL; 903 } 904 } 905 906 /* Clear interface mode bits */ 907 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 908 if (gmac->variant->support_rmii) 909 reg &= ~SYSCON_RMII_EN; 910 911 switch (priv->plat->interface) { 912 case PHY_INTERFACE_MODE_MII: 913 /* default */ 914 break; 915 case PHY_INTERFACE_MODE_RGMII: 916 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 917 break; 918 case PHY_INTERFACE_MODE_RMII: 919 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 920 break; 921 default: 922 dev_err(priv->device, "Unsupported interface mode: %s", 923 phy_modes(priv->plat->interface)); 924 return -EINVAL; 925 } 926 927 regmap_field_write(gmac->regmap_field, reg); 928 929 return 0; 930 } 931 932 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 933 { 934 u32 reg = gmac->variant->default_syscon_value; 935 936 regmap_field_write(gmac->regmap_field, reg); 937 } 938 939 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 940 { 941 struct sunxi_priv_data *gmac = priv; 942 943 if (gmac->variant->soc_has_internal_phy) { 944 /* sun8i_dwmac_exit could be called with mdiomux uninit */ 945 if (gmac->mux_handle) 946 mdio_mux_uninit(gmac->mux_handle); 947 if (gmac->internal_phy_powered) 948 sun8i_dwmac_unpower_internal_phy(gmac); 949 } 950 951 sun8i_dwmac_unset_syscon(gmac); 952 953 reset_control_put(gmac->rst_ephy); 954 955 clk_disable_unprepare(gmac->tx_clk); 956 957 if (gmac->regulator) 958 regulator_disable(gmac->regulator); 959 } 960 961 static const struct stmmac_ops sun8i_dwmac_ops = { 962 .core_init = sun8i_dwmac_core_init, 963 .set_mac = sun8i_dwmac_set_mac, 964 .dump_regs = sun8i_dwmac_dump_mac_regs, 965 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 966 .set_filter = sun8i_dwmac_set_filter, 967 .flow_ctrl = sun8i_dwmac_flow_ctrl, 968 .set_umac_addr = sun8i_dwmac_set_umac_addr, 969 .get_umac_addr = sun8i_dwmac_get_umac_addr, 970 }; 971 972 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 973 { 974 struct mac_device_info *mac; 975 struct stmmac_priv *priv = ppriv; 976 int ret; 977 978 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 979 if (!mac) 980 return NULL; 981 982 ret = sun8i_dwmac_set_syscon(priv); 983 if (ret) 984 return NULL; 985 986 mac->pcsr = priv->ioaddr; 987 mac->mac = &sun8i_dwmac_ops; 988 mac->dma = &sun8i_dwmac_dma_ops; 989 990 /* The loopback bit seems to be re-set when link change 991 * Simply mask it each time 992 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 993 */ 994 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 995 mac->link.speed10 = EMAC_SPEED_10; 996 mac->link.speed100 = EMAC_SPEED_100; 997 mac->link.speed1000 = EMAC_SPEED_1000; 998 mac->link.duplex = EMAC_DUPLEX_FULL; 999 mac->mii.addr = EMAC_MDIO_CMD; 1000 mac->mii.data = EMAC_MDIO_DATA; 1001 mac->mii.reg_shift = 4; 1002 mac->mii.reg_mask = GENMASK(8, 4); 1003 mac->mii.addr_shift = 12; 1004 mac->mii.addr_mask = GENMASK(16, 12); 1005 mac->mii.clk_csr_shift = 20; 1006 mac->mii.clk_csr_mask = GENMASK(22, 20); 1007 mac->unicast_filter_entries = 8; 1008 1009 /* Synopsys Id is not available */ 1010 priv->synopsys_id = 0; 1011 1012 return mac; 1013 } 1014 1015 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1016 { 1017 struct device_node *syscon_node; 1018 struct platform_device *syscon_pdev; 1019 struct regmap *regmap = NULL; 1020 1021 syscon_node = of_parse_phandle(node, "syscon", 0); 1022 if (!syscon_node) 1023 return ERR_PTR(-ENODEV); 1024 1025 syscon_pdev = of_find_device_by_node(syscon_node); 1026 if (!syscon_pdev) { 1027 /* platform device might not be probed yet */ 1028 regmap = ERR_PTR(-EPROBE_DEFER); 1029 goto out_put_node; 1030 } 1031 1032 /* If no regmap is found then the other device driver is at fault */ 1033 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1034 if (!regmap) 1035 regmap = ERR_PTR(-EINVAL); 1036 1037 platform_device_put(syscon_pdev); 1038 out_put_node: 1039 of_node_put(syscon_node); 1040 return regmap; 1041 } 1042 1043 static int sun8i_dwmac_probe(struct platform_device *pdev) 1044 { 1045 struct plat_stmmacenet_data *plat_dat; 1046 struct stmmac_resources stmmac_res; 1047 struct sunxi_priv_data *gmac; 1048 struct device *dev = &pdev->dev; 1049 int ret; 1050 struct stmmac_priv *priv; 1051 struct net_device *ndev; 1052 struct regmap *regmap; 1053 1054 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1055 if (ret) 1056 return ret; 1057 1058 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1059 if (IS_ERR(plat_dat)) 1060 return PTR_ERR(plat_dat); 1061 1062 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1063 if (!gmac) 1064 return -ENOMEM; 1065 1066 gmac->variant = of_device_get_match_data(&pdev->dev); 1067 if (!gmac->variant) { 1068 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1069 return -EINVAL; 1070 } 1071 1072 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1073 if (IS_ERR(gmac->tx_clk)) { 1074 dev_err(dev, "Could not get TX clock\n"); 1075 return PTR_ERR(gmac->tx_clk); 1076 } 1077 1078 /* Optional regulator for PHY */ 1079 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1080 if (IS_ERR(gmac->regulator)) { 1081 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1082 return -EPROBE_DEFER; 1083 dev_info(dev, "No regulator found\n"); 1084 gmac->regulator = NULL; 1085 } 1086 1087 /* The "GMAC clock control" register might be located in the 1088 * CCU address range (on the R40), or the system control address 1089 * range (on most other sun8i and later SoCs). 1090 * 1091 * The former controls most if not all clocks in the SoC. The 1092 * latter has an SoC identification register, and on some SoCs, 1093 * controls to map device specific SRAM to either the intended 1094 * peripheral, or the CPU address space. 1095 * 1096 * In either case, there should be a coordinated and restricted 1097 * method of accessing the register needed here. This is done by 1098 * having the device export a custom regmap, instead of a generic 1099 * syscon, which grants all access to all registers. 1100 * 1101 * To support old device trees, we fall back to using the syscon 1102 * interface if possible. 1103 */ 1104 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1105 if (IS_ERR(regmap)) 1106 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1107 "syscon"); 1108 if (IS_ERR(regmap)) { 1109 ret = PTR_ERR(regmap); 1110 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1111 return ret; 1112 } 1113 1114 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1115 *gmac->variant->syscon_field); 1116 if (IS_ERR(gmac->regmap_field)) { 1117 ret = PTR_ERR(gmac->regmap_field); 1118 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1119 return ret; 1120 } 1121 1122 plat_dat->interface = of_get_phy_mode(dev->of_node); 1123 1124 /* platform data specifying hardware features and callbacks. 1125 * hardware features were copied from Allwinner drivers. 1126 */ 1127 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1128 plat_dat->tx_coe = 1; 1129 plat_dat->has_sun8i = true; 1130 plat_dat->bsp_priv = gmac; 1131 plat_dat->init = sun8i_dwmac_init; 1132 plat_dat->exit = sun8i_dwmac_exit; 1133 plat_dat->setup = sun8i_dwmac_setup; 1134 1135 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1136 if (ret) 1137 return ret; 1138 1139 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1140 if (ret) 1141 goto dwmac_exit; 1142 1143 ndev = dev_get_drvdata(&pdev->dev); 1144 priv = netdev_priv(ndev); 1145 /* The mux must be registered after parent MDIO 1146 * so after stmmac_dvr_probe() 1147 */ 1148 if (gmac->variant->soc_has_internal_phy) { 1149 ret = get_ephy_nodes(priv); 1150 if (ret) 1151 goto dwmac_exit; 1152 ret = sun8i_dwmac_register_mdio_mux(priv); 1153 if (ret) { 1154 dev_err(&pdev->dev, "Failed to register mux\n"); 1155 goto dwmac_mux; 1156 } 1157 } else { 1158 ret = sun8i_dwmac_reset(priv); 1159 if (ret) 1160 goto dwmac_exit; 1161 } 1162 1163 return ret; 1164 dwmac_mux: 1165 sun8i_dwmac_unset_syscon(gmac); 1166 dwmac_exit: 1167 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); 1168 return ret; 1169 } 1170 1171 static const struct of_device_id sun8i_dwmac_match[] = { 1172 { .compatible = "allwinner,sun8i-h3-emac", 1173 .data = &emac_variant_h3 }, 1174 { .compatible = "allwinner,sun8i-v3s-emac", 1175 .data = &emac_variant_v3s }, 1176 { .compatible = "allwinner,sun8i-a83t-emac", 1177 .data = &emac_variant_a83t }, 1178 { .compatible = "allwinner,sun8i-r40-gmac", 1179 .data = &emac_variant_r40 }, 1180 { .compatible = "allwinner,sun50i-a64-emac", 1181 .data = &emac_variant_a64 }, 1182 { } 1183 }; 1184 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1185 1186 static struct platform_driver sun8i_dwmac_driver = { 1187 .probe = sun8i_dwmac_probe, 1188 .remove = stmmac_pltfr_remove, 1189 .driver = { 1190 .name = "dwmac-sun8i", 1191 .pm = &stmmac_pltfr_pm_ops, 1192 .of_match_table = sun8i_dwmac_match, 1193 }, 1194 }; 1195 module_platform_driver(sun8i_dwmac_driver); 1196 1197 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1198 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1199 MODULE_LICENSE("GPL"); 1200