1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU 4 * 5 * Copyright (C) STMicroelectronics SA 2017 6 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_net.h> 15 #include <linux/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/stmmac.h> 21 22 #include "stmmac_platform.h" 23 24 #define SYSCFG_MCU_ETH_MASK BIT(23) 25 #define SYSCFG_MP1_ETH_MASK GENMASK(23, 16) 26 #define SYSCFG_PMCCLRR_OFFSET 0x40 27 28 #define SYSCFG_PMCR_ETH_CLK_SEL BIT(16) 29 #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17) 30 31 /* CLOCK feed to PHY*/ 32 #define ETH_CK_F_25M 25000000 33 #define ETH_CK_F_50M 50000000 34 #define ETH_CK_F_125M 125000000 35 36 /* Ethernet PHY interface selection in register SYSCFG Configuration 37 *------------------------------------------ 38 * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)| 39 *------------------------------------------ 40 * MII | 0 | 0 | 0 | 1 | 41 *------------------------------------------ 42 * GMII | 0 | 0 | 0 | 0 | 43 *------------------------------------------ 44 * RGMII | 0 | 0 | 1 | n/a | 45 *------------------------------------------ 46 * RMII | 1 | 0 | 0 | n/a | 47 *------------------------------------------ 48 */ 49 #define SYSCFG_PMCR_ETH_SEL_MII BIT(20) 50 #define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21) 51 #define SYSCFG_PMCR_ETH_SEL_RMII BIT(23) 52 #define SYSCFG_PMCR_ETH_SEL_GMII 0 53 #define SYSCFG_MCU_ETH_SEL_MII 0 54 #define SYSCFG_MCU_ETH_SEL_RMII 1 55 56 /* STM32MP2 register definitions */ 57 #define SYSCFG_MP2_ETH_MASK GENMASK(31, 0) 58 59 #define SYSCFG_ETHCR_ETH_PTP_CLK_SEL BIT(2) 60 #define SYSCFG_ETHCR_ETH_CLK_SEL BIT(1) 61 #define SYSCFG_ETHCR_ETH_REF_CLK_SEL BIT(0) 62 63 #define SYSCFG_ETHCR_ETH_SEL_MII 0 64 #define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4) 65 #define SYSCFG_ETHCR_ETH_SEL_RMII BIT(6) 66 67 /* STM32MPx register definitions 68 * 69 * Below table summarizes the clock requirement and clock sources for 70 * supported phy interface modes. 71 * __________________________________________________________________________ 72 *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY| 73 *| | | 25MHz | 50MHz | | 74 * --------------------------------------------------------------------------- 75 *| MII | - | eth-ck | n/a | n/a | 76 *| | | st,ext-phyclk | | | 77 * --------------------------------------------------------------------------- 78 *| GMII | - | eth-ck | n/a | n/a | 79 *| | | st,ext-phyclk | | | 80 * --------------------------------------------------------------------------- 81 *| RGMII | - | eth-ck | n/a | eth-ck | 82 *| | | st,ext-phyclk | | st,eth-clk-sel or| 83 *| | | | | st,ext-phyclk | 84 * --------------------------------------------------------------------------- 85 *| RMII | - | eth-ck | eth-ck | n/a | 86 *| | | st,ext-phyclk | st,eth-ref-clk-sel | | 87 *| | | | or st,ext-phyclk | | 88 * --------------------------------------------------------------------------- 89 * 90 */ 91 92 struct stm32_dwmac { 93 struct clk *clk_tx; 94 struct clk *clk_rx; 95 struct clk *clk_eth_ck; 96 struct clk *clk_ethstp; 97 struct clk *syscfg_clk; 98 int ext_phyclk; 99 int enable_eth_ck; 100 int eth_clk_sel_reg; 101 int eth_ref_clk_sel_reg; 102 int irq_pwr_wakeup; 103 u32 mode_reg; /* MAC glue-logic mode register */ 104 u32 mode_mask; 105 struct regmap *regmap; 106 u32 speed; 107 const struct stm32_ops *ops; 108 struct device *dev; 109 }; 110 111 struct stm32_ops { 112 int (*set_mode)(struct plat_stmmacenet_data *plat_dat); 113 int (*suspend)(struct stm32_dwmac *dwmac); 114 void (*resume)(struct stm32_dwmac *dwmac); 115 int (*parse_data)(struct stm32_dwmac *dwmac, 116 struct device *dev); 117 bool clk_rx_enable_in_suspend; 118 bool is_mp13, is_mp2; 119 u32 syscfg_clr_off; 120 }; 121 122 static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume) 123 { 124 int ret; 125 126 ret = clk_prepare_enable(dwmac->clk_tx); 127 if (ret) 128 goto err_clk_tx; 129 130 if (!dwmac->ops->clk_rx_enable_in_suspend || !resume) { 131 ret = clk_prepare_enable(dwmac->clk_rx); 132 if (ret) 133 goto err_clk_rx; 134 } 135 136 ret = clk_prepare_enable(dwmac->syscfg_clk); 137 if (ret) 138 goto err_syscfg_clk; 139 140 if (dwmac->enable_eth_ck) { 141 ret = clk_prepare_enable(dwmac->clk_eth_ck); 142 if (ret) 143 goto err_clk_eth_ck; 144 } 145 146 return ret; 147 148 err_clk_eth_ck: 149 clk_disable_unprepare(dwmac->syscfg_clk); 150 err_syscfg_clk: 151 if (!dwmac->ops->clk_rx_enable_in_suspend || !resume) 152 clk_disable_unprepare(dwmac->clk_rx); 153 err_clk_rx: 154 clk_disable_unprepare(dwmac->clk_tx); 155 err_clk_tx: 156 return ret; 157 } 158 159 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume) 160 { 161 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 162 int ret; 163 164 if (dwmac->ops->set_mode) { 165 ret = dwmac->ops->set_mode(plat_dat); 166 if (ret) 167 return ret; 168 } 169 170 return stm32_dwmac_clk_enable(dwmac, resume); 171 } 172 173 static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) 174 { 175 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 176 177 switch (plat_dat->mac_interface) { 178 case PHY_INTERFACE_MODE_MII: 179 dwmac->enable_eth_ck = dwmac->ext_phyclk; 180 return 0; 181 case PHY_INTERFACE_MODE_GMII: 182 dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || 183 dwmac->ext_phyclk; 184 return 0; 185 case PHY_INTERFACE_MODE_RMII: 186 dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg || 187 dwmac->ext_phyclk; 188 return 0; 189 case PHY_INTERFACE_MODE_RGMII: 190 case PHY_INTERFACE_MODE_RGMII_ID: 191 case PHY_INTERFACE_MODE_RGMII_RXID: 192 case PHY_INTERFACE_MODE_RGMII_TXID: 193 dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || 194 dwmac->ext_phyclk; 195 return 0; 196 default: 197 dwmac->enable_eth_ck = false; 198 dev_err(dwmac->dev, "Mode %s not supported", 199 phy_modes(plat_dat->mac_interface)); 200 return -EINVAL; 201 } 202 } 203 204 static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) 205 { 206 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 207 const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck); 208 209 switch (plat_dat->mac_interface) { 210 case PHY_INTERFACE_MODE_MII: 211 case PHY_INTERFACE_MODE_GMII: 212 if (clk_rate == ETH_CK_F_25M) 213 return 0; 214 break; 215 case PHY_INTERFACE_MODE_RMII: 216 if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) 217 return 0; 218 break; 219 case PHY_INTERFACE_MODE_RGMII: 220 case PHY_INTERFACE_MODE_RGMII_ID: 221 case PHY_INTERFACE_MODE_RGMII_RXID: 222 case PHY_INTERFACE_MODE_RGMII_TXID: 223 if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) 224 return 0; 225 break; 226 default: 227 break; 228 } 229 230 dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", 231 phy_modes(plat_dat->mac_interface), clk_rate); 232 return -EINVAL; 233 } 234 235 static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) 236 { 237 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 238 u32 reg = dwmac->mode_reg; 239 int val = 0; 240 241 switch (plat_dat->mac_interface) { 242 case PHY_INTERFACE_MODE_MII: 243 /* 244 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. 245 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and 246 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx 247 * supports only MII, ETH_SELMII is not present. 248 */ 249 if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */ 250 val |= SYSCFG_PMCR_ETH_SEL_MII; 251 break; 252 case PHY_INTERFACE_MODE_GMII: 253 val = SYSCFG_PMCR_ETH_SEL_GMII; 254 if (dwmac->enable_eth_ck) 255 val |= SYSCFG_PMCR_ETH_CLK_SEL; 256 break; 257 case PHY_INTERFACE_MODE_RMII: 258 val = SYSCFG_PMCR_ETH_SEL_RMII; 259 if (dwmac->enable_eth_ck) 260 val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; 261 break; 262 case PHY_INTERFACE_MODE_RGMII: 263 case PHY_INTERFACE_MODE_RGMII_ID: 264 case PHY_INTERFACE_MODE_RGMII_RXID: 265 case PHY_INTERFACE_MODE_RGMII_TXID: 266 val = SYSCFG_PMCR_ETH_SEL_RGMII; 267 if (dwmac->enable_eth_ck) 268 val |= SYSCFG_PMCR_ETH_CLK_SEL; 269 break; 270 default: 271 dev_err(dwmac->dev, "Mode %s not supported", 272 phy_modes(plat_dat->mac_interface)); 273 /* Do not manage others interfaces */ 274 return -EINVAL; 275 } 276 277 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 278 279 /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ 280 val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); 281 282 /* Need to update PMCCLRR (clear register) */ 283 regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, 284 dwmac->mode_mask); 285 286 /* Update PMCSETR (set register) */ 287 return regmap_update_bits(dwmac->regmap, reg, 288 dwmac->mode_mask, val); 289 } 290 291 static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat) 292 { 293 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 294 u32 reg = dwmac->mode_reg; 295 int val = 0; 296 297 switch (plat_dat->mac_interface) { 298 case PHY_INTERFACE_MODE_MII: 299 /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */ 300 break; 301 case PHY_INTERFACE_MODE_RMII: 302 val = SYSCFG_ETHCR_ETH_SEL_RMII; 303 if (dwmac->enable_eth_ck) { 304 /* Internal clock ETH_CLK of 50MHz from RCC is used */ 305 val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL; 306 } 307 break; 308 case PHY_INTERFACE_MODE_RGMII: 309 case PHY_INTERFACE_MODE_RGMII_ID: 310 case PHY_INTERFACE_MODE_RGMII_RXID: 311 case PHY_INTERFACE_MODE_RGMII_TXID: 312 val = SYSCFG_ETHCR_ETH_SEL_RGMII; 313 fallthrough; 314 case PHY_INTERFACE_MODE_GMII: 315 if (dwmac->enable_eth_ck) { 316 /* Internal clock ETH_CLK of 125MHz from RCC is used */ 317 val |= SYSCFG_ETHCR_ETH_CLK_SEL; 318 } 319 break; 320 default: 321 dev_err(dwmac->dev, "Mode %s not supported", 322 phy_modes(plat_dat->mac_interface)); 323 /* Do not manage others interfaces */ 324 return -EINVAL; 325 } 326 327 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 328 329 /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */ 330 val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL; 331 332 /* Update ETHCR (set register) */ 333 return regmap_update_bits(dwmac->regmap, reg, 334 SYSCFG_MP2_ETH_MASK, val); 335 } 336 337 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) 338 { 339 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 340 int ret; 341 342 ret = stm32mp1_select_ethck_external(plat_dat); 343 if (ret) 344 return ret; 345 346 ret = stm32mp1_validate_ethck_rate(plat_dat); 347 if (ret) 348 return ret; 349 350 if (!dwmac->ops->is_mp2) 351 return stm32mp1_configure_pmcr(plat_dat); 352 else 353 return stm32mp2_configure_syscfg(plat_dat); 354 } 355 356 static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) 357 { 358 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 359 u32 reg = dwmac->mode_reg; 360 int val; 361 362 switch (plat_dat->mac_interface) { 363 case PHY_INTERFACE_MODE_MII: 364 val = SYSCFG_MCU_ETH_SEL_MII; 365 break; 366 case PHY_INTERFACE_MODE_RMII: 367 val = SYSCFG_MCU_ETH_SEL_RMII; 368 break; 369 default: 370 dev_err(dwmac->dev, "Mode %s not supported", 371 phy_modes(plat_dat->mac_interface)); 372 /* Do not manage others interfaces */ 373 return -EINVAL; 374 } 375 376 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 377 378 return regmap_update_bits(dwmac->regmap, reg, 379 SYSCFG_MCU_ETH_MASK, val << 23); 380 } 381 382 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend) 383 { 384 clk_disable_unprepare(dwmac->clk_tx); 385 if (!dwmac->ops->clk_rx_enable_in_suspend || !suspend) 386 clk_disable_unprepare(dwmac->clk_rx); 387 388 clk_disable_unprepare(dwmac->syscfg_clk); 389 if (dwmac->enable_eth_ck) 390 clk_disable_unprepare(dwmac->clk_eth_ck); 391 } 392 393 static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, 394 struct device *dev) 395 { 396 struct device_node *np = dev->of_node; 397 int err; 398 399 /* Get TX/RX clocks */ 400 dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx"); 401 if (IS_ERR(dwmac->clk_tx)) { 402 dev_err(dev, "No ETH Tx clock provided...\n"); 403 return PTR_ERR(dwmac->clk_tx); 404 } 405 406 dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx"); 407 if (IS_ERR(dwmac->clk_rx)) { 408 dev_err(dev, "No ETH Rx clock provided...\n"); 409 return PTR_ERR(dwmac->clk_rx); 410 } 411 412 if (dwmac->ops->parse_data) { 413 err = dwmac->ops->parse_data(dwmac, dev); 414 if (err) 415 return err; 416 } 417 418 /* Get mode register */ 419 dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 420 if (IS_ERR(dwmac->regmap)) 421 return PTR_ERR(dwmac->regmap); 422 423 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); 424 if (err) { 425 dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); 426 return err; 427 } 428 429 if (dwmac->ops->is_mp2) 430 return 0; 431 432 dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; 433 err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); 434 if (err) { 435 if (dwmac->ops->is_mp13) 436 dev_err(dev, "Sysconfig register mask must be set (%d)\n", err); 437 else 438 dev_dbg(dev, "Warning sysconfig register mask not set\n"); 439 } 440 441 return err; 442 } 443 444 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, 445 struct device *dev) 446 { 447 struct platform_device *pdev = to_platform_device(dev); 448 struct device_node *np = dev->of_node; 449 int err = 0; 450 451 /* Ethernet PHY have no crystal */ 452 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 453 454 /* Gigabit Ethernet 125MHz clock selection. */ 455 dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel"); 456 457 /* Ethernet 50MHz RMII clock selection */ 458 dwmac->eth_ref_clk_sel_reg = 459 of_property_read_bool(np, "st,eth-ref-clk-sel"); 460 461 /* Get ETH_CLK clocks */ 462 dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck"); 463 if (IS_ERR(dwmac->clk_eth_ck)) { 464 dev_info(dev, "No phy clock provided...\n"); 465 dwmac->clk_eth_ck = NULL; 466 } 467 468 /* Clock used for low power mode */ 469 dwmac->clk_ethstp = devm_clk_get(dev, "ethstp"); 470 if (IS_ERR(dwmac->clk_ethstp)) { 471 dev_err(dev, 472 "No ETH peripheral clock provided for CStop mode ...\n"); 473 return PTR_ERR(dwmac->clk_ethstp); 474 } 475 476 /* Optional Clock for sysconfig */ 477 dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk"); 478 if (IS_ERR(dwmac->syscfg_clk)) 479 dwmac->syscfg_clk = NULL; 480 481 /* Get IRQ information early to have an ability to ask for deferred 482 * probe if needed before we went too far with resource allocation. 483 */ 484 dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev, 485 "stm32_pwr_wakeup"); 486 if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER) 487 return -EPROBE_DEFER; 488 489 if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) { 490 err = device_init_wakeup(&pdev->dev, true); 491 if (err) { 492 dev_err(&pdev->dev, "Failed to init wake up irq\n"); 493 return err; 494 } 495 err = dev_pm_set_dedicated_wake_irq(&pdev->dev, 496 dwmac->irq_pwr_wakeup); 497 if (err) { 498 dev_err(&pdev->dev, "Failed to set wake up irq\n"); 499 device_init_wakeup(&pdev->dev, false); 500 } 501 device_set_wakeup_enable(&pdev->dev, false); 502 } 503 return err; 504 } 505 506 static int stm32_dwmac_probe(struct platform_device *pdev) 507 { 508 struct plat_stmmacenet_data *plat_dat; 509 struct stmmac_resources stmmac_res; 510 struct stm32_dwmac *dwmac; 511 const struct stm32_ops *data; 512 int ret; 513 514 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 515 if (ret) 516 return ret; 517 518 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 519 if (IS_ERR(plat_dat)) 520 return PTR_ERR(plat_dat); 521 522 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 523 if (!dwmac) 524 return -ENOMEM; 525 526 data = of_device_get_match_data(&pdev->dev); 527 if (!data) { 528 dev_err(&pdev->dev, "no of match data provided\n"); 529 return -EINVAL; 530 } 531 532 dwmac->ops = data; 533 dwmac->dev = &pdev->dev; 534 535 ret = stm32_dwmac_parse_data(dwmac, &pdev->dev); 536 if (ret) { 537 dev_err(&pdev->dev, "Unable to parse OF data\n"); 538 return ret; 539 } 540 541 plat_dat->bsp_priv = dwmac; 542 543 ret = stm32_dwmac_init(plat_dat, false); 544 if (ret) 545 return ret; 546 547 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 548 if (ret) 549 goto err_clk_disable; 550 551 return 0; 552 553 err_clk_disable: 554 stm32_dwmac_clk_disable(dwmac, false); 555 556 return ret; 557 } 558 559 static void stm32_dwmac_remove(struct platform_device *pdev) 560 { 561 struct net_device *ndev = platform_get_drvdata(pdev); 562 struct stmmac_priv *priv = netdev_priv(ndev); 563 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; 564 565 stmmac_dvr_remove(&pdev->dev); 566 567 stm32_dwmac_clk_disable(dwmac, false); 568 569 if (dwmac->irq_pwr_wakeup >= 0) { 570 dev_pm_clear_wake_irq(&pdev->dev); 571 device_init_wakeup(&pdev->dev, false); 572 } 573 } 574 575 static int stm32mp1_suspend(struct stm32_dwmac *dwmac) 576 { 577 return clk_prepare_enable(dwmac->clk_ethstp); 578 } 579 580 static void stm32mp1_resume(struct stm32_dwmac *dwmac) 581 { 582 clk_disable_unprepare(dwmac->clk_ethstp); 583 } 584 585 #ifdef CONFIG_PM_SLEEP 586 static int stm32_dwmac_suspend(struct device *dev) 587 { 588 struct net_device *ndev = dev_get_drvdata(dev); 589 struct stmmac_priv *priv = netdev_priv(ndev); 590 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; 591 592 int ret; 593 594 ret = stmmac_suspend(dev); 595 if (ret) 596 return ret; 597 598 stm32_dwmac_clk_disable(dwmac, true); 599 600 if (dwmac->ops->suspend) 601 ret = dwmac->ops->suspend(dwmac); 602 603 return ret; 604 } 605 606 static int stm32_dwmac_resume(struct device *dev) 607 { 608 struct net_device *ndev = dev_get_drvdata(dev); 609 struct stmmac_priv *priv = netdev_priv(ndev); 610 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; 611 int ret; 612 613 if (dwmac->ops->resume) 614 dwmac->ops->resume(dwmac); 615 616 ret = stm32_dwmac_init(priv->plat, true); 617 if (ret) 618 return ret; 619 620 ret = stmmac_resume(dev); 621 622 return ret; 623 } 624 #endif /* CONFIG_PM_SLEEP */ 625 626 static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, 627 stm32_dwmac_suspend, stm32_dwmac_resume); 628 629 static struct stm32_ops stm32mcu_dwmac_data = { 630 .set_mode = stm32mcu_set_mode 631 }; 632 633 static struct stm32_ops stm32mp1_dwmac_data = { 634 .set_mode = stm32mp1_set_mode, 635 .suspend = stm32mp1_suspend, 636 .resume = stm32mp1_resume, 637 .parse_data = stm32mp1_parse_data, 638 .syscfg_clr_off = 0x44, 639 .is_mp13 = false, 640 .clk_rx_enable_in_suspend = true 641 }; 642 643 static struct stm32_ops stm32mp13_dwmac_data = { 644 .set_mode = stm32mp1_set_mode, 645 .suspend = stm32mp1_suspend, 646 .resume = stm32mp1_resume, 647 .parse_data = stm32mp1_parse_data, 648 .syscfg_clr_off = 0x08, 649 .is_mp13 = true, 650 .clk_rx_enable_in_suspend = true 651 }; 652 653 static struct stm32_ops stm32mp25_dwmac_data = { 654 .set_mode = stm32mp1_set_mode, 655 .suspend = stm32mp1_suspend, 656 .resume = stm32mp1_resume, 657 .parse_data = stm32mp1_parse_data, 658 .is_mp2 = true, 659 .clk_rx_enable_in_suspend = true 660 }; 661 662 static const struct of_device_id stm32_dwmac_match[] = { 663 { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, 664 { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, 665 { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, 666 { .compatible = "st,stm32mp25-dwmac", .data = &stm32mp25_dwmac_data}, 667 { } 668 }; 669 MODULE_DEVICE_TABLE(of, stm32_dwmac_match); 670 671 static struct platform_driver stm32_dwmac_driver = { 672 .probe = stm32_dwmac_probe, 673 .remove_new = stm32_dwmac_remove, 674 .driver = { 675 .name = "stm32-dwmac", 676 .pm = &stm32_dwmac_pm_ops, 677 .of_match_table = stm32_dwmac_match, 678 }, 679 }; 680 module_platform_driver(stm32_dwmac_driver); 681 682 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>"); 683 MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>"); 684 MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer"); 685 MODULE_LICENSE("GPL v2"); 686