1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU 4 * 5 * Copyright (C) STMicroelectronics SA 2017 6 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_net.h> 15 #include <linux/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/stmmac.h> 21 22 #include "stmmac_platform.h" 23 24 #define SYSCFG_MCU_ETH_MASK BIT(23) 25 #define SYSCFG_MP1_ETH_MASK GENMASK(23, 16) 26 #define SYSCFG_PMCCLRR_OFFSET 0x40 27 28 #define SYSCFG_PMCR_ETH_CLK_SEL BIT(16) 29 #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17) 30 31 /* CLOCK feed to PHY*/ 32 #define ETH_CK_F_25M 25000000 33 #define ETH_CK_F_50M 50000000 34 #define ETH_CK_F_125M 125000000 35 36 /* Ethernet PHY interface selection in register SYSCFG Configuration 37 *------------------------------------------ 38 * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)| 39 *------------------------------------------ 40 * MII | 0 | 0 | 0 | 1 | 41 *------------------------------------------ 42 * GMII | 0 | 0 | 0 | 0 | 43 *------------------------------------------ 44 * RGMII | 0 | 0 | 1 | n/a | 45 *------------------------------------------ 46 * RMII | 1 | 0 | 0 | n/a | 47 *------------------------------------------ 48 */ 49 #define SYSCFG_PMCR_ETH_SEL_MII BIT(20) 50 #define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21) 51 #define SYSCFG_PMCR_ETH_SEL_RMII BIT(23) 52 #define SYSCFG_PMCR_ETH_SEL_GMII 0 53 #define SYSCFG_MCU_ETH_SEL_MII 0 54 #define SYSCFG_MCU_ETH_SEL_RMII 1 55 56 /* STM32MP2 register definitions */ 57 #define SYSCFG_MP2_ETH_MASK GENMASK(31, 0) 58 59 #define SYSCFG_ETHCR_ETH_PTP_CLK_SEL BIT(2) 60 #define SYSCFG_ETHCR_ETH_CLK_SEL BIT(1) 61 #define SYSCFG_ETHCR_ETH_REF_CLK_SEL BIT(0) 62 63 #define SYSCFG_ETHCR_ETH_SEL_MII 0 64 #define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4) 65 #define SYSCFG_ETHCR_ETH_SEL_RMII BIT(6) 66 67 /* STM32MPx register definitions 68 * 69 * Below table summarizes the clock requirement and clock sources for 70 * supported phy interface modes. 71 * __________________________________________________________________________ 72 *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY| 73 *| | | 25MHz | 50MHz | | 74 * --------------------------------------------------------------------------- 75 *| MII | - | eth-ck | n/a | n/a | 76 *| | | st,ext-phyclk | | | 77 * --------------------------------------------------------------------------- 78 *| GMII | - | eth-ck | n/a | n/a | 79 *| | | st,ext-phyclk | | | 80 * --------------------------------------------------------------------------- 81 *| RGMII | - | eth-ck | n/a | eth-ck | 82 *| | | st,ext-phyclk | | st,eth-clk-sel or| 83 *| | | | | st,ext-phyclk | 84 * --------------------------------------------------------------------------- 85 *| RMII | - | eth-ck | eth-ck | n/a | 86 *| | | st,ext-phyclk | st,eth-ref-clk-sel | | 87 *| | | | or st,ext-phyclk | | 88 * --------------------------------------------------------------------------- 89 * 90 */ 91 92 struct stm32_dwmac { 93 struct clk *clk_tx; 94 struct clk *clk_rx; 95 struct clk *clk_eth_ck; 96 struct clk *clk_ethstp; 97 struct clk *syscfg_clk; 98 int ext_phyclk; 99 int enable_eth_ck; 100 int eth_clk_sel_reg; 101 int eth_ref_clk_sel_reg; 102 int irq_pwr_wakeup; 103 u32 mode_reg; /* MAC glue-logic mode register */ 104 u32 mode_mask; 105 struct regmap *regmap; 106 u32 speed; 107 const struct stm32_ops *ops; 108 struct device *dev; 109 }; 110 111 struct stm32_ops { 112 int (*set_mode)(struct plat_stmmacenet_data *plat_dat); 113 int (*suspend)(struct stm32_dwmac *dwmac); 114 void (*resume)(struct stm32_dwmac *dwmac); 115 int (*parse_data)(struct stm32_dwmac *dwmac, 116 struct device *dev); 117 bool clk_rx_enable_in_suspend; 118 bool is_mp13, is_mp2; 119 u32 syscfg_clr_off; 120 }; 121 122 static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac) 123 { 124 int ret; 125 126 ret = clk_prepare_enable(dwmac->clk_tx); 127 if (ret) 128 goto err_clk_tx; 129 130 ret = clk_prepare_enable(dwmac->clk_rx); 131 if (ret) 132 goto err_clk_rx; 133 134 ret = clk_prepare_enable(dwmac->syscfg_clk); 135 if (ret) 136 goto err_syscfg_clk; 137 138 if (dwmac->enable_eth_ck) { 139 ret = clk_prepare_enable(dwmac->clk_eth_ck); 140 if (ret) 141 goto err_clk_eth_ck; 142 } 143 144 return ret; 145 146 err_clk_eth_ck: 147 clk_disable_unprepare(dwmac->syscfg_clk); 148 err_syscfg_clk: 149 clk_disable_unprepare(dwmac->clk_rx); 150 err_clk_rx: 151 clk_disable_unprepare(dwmac->clk_tx); 152 err_clk_tx: 153 return ret; 154 } 155 156 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) 157 { 158 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 159 int ret; 160 161 if (dwmac->ops->set_mode) { 162 ret = dwmac->ops->set_mode(plat_dat); 163 if (ret) 164 return ret; 165 } 166 167 return stm32_dwmac_clk_enable(dwmac); 168 } 169 170 static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) 171 { 172 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 173 174 switch (plat_dat->mac_interface) { 175 case PHY_INTERFACE_MODE_MII: 176 dwmac->enable_eth_ck = dwmac->ext_phyclk; 177 return 0; 178 case PHY_INTERFACE_MODE_GMII: 179 dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || 180 dwmac->ext_phyclk; 181 return 0; 182 case PHY_INTERFACE_MODE_RMII: 183 dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg || 184 dwmac->ext_phyclk; 185 return 0; 186 case PHY_INTERFACE_MODE_RGMII: 187 case PHY_INTERFACE_MODE_RGMII_ID: 188 case PHY_INTERFACE_MODE_RGMII_RXID: 189 case PHY_INTERFACE_MODE_RGMII_TXID: 190 dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || 191 dwmac->ext_phyclk; 192 return 0; 193 default: 194 dwmac->enable_eth_ck = false; 195 dev_err(dwmac->dev, "Mode %s not supported", 196 phy_modes(plat_dat->mac_interface)); 197 return -EINVAL; 198 } 199 } 200 201 static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) 202 { 203 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 204 const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck); 205 206 if (!dwmac->enable_eth_ck) 207 return 0; 208 209 switch (plat_dat->mac_interface) { 210 case PHY_INTERFACE_MODE_MII: 211 case PHY_INTERFACE_MODE_GMII: 212 if (clk_rate == ETH_CK_F_25M) 213 return 0; 214 break; 215 case PHY_INTERFACE_MODE_RMII: 216 if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) 217 return 0; 218 break; 219 case PHY_INTERFACE_MODE_RGMII: 220 case PHY_INTERFACE_MODE_RGMII_ID: 221 case PHY_INTERFACE_MODE_RGMII_RXID: 222 case PHY_INTERFACE_MODE_RGMII_TXID: 223 if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) 224 return 0; 225 break; 226 default: 227 break; 228 } 229 230 dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", 231 phy_modes(plat_dat->mac_interface), clk_rate); 232 return -EINVAL; 233 } 234 235 static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) 236 { 237 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 238 u32 reg = dwmac->mode_reg; 239 int val = 0; 240 241 switch (plat_dat->mac_interface) { 242 case PHY_INTERFACE_MODE_MII: 243 /* 244 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. 245 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and 246 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx 247 * supports only MII, ETH_SELMII is not present. 248 */ 249 if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */ 250 val |= SYSCFG_PMCR_ETH_SEL_MII; 251 break; 252 case PHY_INTERFACE_MODE_GMII: 253 val = SYSCFG_PMCR_ETH_SEL_GMII; 254 if (dwmac->enable_eth_ck) 255 val |= SYSCFG_PMCR_ETH_CLK_SEL; 256 break; 257 case PHY_INTERFACE_MODE_RMII: 258 val = SYSCFG_PMCR_ETH_SEL_RMII; 259 if (dwmac->enable_eth_ck) 260 val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; 261 break; 262 case PHY_INTERFACE_MODE_RGMII: 263 case PHY_INTERFACE_MODE_RGMII_ID: 264 case PHY_INTERFACE_MODE_RGMII_RXID: 265 case PHY_INTERFACE_MODE_RGMII_TXID: 266 val = SYSCFG_PMCR_ETH_SEL_RGMII; 267 if (dwmac->enable_eth_ck) 268 val |= SYSCFG_PMCR_ETH_CLK_SEL; 269 break; 270 default: 271 dev_err(dwmac->dev, "Mode %s not supported", 272 phy_modes(plat_dat->mac_interface)); 273 /* Do not manage others interfaces */ 274 return -EINVAL; 275 } 276 277 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 278 279 /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ 280 val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); 281 282 /* Need to update PMCCLRR (clear register) */ 283 regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, 284 dwmac->mode_mask); 285 286 /* Update PMCSETR (set register) */ 287 return regmap_update_bits(dwmac->regmap, reg, 288 dwmac->mode_mask, val); 289 } 290 291 static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat) 292 { 293 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 294 u32 reg = dwmac->mode_reg; 295 int val = 0; 296 297 switch (plat_dat->mac_interface) { 298 case PHY_INTERFACE_MODE_MII: 299 /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */ 300 break; 301 case PHY_INTERFACE_MODE_RMII: 302 val = SYSCFG_ETHCR_ETH_SEL_RMII; 303 if (dwmac->enable_eth_ck) { 304 /* Internal clock ETH_CLK of 50MHz from RCC is used */ 305 val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL; 306 } 307 break; 308 case PHY_INTERFACE_MODE_RGMII: 309 case PHY_INTERFACE_MODE_RGMII_ID: 310 case PHY_INTERFACE_MODE_RGMII_RXID: 311 case PHY_INTERFACE_MODE_RGMII_TXID: 312 val = SYSCFG_ETHCR_ETH_SEL_RGMII; 313 fallthrough; 314 case PHY_INTERFACE_MODE_GMII: 315 if (dwmac->enable_eth_ck) { 316 /* Internal clock ETH_CLK of 125MHz from RCC is used */ 317 val |= SYSCFG_ETHCR_ETH_CLK_SEL; 318 } 319 break; 320 default: 321 dev_err(dwmac->dev, "Mode %s not supported", 322 phy_modes(plat_dat->mac_interface)); 323 /* Do not manage others interfaces */ 324 return -EINVAL; 325 } 326 327 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 328 329 /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */ 330 val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL; 331 332 /* Update ETHCR (set register) */ 333 return regmap_update_bits(dwmac->regmap, reg, 334 SYSCFG_MP2_ETH_MASK, val); 335 } 336 337 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) 338 { 339 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 340 int ret; 341 342 ret = stm32mp1_select_ethck_external(plat_dat); 343 if (ret) 344 return ret; 345 346 ret = stm32mp1_validate_ethck_rate(plat_dat); 347 if (ret) 348 return ret; 349 350 if (!dwmac->ops->is_mp2) 351 return stm32mp1_configure_pmcr(plat_dat); 352 else 353 return stm32mp2_configure_syscfg(plat_dat); 354 } 355 356 static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) 357 { 358 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 359 u32 reg = dwmac->mode_reg; 360 int val; 361 362 switch (plat_dat->mac_interface) { 363 case PHY_INTERFACE_MODE_MII: 364 val = SYSCFG_MCU_ETH_SEL_MII; 365 break; 366 case PHY_INTERFACE_MODE_RMII: 367 val = SYSCFG_MCU_ETH_SEL_RMII; 368 break; 369 default: 370 dev_err(dwmac->dev, "Mode %s not supported", 371 phy_modes(plat_dat->mac_interface)); 372 /* Do not manage others interfaces */ 373 return -EINVAL; 374 } 375 376 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 377 378 return regmap_update_bits(dwmac->regmap, reg, 379 SYSCFG_MCU_ETH_MASK, val << 23); 380 } 381 382 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac) 383 { 384 clk_disable_unprepare(dwmac->clk_tx); 385 clk_disable_unprepare(dwmac->clk_rx); 386 clk_disable_unprepare(dwmac->syscfg_clk); 387 if (dwmac->enable_eth_ck) 388 clk_disable_unprepare(dwmac->clk_eth_ck); 389 } 390 391 static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, 392 struct device *dev) 393 { 394 struct device_node *np = dev->of_node; 395 int err; 396 397 /* Get TX/RX clocks */ 398 dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx"); 399 if (IS_ERR(dwmac->clk_tx)) { 400 dev_err(dev, "No ETH Tx clock provided...\n"); 401 return PTR_ERR(dwmac->clk_tx); 402 } 403 404 dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx"); 405 if (IS_ERR(dwmac->clk_rx)) { 406 dev_err(dev, "No ETH Rx clock provided...\n"); 407 return PTR_ERR(dwmac->clk_rx); 408 } 409 410 if (dwmac->ops->parse_data) { 411 err = dwmac->ops->parse_data(dwmac, dev); 412 if (err) 413 return err; 414 } 415 416 /* Get mode register */ 417 dwmac->regmap = syscon_regmap_lookup_by_phandle_args(np, "st,syscon", 418 1, &dwmac->mode_reg); 419 if (IS_ERR(dwmac->regmap)) 420 return PTR_ERR(dwmac->regmap); 421 422 if (dwmac->ops->is_mp2) 423 return 0; 424 425 dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; 426 err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); 427 if (err) { 428 if (dwmac->ops->is_mp13) { 429 dev_err(dev, "Sysconfig register mask must be set (%d)\n", err); 430 } else { 431 dev_dbg(dev, "Warning sysconfig register mask not set\n"); 432 err = 0; 433 } 434 } 435 436 return err; 437 } 438 439 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, 440 struct device *dev) 441 { 442 struct platform_device *pdev = to_platform_device(dev); 443 struct device_node *np = dev->of_node; 444 int err = 0; 445 446 /* Ethernet PHY have no crystal */ 447 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 448 449 /* Gigabit Ethernet 125MHz clock selection. */ 450 dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel"); 451 452 /* Ethernet 50MHz RMII clock selection */ 453 dwmac->eth_ref_clk_sel_reg = 454 of_property_read_bool(np, "st,eth-ref-clk-sel"); 455 456 /* Get ETH_CLK clocks */ 457 dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck"); 458 if (IS_ERR(dwmac->clk_eth_ck)) { 459 dev_info(dev, "No phy clock provided...\n"); 460 dwmac->clk_eth_ck = NULL; 461 } 462 463 /* Clock used for low power mode */ 464 dwmac->clk_ethstp = devm_clk_get(dev, "ethstp"); 465 if (IS_ERR(dwmac->clk_ethstp)) { 466 dev_err(dev, 467 "No ETH peripheral clock provided for CStop mode ...\n"); 468 return PTR_ERR(dwmac->clk_ethstp); 469 } 470 471 /* Optional Clock for sysconfig */ 472 dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk"); 473 if (IS_ERR(dwmac->syscfg_clk)) 474 dwmac->syscfg_clk = NULL; 475 476 /* Get IRQ information early to have an ability to ask for deferred 477 * probe if needed before we went too far with resource allocation. 478 */ 479 dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev, 480 "stm32_pwr_wakeup"); 481 if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER) 482 return -EPROBE_DEFER; 483 484 if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) { 485 err = device_init_wakeup(&pdev->dev, true); 486 if (err) { 487 dev_err(&pdev->dev, "Failed to init wake up irq\n"); 488 return err; 489 } 490 err = dev_pm_set_dedicated_wake_irq(&pdev->dev, 491 dwmac->irq_pwr_wakeup); 492 if (err) { 493 dev_err(&pdev->dev, "Failed to set wake up irq\n"); 494 device_init_wakeup(&pdev->dev, false); 495 } 496 device_set_wakeup_enable(&pdev->dev, false); 497 } 498 return err; 499 } 500 501 static int stm32_dwmac_suspend(struct device *dev, void *bsp_priv) 502 { 503 struct stm32_dwmac *dwmac = bsp_priv; 504 505 stm32_dwmac_clk_disable(dwmac); 506 507 return dwmac->ops->suspend ? dwmac->ops->suspend(dwmac) : 0; 508 } 509 510 static int stm32_dwmac_resume(struct device *dev, void *bsp_priv) 511 { 512 struct stmmac_priv *priv = netdev_priv(dev_get_drvdata(dev)); 513 struct stm32_dwmac *dwmac = bsp_priv; 514 515 if (dwmac->ops->resume) 516 dwmac->ops->resume(dwmac); 517 518 return stm32_dwmac_init(priv->plat); 519 } 520 521 static int stm32_dwmac_probe(struct platform_device *pdev) 522 { 523 struct plat_stmmacenet_data *plat_dat; 524 struct stmmac_resources stmmac_res; 525 struct stm32_dwmac *dwmac; 526 const struct stm32_ops *data; 527 int ret; 528 529 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 530 if (ret) 531 return ret; 532 533 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 534 if (IS_ERR(plat_dat)) 535 return PTR_ERR(plat_dat); 536 537 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 538 if (!dwmac) 539 return -ENOMEM; 540 541 data = of_device_get_match_data(&pdev->dev); 542 if (!data) { 543 dev_err(&pdev->dev, "no of match data provided\n"); 544 return -EINVAL; 545 } 546 547 dwmac->ops = data; 548 dwmac->dev = &pdev->dev; 549 550 ret = stm32_dwmac_parse_data(dwmac, &pdev->dev); 551 if (ret) { 552 dev_err(&pdev->dev, "Unable to parse OF data\n"); 553 return ret; 554 } 555 556 plat_dat->flags |= STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP; 557 plat_dat->bsp_priv = dwmac; 558 plat_dat->suspend = stm32_dwmac_suspend; 559 plat_dat->resume = stm32_dwmac_resume; 560 561 ret = stm32_dwmac_init(plat_dat); 562 if (ret) 563 return ret; 564 565 /* If this platform requires the clock to be running in suspend, 566 * prepare and enable the receive clock an additional time to keep 567 * it running. 568 */ 569 if (dwmac->ops->clk_rx_enable_in_suspend) { 570 ret = clk_prepare_enable(dwmac->clk_rx); 571 if (ret) 572 goto err_clk_disable; 573 } 574 575 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 576 if (ret) 577 goto err_clk_disable_suspend; 578 579 return 0; 580 581 err_clk_disable_suspend: 582 if (dwmac->ops->clk_rx_enable_in_suspend) 583 clk_disable_unprepare(dwmac->clk_rx); 584 585 err_clk_disable: 586 stm32_dwmac_clk_disable(dwmac); 587 588 return ret; 589 } 590 591 static void stm32_dwmac_remove(struct platform_device *pdev) 592 { 593 struct net_device *ndev = platform_get_drvdata(pdev); 594 struct stmmac_priv *priv = netdev_priv(ndev); 595 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; 596 597 stmmac_dvr_remove(&pdev->dev); 598 599 /* If this platform requires the clock to be running in suspend, 600 * we need to disable and unprepare the receive clock an additional 601 * time to balance the extra clk_prepare_enable() in the probe 602 * function. 603 */ 604 if (dwmac->ops->clk_rx_enable_in_suspend) 605 clk_disable_unprepare(dwmac->clk_rx); 606 607 stm32_dwmac_clk_disable(dwmac); 608 609 if (dwmac->irq_pwr_wakeup >= 0) { 610 dev_pm_clear_wake_irq(&pdev->dev); 611 device_init_wakeup(&pdev->dev, false); 612 } 613 } 614 615 static int stm32mp1_suspend(struct stm32_dwmac *dwmac) 616 { 617 return clk_prepare_enable(dwmac->clk_ethstp); 618 } 619 620 static void stm32mp1_resume(struct stm32_dwmac *dwmac) 621 { 622 clk_disable_unprepare(dwmac->clk_ethstp); 623 } 624 625 static struct stm32_ops stm32mcu_dwmac_data = { 626 .set_mode = stm32mcu_set_mode 627 }; 628 629 static struct stm32_ops stm32mp1_dwmac_data = { 630 .set_mode = stm32mp1_set_mode, 631 .suspend = stm32mp1_suspend, 632 .resume = stm32mp1_resume, 633 .parse_data = stm32mp1_parse_data, 634 .syscfg_clr_off = 0x44, 635 .is_mp13 = false, 636 .clk_rx_enable_in_suspend = true 637 }; 638 639 static struct stm32_ops stm32mp13_dwmac_data = { 640 .set_mode = stm32mp1_set_mode, 641 .suspend = stm32mp1_suspend, 642 .resume = stm32mp1_resume, 643 .parse_data = stm32mp1_parse_data, 644 .syscfg_clr_off = 0x08, 645 .is_mp13 = true, 646 .clk_rx_enable_in_suspend = true 647 }; 648 649 static struct stm32_ops stm32mp25_dwmac_data = { 650 .set_mode = stm32mp1_set_mode, 651 .suspend = stm32mp1_suspend, 652 .resume = stm32mp1_resume, 653 .parse_data = stm32mp1_parse_data, 654 .is_mp2 = true, 655 .clk_rx_enable_in_suspend = true 656 }; 657 658 static const struct of_device_id stm32_dwmac_match[] = { 659 { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, 660 { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, 661 { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, 662 { .compatible = "st,stm32mp25-dwmac", .data = &stm32mp25_dwmac_data}, 663 { } 664 }; 665 MODULE_DEVICE_TABLE(of, stm32_dwmac_match); 666 667 static struct platform_driver stm32_dwmac_driver = { 668 .probe = stm32_dwmac_probe, 669 .remove = stm32_dwmac_remove, 670 .driver = { 671 .name = "stm32-dwmac", 672 .pm = &stmmac_simple_pm_ops, 673 .of_match_table = stm32_dwmac_match, 674 }, 675 }; 676 module_platform_driver(stm32_dwmac_driver); 677 678 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>"); 679 MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>"); 680 MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer"); 681 MODULE_LICENSE("GPL v2"); 682