1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 4 * 5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 7 * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/platform_device.h> 13 #include <linux/stmmac.h> 14 #include <linux/phy.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/regmap.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_net.h> 22 23 #include "stmmac_platform.h" 24 25 #define DWMAC_125MHZ 125000000 26 #define DWMAC_50MHZ 50000000 27 #define DWMAC_25MHZ 25000000 28 #define DWMAC_2_5MHZ 2500000 29 30 #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 31 iface == PHY_INTERFACE_MODE_RGMII_ID || \ 32 iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 33 iface == PHY_INTERFACE_MODE_RGMII_TXID) 34 35 #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 36 iface == PHY_INTERFACE_MODE_GMII) 37 38 /* STiH4xx register definitions (STiH407/STiH410 families) 39 * 40 * Below table summarizes the clock requirement and clock sources for 41 * supported phy interface modes with link speeds. 42 * ________________________________________________ 43 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 44 * ------------------------------------------------ 45 *| MII | n/a | 25Mhz | 46 *| | | txclk | 47 * ------------------------------------------------ 48 *| GMII | 125Mhz | 25Mhz | 49 *| | clk-125/txclk | txclk | 50 * ------------------------------------------------ 51 *| RGMII | 125Mhz | 25Mhz | 52 *| | clk-125/txclk | clkgen | 53 *| | clkgen | | 54 * ------------------------------------------------ 55 *| RMII | n/a | 25Mhz | 56 *| | |clkgen/phyclk-in | 57 * ------------------------------------------------ 58 * 59 * Register Configuration 60 *------------------------------- 61 * src |BIT(8)| BIT(7)| BIT(6)| 62 *------------------------------- 63 * txclk | 0 | n/a | 1 | 64 *------------------------------- 65 * ck_125| 0 | n/a | 0 | 66 *------------------------------- 67 * phyclk| 1 | 0 | n/a | 68 *------------------------------- 69 * clkgen| 1 | 1 | n/a | 70 *------------------------------- 71 */ 72 73 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 74 #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 75 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 76 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 77 78 #define ENMII_MASK GENMASK(5, 5) 79 #define ENMII BIT(5) 80 #define EN_MASK GENMASK(1, 1) 81 #define EN BIT(1) 82 83 /* 84 * 3 bits [4:2] 85 * 000-GMII/MII 86 * 001-RGMII 87 * 010-SGMII 88 * 100-RMII 89 */ 90 #define MII_PHY_SEL_MASK GENMASK(4, 2) 91 #define ETH_PHY_SEL_RMII BIT(4) 92 #define ETH_PHY_SEL_SGMII BIT(3) 93 #define ETH_PHY_SEL_RGMII BIT(2) 94 #define ETH_PHY_SEL_GMII 0x0 95 #define ETH_PHY_SEL_MII 0x0 96 97 struct sti_dwmac { 98 phy_interface_t interface; /* MII interface */ 99 bool ext_phyclk; /* Clock from external PHY */ 100 u32 tx_retime_src; /* TXCLK Retiming*/ 101 struct clk *clk; /* PHY clock */ 102 u32 ctrl_reg; /* GMAC glue-logic control register */ 103 int clk_sel_reg; /* GMAC ext clk selection register */ 104 struct regmap *regmap; 105 bool gmac_en; 106 u32 speed; 107 void (*fix_retime_src)(void *priv, unsigned int speed); 108 }; 109 110 struct sti_dwmac_of_data { 111 void (*fix_retime_src)(void *priv, unsigned int speed); 112 }; 113 114 static u32 phy_intf_sels[] = { 115 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 116 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 117 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 118 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 119 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 120 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 121 }; 122 123 enum { 124 TX_RETIME_SRC_NA = 0, 125 TX_RETIME_SRC_TXCLK = 1, 126 TX_RETIME_SRC_CLK_125, 127 TX_RETIME_SRC_PHYCLK, 128 TX_RETIME_SRC_CLKGEN, 129 }; 130 131 static u32 stih4xx_tx_retime_val[] = { 132 [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 133 [TX_RETIME_SRC_CLK_125] = 0x0, 134 [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 135 [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 136 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 137 }; 138 139 static void stih4xx_fix_retime_src(void *priv, u32 spd) 140 { 141 struct sti_dwmac *dwmac = priv; 142 u32 src = dwmac->tx_retime_src; 143 u32 reg = dwmac->ctrl_reg; 144 u32 freq = 0; 145 146 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 147 src = TX_RETIME_SRC_TXCLK; 148 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 149 if (dwmac->ext_phyclk) { 150 src = TX_RETIME_SRC_PHYCLK; 151 } else { 152 src = TX_RETIME_SRC_CLKGEN; 153 freq = DWMAC_50MHZ; 154 } 155 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 156 /* On GiGa clk source can be either ext or from clkgen */ 157 if (spd == SPEED_1000) { 158 freq = DWMAC_125MHZ; 159 } else { 160 /* Switch to clkgen for these speeds */ 161 src = TX_RETIME_SRC_CLKGEN; 162 if (spd == SPEED_100) 163 freq = DWMAC_25MHZ; 164 else if (spd == SPEED_10) 165 freq = DWMAC_2_5MHZ; 166 } 167 } 168 169 if (src == TX_RETIME_SRC_CLKGEN && freq) 170 clk_set_rate(dwmac->clk, freq); 171 172 regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 173 stih4xx_tx_retime_val[src]); 174 } 175 176 static int sti_dwmac_set_mode(struct sti_dwmac *dwmac) 177 { 178 struct regmap *regmap = dwmac->regmap; 179 int iface = dwmac->interface; 180 u32 reg = dwmac->ctrl_reg; 181 u32 val; 182 183 if (dwmac->gmac_en) 184 regmap_update_bits(regmap, reg, EN_MASK, EN); 185 186 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 187 188 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 189 regmap_update_bits(regmap, reg, ENMII_MASK, val); 190 191 dwmac->fix_retime_src(dwmac, dwmac->speed); 192 193 return 0; 194 } 195 196 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 197 struct platform_device *pdev) 198 { 199 struct resource *res; 200 struct device *dev = &pdev->dev; 201 struct device_node *np = dev->of_node; 202 struct regmap *regmap; 203 int err; 204 205 /* clk selection from extra syscfg register */ 206 dwmac->clk_sel_reg = -ENXIO; 207 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 208 if (res) 209 dwmac->clk_sel_reg = res->start; 210 211 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 212 if (IS_ERR(regmap)) 213 return PTR_ERR(regmap); 214 215 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg); 216 if (err) { 217 dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err); 218 return err; 219 } 220 221 err = of_get_phy_mode(np, &dwmac->interface); 222 if (err && err != -ENODEV) { 223 dev_err(dev, "Can't get phy-mode\n"); 224 return err; 225 } 226 227 dwmac->regmap = regmap; 228 dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en"); 229 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 230 dwmac->tx_retime_src = TX_RETIME_SRC_NA; 231 dwmac->speed = SPEED_100; 232 233 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 234 const char *rs; 235 236 dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 237 238 err = of_property_read_string(np, "st,tx-retime-src", &rs); 239 if (err < 0) { 240 dev_warn(dev, "Use internal clock source\n"); 241 } else { 242 if (!strcasecmp(rs, "clk_125")) 243 dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 244 else if (!strcasecmp(rs, "txclk")) 245 dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 246 } 247 dwmac->speed = SPEED_1000; 248 } 249 250 dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 251 if (IS_ERR(dwmac->clk)) { 252 dev_warn(dev, "No phy clock provided...\n"); 253 dwmac->clk = NULL; 254 } 255 256 return 0; 257 } 258 259 static int sti_dwmac_probe(struct platform_device *pdev) 260 { 261 struct plat_stmmacenet_data *plat_dat; 262 const struct sti_dwmac_of_data *data; 263 struct stmmac_resources stmmac_res; 264 struct sti_dwmac *dwmac; 265 int ret; 266 267 data = of_device_get_match_data(&pdev->dev); 268 if (!data) { 269 dev_err(&pdev->dev, "No OF match data provided\n"); 270 return -EINVAL; 271 } 272 273 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 274 if (ret) 275 return ret; 276 277 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 278 if (IS_ERR(plat_dat)) 279 return PTR_ERR(plat_dat); 280 281 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 282 if (!dwmac) { 283 ret = -ENOMEM; 284 goto err_remove_config_dt; 285 } 286 287 ret = sti_dwmac_parse_data(dwmac, pdev); 288 if (ret) { 289 dev_err(&pdev->dev, "Unable to parse OF data\n"); 290 goto err_remove_config_dt; 291 } 292 293 dwmac->fix_retime_src = data->fix_retime_src; 294 295 plat_dat->bsp_priv = dwmac; 296 plat_dat->fix_mac_speed = data->fix_retime_src; 297 298 ret = clk_prepare_enable(dwmac->clk); 299 if (ret) 300 goto err_remove_config_dt; 301 302 ret = sti_dwmac_set_mode(dwmac); 303 if (ret) 304 goto disable_clk; 305 306 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 307 if (ret) 308 goto disable_clk; 309 310 return 0; 311 312 disable_clk: 313 clk_disable_unprepare(dwmac->clk); 314 err_remove_config_dt: 315 stmmac_remove_config_dt(pdev, plat_dat); 316 317 return ret; 318 } 319 320 static void sti_dwmac_remove(struct platform_device *pdev) 321 { 322 struct sti_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); 323 324 stmmac_dvr_remove(&pdev->dev); 325 326 clk_disable_unprepare(dwmac->clk); 327 } 328 329 #ifdef CONFIG_PM_SLEEP 330 static int sti_dwmac_suspend(struct device *dev) 331 { 332 struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev); 333 int ret = stmmac_suspend(dev); 334 335 clk_disable_unprepare(dwmac->clk); 336 337 return ret; 338 } 339 340 static int sti_dwmac_resume(struct device *dev) 341 { 342 struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev); 343 344 clk_prepare_enable(dwmac->clk); 345 sti_dwmac_set_mode(dwmac); 346 347 return stmmac_resume(dev); 348 } 349 #endif /* CONFIG_PM_SLEEP */ 350 351 static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, 352 sti_dwmac_resume); 353 354 static const struct sti_dwmac_of_data stih4xx_dwmac_data = { 355 .fix_retime_src = stih4xx_fix_retime_src, 356 }; 357 358 static const struct of_device_id sti_dwmac_match[] = { 359 { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 360 { } 361 }; 362 MODULE_DEVICE_TABLE(of, sti_dwmac_match); 363 364 static struct platform_driver sti_dwmac_driver = { 365 .probe = sti_dwmac_probe, 366 .remove_new = sti_dwmac_remove, 367 .driver = { 368 .name = "sti-dwmac", 369 .pm = &sti_dwmac_pm_ops, 370 .of_match_table = sti_dwmac_match, 371 }, 372 }; 373 module_platform_driver(sti_dwmac_driver); 374 375 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 376 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 377 MODULE_LICENSE("GPL"); 378