1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 4 * 5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 7 * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/platform_device.h> 13 #include <linux/stmmac.h> 14 #include <linux/phy.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/regmap.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_net.h> 21 22 #include "stmmac_platform.h" 23 24 #define DWMAC_50MHZ 50000000 25 26 #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 27 iface == PHY_INTERFACE_MODE_RGMII_ID || \ 28 iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 29 iface == PHY_INTERFACE_MODE_RGMII_TXID) 30 31 #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 32 iface == PHY_INTERFACE_MODE_GMII) 33 34 /* STiH4xx register definitions (STiH407/STiH410 families) 35 * 36 * Below table summarizes the clock requirement and clock sources for 37 * supported phy interface modes with link speeds. 38 * ________________________________________________ 39 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 40 * ------------------------------------------------ 41 *| MII | n/a | 25Mhz | 42 *| | | txclk | 43 * ------------------------------------------------ 44 *| GMII | 125Mhz | 25Mhz | 45 *| | clk-125/txclk | txclk | 46 * ------------------------------------------------ 47 *| RGMII | 125Mhz | 25Mhz | 48 *| | clk-125/txclk | clkgen | 49 *| | clkgen | | 50 * ------------------------------------------------ 51 *| RMII | n/a | 25Mhz | 52 *| | |clkgen/phyclk-in | 53 * ------------------------------------------------ 54 * 55 * Register Configuration 56 *------------------------------- 57 * src |BIT(8)| BIT(7)| BIT(6)| 58 *------------------------------- 59 * txclk | 0 | n/a | 1 | 60 *------------------------------- 61 * ck_125| 0 | n/a | 0 | 62 *------------------------------- 63 * phyclk| 1 | 0 | n/a | 64 *------------------------------- 65 * clkgen| 1 | 1 | n/a | 66 *------------------------------- 67 */ 68 69 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 70 #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 71 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 72 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 73 74 #define ENMII_MASK GENMASK(5, 5) 75 #define ENMII BIT(5) 76 #define EN_MASK GENMASK(1, 1) 77 #define EN BIT(1) 78 79 /* 80 * 3 bits [4:2] 81 * 000-GMII/MII 82 * 001-RGMII 83 * 010-SGMII 84 * 100-RMII 85 */ 86 #define MII_PHY_SEL_MASK GENMASK(4, 2) 87 #define ETH_PHY_SEL_RMII BIT(4) 88 #define ETH_PHY_SEL_SGMII BIT(3) 89 #define ETH_PHY_SEL_RGMII BIT(2) 90 #define ETH_PHY_SEL_GMII 0x0 91 #define ETH_PHY_SEL_MII 0x0 92 93 struct sti_dwmac { 94 phy_interface_t interface; /* MII interface */ 95 bool ext_phyclk; /* Clock from external PHY */ 96 u32 tx_retime_src; /* TXCLK Retiming*/ 97 struct clk *clk; /* PHY clock */ 98 u32 ctrl_reg; /* GMAC glue-logic control register */ 99 int clk_sel_reg; /* GMAC ext clk selection register */ 100 struct regmap *regmap; 101 bool gmac_en; 102 u32 speed; 103 void (*fix_retime_src)(void *priv, unsigned int speed, unsigned int mode); 104 }; 105 106 struct sti_dwmac_of_data { 107 void (*fix_retime_src)(void *priv, unsigned int speed, unsigned int mode); 108 }; 109 110 static u32 phy_intf_sels[] = { 111 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 112 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 113 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 114 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 115 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 116 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 117 }; 118 119 enum { 120 TX_RETIME_SRC_NA = 0, 121 TX_RETIME_SRC_TXCLK = 1, 122 TX_RETIME_SRC_CLK_125, 123 TX_RETIME_SRC_PHYCLK, 124 TX_RETIME_SRC_CLKGEN, 125 }; 126 127 static u32 stih4xx_tx_retime_val[] = { 128 [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 129 [TX_RETIME_SRC_CLK_125] = 0x0, 130 [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 131 [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 132 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 133 }; 134 135 static void stih4xx_fix_retime_src(void *priv, u32 spd, unsigned int mode) 136 { 137 struct sti_dwmac *dwmac = priv; 138 u32 src = dwmac->tx_retime_src; 139 u32 reg = dwmac->ctrl_reg; 140 long freq = 0; 141 142 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 143 src = TX_RETIME_SRC_TXCLK; 144 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 145 if (dwmac->ext_phyclk) { 146 src = TX_RETIME_SRC_PHYCLK; 147 } else { 148 src = TX_RETIME_SRC_CLKGEN; 149 freq = DWMAC_50MHZ; 150 } 151 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 152 /* On GiGa clk source can be either ext or from clkgen */ 153 freq = rgmii_clock(spd); 154 155 if (spd != SPEED_1000 && freq > 0) 156 /* Switch to clkgen for these speeds */ 157 src = TX_RETIME_SRC_CLKGEN; 158 } 159 160 if (src == TX_RETIME_SRC_CLKGEN && freq > 0) 161 clk_set_rate(dwmac->clk, freq); 162 163 regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 164 stih4xx_tx_retime_val[src]); 165 } 166 167 static int sti_dwmac_set_mode(struct sti_dwmac *dwmac) 168 { 169 struct regmap *regmap = dwmac->regmap; 170 int iface = dwmac->interface; 171 u32 reg = dwmac->ctrl_reg; 172 u32 val; 173 174 if (dwmac->gmac_en) 175 regmap_update_bits(regmap, reg, EN_MASK, EN); 176 177 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 178 179 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 180 regmap_update_bits(regmap, reg, ENMII_MASK, val); 181 182 dwmac->fix_retime_src(dwmac, dwmac->speed, 0); 183 184 return 0; 185 } 186 187 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 188 struct platform_device *pdev) 189 { 190 struct resource *res; 191 struct device *dev = &pdev->dev; 192 struct device_node *np = dev->of_node; 193 struct regmap *regmap; 194 int err; 195 196 /* clk selection from extra syscfg register */ 197 dwmac->clk_sel_reg = -ENXIO; 198 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 199 if (res) 200 dwmac->clk_sel_reg = res->start; 201 202 regmap = syscon_regmap_lookup_by_phandle_args(np, "st,syscon", 203 1, &dwmac->ctrl_reg); 204 if (IS_ERR(regmap)) 205 return PTR_ERR(regmap); 206 207 err = of_get_phy_mode(np, &dwmac->interface); 208 if (err && err != -ENODEV) { 209 dev_err(dev, "Can't get phy-mode\n"); 210 return err; 211 } 212 213 dwmac->regmap = regmap; 214 dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en"); 215 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 216 dwmac->tx_retime_src = TX_RETIME_SRC_NA; 217 dwmac->speed = SPEED_100; 218 219 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 220 const char *rs; 221 222 dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 223 224 err = of_property_read_string(np, "st,tx-retime-src", &rs); 225 if (err < 0) { 226 dev_warn(dev, "Use internal clock source\n"); 227 } else { 228 if (!strcasecmp(rs, "clk_125")) 229 dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 230 else if (!strcasecmp(rs, "txclk")) 231 dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 232 } 233 dwmac->speed = SPEED_1000; 234 } 235 236 dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 237 if (IS_ERR(dwmac->clk)) { 238 dev_warn(dev, "No phy clock provided...\n"); 239 dwmac->clk = NULL; 240 } 241 242 return 0; 243 } 244 245 static int sti_dwmac_probe(struct platform_device *pdev) 246 { 247 struct plat_stmmacenet_data *plat_dat; 248 const struct sti_dwmac_of_data *data; 249 struct stmmac_resources stmmac_res; 250 struct sti_dwmac *dwmac; 251 int ret; 252 253 data = of_device_get_match_data(&pdev->dev); 254 if (!data) { 255 dev_err(&pdev->dev, "No OF match data provided\n"); 256 return -EINVAL; 257 } 258 259 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 260 if (ret) 261 return ret; 262 263 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 264 if (IS_ERR(plat_dat)) 265 return PTR_ERR(plat_dat); 266 267 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 268 if (!dwmac) 269 return -ENOMEM; 270 271 ret = sti_dwmac_parse_data(dwmac, pdev); 272 if (ret) { 273 dev_err(&pdev->dev, "Unable to parse OF data\n"); 274 return ret; 275 } 276 277 dwmac->fix_retime_src = data->fix_retime_src; 278 279 plat_dat->bsp_priv = dwmac; 280 plat_dat->fix_mac_speed = data->fix_retime_src; 281 282 ret = clk_prepare_enable(dwmac->clk); 283 if (ret) 284 return ret; 285 286 ret = sti_dwmac_set_mode(dwmac); 287 if (ret) 288 goto disable_clk; 289 290 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 291 if (ret) 292 goto disable_clk; 293 294 return 0; 295 296 disable_clk: 297 clk_disable_unprepare(dwmac->clk); 298 299 return ret; 300 } 301 302 static void sti_dwmac_remove(struct platform_device *pdev) 303 { 304 struct sti_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); 305 306 stmmac_dvr_remove(&pdev->dev); 307 308 clk_disable_unprepare(dwmac->clk); 309 } 310 311 static int sti_dwmac_suspend(struct device *dev) 312 { 313 struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev); 314 int ret = stmmac_suspend(dev); 315 316 clk_disable_unprepare(dwmac->clk); 317 318 return ret; 319 } 320 321 static int sti_dwmac_resume(struct device *dev) 322 { 323 struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev); 324 325 clk_prepare_enable(dwmac->clk); 326 sti_dwmac_set_mode(dwmac); 327 328 return stmmac_resume(dev); 329 } 330 331 static DEFINE_SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, 332 sti_dwmac_resume); 333 334 static const struct sti_dwmac_of_data stih4xx_dwmac_data = { 335 .fix_retime_src = stih4xx_fix_retime_src, 336 }; 337 338 static const struct of_device_id sti_dwmac_match[] = { 339 { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 340 { } 341 }; 342 MODULE_DEVICE_TABLE(of, sti_dwmac_match); 343 344 static struct platform_driver sti_dwmac_driver = { 345 .probe = sti_dwmac_probe, 346 .remove = sti_dwmac_remove, 347 .driver = { 348 .name = "sti-dwmac", 349 .pm = pm_sleep_ptr(&sti_dwmac_pm_ops), 350 .of_match_table = sti_dwmac_match, 351 }, 352 }; 353 module_platform_driver(sti_dwmac_driver); 354 355 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 356 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 357 MODULE_LICENSE("GPL"); 358