1 /* Copyright Altera Corporation (C) 2014. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License, version 2, 5 * as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * 15 * Adopted from dwmac-sti.c 16 */ 17 18 #include <linux/mfd/altera-sysmgr.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/phy.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/stmmac.h> 26 27 #include "stmmac.h" 28 #include "stmmac_platform.h" 29 30 #include "altr_tse_pcs.h" 31 32 #define SGMII_ADAPTER_CTRL_REG 0x00 33 #define SGMII_ADAPTER_DISABLE 0x0001 34 35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 38 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 39 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 40 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010 41 #define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100 42 43 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028 44 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004 45 #define SYSMGR_FPGAINTF_EMAC_REG 0x00000070 46 #define SYSMGR_FPGAINTF_EMAC_BIT 0x1 47 48 #define EMAC_SPLITTER_CTRL_REG 0x0 49 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3 50 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2 51 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3 52 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0 53 54 struct socfpga_dwmac; 55 struct socfpga_dwmac_ops { 56 int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv); 57 }; 58 59 struct socfpga_dwmac { 60 int interface; 61 u32 reg_offset; 62 u32 reg_shift; 63 struct device *dev; 64 struct regmap *sys_mgr_base_addr; 65 struct reset_control *stmmac_rst; 66 struct reset_control *stmmac_ocp_rst; 67 void __iomem *splitter_base; 68 bool f2h_ptp_ref_clk; 69 struct tse_pcs pcs; 70 const struct socfpga_dwmac_ops *ops; 71 }; 72 73 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) 74 { 75 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; 76 void __iomem *splitter_base = dwmac->splitter_base; 77 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; 78 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; 79 struct device *dev = dwmac->dev; 80 struct net_device *ndev = dev_get_drvdata(dev); 81 struct phy_device *phy_dev = ndev->phydev; 82 u32 val; 83 84 if ((tse_pcs_base) && (sgmii_adapter_base)) 85 writew(SGMII_ADAPTER_DISABLE, 86 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); 87 88 if (splitter_base) { 89 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); 90 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; 91 92 switch (speed) { 93 case 1000: 94 val |= EMAC_SPLITTER_CTRL_SPEED_1000; 95 break; 96 case 100: 97 val |= EMAC_SPLITTER_CTRL_SPEED_100; 98 break; 99 case 10: 100 val |= EMAC_SPLITTER_CTRL_SPEED_10; 101 break; 102 default: 103 return; 104 } 105 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); 106 } 107 108 if (tse_pcs_base && sgmii_adapter_base) 109 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); 110 } 111 112 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) 113 { 114 struct device_node *np = dev->of_node; 115 struct regmap *sys_mgr_base_addr; 116 u32 reg_offset, reg_shift; 117 int ret, index; 118 struct device_node *np_splitter = NULL; 119 struct device_node *np_sgmii_adapter = NULL; 120 struct resource res_splitter; 121 struct resource res_tse_pcs; 122 struct resource res_sgmii_adapter; 123 124 dwmac->interface = of_get_phy_mode(np); 125 126 sys_mgr_base_addr = 127 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 128 if (IS_ERR(sys_mgr_base_addr)) { 129 dev_info(dev, "No sysmgr-syscon node found\n"); 130 return PTR_ERR(sys_mgr_base_addr); 131 } 132 133 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 134 if (ret) { 135 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); 136 return -EINVAL; 137 } 138 139 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); 140 if (ret) { 141 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); 142 return -EINVAL; 143 } 144 145 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); 146 147 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); 148 if (np_splitter) { 149 ret = of_address_to_resource(np_splitter, 0, &res_splitter); 150 of_node_put(np_splitter); 151 if (ret) { 152 dev_info(dev, "Missing emac splitter address\n"); 153 return -EINVAL; 154 } 155 156 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); 157 if (IS_ERR(dwmac->splitter_base)) { 158 dev_info(dev, "Failed to mapping emac splitter\n"); 159 return PTR_ERR(dwmac->splitter_base); 160 } 161 } 162 163 np_sgmii_adapter = of_parse_phandle(np, 164 "altr,gmii-to-sgmii-converter", 0); 165 if (np_sgmii_adapter) { 166 index = of_property_match_string(np_sgmii_adapter, "reg-names", 167 "hps_emac_interface_splitter_avalon_slave"); 168 169 if (index >= 0) { 170 if (of_address_to_resource(np_sgmii_adapter, index, 171 &res_splitter)) { 172 dev_err(dev, 173 "%s: ERROR: missing emac splitter address\n", 174 __func__); 175 ret = -EINVAL; 176 goto err_node_put; 177 } 178 179 dwmac->splitter_base = 180 devm_ioremap_resource(dev, &res_splitter); 181 182 if (IS_ERR(dwmac->splitter_base)) { 183 ret = PTR_ERR(dwmac->splitter_base); 184 goto err_node_put; 185 } 186 } 187 188 index = of_property_match_string(np_sgmii_adapter, "reg-names", 189 "gmii_to_sgmii_adapter_avalon_slave"); 190 191 if (index >= 0) { 192 if (of_address_to_resource(np_sgmii_adapter, index, 193 &res_sgmii_adapter)) { 194 dev_err(dev, 195 "%s: ERROR: failed mapping adapter\n", 196 __func__); 197 ret = -EINVAL; 198 goto err_node_put; 199 } 200 201 dwmac->pcs.sgmii_adapter_base = 202 devm_ioremap_resource(dev, &res_sgmii_adapter); 203 204 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { 205 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); 206 goto err_node_put; 207 } 208 } 209 210 index = of_property_match_string(np_sgmii_adapter, "reg-names", 211 "eth_tse_control_port"); 212 213 if (index >= 0) { 214 if (of_address_to_resource(np_sgmii_adapter, index, 215 &res_tse_pcs)) { 216 dev_err(dev, 217 "%s: ERROR: failed mapping tse control port\n", 218 __func__); 219 ret = -EINVAL; 220 goto err_node_put; 221 } 222 223 dwmac->pcs.tse_pcs_base = 224 devm_ioremap_resource(dev, &res_tse_pcs); 225 226 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { 227 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); 228 goto err_node_put; 229 } 230 } 231 } 232 dwmac->reg_offset = reg_offset; 233 dwmac->reg_shift = reg_shift; 234 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; 235 dwmac->dev = dev; 236 of_node_put(np_sgmii_adapter); 237 238 return 0; 239 240 err_node_put: 241 of_node_put(np_sgmii_adapter); 242 return ret; 243 } 244 245 static int socfpga_set_phy_mode_common(int phymode, u32 *val) 246 { 247 switch (phymode) { 248 case PHY_INTERFACE_MODE_RGMII: 249 case PHY_INTERFACE_MODE_RGMII_ID: 250 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 251 break; 252 case PHY_INTERFACE_MODE_MII: 253 case PHY_INTERFACE_MODE_GMII: 254 case PHY_INTERFACE_MODE_SGMII: 255 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 256 break; 257 case PHY_INTERFACE_MODE_RMII: 258 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; 259 break; 260 default: 261 return -EINVAL; 262 } 263 return 0; 264 } 265 266 static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac) 267 { 268 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 269 int phymode = dwmac->interface; 270 u32 reg_offset = dwmac->reg_offset; 271 u32 reg_shift = dwmac->reg_shift; 272 u32 ctrl, val, module; 273 274 if (socfpga_set_phy_mode_common(phymode, &val)) { 275 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); 276 return -EINVAL; 277 } 278 279 /* Overwrite val to GMII if splitter core is enabled. The phymode here 280 * is the actual phy mode on phy hardware, but phy interface from 281 * EMAC core is GMII. 282 */ 283 if (dwmac->splitter_base) 284 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 285 286 /* Assert reset to the enet controller before changing the phy mode */ 287 reset_control_assert(dwmac->stmmac_ocp_rst); 288 reset_control_assert(dwmac->stmmac_rst); 289 290 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 291 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); 292 ctrl |= val << reg_shift; 293 294 if (dwmac->f2h_ptp_ref_clk || 295 phymode == PHY_INTERFACE_MODE_MII || 296 phymode == PHY_INTERFACE_MODE_GMII || 297 phymode == PHY_INTERFACE_MODE_SGMII) { 298 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); 299 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 300 &module); 301 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); 302 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 303 module); 304 } else { 305 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); 306 } 307 308 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 309 310 /* Deassert reset for the phy configuration to be sampled by 311 * the enet controller, and operation to start in requested mode 312 */ 313 reset_control_deassert(dwmac->stmmac_ocp_rst); 314 reset_control_deassert(dwmac->stmmac_rst); 315 if (phymode == PHY_INTERFACE_MODE_SGMII) { 316 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { 317 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); 318 return -EINVAL; 319 } 320 } 321 322 return 0; 323 } 324 325 static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac) 326 { 327 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 328 int phymode = dwmac->interface; 329 u32 reg_offset = dwmac->reg_offset; 330 u32 reg_shift = dwmac->reg_shift; 331 u32 ctrl, val, module; 332 333 if (socfpga_set_phy_mode_common(phymode, &val)) 334 return -EINVAL; 335 336 /* Overwrite val to GMII if splitter core is enabled. The phymode here 337 * is the actual phy mode on phy hardware, but phy interface from 338 * EMAC core is GMII. 339 */ 340 if (dwmac->splitter_base) 341 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 342 343 /* Assert reset to the enet controller before changing the phy mode */ 344 reset_control_assert(dwmac->stmmac_ocp_rst); 345 reset_control_assert(dwmac->stmmac_rst); 346 347 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 348 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); 349 ctrl |= val; 350 351 if (dwmac->f2h_ptp_ref_clk || 352 phymode == PHY_INTERFACE_MODE_MII || 353 phymode == PHY_INTERFACE_MODE_GMII || 354 phymode == PHY_INTERFACE_MODE_SGMII) { 355 ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK; 356 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG, 357 &module); 358 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift); 359 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG, 360 module); 361 } else { 362 ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK; 363 } 364 365 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 366 367 /* Deassert reset for the phy configuration to be sampled by 368 * the enet controller, and operation to start in requested mode 369 */ 370 reset_control_deassert(dwmac->stmmac_ocp_rst); 371 reset_control_deassert(dwmac->stmmac_rst); 372 if (phymode == PHY_INTERFACE_MODE_SGMII) { 373 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { 374 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); 375 return -EINVAL; 376 } 377 } 378 return 0; 379 } 380 381 static int socfpga_dwmac_probe(struct platform_device *pdev) 382 { 383 struct plat_stmmacenet_data *plat_dat; 384 struct stmmac_resources stmmac_res; 385 struct device *dev = &pdev->dev; 386 int ret; 387 struct socfpga_dwmac *dwmac; 388 struct net_device *ndev; 389 struct stmmac_priv *stpriv; 390 const struct socfpga_dwmac_ops *ops; 391 392 ops = device_get_match_data(&pdev->dev); 393 if (!ops) { 394 dev_err(&pdev->dev, "no of match data provided\n"); 395 return -EINVAL; 396 } 397 398 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 399 if (ret) 400 return ret; 401 402 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 403 if (IS_ERR(plat_dat)) 404 return PTR_ERR(plat_dat); 405 406 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); 407 if (!dwmac) { 408 ret = -ENOMEM; 409 goto err_remove_config_dt; 410 } 411 412 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp"); 413 if (IS_ERR(dwmac->stmmac_ocp_rst)) { 414 ret = PTR_ERR(dwmac->stmmac_ocp_rst); 415 dev_err(dev, "error getting reset control of ocp %d\n", ret); 416 goto err_remove_config_dt; 417 } 418 419 reset_control_deassert(dwmac->stmmac_ocp_rst); 420 421 ret = socfpga_dwmac_parse_data(dwmac, dev); 422 if (ret) { 423 dev_err(dev, "Unable to parse OF data\n"); 424 goto err_remove_config_dt; 425 } 426 427 dwmac->ops = ops; 428 plat_dat->bsp_priv = dwmac; 429 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; 430 431 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 432 if (ret) 433 goto err_remove_config_dt; 434 435 ndev = platform_get_drvdata(pdev); 436 stpriv = netdev_priv(ndev); 437 438 /* The socfpga driver needs to control the stmmac reset to set the phy 439 * mode. Create a copy of the core reset handle so it can be used by 440 * the driver later. 441 */ 442 dwmac->stmmac_rst = stpriv->plat->stmmac_rst; 443 444 ret = ops->set_phy_mode(dwmac); 445 if (ret) 446 goto err_dvr_remove; 447 448 return 0; 449 450 err_dvr_remove: 451 stmmac_dvr_remove(&pdev->dev); 452 err_remove_config_dt: 453 stmmac_remove_config_dt(pdev, plat_dat); 454 455 return ret; 456 } 457 458 #ifdef CONFIG_PM_SLEEP 459 static int socfpga_dwmac_resume(struct device *dev) 460 { 461 struct net_device *ndev = dev_get_drvdata(dev); 462 struct stmmac_priv *priv = netdev_priv(ndev); 463 struct socfpga_dwmac *dwmac_priv = get_stmmac_bsp_priv(dev); 464 465 dwmac_priv->ops->set_phy_mode(priv->plat->bsp_priv); 466 467 /* Before the enet controller is suspended, the phy is suspended. 468 * This causes the phy clock to be gated. The enet controller is 469 * resumed before the phy, so the clock is still gated "off" when 470 * the enet controller is resumed. This code makes sure the phy 471 * is "resumed" before reinitializing the enet controller since 472 * the enet controller depends on an active phy clock to complete 473 * a DMA reset. A DMA reset will "time out" if executed 474 * with no phy clock input on the Synopsys enet controller. 475 * Verified through Synopsys Case #8000711656. 476 * 477 * Note that the phy clock is also gated when the phy is isolated. 478 * Phy "suspend" and "isolate" controls are located in phy basic 479 * control register 0, and can be modified by the phy driver 480 * framework. 481 */ 482 if (ndev->phydev) 483 phy_resume(ndev->phydev); 484 485 return stmmac_resume(dev); 486 } 487 #endif /* CONFIG_PM_SLEEP */ 488 489 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend, 490 socfpga_dwmac_resume); 491 492 static const struct socfpga_dwmac_ops socfpga_gen5_ops = { 493 .set_phy_mode = socfpga_gen5_set_phy_mode, 494 }; 495 496 static const struct socfpga_dwmac_ops socfpga_gen10_ops = { 497 .set_phy_mode = socfpga_gen10_set_phy_mode, 498 }; 499 500 static const struct of_device_id socfpga_dwmac_match[] = { 501 { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops }, 502 { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops }, 503 { } 504 }; 505 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); 506 507 static struct platform_driver socfpga_dwmac_driver = { 508 .probe = socfpga_dwmac_probe, 509 .remove = stmmac_pltfr_remove, 510 .driver = { 511 .name = "socfpga-dwmac", 512 .pm = &socfpga_dwmac_pm_ops, 513 .of_match_table = socfpga_dwmac_match, 514 }, 515 }; 516 module_platform_driver(socfpga_dwmac_driver); 517 518 MODULE_LICENSE("GPL v2"); 519