1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/phy.h> 14 #include <linux/of_net.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 24 #include "stmmac_platform.h" 25 26 struct rk_priv_data; 27 struct rk_gmac_ops { 28 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 29 int tx_delay, int rx_delay); 30 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 31 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 32 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 33 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 34 bool enable); 35 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 36 bool php_grf_required; 37 bool regs_valid; 38 u32 regs[]; 39 }; 40 41 static const char * const rk_clocks[] = { 42 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 43 }; 44 45 static const char * const rk_rmii_clocks[] = { 46 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 47 }; 48 49 enum rk_clocks_index { 50 RK_ACLK_MAC = 0, 51 RK_PCLK_MAC, 52 RK_MAC_CLK_TX, 53 RK_CLK_MAC_SPEED, 54 RK_MAC_CLK_RX, 55 RK_CLK_MAC_REF, 56 RK_CLK_MAC_REFOUT, 57 }; 58 59 struct rk_priv_data { 60 struct platform_device *pdev; 61 phy_interface_t phy_iface; 62 int id; 63 struct regulator *regulator; 64 bool suspended; 65 const struct rk_gmac_ops *ops; 66 67 bool clk_enabled; 68 bool clock_input; 69 bool integrated_phy; 70 71 struct clk_bulk_data *clks; 72 int num_clks; 73 struct clk *clk_mac; 74 struct clk *clk_phy; 75 76 struct reset_control *phy_reset; 77 78 int tx_delay; 79 int rx_delay; 80 81 struct regmap *grf; 82 struct regmap *php_grf; 83 }; 84 85 #define HIWORD_UPDATE(val, mask, shift) \ 86 ((val) << (shift) | (mask) << ((shift) + 16)) 87 88 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 89 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 90 91 #define DELAY_ENABLE(soc, tx, rx) \ 92 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 93 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 94 95 #define PX30_GRF_GMAC_CON1 0x0904 96 97 /* PX30_GRF_GMAC_CON1 */ 98 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 99 GRF_BIT(6)) 100 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 101 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 102 103 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 104 { 105 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 106 PX30_GMAC_PHY_INTF_SEL_RMII); 107 } 108 109 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 110 { 111 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 112 struct device *dev = &bsp_priv->pdev->dev; 113 int ret; 114 115 if (!clk_mac_speed) { 116 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 117 return; 118 } 119 120 if (speed == 10) { 121 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 122 PX30_GMAC_SPEED_10M); 123 124 ret = clk_set_rate(clk_mac_speed, 2500000); 125 if (ret) 126 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n", 127 __func__, ret); 128 } else if (speed == 100) { 129 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 130 PX30_GMAC_SPEED_100M); 131 132 ret = clk_set_rate(clk_mac_speed, 25000000); 133 if (ret) 134 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n", 135 __func__, ret); 136 137 } else { 138 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 139 } 140 } 141 142 static const struct rk_gmac_ops px30_ops = { 143 .set_to_rmii = px30_set_to_rmii, 144 .set_rmii_speed = px30_set_rmii_speed, 145 }; 146 147 #define RK3128_GRF_MAC_CON0 0x0168 148 #define RK3128_GRF_MAC_CON1 0x016c 149 150 /* RK3128_GRF_MAC_CON0 */ 151 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 152 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 153 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 154 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 155 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 156 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 157 158 /* RK3128_GRF_MAC_CON1 */ 159 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 160 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 161 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 162 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 163 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 164 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 165 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 166 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 167 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 168 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 169 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 170 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 171 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 172 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 173 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 174 175 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 176 int tx_delay, int rx_delay) 177 { 178 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 179 RK3128_GMAC_PHY_INTF_SEL_RGMII | 180 RK3128_GMAC_RMII_MODE_CLR); 181 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 182 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 183 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 184 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 185 } 186 187 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 188 { 189 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 190 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 191 } 192 193 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 194 { 195 struct device *dev = &bsp_priv->pdev->dev; 196 197 if (speed == 10) 198 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 199 RK3128_GMAC_CLK_2_5M); 200 else if (speed == 100) 201 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 202 RK3128_GMAC_CLK_25M); 203 else if (speed == 1000) 204 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 205 RK3128_GMAC_CLK_125M); 206 else 207 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 208 } 209 210 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 211 { 212 struct device *dev = &bsp_priv->pdev->dev; 213 214 if (speed == 10) { 215 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 216 RK3128_GMAC_RMII_CLK_2_5M | 217 RK3128_GMAC_SPEED_10M); 218 } else if (speed == 100) { 219 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 220 RK3128_GMAC_RMII_CLK_25M | 221 RK3128_GMAC_SPEED_100M); 222 } else { 223 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 224 } 225 } 226 227 static const struct rk_gmac_ops rk3128_ops = { 228 .set_to_rgmii = rk3128_set_to_rgmii, 229 .set_to_rmii = rk3128_set_to_rmii, 230 .set_rgmii_speed = rk3128_set_rgmii_speed, 231 .set_rmii_speed = rk3128_set_rmii_speed, 232 }; 233 234 #define RK3228_GRF_MAC_CON0 0x0900 235 #define RK3228_GRF_MAC_CON1 0x0904 236 237 #define RK3228_GRF_CON_MUX 0x50 238 239 /* RK3228_GRF_MAC_CON0 */ 240 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 241 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 242 243 /* RK3228_GRF_MAC_CON1 */ 244 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 245 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 246 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 247 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 248 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 249 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 250 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 251 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 252 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 253 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 254 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 255 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 256 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 257 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 258 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 259 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 260 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 261 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 262 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 263 264 /* RK3228_GRF_COM_MUX */ 265 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 266 267 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 268 int tx_delay, int rx_delay) 269 { 270 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 271 RK3228_GMAC_PHY_INTF_SEL_RGMII | 272 RK3228_GMAC_RMII_MODE_CLR | 273 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 274 275 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 276 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 277 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 278 } 279 280 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 281 { 282 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 283 RK3228_GMAC_PHY_INTF_SEL_RMII | 284 RK3228_GMAC_RMII_MODE); 285 286 /* set MAC to RMII mode */ 287 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 288 } 289 290 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 291 { 292 struct device *dev = &bsp_priv->pdev->dev; 293 294 if (speed == 10) 295 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 296 RK3228_GMAC_CLK_2_5M); 297 else if (speed == 100) 298 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 299 RK3228_GMAC_CLK_25M); 300 else if (speed == 1000) 301 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 302 RK3228_GMAC_CLK_125M); 303 else 304 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 305 } 306 307 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 308 { 309 struct device *dev = &bsp_priv->pdev->dev; 310 311 if (speed == 10) 312 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 313 RK3228_GMAC_RMII_CLK_2_5M | 314 RK3228_GMAC_SPEED_10M); 315 else if (speed == 100) 316 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 317 RK3228_GMAC_RMII_CLK_25M | 318 RK3228_GMAC_SPEED_100M); 319 else 320 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 321 } 322 323 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 324 { 325 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 326 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 327 } 328 329 static const struct rk_gmac_ops rk3228_ops = { 330 .set_to_rgmii = rk3228_set_to_rgmii, 331 .set_to_rmii = rk3228_set_to_rmii, 332 .set_rgmii_speed = rk3228_set_rgmii_speed, 333 .set_rmii_speed = rk3228_set_rmii_speed, 334 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 335 }; 336 337 #define RK3288_GRF_SOC_CON1 0x0248 338 #define RK3288_GRF_SOC_CON3 0x0250 339 340 /*RK3288_GRF_SOC_CON1*/ 341 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 342 GRF_CLR_BIT(8)) 343 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 344 GRF_BIT(8)) 345 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 346 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 347 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 348 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 349 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 350 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 351 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 352 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 353 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 354 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 355 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 356 357 /*RK3288_GRF_SOC_CON3*/ 358 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 359 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 360 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 361 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 362 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 363 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 364 365 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 366 int tx_delay, int rx_delay) 367 { 368 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 369 RK3288_GMAC_PHY_INTF_SEL_RGMII | 370 RK3288_GMAC_RMII_MODE_CLR); 371 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 372 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 373 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 374 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 375 } 376 377 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 378 { 379 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 380 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 381 } 382 383 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 384 { 385 struct device *dev = &bsp_priv->pdev->dev; 386 387 if (speed == 10) 388 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 389 RK3288_GMAC_CLK_2_5M); 390 else if (speed == 100) 391 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 392 RK3288_GMAC_CLK_25M); 393 else if (speed == 1000) 394 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 395 RK3288_GMAC_CLK_125M); 396 else 397 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 398 } 399 400 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 401 { 402 struct device *dev = &bsp_priv->pdev->dev; 403 404 if (speed == 10) { 405 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 406 RK3288_GMAC_RMII_CLK_2_5M | 407 RK3288_GMAC_SPEED_10M); 408 } else if (speed == 100) { 409 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 410 RK3288_GMAC_RMII_CLK_25M | 411 RK3288_GMAC_SPEED_100M); 412 } else { 413 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 414 } 415 } 416 417 static const struct rk_gmac_ops rk3288_ops = { 418 .set_to_rgmii = rk3288_set_to_rgmii, 419 .set_to_rmii = rk3288_set_to_rmii, 420 .set_rgmii_speed = rk3288_set_rgmii_speed, 421 .set_rmii_speed = rk3288_set_rmii_speed, 422 }; 423 424 #define RK3308_GRF_MAC_CON0 0x04a0 425 426 /* RK3308_GRF_MAC_CON0 */ 427 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 428 GRF_BIT(4)) 429 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 430 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 431 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 432 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 433 434 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 435 { 436 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 437 RK3308_GMAC_PHY_INTF_SEL_RMII); 438 } 439 440 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 441 { 442 struct device *dev = &bsp_priv->pdev->dev; 443 444 if (speed == 10) { 445 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 446 RK3308_GMAC_SPEED_10M); 447 } else if (speed == 100) { 448 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 449 RK3308_GMAC_SPEED_100M); 450 } else { 451 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 452 } 453 } 454 455 static const struct rk_gmac_ops rk3308_ops = { 456 .set_to_rmii = rk3308_set_to_rmii, 457 .set_rmii_speed = rk3308_set_rmii_speed, 458 }; 459 460 #define RK3328_GRF_MAC_CON0 0x0900 461 #define RK3328_GRF_MAC_CON1 0x0904 462 #define RK3328_GRF_MAC_CON2 0x0908 463 #define RK3328_GRF_MACPHY_CON1 0xb04 464 465 /* RK3328_GRF_MAC_CON0 */ 466 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 467 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 468 469 /* RK3328_GRF_MAC_CON1 */ 470 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 471 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 472 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 473 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 474 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 475 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 476 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 477 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 478 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 479 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 480 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 481 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 482 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 483 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 484 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 485 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 486 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 487 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 488 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 489 490 /* RK3328_GRF_MACPHY_CON1 */ 491 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 492 493 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 494 int tx_delay, int rx_delay) 495 { 496 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 497 RK3328_GMAC_PHY_INTF_SEL_RGMII | 498 RK3328_GMAC_RMII_MODE_CLR | 499 RK3328_GMAC_RXCLK_DLY_ENABLE | 500 RK3328_GMAC_TXCLK_DLY_ENABLE); 501 502 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 503 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 504 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 505 } 506 507 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 508 { 509 unsigned int reg; 510 511 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 512 RK3328_GRF_MAC_CON1; 513 514 regmap_write(bsp_priv->grf, reg, 515 RK3328_GMAC_PHY_INTF_SEL_RMII | 516 RK3328_GMAC_RMII_MODE); 517 } 518 519 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 520 { 521 struct device *dev = &bsp_priv->pdev->dev; 522 523 if (speed == 10) 524 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 525 RK3328_GMAC_CLK_2_5M); 526 else if (speed == 100) 527 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 528 RK3328_GMAC_CLK_25M); 529 else if (speed == 1000) 530 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 531 RK3328_GMAC_CLK_125M); 532 else 533 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 534 } 535 536 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 537 { 538 struct device *dev = &bsp_priv->pdev->dev; 539 unsigned int reg; 540 541 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 542 RK3328_GRF_MAC_CON1; 543 544 if (speed == 10) 545 regmap_write(bsp_priv->grf, reg, 546 RK3328_GMAC_RMII_CLK_2_5M | 547 RK3328_GMAC_SPEED_10M); 548 else if (speed == 100) 549 regmap_write(bsp_priv->grf, reg, 550 RK3328_GMAC_RMII_CLK_25M | 551 RK3328_GMAC_SPEED_100M); 552 else 553 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 554 } 555 556 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 557 { 558 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 559 RK3328_MACPHY_RMII_MODE); 560 } 561 562 static const struct rk_gmac_ops rk3328_ops = { 563 .set_to_rgmii = rk3328_set_to_rgmii, 564 .set_to_rmii = rk3328_set_to_rmii, 565 .set_rgmii_speed = rk3328_set_rgmii_speed, 566 .set_rmii_speed = rk3328_set_rmii_speed, 567 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 568 }; 569 570 #define RK3366_GRF_SOC_CON6 0x0418 571 #define RK3366_GRF_SOC_CON7 0x041c 572 573 /* RK3366_GRF_SOC_CON6 */ 574 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 575 GRF_CLR_BIT(11)) 576 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 577 GRF_BIT(11)) 578 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 579 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 580 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 581 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 582 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 583 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 584 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 585 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 586 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 587 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 588 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 589 590 /* RK3366_GRF_SOC_CON7 */ 591 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 592 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 593 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 594 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 595 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 596 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 597 598 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 599 int tx_delay, int rx_delay) 600 { 601 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 602 RK3366_GMAC_PHY_INTF_SEL_RGMII | 603 RK3366_GMAC_RMII_MODE_CLR); 604 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 605 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 606 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 607 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 608 } 609 610 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 611 { 612 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 613 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 614 } 615 616 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 617 { 618 struct device *dev = &bsp_priv->pdev->dev; 619 620 if (speed == 10) 621 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 622 RK3366_GMAC_CLK_2_5M); 623 else if (speed == 100) 624 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 625 RK3366_GMAC_CLK_25M); 626 else if (speed == 1000) 627 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 628 RK3366_GMAC_CLK_125M); 629 else 630 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 631 } 632 633 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 634 { 635 struct device *dev = &bsp_priv->pdev->dev; 636 637 if (speed == 10) { 638 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 639 RK3366_GMAC_RMII_CLK_2_5M | 640 RK3366_GMAC_SPEED_10M); 641 } else if (speed == 100) { 642 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 643 RK3366_GMAC_RMII_CLK_25M | 644 RK3366_GMAC_SPEED_100M); 645 } else { 646 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 647 } 648 } 649 650 static const struct rk_gmac_ops rk3366_ops = { 651 .set_to_rgmii = rk3366_set_to_rgmii, 652 .set_to_rmii = rk3366_set_to_rmii, 653 .set_rgmii_speed = rk3366_set_rgmii_speed, 654 .set_rmii_speed = rk3366_set_rmii_speed, 655 }; 656 657 #define RK3368_GRF_SOC_CON15 0x043c 658 #define RK3368_GRF_SOC_CON16 0x0440 659 660 /* RK3368_GRF_SOC_CON15 */ 661 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 662 GRF_CLR_BIT(11)) 663 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 664 GRF_BIT(11)) 665 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 666 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 667 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 668 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 669 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 670 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 671 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 672 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 673 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 674 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 675 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 676 677 /* RK3368_GRF_SOC_CON16 */ 678 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 679 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 680 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 681 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 682 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 683 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 684 685 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 686 int tx_delay, int rx_delay) 687 { 688 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 689 RK3368_GMAC_PHY_INTF_SEL_RGMII | 690 RK3368_GMAC_RMII_MODE_CLR); 691 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 692 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 693 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 694 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 695 } 696 697 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 698 { 699 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 700 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 701 } 702 703 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 704 { 705 struct device *dev = &bsp_priv->pdev->dev; 706 707 if (speed == 10) 708 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 709 RK3368_GMAC_CLK_2_5M); 710 else if (speed == 100) 711 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 712 RK3368_GMAC_CLK_25M); 713 else if (speed == 1000) 714 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 715 RK3368_GMAC_CLK_125M); 716 else 717 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 718 } 719 720 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 721 { 722 struct device *dev = &bsp_priv->pdev->dev; 723 724 if (speed == 10) { 725 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 726 RK3368_GMAC_RMII_CLK_2_5M | 727 RK3368_GMAC_SPEED_10M); 728 } else if (speed == 100) { 729 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 730 RK3368_GMAC_RMII_CLK_25M | 731 RK3368_GMAC_SPEED_100M); 732 } else { 733 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 734 } 735 } 736 737 static const struct rk_gmac_ops rk3368_ops = { 738 .set_to_rgmii = rk3368_set_to_rgmii, 739 .set_to_rmii = rk3368_set_to_rmii, 740 .set_rgmii_speed = rk3368_set_rgmii_speed, 741 .set_rmii_speed = rk3368_set_rmii_speed, 742 }; 743 744 #define RK3399_GRF_SOC_CON5 0xc214 745 #define RK3399_GRF_SOC_CON6 0xc218 746 747 /* RK3399_GRF_SOC_CON5 */ 748 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 749 GRF_CLR_BIT(11)) 750 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 751 GRF_BIT(11)) 752 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 753 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 754 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 755 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 756 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 757 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 758 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 759 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 760 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 761 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 762 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 763 764 /* RK3399_GRF_SOC_CON6 */ 765 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 766 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 767 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 768 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 769 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 770 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 771 772 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 773 int tx_delay, int rx_delay) 774 { 775 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 776 RK3399_GMAC_PHY_INTF_SEL_RGMII | 777 RK3399_GMAC_RMII_MODE_CLR); 778 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 779 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 780 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 781 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 782 } 783 784 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 785 { 786 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 787 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 788 } 789 790 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 791 { 792 struct device *dev = &bsp_priv->pdev->dev; 793 794 if (speed == 10) 795 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 796 RK3399_GMAC_CLK_2_5M); 797 else if (speed == 100) 798 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 799 RK3399_GMAC_CLK_25M); 800 else if (speed == 1000) 801 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 802 RK3399_GMAC_CLK_125M); 803 else 804 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 805 } 806 807 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 808 { 809 struct device *dev = &bsp_priv->pdev->dev; 810 811 if (speed == 10) { 812 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 813 RK3399_GMAC_RMII_CLK_2_5M | 814 RK3399_GMAC_SPEED_10M); 815 } else if (speed == 100) { 816 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 817 RK3399_GMAC_RMII_CLK_25M | 818 RK3399_GMAC_SPEED_100M); 819 } else { 820 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 821 } 822 } 823 824 static const struct rk_gmac_ops rk3399_ops = { 825 .set_to_rgmii = rk3399_set_to_rgmii, 826 .set_to_rmii = rk3399_set_to_rmii, 827 .set_rgmii_speed = rk3399_set_rgmii_speed, 828 .set_rmii_speed = rk3399_set_rmii_speed, 829 }; 830 831 #define RK3568_GRF_GMAC0_CON0 0x0380 832 #define RK3568_GRF_GMAC0_CON1 0x0384 833 #define RK3568_GRF_GMAC1_CON0 0x0388 834 #define RK3568_GRF_GMAC1_CON1 0x038c 835 836 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 837 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 838 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 839 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 840 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 841 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 842 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 843 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 844 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 845 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 846 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 847 848 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 849 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 850 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 851 852 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 853 int tx_delay, int rx_delay) 854 { 855 u32 con0, con1; 856 857 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 858 RK3568_GRF_GMAC0_CON0; 859 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 860 RK3568_GRF_GMAC0_CON1; 861 862 regmap_write(bsp_priv->grf, con0, 863 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 864 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 865 866 regmap_write(bsp_priv->grf, con1, 867 RK3568_GMAC_PHY_INTF_SEL_RGMII | 868 RK3568_GMAC_RXCLK_DLY_ENABLE | 869 RK3568_GMAC_TXCLK_DLY_ENABLE); 870 } 871 872 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 873 { 874 u32 con1; 875 876 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 877 RK3568_GRF_GMAC0_CON1; 878 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 879 } 880 881 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 882 { 883 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 884 struct device *dev = &bsp_priv->pdev->dev; 885 long rate; 886 int ret; 887 888 rate = rgmii_clock(speed); 889 if (rate < 0) { 890 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 891 return; 892 } 893 894 ret = clk_set_rate(clk_mac_speed, rate); 895 if (ret) 896 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 897 __func__, rate, ret); 898 } 899 900 static const struct rk_gmac_ops rk3568_ops = { 901 .set_to_rgmii = rk3568_set_to_rgmii, 902 .set_to_rmii = rk3568_set_to_rmii, 903 .set_rgmii_speed = rk3568_set_gmac_speed, 904 .set_rmii_speed = rk3568_set_gmac_speed, 905 .regs_valid = true, 906 .regs = { 907 0xfe2a0000, /* gmac0 */ 908 0xfe010000, /* gmac1 */ 909 0x0, /* sentinel */ 910 }, 911 }; 912 913 /* VCCIO0_1_3_IOC */ 914 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 915 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 916 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 917 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 918 919 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 920 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 921 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 922 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 923 924 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 925 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 926 927 /* SDGMAC_GRF */ 928 #define RK3576_GRF_GMAC_CON0 0X0020 929 #define RK3576_GRF_GMAC_CON1 0X0024 930 931 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 932 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 933 934 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 935 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 936 937 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 938 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 939 940 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 941 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 942 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 943 (GRF_BIT(6) | GRF_BIT(5)) 944 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 945 (GRF_BIT(6) | GRF_CLR_BIT(5)) 946 947 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 948 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 949 950 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 951 int tx_delay, int rx_delay) 952 { 953 unsigned int offset_con; 954 955 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 956 RK3576_GRF_GMAC_CON0; 957 958 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 959 960 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 961 RK3576_VCCIO0_1_3_IOC_CON2; 962 963 /* m0 && m1 delay enabled */ 964 regmap_write(bsp_priv->php_grf, offset_con, 965 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 966 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 967 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 968 969 /* m0 && m1 delay value */ 970 regmap_write(bsp_priv->php_grf, offset_con, 971 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 972 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 973 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 974 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 975 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 976 } 977 978 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 979 { 980 unsigned int offset_con; 981 982 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 983 RK3576_GRF_GMAC_CON0; 984 985 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 986 } 987 988 static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 989 { 990 struct device *dev = &bsp_priv->pdev->dev; 991 unsigned int val = 0, offset_con; 992 993 switch (speed) { 994 case 10: 995 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 996 val = RK3576_GMAC_CLK_RMII_DIV20; 997 else 998 val = RK3576_GMAC_CLK_RGMII_DIV50; 999 break; 1000 case 100: 1001 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1002 val = RK3576_GMAC_CLK_RMII_DIV2; 1003 else 1004 val = RK3576_GMAC_CLK_RGMII_DIV5; 1005 break; 1006 case 1000: 1007 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) 1008 val = RK3576_GMAC_CLK_RGMII_DIV1; 1009 else 1010 goto err; 1011 break; 1012 default: 1013 goto err; 1014 } 1015 1016 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1017 RK3576_GRF_GMAC_CON0; 1018 1019 regmap_write(bsp_priv->grf, offset_con, val); 1020 1021 return; 1022 err: 1023 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1024 } 1025 1026 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1027 bool enable) 1028 { 1029 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1030 RK3576_GMAC_CLK_SELECT_CRU; 1031 unsigned int offset_con; 1032 1033 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1034 RK3576_GMAC_CLK_RMII_GATE; 1035 1036 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1037 RK3576_GRF_GMAC_CON0; 1038 1039 regmap_write(bsp_priv->grf, offset_con, val); 1040 } 1041 1042 static const struct rk_gmac_ops rk3576_ops = { 1043 .set_to_rgmii = rk3576_set_to_rgmii, 1044 .set_to_rmii = rk3576_set_to_rmii, 1045 .set_rgmii_speed = rk3576_set_gmac_speed, 1046 .set_rmii_speed = rk3576_set_gmac_speed, 1047 .set_clock_selection = rk3576_set_clock_selection, 1048 .php_grf_required = true, 1049 .regs_valid = true, 1050 .regs = { 1051 0x2a220000, /* gmac0 */ 1052 0x2a230000, /* gmac1 */ 1053 0x0, /* sentinel */ 1054 }, 1055 }; 1056 1057 /* sys_grf */ 1058 #define RK3588_GRF_GMAC_CON7 0X031c 1059 #define RK3588_GRF_GMAC_CON8 0X0320 1060 #define RK3588_GRF_GMAC_CON9 0X0324 1061 1062 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1063 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1064 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1065 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1066 1067 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1068 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1069 1070 /* php_grf */ 1071 #define RK3588_GRF_GMAC_CON0 0X0008 1072 #define RK3588_GRF_CLK_CON1 0X0070 1073 1074 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1075 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1076 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1077 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1078 1079 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1080 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1081 1082 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1083 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1084 1085 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1086 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1087 1088 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1089 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1090 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1091 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1092 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1093 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1094 1095 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1096 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1097 1098 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1099 int tx_delay, int rx_delay) 1100 { 1101 u32 offset_con, id = bsp_priv->id; 1102 1103 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1104 RK3588_GRF_GMAC_CON8; 1105 1106 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1107 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1108 1109 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1110 RK3588_GMAC_CLK_RGMII_MODE(id)); 1111 1112 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1113 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1114 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1115 1116 regmap_write(bsp_priv->grf, offset_con, 1117 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1118 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1119 } 1120 1121 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1122 { 1123 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1124 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1125 1126 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1127 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1128 } 1129 1130 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 1131 { 1132 struct device *dev = &bsp_priv->pdev->dev; 1133 unsigned int val = 0, id = bsp_priv->id; 1134 1135 switch (speed) { 1136 case 10: 1137 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1138 val = RK3588_GMA_CLK_RMII_DIV20(id); 1139 else 1140 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1141 break; 1142 case 100: 1143 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1144 val = RK3588_GMA_CLK_RMII_DIV2(id); 1145 else 1146 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1147 break; 1148 case 1000: 1149 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) 1150 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1151 else 1152 goto err; 1153 break; 1154 default: 1155 goto err; 1156 } 1157 1158 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1159 1160 return; 1161 err: 1162 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1163 } 1164 1165 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1166 bool enable) 1167 { 1168 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1169 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1170 1171 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1172 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1173 1174 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1175 } 1176 1177 static const struct rk_gmac_ops rk3588_ops = { 1178 .set_to_rgmii = rk3588_set_to_rgmii, 1179 .set_to_rmii = rk3588_set_to_rmii, 1180 .set_rgmii_speed = rk3588_set_gmac_speed, 1181 .set_rmii_speed = rk3588_set_gmac_speed, 1182 .set_clock_selection = rk3588_set_clock_selection, 1183 .php_grf_required = true, 1184 .regs_valid = true, 1185 .regs = { 1186 0xfe1b0000, /* gmac0 */ 1187 0xfe1c0000, /* gmac1 */ 1188 0x0, /* sentinel */ 1189 }, 1190 }; 1191 1192 #define RV1108_GRF_GMAC_CON0 0X0900 1193 1194 /* RV1108_GRF_GMAC_CON0 */ 1195 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1196 GRF_BIT(6)) 1197 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1198 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1199 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1200 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1201 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1202 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1203 1204 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1205 { 1206 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1207 RV1108_GMAC_PHY_INTF_SEL_RMII); 1208 } 1209 1210 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 1211 { 1212 struct device *dev = &bsp_priv->pdev->dev; 1213 1214 if (speed == 10) { 1215 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1216 RV1108_GMAC_RMII_CLK_2_5M | 1217 RV1108_GMAC_SPEED_10M); 1218 } else if (speed == 100) { 1219 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1220 RV1108_GMAC_RMII_CLK_25M | 1221 RV1108_GMAC_SPEED_100M); 1222 } else { 1223 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 1224 } 1225 } 1226 1227 static const struct rk_gmac_ops rv1108_ops = { 1228 .set_to_rmii = rv1108_set_to_rmii, 1229 .set_rmii_speed = rv1108_set_rmii_speed, 1230 }; 1231 1232 #define RV1126_GRF_GMAC_CON0 0X0070 1233 #define RV1126_GRF_GMAC_CON1 0X0074 1234 #define RV1126_GRF_GMAC_CON2 0X0078 1235 1236 /* RV1126_GRF_GMAC_CON0 */ 1237 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1238 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1239 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1240 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1241 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1242 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1243 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1244 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1245 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1246 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1247 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1248 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1249 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1250 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1251 1252 /* RV1126_GRF_GMAC_CON1 */ 1253 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1254 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1255 /* RV1126_GRF_GMAC_CON2 */ 1256 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1257 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1258 1259 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1260 int tx_delay, int rx_delay) 1261 { 1262 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1263 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1264 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1265 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1266 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1267 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1268 1269 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1270 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1271 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1272 1273 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1274 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1275 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1276 } 1277 1278 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1279 { 1280 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1281 RV1126_GMAC_PHY_INTF_SEL_RMII); 1282 } 1283 1284 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 1285 { 1286 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1287 struct device *dev = &bsp_priv->pdev->dev; 1288 long rate; 1289 int ret; 1290 1291 rate = rgmii_clock(speed); 1292 if (rate < 0) { 1293 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); 1294 return; 1295 } 1296 1297 ret = clk_set_rate(clk_mac_speed, rate); 1298 if (ret) 1299 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1300 __func__, rate, ret); 1301 } 1302 1303 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 1304 { 1305 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1306 struct device *dev = &bsp_priv->pdev->dev; 1307 unsigned long rate; 1308 int ret; 1309 1310 switch (speed) { 1311 case 10: 1312 rate = 2500000; 1313 break; 1314 case 100: 1315 rate = 25000000; 1316 break; 1317 default: 1318 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); 1319 return; 1320 } 1321 1322 ret = clk_set_rate(clk_mac_speed, rate); 1323 if (ret) 1324 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1325 __func__, rate, ret); 1326 } 1327 1328 static const struct rk_gmac_ops rv1126_ops = { 1329 .set_to_rgmii = rv1126_set_to_rgmii, 1330 .set_to_rmii = rv1126_set_to_rmii, 1331 .set_rgmii_speed = rv1126_set_rgmii_speed, 1332 .set_rmii_speed = rv1126_set_rmii_speed, 1333 }; 1334 1335 #define RK_GRF_MACPHY_CON0 0xb00 1336 #define RK_GRF_MACPHY_CON1 0xb04 1337 #define RK_GRF_MACPHY_CON2 0xb08 1338 #define RK_GRF_MACPHY_CON3 0xb0c 1339 1340 #define RK_MACPHY_ENABLE GRF_BIT(0) 1341 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 1342 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 1343 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 1344 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 1345 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 1346 1347 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) 1348 { 1349 if (priv->ops->integrated_phy_powerup) 1350 priv->ops->integrated_phy_powerup(priv); 1351 1352 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 1353 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 1354 1355 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 1356 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 1357 1358 if (priv->phy_reset) { 1359 /* PHY needs to be disabled before trying to reset it */ 1360 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1361 if (priv->phy_reset) 1362 reset_control_assert(priv->phy_reset); 1363 usleep_range(10, 20); 1364 if (priv->phy_reset) 1365 reset_control_deassert(priv->phy_reset); 1366 usleep_range(10, 20); 1367 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 1368 msleep(30); 1369 } 1370 } 1371 1372 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) 1373 { 1374 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1375 if (priv->phy_reset) 1376 reset_control_assert(priv->phy_reset); 1377 } 1378 1379 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1380 { 1381 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1382 struct device *dev = &bsp_priv->pdev->dev; 1383 int phy_iface = bsp_priv->phy_iface; 1384 int i, j, ret; 1385 1386 bsp_priv->clk_enabled = false; 1387 1388 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1389 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1390 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1391 1392 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1393 sizeof(*bsp_priv->clks), GFP_KERNEL); 1394 if (!bsp_priv->clks) 1395 return -ENOMEM; 1396 1397 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1398 bsp_priv->clks[i].id = rk_clocks[i]; 1399 1400 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1401 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1402 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1403 } 1404 1405 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1406 bsp_priv->clks); 1407 if (ret) 1408 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1409 1410 /* "stmmaceth" will be enabled by the core */ 1411 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 1412 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac); 1413 if (ret) 1414 return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n"); 1415 1416 if (bsp_priv->clock_input) { 1417 dev_info(dev, "clock input from PHY\n"); 1418 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1419 clk_set_rate(bsp_priv->clk_mac, 50000000); 1420 } 1421 1422 if (plat->phy_node && bsp_priv->integrated_phy) { 1423 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1424 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1425 if (ret) 1426 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1427 clk_set_rate(bsp_priv->clk_phy, 50000000); 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1434 { 1435 int ret; 1436 1437 if (enable) { 1438 if (!bsp_priv->clk_enabled) { 1439 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1440 bsp_priv->clks); 1441 if (ret) 1442 return ret; 1443 1444 ret = clk_prepare_enable(bsp_priv->clk_phy); 1445 if (ret) 1446 return ret; 1447 1448 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1449 bsp_priv->ops->set_clock_selection(bsp_priv, 1450 bsp_priv->clock_input, true); 1451 1452 mdelay(5); 1453 bsp_priv->clk_enabled = true; 1454 } 1455 } else { 1456 if (bsp_priv->clk_enabled) { 1457 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1458 bsp_priv->clks); 1459 clk_disable_unprepare(bsp_priv->clk_phy); 1460 1461 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1462 bsp_priv->ops->set_clock_selection(bsp_priv, 1463 bsp_priv->clock_input, false); 1464 1465 bsp_priv->clk_enabled = false; 1466 } 1467 } 1468 1469 return 0; 1470 } 1471 1472 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1473 { 1474 struct regulator *ldo = bsp_priv->regulator; 1475 int ret; 1476 struct device *dev = &bsp_priv->pdev->dev; 1477 1478 if (enable) { 1479 ret = regulator_enable(ldo); 1480 if (ret) 1481 dev_err(dev, "fail to enable phy-supply\n"); 1482 } else { 1483 ret = regulator_disable(ldo); 1484 if (ret) 1485 dev_err(dev, "fail to disable phy-supply\n"); 1486 } 1487 1488 return 0; 1489 } 1490 1491 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1492 struct plat_stmmacenet_data *plat, 1493 const struct rk_gmac_ops *ops) 1494 { 1495 struct rk_priv_data *bsp_priv; 1496 struct device *dev = &pdev->dev; 1497 struct resource *res; 1498 int ret; 1499 const char *strings = NULL; 1500 int value; 1501 1502 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1503 if (!bsp_priv) 1504 return ERR_PTR(-ENOMEM); 1505 1506 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface); 1507 bsp_priv->ops = ops; 1508 1509 /* Some SoCs have multiple MAC controllers, which need 1510 * to be distinguished. 1511 */ 1512 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1513 if (res && ops->regs_valid) { 1514 int i = 0; 1515 1516 while (ops->regs[i]) { 1517 if (ops->regs[i] == res->start) { 1518 bsp_priv->id = i; 1519 break; 1520 } 1521 i++; 1522 } 1523 } 1524 1525 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1526 if (IS_ERR(bsp_priv->regulator)) { 1527 ret = PTR_ERR(bsp_priv->regulator); 1528 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1529 return ERR_PTR(ret); 1530 } 1531 1532 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1533 if (ret) { 1534 dev_err(dev, "Can not read property: clock_in_out.\n"); 1535 bsp_priv->clock_input = true; 1536 } else { 1537 dev_info(dev, "clock input or output? (%s).\n", 1538 strings); 1539 if (!strcmp(strings, "input")) 1540 bsp_priv->clock_input = true; 1541 else 1542 bsp_priv->clock_input = false; 1543 } 1544 1545 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1546 if (ret) { 1547 bsp_priv->tx_delay = 0x30; 1548 dev_err(dev, "Can not read property: tx_delay."); 1549 dev_err(dev, "set tx_delay to 0x%x\n", 1550 bsp_priv->tx_delay); 1551 } else { 1552 dev_info(dev, "TX delay(0x%x).\n", value); 1553 bsp_priv->tx_delay = value; 1554 } 1555 1556 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1557 if (ret) { 1558 bsp_priv->rx_delay = 0x10; 1559 dev_err(dev, "Can not read property: rx_delay."); 1560 dev_err(dev, "set rx_delay to 0x%x\n", 1561 bsp_priv->rx_delay); 1562 } else { 1563 dev_info(dev, "RX delay(0x%x).\n", value); 1564 bsp_priv->rx_delay = value; 1565 } 1566 1567 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1568 "rockchip,grf"); 1569 if (IS_ERR(bsp_priv->grf)) { 1570 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1571 "failed to lookup rockchip,grf\n"); 1572 return ERR_CAST(bsp_priv->grf); 1573 } 1574 1575 if (ops->php_grf_required) { 1576 bsp_priv->php_grf = 1577 syscon_regmap_lookup_by_phandle(dev->of_node, 1578 "rockchip,php-grf"); 1579 if (IS_ERR(bsp_priv->php_grf)) { 1580 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1581 "failed to lookup rockchip,php-grf\n"); 1582 return ERR_CAST(bsp_priv->php_grf); 1583 } 1584 } 1585 1586 if (plat->phy_node) { 1587 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1588 "phy-is-integrated"); 1589 if (bsp_priv->integrated_phy) { 1590 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1591 if (IS_ERR(bsp_priv->phy_reset)) { 1592 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1593 bsp_priv->phy_reset = NULL; 1594 } 1595 } 1596 } 1597 dev_info(dev, "integrated PHY? (%s).\n", 1598 bsp_priv->integrated_phy ? "yes" : "no"); 1599 1600 bsp_priv->pdev = pdev; 1601 1602 return bsp_priv; 1603 } 1604 1605 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1606 { 1607 switch (bsp_priv->phy_iface) { 1608 case PHY_INTERFACE_MODE_RGMII: 1609 case PHY_INTERFACE_MODE_RGMII_ID: 1610 case PHY_INTERFACE_MODE_RGMII_RXID: 1611 case PHY_INTERFACE_MODE_RGMII_TXID: 1612 if (!bsp_priv->ops->set_to_rgmii) 1613 return -EINVAL; 1614 break; 1615 case PHY_INTERFACE_MODE_RMII: 1616 if (!bsp_priv->ops->set_to_rmii) 1617 return -EINVAL; 1618 break; 1619 default: 1620 dev_err(&bsp_priv->pdev->dev, 1621 "unsupported interface %d", bsp_priv->phy_iface); 1622 } 1623 return 0; 1624 } 1625 1626 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1627 { 1628 int ret; 1629 struct device *dev = &bsp_priv->pdev->dev; 1630 1631 ret = rk_gmac_check_ops(bsp_priv); 1632 if (ret) 1633 return ret; 1634 1635 ret = gmac_clk_enable(bsp_priv, true); 1636 if (ret) 1637 return ret; 1638 1639 /*rmii or rgmii*/ 1640 switch (bsp_priv->phy_iface) { 1641 case PHY_INTERFACE_MODE_RGMII: 1642 dev_info(dev, "init for RGMII\n"); 1643 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1644 bsp_priv->rx_delay); 1645 break; 1646 case PHY_INTERFACE_MODE_RGMII_ID: 1647 dev_info(dev, "init for RGMII_ID\n"); 1648 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1649 break; 1650 case PHY_INTERFACE_MODE_RGMII_RXID: 1651 dev_info(dev, "init for RGMII_RXID\n"); 1652 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1653 break; 1654 case PHY_INTERFACE_MODE_RGMII_TXID: 1655 dev_info(dev, "init for RGMII_TXID\n"); 1656 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1657 break; 1658 case PHY_INTERFACE_MODE_RMII: 1659 dev_info(dev, "init for RMII\n"); 1660 bsp_priv->ops->set_to_rmii(bsp_priv); 1661 break; 1662 default: 1663 dev_err(dev, "NO interface defined!\n"); 1664 } 1665 1666 ret = phy_power_on(bsp_priv, true); 1667 if (ret) { 1668 gmac_clk_enable(bsp_priv, false); 1669 return ret; 1670 } 1671 1672 pm_runtime_get_sync(dev); 1673 1674 if (bsp_priv->integrated_phy) 1675 rk_gmac_integrated_phy_powerup(bsp_priv); 1676 1677 return 0; 1678 } 1679 1680 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1681 { 1682 if (gmac->integrated_phy) 1683 rk_gmac_integrated_phy_powerdown(gmac); 1684 1685 pm_runtime_put_sync(&gmac->pdev->dev); 1686 1687 phy_power_on(gmac, false); 1688 gmac_clk_enable(gmac, false); 1689 } 1690 1691 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1692 phy_interface_t interface, int speed) 1693 { 1694 struct rk_priv_data *bsp_priv = bsp_priv_; 1695 struct device *dev = &bsp_priv->pdev->dev; 1696 1697 switch (bsp_priv->phy_iface) { 1698 case PHY_INTERFACE_MODE_RGMII: 1699 case PHY_INTERFACE_MODE_RGMII_ID: 1700 case PHY_INTERFACE_MODE_RGMII_RXID: 1701 case PHY_INTERFACE_MODE_RGMII_TXID: 1702 if (bsp_priv->ops->set_rgmii_speed) 1703 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 1704 break; 1705 case PHY_INTERFACE_MODE_RMII: 1706 if (bsp_priv->ops->set_rmii_speed) 1707 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 1708 break; 1709 default: 1710 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 1711 } 1712 1713 return 0; 1714 } 1715 1716 static int rk_gmac_probe(struct platform_device *pdev) 1717 { 1718 struct plat_stmmacenet_data *plat_dat; 1719 struct stmmac_resources stmmac_res; 1720 const struct rk_gmac_ops *data; 1721 int ret; 1722 1723 data = of_device_get_match_data(&pdev->dev); 1724 if (!data) { 1725 dev_err(&pdev->dev, "no of match data provided\n"); 1726 return -EINVAL; 1727 } 1728 1729 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1730 if (ret) 1731 return ret; 1732 1733 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1734 if (IS_ERR(plat_dat)) 1735 return PTR_ERR(plat_dat); 1736 1737 /* If the stmmac is not already selected as gmac4, 1738 * then make sure we fallback to gmac. 1739 */ 1740 if (!plat_dat->has_gmac4) 1741 plat_dat->has_gmac = true; 1742 1743 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1744 1745 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1746 if (IS_ERR(plat_dat->bsp_priv)) 1747 return PTR_ERR(plat_dat->bsp_priv); 1748 1749 ret = rk_gmac_clk_init(plat_dat); 1750 if (ret) 1751 return ret; 1752 1753 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1754 if (ret) 1755 return ret; 1756 1757 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1758 if (ret) 1759 goto err_gmac_powerdown; 1760 1761 return 0; 1762 1763 err_gmac_powerdown: 1764 rk_gmac_powerdown(plat_dat->bsp_priv); 1765 1766 return ret; 1767 } 1768 1769 static void rk_gmac_remove(struct platform_device *pdev) 1770 { 1771 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 1772 1773 stmmac_dvr_remove(&pdev->dev); 1774 1775 rk_gmac_powerdown(bsp_priv); 1776 } 1777 1778 #ifdef CONFIG_PM_SLEEP 1779 static int rk_gmac_suspend(struct device *dev) 1780 { 1781 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1782 int ret = stmmac_suspend(dev); 1783 1784 /* Keep the PHY up if we use Wake-on-Lan. */ 1785 if (!device_may_wakeup(dev)) { 1786 rk_gmac_powerdown(bsp_priv); 1787 bsp_priv->suspended = true; 1788 } 1789 1790 return ret; 1791 } 1792 1793 static int rk_gmac_resume(struct device *dev) 1794 { 1795 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1796 1797 /* The PHY was up for Wake-on-Lan. */ 1798 if (bsp_priv->suspended) { 1799 rk_gmac_powerup(bsp_priv); 1800 bsp_priv->suspended = false; 1801 } 1802 1803 return stmmac_resume(dev); 1804 } 1805 #endif /* CONFIG_PM_SLEEP */ 1806 1807 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1808 1809 static const struct of_device_id rk_gmac_dwmac_match[] = { 1810 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1811 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1812 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1813 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1814 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1815 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1816 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1817 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1818 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1819 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1820 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1821 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1822 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1823 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1824 { } 1825 }; 1826 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1827 1828 static struct platform_driver rk_gmac_dwmac_driver = { 1829 .probe = rk_gmac_probe, 1830 .remove = rk_gmac_remove, 1831 .driver = { 1832 .name = "rk_gmac-dwmac", 1833 .pm = &rk_gmac_pm_ops, 1834 .of_match_table = rk_gmac_dwmac_match, 1835 }, 1836 }; 1837 module_platform_driver(rk_gmac_dwmac_driver); 1838 1839 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1840 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1841 MODULE_LICENSE("GPL"); 1842