1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/phy.h> 14 #include <linux/of_net.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 24 #include "stmmac_platform.h" 25 26 struct rk_priv_data; 27 28 struct rk_reg_speed_data { 29 unsigned int rgmii_10; 30 unsigned int rgmii_100; 31 unsigned int rgmii_1000; 32 unsigned int rmii_10; 33 unsigned int rmii_100; 34 }; 35 36 struct rk_gmac_ops { 37 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 38 int tx_delay, int rx_delay); 39 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 40 int (*set_speed)(struct rk_priv_data *bsp_priv, 41 phy_interface_t interface, int speed); 42 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 43 bool enable); 44 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 46 bool php_grf_required; 47 bool regs_valid; 48 u32 regs[]; 49 }; 50 51 static const char * const rk_clocks[] = { 52 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 53 }; 54 55 static const char * const rk_rmii_clocks[] = { 56 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 57 }; 58 59 enum rk_clocks_index { 60 RK_ACLK_MAC = 0, 61 RK_PCLK_MAC, 62 RK_MAC_CLK_TX, 63 RK_CLK_MAC_SPEED, 64 RK_MAC_CLK_RX, 65 RK_CLK_MAC_REF, 66 RK_CLK_MAC_REFOUT, 67 }; 68 69 struct rk_priv_data { 70 struct device *dev; 71 phy_interface_t phy_iface; 72 int id; 73 struct regulator *regulator; 74 bool suspended; 75 const struct rk_gmac_ops *ops; 76 77 bool clk_enabled; 78 bool clock_input; 79 bool integrated_phy; 80 81 struct clk_bulk_data *clks; 82 int num_clks; 83 struct clk *clk_phy; 84 85 struct reset_control *phy_reset; 86 87 int tx_delay; 88 int rx_delay; 89 90 struct regmap *grf; 91 struct regmap *php_grf; 92 }; 93 94 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 95 const struct rk_reg_speed_data *rsd, 96 unsigned int reg, phy_interface_t interface, 97 int speed) 98 { 99 unsigned int val; 100 101 if (phy_interface_mode_is_rgmii(interface)) { 102 if (speed == SPEED_10) { 103 val = rsd->rgmii_10; 104 } else if (speed == SPEED_100) { 105 val = rsd->rgmii_100; 106 } else if (speed == SPEED_1000) { 107 val = rsd->rgmii_1000; 108 } else { 109 /* Phylink will not allow inappropriate speeds for 110 * interface modes, so this should never happen. 111 */ 112 return -EINVAL; 113 } 114 } else if (interface == PHY_INTERFACE_MODE_RMII) { 115 if (speed == SPEED_10) { 116 val = rsd->rmii_10; 117 } else if (speed == SPEED_100) { 118 val = rsd->rmii_100; 119 } else { 120 /* Phylink will not allow inappropriate speeds for 121 * interface modes, so this should never happen. 122 */ 123 return -EINVAL; 124 } 125 } else { 126 /* This should never happen, as .get_interfaces() limits 127 * the interface modes that are supported to RGMII and/or 128 * RMII. 129 */ 130 return -EINVAL; 131 } 132 133 regmap_write(bsp_priv->grf, reg, val); 134 135 return 0; 136 137 } 138 139 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, 140 phy_interface_t interface, int speed) 141 { 142 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 143 long rate; 144 145 rate = rgmii_clock(speed); 146 if (rate < 0) 147 return rate; 148 149 return clk_set_rate(clk_mac_speed, rate); 150 } 151 152 #define HIWORD_UPDATE(val, mask, shift) \ 153 ((val) << (shift) | (mask) << ((shift) + 16)) 154 155 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 156 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 157 158 #define DELAY_ENABLE(soc, tx, rx) \ 159 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 160 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 161 162 #define RK_GRF_MACPHY_CON0 0xb00 163 #define RK_GRF_MACPHY_CON1 0xb04 164 #define RK_GRF_MACPHY_CON2 0xb08 165 #define RK_GRF_MACPHY_CON3 0xb0c 166 167 #define RK_MACPHY_ENABLE GRF_BIT(0) 168 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 169 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 170 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 171 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 172 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 173 174 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 175 { 176 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 177 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 178 179 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 180 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 181 182 if (priv->phy_reset) { 183 /* PHY needs to be disabled before trying to reset it */ 184 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 185 if (priv->phy_reset) 186 reset_control_assert(priv->phy_reset); 187 usleep_range(10, 20); 188 if (priv->phy_reset) 189 reset_control_deassert(priv->phy_reset); 190 usleep_range(10, 20); 191 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 192 msleep(30); 193 } 194 } 195 196 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) 197 { 198 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 199 if (priv->phy_reset) 200 reset_control_assert(priv->phy_reset); 201 } 202 203 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 204 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 205 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 206 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) 207 #define RK_FEPHY_PHY_ID GRF_BIT(11) 208 209 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, 210 unsigned int reg) 211 { 212 reset_control_assert(priv->phy_reset); 213 usleep_range(20, 30); 214 215 regmap_write(priv->grf, reg, 216 RK_FEPHY_POWERUP | 217 RK_FEPHY_INTERNAL_RMII_SEL | 218 RK_FEPHY_24M_CLK_SEL | 219 RK_FEPHY_PHY_ID); 220 usleep_range(10000, 12000); 221 222 reset_control_deassert(priv->phy_reset); 223 usleep_range(50000, 60000); 224 } 225 226 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 227 unsigned int reg) 228 { 229 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); 230 } 231 232 #define PX30_GRF_GMAC_CON1 0x0904 233 234 /* PX30_GRF_GMAC_CON1 */ 235 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 236 GRF_BIT(6)) 237 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 238 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 239 240 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 241 { 242 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 243 PX30_GMAC_PHY_INTF_SEL_RMII); 244 } 245 246 static int px30_set_speed(struct rk_priv_data *bsp_priv, 247 phy_interface_t interface, int speed) 248 { 249 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 250 struct device *dev = bsp_priv->dev; 251 unsigned int con1; 252 long rate; 253 254 if (!clk_mac_speed) { 255 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 256 return -EINVAL; 257 } 258 259 if (speed == 10) { 260 con1 = PX30_GMAC_SPEED_10M; 261 rate = 2500000; 262 } else if (speed == 100) { 263 con1 = PX30_GMAC_SPEED_100M; 264 rate = 25000000; 265 } else { 266 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 267 return -EINVAL; 268 } 269 270 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); 271 272 return clk_set_rate(clk_mac_speed, rate); 273 } 274 275 static const struct rk_gmac_ops px30_ops = { 276 .set_to_rmii = px30_set_to_rmii, 277 .set_speed = px30_set_speed, 278 }; 279 280 #define RK3128_GRF_MAC_CON0 0x0168 281 #define RK3128_GRF_MAC_CON1 0x016c 282 283 /* RK3128_GRF_MAC_CON0 */ 284 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 285 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 286 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 287 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 288 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 289 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 290 291 /* RK3128_GRF_MAC_CON1 */ 292 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 293 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 294 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 295 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 296 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 297 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 298 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 299 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 300 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 301 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 302 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 303 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 304 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 305 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 306 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 307 308 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 309 int tx_delay, int rx_delay) 310 { 311 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 312 RK3128_GMAC_PHY_INTF_SEL_RGMII | 313 RK3128_GMAC_RMII_MODE_CLR); 314 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 315 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 316 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 317 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 318 } 319 320 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 321 { 322 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 323 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 324 } 325 326 static const struct rk_reg_speed_data rk3128_reg_speed_data = { 327 .rgmii_10 = RK3128_GMAC_CLK_2_5M, 328 .rgmii_100 = RK3128_GMAC_CLK_25M, 329 .rgmii_1000 = RK3128_GMAC_CLK_125M, 330 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 331 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 332 }; 333 334 static int rk3128_set_speed(struct rk_priv_data *bsp_priv, 335 phy_interface_t interface, int speed) 336 { 337 return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data, 338 RK3128_GRF_MAC_CON1, interface, speed); 339 } 340 341 static const struct rk_gmac_ops rk3128_ops = { 342 .set_to_rgmii = rk3128_set_to_rgmii, 343 .set_to_rmii = rk3128_set_to_rmii, 344 .set_speed = rk3128_set_speed, 345 }; 346 347 #define RK3228_GRF_MAC_CON0 0x0900 348 #define RK3228_GRF_MAC_CON1 0x0904 349 350 #define RK3228_GRF_CON_MUX 0x50 351 352 /* RK3228_GRF_MAC_CON0 */ 353 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 354 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 355 356 /* RK3228_GRF_MAC_CON1 */ 357 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 358 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 359 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 360 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 361 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 362 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 363 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 364 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 365 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 366 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 367 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 368 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 369 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 370 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 371 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 372 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 373 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 374 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 375 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 376 377 /* RK3228_GRF_COM_MUX */ 378 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 379 380 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 381 int tx_delay, int rx_delay) 382 { 383 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 384 RK3228_GMAC_PHY_INTF_SEL_RGMII | 385 RK3228_GMAC_RMII_MODE_CLR | 386 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 387 388 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 389 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 390 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 391 } 392 393 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 394 { 395 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 396 RK3228_GMAC_PHY_INTF_SEL_RMII | 397 RK3228_GMAC_RMII_MODE); 398 399 /* set MAC to RMII mode */ 400 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 401 } 402 403 static const struct rk_reg_speed_data rk3228_reg_speed_data = { 404 .rgmii_10 = RK3228_GMAC_CLK_2_5M, 405 .rgmii_100 = RK3228_GMAC_CLK_25M, 406 .rgmii_1000 = RK3228_GMAC_CLK_125M, 407 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 408 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 409 }; 410 411 static int rk3228_set_speed(struct rk_priv_data *bsp_priv, 412 phy_interface_t interface, int speed) 413 { 414 return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data, 415 RK3228_GRF_MAC_CON1, interface, speed); 416 } 417 418 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 419 { 420 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 421 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 422 423 rk_gmac_integrated_ephy_powerup(priv); 424 } 425 426 static const struct rk_gmac_ops rk3228_ops = { 427 .set_to_rgmii = rk3228_set_to_rgmii, 428 .set_to_rmii = rk3228_set_to_rmii, 429 .set_speed = rk3228_set_speed, 430 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 431 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 432 }; 433 434 #define RK3288_GRF_SOC_CON1 0x0248 435 #define RK3288_GRF_SOC_CON3 0x0250 436 437 /*RK3288_GRF_SOC_CON1*/ 438 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 439 GRF_CLR_BIT(8)) 440 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 441 GRF_BIT(8)) 442 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 443 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 444 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 445 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 446 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 447 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 448 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 449 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 450 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 451 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 452 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 453 454 /*RK3288_GRF_SOC_CON3*/ 455 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 456 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 457 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 458 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 459 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 460 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 461 462 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 463 int tx_delay, int rx_delay) 464 { 465 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 466 RK3288_GMAC_PHY_INTF_SEL_RGMII | 467 RK3288_GMAC_RMII_MODE_CLR); 468 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 469 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 470 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 471 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 472 } 473 474 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 475 { 476 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 477 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 478 } 479 480 static const struct rk_reg_speed_data rk3288_reg_speed_data = { 481 .rgmii_10 = RK3288_GMAC_CLK_2_5M, 482 .rgmii_100 = RK3288_GMAC_CLK_25M, 483 .rgmii_1000 = RK3288_GMAC_CLK_125M, 484 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 485 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 486 }; 487 488 static int rk3288_set_speed(struct rk_priv_data *bsp_priv, 489 phy_interface_t interface, int speed) 490 { 491 return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data, 492 RK3288_GRF_SOC_CON1, interface, speed); 493 } 494 495 static const struct rk_gmac_ops rk3288_ops = { 496 .set_to_rgmii = rk3288_set_to_rgmii, 497 .set_to_rmii = rk3288_set_to_rmii, 498 .set_speed = rk3288_set_speed, 499 }; 500 501 #define RK3308_GRF_MAC_CON0 0x04a0 502 503 /* RK3308_GRF_MAC_CON0 */ 504 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 505 GRF_BIT(4)) 506 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 507 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 508 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 509 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 510 511 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 512 { 513 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 514 RK3308_GMAC_PHY_INTF_SEL_RMII); 515 } 516 517 static const struct rk_reg_speed_data rk3308_reg_speed_data = { 518 .rmii_10 = RK3308_GMAC_SPEED_10M, 519 .rmii_100 = RK3308_GMAC_SPEED_100M, 520 }; 521 522 static int rk3308_set_speed(struct rk_priv_data *bsp_priv, 523 phy_interface_t interface, int speed) 524 { 525 return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, 526 RK3308_GRF_MAC_CON0, interface, speed); 527 } 528 529 static const struct rk_gmac_ops rk3308_ops = { 530 .set_to_rmii = rk3308_set_to_rmii, 531 .set_speed = rk3308_set_speed, 532 }; 533 534 #define RK3328_GRF_MAC_CON0 0x0900 535 #define RK3328_GRF_MAC_CON1 0x0904 536 #define RK3328_GRF_MAC_CON2 0x0908 537 #define RK3328_GRF_MACPHY_CON1 0xb04 538 539 /* RK3328_GRF_MAC_CON0 */ 540 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 541 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 542 543 /* RK3328_GRF_MAC_CON1 */ 544 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 545 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 546 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 547 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 548 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 549 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 550 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 551 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 552 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 553 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 554 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 555 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 556 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 557 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 558 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 559 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 560 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 561 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 562 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 563 564 /* RK3328_GRF_MACPHY_CON1 */ 565 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 566 567 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 568 int tx_delay, int rx_delay) 569 { 570 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 571 RK3328_GMAC_PHY_INTF_SEL_RGMII | 572 RK3328_GMAC_RMII_MODE_CLR | 573 RK3328_GMAC_RXCLK_DLY_ENABLE | 574 RK3328_GMAC_TXCLK_DLY_ENABLE); 575 576 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 577 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 578 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 579 } 580 581 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 582 { 583 unsigned int reg; 584 585 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 586 RK3328_GRF_MAC_CON1; 587 588 regmap_write(bsp_priv->grf, reg, 589 RK3328_GMAC_PHY_INTF_SEL_RMII | 590 RK3328_GMAC_RMII_MODE); 591 } 592 593 static const struct rk_reg_speed_data rk3328_reg_speed_data = { 594 .rgmii_10 = RK3328_GMAC_CLK_2_5M, 595 .rgmii_100 = RK3328_GMAC_CLK_25M, 596 .rgmii_1000 = RK3328_GMAC_CLK_125M, 597 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 598 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 599 }; 600 601 static int rk3328_set_speed(struct rk_priv_data *bsp_priv, 602 phy_interface_t interface, int speed) 603 { 604 unsigned int reg; 605 606 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy) 607 reg = RK3328_GRF_MAC_CON2; 608 else 609 reg = RK3328_GRF_MAC_CON1; 610 611 return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg, 612 interface, speed); 613 } 614 615 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 616 { 617 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 618 RK3328_MACPHY_RMII_MODE); 619 620 rk_gmac_integrated_ephy_powerup(priv); 621 } 622 623 static const struct rk_gmac_ops rk3328_ops = { 624 .set_to_rgmii = rk3328_set_to_rgmii, 625 .set_to_rmii = rk3328_set_to_rmii, 626 .set_speed = rk3328_set_speed, 627 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 628 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 629 }; 630 631 #define RK3366_GRF_SOC_CON6 0x0418 632 #define RK3366_GRF_SOC_CON7 0x041c 633 634 /* RK3366_GRF_SOC_CON6 */ 635 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 636 GRF_CLR_BIT(11)) 637 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 638 GRF_BIT(11)) 639 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 640 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 641 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 642 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 643 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 644 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 645 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 646 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 647 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 648 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 649 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 650 651 /* RK3366_GRF_SOC_CON7 */ 652 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 653 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 654 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 655 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 656 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 657 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 658 659 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 660 int tx_delay, int rx_delay) 661 { 662 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 663 RK3366_GMAC_PHY_INTF_SEL_RGMII | 664 RK3366_GMAC_RMII_MODE_CLR); 665 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 666 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 667 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 668 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 669 } 670 671 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 672 { 673 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 674 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 675 } 676 677 static const struct rk_reg_speed_data rk3366_reg_speed_data = { 678 .rgmii_10 = RK3366_GMAC_CLK_2_5M, 679 .rgmii_100 = RK3366_GMAC_CLK_25M, 680 .rgmii_1000 = RK3366_GMAC_CLK_125M, 681 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 682 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 683 }; 684 685 static int rk3366_set_speed(struct rk_priv_data *bsp_priv, 686 phy_interface_t interface, int speed) 687 { 688 return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data, 689 RK3366_GRF_SOC_CON6, interface, speed); 690 } 691 692 static const struct rk_gmac_ops rk3366_ops = { 693 .set_to_rgmii = rk3366_set_to_rgmii, 694 .set_to_rmii = rk3366_set_to_rmii, 695 .set_speed = rk3366_set_speed, 696 }; 697 698 #define RK3368_GRF_SOC_CON15 0x043c 699 #define RK3368_GRF_SOC_CON16 0x0440 700 701 /* RK3368_GRF_SOC_CON15 */ 702 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 703 GRF_CLR_BIT(11)) 704 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 705 GRF_BIT(11)) 706 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 707 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 708 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 709 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 710 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 711 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 712 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 713 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 714 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 715 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 716 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 717 718 /* RK3368_GRF_SOC_CON16 */ 719 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 720 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 721 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 722 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 723 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 724 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 725 726 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 727 int tx_delay, int rx_delay) 728 { 729 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 730 RK3368_GMAC_PHY_INTF_SEL_RGMII | 731 RK3368_GMAC_RMII_MODE_CLR); 732 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 733 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 734 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 735 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 736 } 737 738 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 739 { 740 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 741 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 742 } 743 744 static const struct rk_reg_speed_data rk3368_reg_speed_data = { 745 .rgmii_10 = RK3368_GMAC_CLK_2_5M, 746 .rgmii_100 = RK3368_GMAC_CLK_25M, 747 .rgmii_1000 = RK3368_GMAC_CLK_125M, 748 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 749 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 750 }; 751 752 static int rk3368_set_speed(struct rk_priv_data *bsp_priv, 753 phy_interface_t interface, int speed) 754 { 755 return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data, 756 RK3368_GRF_SOC_CON15, interface, speed); 757 } 758 759 static const struct rk_gmac_ops rk3368_ops = { 760 .set_to_rgmii = rk3368_set_to_rgmii, 761 .set_to_rmii = rk3368_set_to_rmii, 762 .set_speed = rk3368_set_speed, 763 }; 764 765 #define RK3399_GRF_SOC_CON5 0xc214 766 #define RK3399_GRF_SOC_CON6 0xc218 767 768 /* RK3399_GRF_SOC_CON5 */ 769 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 770 GRF_CLR_BIT(11)) 771 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 772 GRF_BIT(11)) 773 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 774 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 775 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 776 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 777 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 778 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 779 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 780 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 781 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 782 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 783 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 784 785 /* RK3399_GRF_SOC_CON6 */ 786 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 787 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 788 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 789 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 790 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 791 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 792 793 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 794 int tx_delay, int rx_delay) 795 { 796 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 797 RK3399_GMAC_PHY_INTF_SEL_RGMII | 798 RK3399_GMAC_RMII_MODE_CLR); 799 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 800 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 801 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 802 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 803 } 804 805 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 806 { 807 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 808 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 809 } 810 811 static const struct rk_reg_speed_data rk3399_reg_speed_data = { 812 .rgmii_10 = RK3399_GMAC_CLK_2_5M, 813 .rgmii_100 = RK3399_GMAC_CLK_25M, 814 .rgmii_1000 = RK3399_GMAC_CLK_125M, 815 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 816 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 817 }; 818 819 static int rk3399_set_speed(struct rk_priv_data *bsp_priv, 820 phy_interface_t interface, int speed) 821 { 822 return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data, 823 RK3399_GRF_SOC_CON5, interface, speed); 824 } 825 826 static const struct rk_gmac_ops rk3399_ops = { 827 .set_to_rgmii = rk3399_set_to_rgmii, 828 .set_to_rmii = rk3399_set_to_rmii, 829 .set_speed = rk3399_set_speed, 830 }; 831 832 #define RK3528_VO_GRF_GMAC_CON 0x0018 833 #define RK3528_VO_GRF_MACPHY_CON0 0x001c 834 #define RK3528_VO_GRF_MACPHY_CON1 0x0020 835 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 836 #define RK3528_VPU_GRF_GMAC_CON6 0x001c 837 838 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 839 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 840 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 841 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 842 843 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 844 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 845 846 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 847 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 848 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 849 850 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 851 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 852 853 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) 854 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) 855 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 856 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 857 858 #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) 859 #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) 860 #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) 861 862 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 863 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 864 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 865 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 866 867 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 868 int tx_delay, int rx_delay) 869 { 870 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 871 RK3528_GMAC1_PHY_INTF_SEL_RGMII); 872 873 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 874 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 875 876 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 877 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 878 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 879 } 880 881 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 882 { 883 if (bsp_priv->id == 1) 884 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 885 RK3528_GMAC1_PHY_INTF_SEL_RMII); 886 else 887 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 888 RK3528_GMAC0_PHY_INTF_SEL_RMII | 889 RK3528_GMAC0_CLK_RMII_DIV2); 890 } 891 892 static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = { 893 .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20, 894 .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2, 895 }; 896 897 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 898 .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50, 899 .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5, 900 .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1, 901 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 902 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 903 }; 904 905 static int rk3528_set_speed(struct rk_priv_data *bsp_priv, 906 phy_interface_t interface, int speed) 907 { 908 const struct rk_reg_speed_data *rsd; 909 unsigned int reg; 910 911 if (bsp_priv->id == 1) { 912 rsd = &rk3528_gmac1_reg_speed_data; 913 reg = RK3528_VPU_GRF_GMAC_CON5; 914 } else { 915 rsd = &rk3528_gmac0_reg_speed_data; 916 reg = RK3528_VO_GRF_GMAC_CON; 917 } 918 919 return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed); 920 } 921 922 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 923 bool input, bool enable) 924 { 925 unsigned int val; 926 927 if (bsp_priv->id == 1) { 928 val = input ? RK3528_GMAC1_CLK_SELECT_IO : 929 RK3528_GMAC1_CLK_SELECT_CRU; 930 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 931 RK3528_GMAC1_CLK_RMII_GATE; 932 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 933 } else { 934 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 935 RK3528_GMAC0_CLK_RMII_GATE; 936 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 937 } 938 } 939 940 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) 941 { 942 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 943 } 944 945 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) 946 { 947 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 948 } 949 950 static const struct rk_gmac_ops rk3528_ops = { 951 .set_to_rgmii = rk3528_set_to_rgmii, 952 .set_to_rmii = rk3528_set_to_rmii, 953 .set_speed = rk3528_set_speed, 954 .set_clock_selection = rk3528_set_clock_selection, 955 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 956 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 957 .regs_valid = true, 958 .regs = { 959 0xffbd0000, /* gmac0 */ 960 0xffbe0000, /* gmac1 */ 961 0x0, /* sentinel */ 962 }, 963 }; 964 965 #define RK3568_GRF_GMAC0_CON0 0x0380 966 #define RK3568_GRF_GMAC0_CON1 0x0384 967 #define RK3568_GRF_GMAC1_CON0 0x0388 968 #define RK3568_GRF_GMAC1_CON1 0x038c 969 970 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 971 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 972 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 973 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 974 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 975 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 976 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 977 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 978 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 979 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 980 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 981 982 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 983 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 984 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 985 986 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 987 int tx_delay, int rx_delay) 988 { 989 u32 con0, con1; 990 991 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 992 RK3568_GRF_GMAC0_CON0; 993 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 994 RK3568_GRF_GMAC0_CON1; 995 996 regmap_write(bsp_priv->grf, con0, 997 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 998 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 999 1000 regmap_write(bsp_priv->grf, con1, 1001 RK3568_GMAC_PHY_INTF_SEL_RGMII | 1002 RK3568_GMAC_RXCLK_DLY_ENABLE | 1003 RK3568_GMAC_TXCLK_DLY_ENABLE); 1004 } 1005 1006 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1007 { 1008 u32 con1; 1009 1010 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1011 RK3568_GRF_GMAC0_CON1; 1012 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1013 } 1014 1015 static const struct rk_gmac_ops rk3568_ops = { 1016 .set_to_rgmii = rk3568_set_to_rgmii, 1017 .set_to_rmii = rk3568_set_to_rmii, 1018 .set_speed = rk_set_clk_mac_speed, 1019 .regs_valid = true, 1020 .regs = { 1021 0xfe2a0000, /* gmac0 */ 1022 0xfe010000, /* gmac1 */ 1023 0x0, /* sentinel */ 1024 }, 1025 }; 1026 1027 /* VCCIO0_1_3_IOC */ 1028 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 1029 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 1030 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 1031 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 1032 1033 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 1034 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 1035 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1036 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1037 1038 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1039 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1040 1041 /* SDGMAC_GRF */ 1042 #define RK3576_GRF_GMAC_CON0 0X0020 1043 #define RK3576_GRF_GMAC_CON1 0X0024 1044 1045 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 1046 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 1047 1048 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 1049 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 1050 1051 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1052 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1053 1054 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1055 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1056 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1057 (GRF_BIT(6) | GRF_BIT(5)) 1058 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1059 (GRF_BIT(6) | GRF_CLR_BIT(5)) 1060 1061 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1062 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1063 1064 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 1065 int tx_delay, int rx_delay) 1066 { 1067 unsigned int offset_con; 1068 1069 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1070 RK3576_GRF_GMAC_CON0; 1071 1072 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 1073 1074 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 1075 RK3576_VCCIO0_1_3_IOC_CON2; 1076 1077 /* m0 && m1 delay enabled */ 1078 regmap_write(bsp_priv->php_grf, offset_con, 1079 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1080 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1081 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1082 1083 /* m0 && m1 delay value */ 1084 regmap_write(bsp_priv->php_grf, offset_con, 1085 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1086 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1087 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1088 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1089 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1090 } 1091 1092 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 1093 { 1094 unsigned int offset_con; 1095 1096 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1097 RK3576_GRF_GMAC_CON0; 1098 1099 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 1100 } 1101 1102 static const struct rk_reg_speed_data rk3578_reg_speed_data = { 1103 .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50, 1104 .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5, 1105 .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1, 1106 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 1107 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 1108 }; 1109 1110 static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, 1111 phy_interface_t interface, int speed) 1112 { 1113 unsigned int offset_con; 1114 1115 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1116 RK3576_GRF_GMAC_CON0; 1117 1118 return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con, 1119 interface, speed); 1120 } 1121 1122 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1123 bool enable) 1124 { 1125 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1126 RK3576_GMAC_CLK_SELECT_CRU; 1127 unsigned int offset_con; 1128 1129 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1130 RK3576_GMAC_CLK_RMII_GATE; 1131 1132 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1133 RK3576_GRF_GMAC_CON0; 1134 1135 regmap_write(bsp_priv->grf, offset_con, val); 1136 } 1137 1138 static const struct rk_gmac_ops rk3576_ops = { 1139 .set_to_rgmii = rk3576_set_to_rgmii, 1140 .set_to_rmii = rk3576_set_to_rmii, 1141 .set_speed = rk3576_set_gmac_speed, 1142 .set_clock_selection = rk3576_set_clock_selection, 1143 .php_grf_required = true, 1144 .regs_valid = true, 1145 .regs = { 1146 0x2a220000, /* gmac0 */ 1147 0x2a230000, /* gmac1 */ 1148 0x0, /* sentinel */ 1149 }, 1150 }; 1151 1152 /* sys_grf */ 1153 #define RK3588_GRF_GMAC_CON7 0X031c 1154 #define RK3588_GRF_GMAC_CON8 0X0320 1155 #define RK3588_GRF_GMAC_CON9 0X0324 1156 1157 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1158 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1159 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1160 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1161 1162 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1163 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1164 1165 /* php_grf */ 1166 #define RK3588_GRF_GMAC_CON0 0X0008 1167 #define RK3588_GRF_CLK_CON1 0X0070 1168 1169 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1170 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1171 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1172 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1173 1174 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1175 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1176 1177 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1178 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1179 1180 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1181 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1182 1183 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1184 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1185 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1186 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1187 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1188 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1189 1190 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1191 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1192 1193 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1194 int tx_delay, int rx_delay) 1195 { 1196 u32 offset_con, id = bsp_priv->id; 1197 1198 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1199 RK3588_GRF_GMAC_CON8; 1200 1201 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1202 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1203 1204 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1205 RK3588_GMAC_CLK_RGMII_MODE(id)); 1206 1207 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1208 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1209 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1210 1211 regmap_write(bsp_priv->grf, offset_con, 1212 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1213 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1214 } 1215 1216 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1217 { 1218 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1219 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1220 1221 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1222 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1223 } 1224 1225 static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, 1226 phy_interface_t interface, int speed) 1227 { 1228 unsigned int val = 0, id = bsp_priv->id; 1229 1230 switch (speed) { 1231 case 10: 1232 if (interface == PHY_INTERFACE_MODE_RMII) 1233 val = RK3588_GMA_CLK_RMII_DIV20(id); 1234 else 1235 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1236 break; 1237 case 100: 1238 if (interface == PHY_INTERFACE_MODE_RMII) 1239 val = RK3588_GMA_CLK_RMII_DIV2(id); 1240 else 1241 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1242 break; 1243 case 1000: 1244 if (interface != PHY_INTERFACE_MODE_RMII) 1245 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1246 else 1247 goto err; 1248 break; 1249 default: 1250 goto err; 1251 } 1252 1253 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1254 1255 return 0; 1256 err: 1257 return -EINVAL; 1258 } 1259 1260 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1261 bool enable) 1262 { 1263 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1264 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1265 1266 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1267 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1268 1269 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1270 } 1271 1272 static const struct rk_gmac_ops rk3588_ops = { 1273 .set_to_rgmii = rk3588_set_to_rgmii, 1274 .set_to_rmii = rk3588_set_to_rmii, 1275 .set_speed = rk3588_set_gmac_speed, 1276 .set_clock_selection = rk3588_set_clock_selection, 1277 .php_grf_required = true, 1278 .regs_valid = true, 1279 .regs = { 1280 0xfe1b0000, /* gmac0 */ 1281 0xfe1c0000, /* gmac1 */ 1282 0x0, /* sentinel */ 1283 }, 1284 }; 1285 1286 #define RV1108_GRF_GMAC_CON0 0X0900 1287 1288 /* RV1108_GRF_GMAC_CON0 */ 1289 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1290 GRF_BIT(6)) 1291 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1292 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1293 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1294 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1295 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1296 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1297 1298 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1299 { 1300 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1301 RV1108_GMAC_PHY_INTF_SEL_RMII); 1302 } 1303 1304 static const struct rk_reg_speed_data rv1108_reg_speed_data = { 1305 .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M, 1306 .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M, 1307 }; 1308 1309 static int rv1108_set_speed(struct rk_priv_data *bsp_priv, 1310 phy_interface_t interface, int speed) 1311 { 1312 return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data, 1313 RV1108_GRF_GMAC_CON0, interface, speed); 1314 } 1315 1316 static const struct rk_gmac_ops rv1108_ops = { 1317 .set_to_rmii = rv1108_set_to_rmii, 1318 .set_speed = rv1108_set_speed, 1319 }; 1320 1321 #define RV1126_GRF_GMAC_CON0 0X0070 1322 #define RV1126_GRF_GMAC_CON1 0X0074 1323 #define RV1126_GRF_GMAC_CON2 0X0078 1324 1325 /* RV1126_GRF_GMAC_CON0 */ 1326 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1327 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1328 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1329 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1330 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1331 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1332 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1333 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1334 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1335 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1336 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1337 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1338 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1339 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1340 1341 /* RV1126_GRF_GMAC_CON1 */ 1342 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1343 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1344 /* RV1126_GRF_GMAC_CON2 */ 1345 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1346 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1347 1348 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1349 int tx_delay, int rx_delay) 1350 { 1351 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1352 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1353 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1354 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1355 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1356 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1357 1358 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1359 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1360 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1361 1362 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1363 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1364 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1365 } 1366 1367 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1368 { 1369 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1370 RV1126_GMAC_PHY_INTF_SEL_RMII); 1371 } 1372 1373 static const struct rk_gmac_ops rv1126_ops = { 1374 .set_to_rgmii = rv1126_set_to_rgmii, 1375 .set_to_rmii = rv1126_set_to_rmii, 1376 .set_speed = rk_set_clk_mac_speed, 1377 }; 1378 1379 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1380 { 1381 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1382 int phy_iface = bsp_priv->phy_iface; 1383 struct device *dev = bsp_priv->dev; 1384 int i, j, ret; 1385 1386 bsp_priv->clk_enabled = false; 1387 1388 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1389 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1390 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1391 1392 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1393 sizeof(*bsp_priv->clks), GFP_KERNEL); 1394 if (!bsp_priv->clks) 1395 return -ENOMEM; 1396 1397 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1398 bsp_priv->clks[i].id = rk_clocks[i]; 1399 1400 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1401 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1402 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1403 } 1404 1405 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1406 bsp_priv->clks); 1407 if (ret) 1408 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1409 1410 if (bsp_priv->clock_input) { 1411 dev_info(dev, "clock input from PHY\n"); 1412 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1413 clk_set_rate(plat->stmmac_clk, 50000000); 1414 } 1415 1416 if (plat->phy_node && bsp_priv->integrated_phy) { 1417 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1418 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1419 if (ret) 1420 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1421 clk_set_rate(bsp_priv->clk_phy, 50000000); 1422 } 1423 1424 return 0; 1425 } 1426 1427 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1428 { 1429 int ret; 1430 1431 if (enable) { 1432 if (!bsp_priv->clk_enabled) { 1433 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1434 bsp_priv->clks); 1435 if (ret) 1436 return ret; 1437 1438 ret = clk_prepare_enable(bsp_priv->clk_phy); 1439 if (ret) 1440 return ret; 1441 1442 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1443 bsp_priv->ops->set_clock_selection(bsp_priv, 1444 bsp_priv->clock_input, true); 1445 1446 mdelay(5); 1447 bsp_priv->clk_enabled = true; 1448 } 1449 } else { 1450 if (bsp_priv->clk_enabled) { 1451 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1452 bsp_priv->clks); 1453 clk_disable_unprepare(bsp_priv->clk_phy); 1454 1455 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1456 bsp_priv->ops->set_clock_selection(bsp_priv, 1457 bsp_priv->clock_input, false); 1458 1459 bsp_priv->clk_enabled = false; 1460 } 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1467 { 1468 struct regulator *ldo = bsp_priv->regulator; 1469 struct device *dev = bsp_priv->dev; 1470 int ret; 1471 1472 if (enable) { 1473 ret = regulator_enable(ldo); 1474 if (ret) 1475 dev_err(dev, "fail to enable phy-supply\n"); 1476 } else { 1477 ret = regulator_disable(ldo); 1478 if (ret) 1479 dev_err(dev, "fail to disable phy-supply\n"); 1480 } 1481 1482 return 0; 1483 } 1484 1485 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1486 struct plat_stmmacenet_data *plat, 1487 const struct rk_gmac_ops *ops) 1488 { 1489 struct rk_priv_data *bsp_priv; 1490 struct device *dev = &pdev->dev; 1491 struct resource *res; 1492 int ret; 1493 const char *strings = NULL; 1494 int value; 1495 1496 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1497 if (!bsp_priv) 1498 return ERR_PTR(-ENOMEM); 1499 1500 bsp_priv->phy_iface = plat->phy_interface; 1501 bsp_priv->ops = ops; 1502 1503 /* Some SoCs have multiple MAC controllers, which need 1504 * to be distinguished. 1505 */ 1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1507 if (res && ops->regs_valid) { 1508 int i = 0; 1509 1510 while (ops->regs[i]) { 1511 if (ops->regs[i] == res->start) { 1512 bsp_priv->id = i; 1513 break; 1514 } 1515 i++; 1516 } 1517 } 1518 1519 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1520 if (IS_ERR(bsp_priv->regulator)) { 1521 ret = PTR_ERR(bsp_priv->regulator); 1522 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1523 return ERR_PTR(ret); 1524 } 1525 1526 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1527 if (ret) { 1528 dev_err(dev, "Can not read property: clock_in_out.\n"); 1529 bsp_priv->clock_input = true; 1530 } else { 1531 dev_info(dev, "clock input or output? (%s).\n", 1532 strings); 1533 if (!strcmp(strings, "input")) 1534 bsp_priv->clock_input = true; 1535 else 1536 bsp_priv->clock_input = false; 1537 } 1538 1539 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1540 if (ret) { 1541 bsp_priv->tx_delay = 0x30; 1542 dev_err(dev, "Can not read property: tx_delay."); 1543 dev_err(dev, "set tx_delay to 0x%x\n", 1544 bsp_priv->tx_delay); 1545 } else { 1546 dev_info(dev, "TX delay(0x%x).\n", value); 1547 bsp_priv->tx_delay = value; 1548 } 1549 1550 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1551 if (ret) { 1552 bsp_priv->rx_delay = 0x10; 1553 dev_err(dev, "Can not read property: rx_delay."); 1554 dev_err(dev, "set rx_delay to 0x%x\n", 1555 bsp_priv->rx_delay); 1556 } else { 1557 dev_info(dev, "RX delay(0x%x).\n", value); 1558 bsp_priv->rx_delay = value; 1559 } 1560 1561 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1562 "rockchip,grf"); 1563 if (IS_ERR(bsp_priv->grf)) { 1564 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1565 "failed to lookup rockchip,grf\n"); 1566 return ERR_CAST(bsp_priv->grf); 1567 } 1568 1569 if (ops->php_grf_required) { 1570 bsp_priv->php_grf = 1571 syscon_regmap_lookup_by_phandle(dev->of_node, 1572 "rockchip,php-grf"); 1573 if (IS_ERR(bsp_priv->php_grf)) { 1574 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1575 "failed to lookup rockchip,php-grf\n"); 1576 return ERR_CAST(bsp_priv->php_grf); 1577 } 1578 } 1579 1580 if (plat->phy_node) { 1581 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1582 "phy-is-integrated"); 1583 if (bsp_priv->integrated_phy) { 1584 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1585 if (IS_ERR(bsp_priv->phy_reset)) { 1586 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1587 bsp_priv->phy_reset = NULL; 1588 } 1589 } 1590 } 1591 dev_info(dev, "integrated PHY? (%s).\n", 1592 bsp_priv->integrated_phy ? "yes" : "no"); 1593 1594 bsp_priv->dev = dev; 1595 1596 return bsp_priv; 1597 } 1598 1599 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1600 { 1601 switch (bsp_priv->phy_iface) { 1602 case PHY_INTERFACE_MODE_RGMII: 1603 case PHY_INTERFACE_MODE_RGMII_ID: 1604 case PHY_INTERFACE_MODE_RGMII_RXID: 1605 case PHY_INTERFACE_MODE_RGMII_TXID: 1606 if (!bsp_priv->ops->set_to_rgmii) 1607 return -EINVAL; 1608 break; 1609 case PHY_INTERFACE_MODE_RMII: 1610 if (!bsp_priv->ops->set_to_rmii) 1611 return -EINVAL; 1612 break; 1613 default: 1614 dev_err(bsp_priv->dev, 1615 "unsupported interface %d", bsp_priv->phy_iface); 1616 } 1617 return 0; 1618 } 1619 1620 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1621 { 1622 struct device *dev = bsp_priv->dev; 1623 int ret; 1624 1625 ret = rk_gmac_check_ops(bsp_priv); 1626 if (ret) 1627 return ret; 1628 1629 ret = gmac_clk_enable(bsp_priv, true); 1630 if (ret) 1631 return ret; 1632 1633 /*rmii or rgmii*/ 1634 switch (bsp_priv->phy_iface) { 1635 case PHY_INTERFACE_MODE_RGMII: 1636 dev_info(dev, "init for RGMII\n"); 1637 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1638 bsp_priv->rx_delay); 1639 break; 1640 case PHY_INTERFACE_MODE_RGMII_ID: 1641 dev_info(dev, "init for RGMII_ID\n"); 1642 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1643 break; 1644 case PHY_INTERFACE_MODE_RGMII_RXID: 1645 dev_info(dev, "init for RGMII_RXID\n"); 1646 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1647 break; 1648 case PHY_INTERFACE_MODE_RGMII_TXID: 1649 dev_info(dev, "init for RGMII_TXID\n"); 1650 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1651 break; 1652 case PHY_INTERFACE_MODE_RMII: 1653 dev_info(dev, "init for RMII\n"); 1654 bsp_priv->ops->set_to_rmii(bsp_priv); 1655 break; 1656 default: 1657 dev_err(dev, "NO interface defined!\n"); 1658 } 1659 1660 ret = phy_power_on(bsp_priv, true); 1661 if (ret) { 1662 gmac_clk_enable(bsp_priv, false); 1663 return ret; 1664 } 1665 1666 pm_runtime_get_sync(dev); 1667 1668 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) 1669 bsp_priv->ops->integrated_phy_powerup(bsp_priv); 1670 1671 return 0; 1672 } 1673 1674 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1675 { 1676 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) 1677 gmac->ops->integrated_phy_powerdown(gmac); 1678 1679 pm_runtime_put_sync(gmac->dev); 1680 1681 phy_power_on(gmac, false); 1682 gmac_clk_enable(gmac, false); 1683 } 1684 1685 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 1686 unsigned long *interfaces) 1687 { 1688 struct rk_priv_data *rk = bsp_priv; 1689 1690 if (rk->ops->set_to_rgmii) 1691 phy_interface_set_rgmii(interfaces); 1692 1693 if (rk->ops->set_to_rmii) 1694 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1695 } 1696 1697 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1698 phy_interface_t interface, int speed) 1699 { 1700 struct rk_priv_data *bsp_priv = bsp_priv_; 1701 1702 if (bsp_priv->ops->set_speed) 1703 return bsp_priv->ops->set_speed(bsp_priv, bsp_priv->phy_iface, 1704 speed); 1705 1706 return -EINVAL; 1707 } 1708 1709 static int rk_gmac_probe(struct platform_device *pdev) 1710 { 1711 struct plat_stmmacenet_data *plat_dat; 1712 struct stmmac_resources stmmac_res; 1713 const struct rk_gmac_ops *data; 1714 int ret; 1715 1716 data = of_device_get_match_data(&pdev->dev); 1717 if (!data) { 1718 dev_err(&pdev->dev, "no of match data provided\n"); 1719 return -EINVAL; 1720 } 1721 1722 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1723 if (ret) 1724 return ret; 1725 1726 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1727 if (IS_ERR(plat_dat)) 1728 return PTR_ERR(plat_dat); 1729 1730 /* If the stmmac is not already selected as gmac4, 1731 * then make sure we fallback to gmac. 1732 */ 1733 if (!plat_dat->has_gmac4) { 1734 plat_dat->has_gmac = true; 1735 plat_dat->rx_fifo_size = 4096; 1736 plat_dat->tx_fifo_size = 2048; 1737 } 1738 1739 plat_dat->get_interfaces = rk_get_interfaces; 1740 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1741 1742 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1743 if (IS_ERR(plat_dat->bsp_priv)) 1744 return PTR_ERR(plat_dat->bsp_priv); 1745 1746 ret = rk_gmac_clk_init(plat_dat); 1747 if (ret) 1748 return ret; 1749 1750 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1751 if (ret) 1752 return ret; 1753 1754 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1755 if (ret) 1756 goto err_gmac_powerdown; 1757 1758 return 0; 1759 1760 err_gmac_powerdown: 1761 rk_gmac_powerdown(plat_dat->bsp_priv); 1762 1763 return ret; 1764 } 1765 1766 static void rk_gmac_remove(struct platform_device *pdev) 1767 { 1768 struct stmmac_priv *priv = netdev_priv(platform_get_drvdata(pdev)); 1769 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv; 1770 1771 stmmac_dvr_remove(&pdev->dev); 1772 1773 rk_gmac_powerdown(bsp_priv); 1774 1775 if (priv->plat->phy_node && bsp_priv->integrated_phy) 1776 clk_put(bsp_priv->clk_phy); 1777 } 1778 1779 #ifdef CONFIG_PM_SLEEP 1780 static int rk_gmac_suspend(struct device *dev) 1781 { 1782 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1783 int ret = stmmac_suspend(dev); 1784 1785 /* Keep the PHY up if we use Wake-on-Lan. */ 1786 if (!device_may_wakeup(dev)) { 1787 rk_gmac_powerdown(bsp_priv); 1788 bsp_priv->suspended = true; 1789 } 1790 1791 return ret; 1792 } 1793 1794 static int rk_gmac_resume(struct device *dev) 1795 { 1796 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1797 1798 /* The PHY was up for Wake-on-Lan. */ 1799 if (bsp_priv->suspended) { 1800 rk_gmac_powerup(bsp_priv); 1801 bsp_priv->suspended = false; 1802 } 1803 1804 return stmmac_resume(dev); 1805 } 1806 #endif /* CONFIG_PM_SLEEP */ 1807 1808 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1809 1810 static const struct of_device_id rk_gmac_dwmac_match[] = { 1811 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1812 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1813 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1814 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1815 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1816 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1817 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1818 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1819 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1820 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, 1821 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1822 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1823 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1824 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1825 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1826 { } 1827 }; 1828 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1829 1830 static struct platform_driver rk_gmac_dwmac_driver = { 1831 .probe = rk_gmac_probe, 1832 .remove = rk_gmac_remove, 1833 .driver = { 1834 .name = "rk_gmac-dwmac", 1835 .pm = &rk_gmac_pm_ops, 1836 .of_match_table = rk_gmac_dwmac_match, 1837 }, 1838 }; 1839 module_platform_driver(rk_gmac_dwmac_driver); 1840 1841 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1842 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1843 MODULE_LICENSE("GPL"); 1844