1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/phy.h> 14 #include <linux/of_net.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 24 #include "stmmac_platform.h" 25 26 struct rk_priv_data; 27 28 struct rk_reg_speed_data { 29 unsigned int rgmii_10; 30 unsigned int rgmii_100; 31 unsigned int rgmii_1000; 32 unsigned int rmii_10; 33 unsigned int rmii_100; 34 }; 35 36 struct rk_gmac_ops { 37 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 38 int tx_delay, int rx_delay); 39 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 40 int (*set_speed)(struct rk_priv_data *bsp_priv, 41 phy_interface_t interface, int speed); 42 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 43 bool enable); 44 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 46 bool php_grf_required; 47 bool regs_valid; 48 u32 regs[]; 49 }; 50 51 static const char * const rk_clocks[] = { 52 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 53 }; 54 55 static const char * const rk_rmii_clocks[] = { 56 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 57 }; 58 59 enum rk_clocks_index { 60 RK_ACLK_MAC = 0, 61 RK_PCLK_MAC, 62 RK_MAC_CLK_TX, 63 RK_CLK_MAC_SPEED, 64 RK_MAC_CLK_RX, 65 RK_CLK_MAC_REF, 66 RK_CLK_MAC_REFOUT, 67 }; 68 69 struct rk_priv_data { 70 struct device *dev; 71 phy_interface_t phy_iface; 72 int id; 73 struct regulator *regulator; 74 const struct rk_gmac_ops *ops; 75 76 bool clk_enabled; 77 bool clock_input; 78 bool integrated_phy; 79 80 struct clk_bulk_data *clks; 81 int num_clks; 82 struct clk *clk_phy; 83 84 struct reset_control *phy_reset; 85 86 int tx_delay; 87 int rx_delay; 88 89 struct regmap *grf; 90 struct regmap *php_grf; 91 }; 92 93 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 94 const struct rk_reg_speed_data *rsd, 95 unsigned int reg, phy_interface_t interface, 96 int speed) 97 { 98 unsigned int val; 99 100 if (phy_interface_mode_is_rgmii(interface)) { 101 if (speed == SPEED_10) { 102 val = rsd->rgmii_10; 103 } else if (speed == SPEED_100) { 104 val = rsd->rgmii_100; 105 } else if (speed == SPEED_1000) { 106 val = rsd->rgmii_1000; 107 } else { 108 /* Phylink will not allow inappropriate speeds for 109 * interface modes, so this should never happen. 110 */ 111 return -EINVAL; 112 } 113 } else if (interface == PHY_INTERFACE_MODE_RMII) { 114 if (speed == SPEED_10) { 115 val = rsd->rmii_10; 116 } else if (speed == SPEED_100) { 117 val = rsd->rmii_100; 118 } else { 119 /* Phylink will not allow inappropriate speeds for 120 * interface modes, so this should never happen. 121 */ 122 return -EINVAL; 123 } 124 } else { 125 /* This should never happen, as .get_interfaces() limits 126 * the interface modes that are supported to RGMII and/or 127 * RMII. 128 */ 129 return -EINVAL; 130 } 131 132 regmap_write(bsp_priv->grf, reg, val); 133 134 return 0; 135 136 } 137 138 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, 139 phy_interface_t interface, int speed) 140 { 141 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 142 long rate; 143 144 rate = rgmii_clock(speed); 145 if (rate < 0) 146 return rate; 147 148 return clk_set_rate(clk_mac_speed, rate); 149 } 150 151 #define HIWORD_UPDATE(val, mask, shift) \ 152 ((val) << (shift) | (mask) << ((shift) + 16)) 153 154 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 155 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 156 157 #define DELAY_ENABLE(soc, tx, rx) \ 158 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 159 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 160 161 #define RK_GRF_MACPHY_CON0 0xb00 162 #define RK_GRF_MACPHY_CON1 0xb04 163 #define RK_GRF_MACPHY_CON2 0xb08 164 #define RK_GRF_MACPHY_CON3 0xb0c 165 166 #define RK_MACPHY_ENABLE GRF_BIT(0) 167 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 168 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 169 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 170 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 171 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 172 173 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 174 { 175 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 176 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 177 178 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 179 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 180 181 if (priv->phy_reset) { 182 /* PHY needs to be disabled before trying to reset it */ 183 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 184 if (priv->phy_reset) 185 reset_control_assert(priv->phy_reset); 186 usleep_range(10, 20); 187 if (priv->phy_reset) 188 reset_control_deassert(priv->phy_reset); 189 usleep_range(10, 20); 190 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 191 msleep(30); 192 } 193 } 194 195 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) 196 { 197 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 198 if (priv->phy_reset) 199 reset_control_assert(priv->phy_reset); 200 } 201 202 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 203 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 204 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 205 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) 206 #define RK_FEPHY_PHY_ID GRF_BIT(11) 207 208 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, 209 unsigned int reg) 210 { 211 reset_control_assert(priv->phy_reset); 212 usleep_range(20, 30); 213 214 regmap_write(priv->grf, reg, 215 RK_FEPHY_POWERUP | 216 RK_FEPHY_INTERNAL_RMII_SEL | 217 RK_FEPHY_24M_CLK_SEL | 218 RK_FEPHY_PHY_ID); 219 usleep_range(10000, 12000); 220 221 reset_control_deassert(priv->phy_reset); 222 usleep_range(50000, 60000); 223 } 224 225 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 226 unsigned int reg) 227 { 228 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); 229 } 230 231 #define PX30_GRF_GMAC_CON1 0x0904 232 233 /* PX30_GRF_GMAC_CON1 */ 234 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 235 GRF_BIT(6)) 236 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 237 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 238 239 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 240 { 241 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 242 PX30_GMAC_PHY_INTF_SEL_RMII); 243 } 244 245 static int px30_set_speed(struct rk_priv_data *bsp_priv, 246 phy_interface_t interface, int speed) 247 { 248 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 249 struct device *dev = bsp_priv->dev; 250 unsigned int con1; 251 long rate; 252 253 if (!clk_mac_speed) { 254 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 255 return -EINVAL; 256 } 257 258 if (speed == 10) { 259 con1 = PX30_GMAC_SPEED_10M; 260 rate = 2500000; 261 } else if (speed == 100) { 262 con1 = PX30_GMAC_SPEED_100M; 263 rate = 25000000; 264 } else { 265 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 266 return -EINVAL; 267 } 268 269 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); 270 271 return clk_set_rate(clk_mac_speed, rate); 272 } 273 274 static const struct rk_gmac_ops px30_ops = { 275 .set_to_rmii = px30_set_to_rmii, 276 .set_speed = px30_set_speed, 277 }; 278 279 #define RK3128_GRF_MAC_CON0 0x0168 280 #define RK3128_GRF_MAC_CON1 0x016c 281 282 /* RK3128_GRF_MAC_CON0 */ 283 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 284 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 285 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 286 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 287 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 288 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 289 290 /* RK3128_GRF_MAC_CON1 */ 291 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 292 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 293 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 294 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 295 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 296 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 297 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 298 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 299 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 300 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 301 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 302 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 303 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 304 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 305 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 306 307 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 308 int tx_delay, int rx_delay) 309 { 310 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 311 RK3128_GMAC_PHY_INTF_SEL_RGMII | 312 RK3128_GMAC_RMII_MODE_CLR); 313 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 314 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 315 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 316 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 317 } 318 319 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 320 { 321 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 322 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 323 } 324 325 static const struct rk_reg_speed_data rk3128_reg_speed_data = { 326 .rgmii_10 = RK3128_GMAC_CLK_2_5M, 327 .rgmii_100 = RK3128_GMAC_CLK_25M, 328 .rgmii_1000 = RK3128_GMAC_CLK_125M, 329 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 330 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 331 }; 332 333 static int rk3128_set_speed(struct rk_priv_data *bsp_priv, 334 phy_interface_t interface, int speed) 335 { 336 return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data, 337 RK3128_GRF_MAC_CON1, interface, speed); 338 } 339 340 static const struct rk_gmac_ops rk3128_ops = { 341 .set_to_rgmii = rk3128_set_to_rgmii, 342 .set_to_rmii = rk3128_set_to_rmii, 343 .set_speed = rk3128_set_speed, 344 }; 345 346 #define RK3228_GRF_MAC_CON0 0x0900 347 #define RK3228_GRF_MAC_CON1 0x0904 348 349 #define RK3228_GRF_CON_MUX 0x50 350 351 /* RK3228_GRF_MAC_CON0 */ 352 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 353 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 354 355 /* RK3228_GRF_MAC_CON1 */ 356 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 357 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 358 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 359 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 360 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 361 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 362 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 363 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 364 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 365 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 366 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 367 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 368 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 369 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 370 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 371 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 372 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 373 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 374 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 375 376 /* RK3228_GRF_COM_MUX */ 377 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 378 379 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 380 int tx_delay, int rx_delay) 381 { 382 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 383 RK3228_GMAC_PHY_INTF_SEL_RGMII | 384 RK3228_GMAC_RMII_MODE_CLR | 385 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 386 387 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 388 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 389 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 390 } 391 392 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 393 { 394 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 395 RK3228_GMAC_PHY_INTF_SEL_RMII | 396 RK3228_GMAC_RMII_MODE); 397 398 /* set MAC to RMII mode */ 399 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 400 } 401 402 static const struct rk_reg_speed_data rk3228_reg_speed_data = { 403 .rgmii_10 = RK3228_GMAC_CLK_2_5M, 404 .rgmii_100 = RK3228_GMAC_CLK_25M, 405 .rgmii_1000 = RK3228_GMAC_CLK_125M, 406 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 407 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 408 }; 409 410 static int rk3228_set_speed(struct rk_priv_data *bsp_priv, 411 phy_interface_t interface, int speed) 412 { 413 return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data, 414 RK3228_GRF_MAC_CON1, interface, speed); 415 } 416 417 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 418 { 419 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 420 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 421 422 rk_gmac_integrated_ephy_powerup(priv); 423 } 424 425 static const struct rk_gmac_ops rk3228_ops = { 426 .set_to_rgmii = rk3228_set_to_rgmii, 427 .set_to_rmii = rk3228_set_to_rmii, 428 .set_speed = rk3228_set_speed, 429 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 430 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 431 }; 432 433 #define RK3288_GRF_SOC_CON1 0x0248 434 #define RK3288_GRF_SOC_CON3 0x0250 435 436 /*RK3288_GRF_SOC_CON1*/ 437 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 438 GRF_CLR_BIT(8)) 439 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 440 GRF_BIT(8)) 441 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 442 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 443 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 444 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 445 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 446 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 447 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 448 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 449 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 450 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 451 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 452 453 /*RK3288_GRF_SOC_CON3*/ 454 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 455 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 456 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 457 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 458 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 459 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 460 461 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 462 int tx_delay, int rx_delay) 463 { 464 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 465 RK3288_GMAC_PHY_INTF_SEL_RGMII | 466 RK3288_GMAC_RMII_MODE_CLR); 467 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 468 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 469 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 470 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 471 } 472 473 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 474 { 475 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 476 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 477 } 478 479 static const struct rk_reg_speed_data rk3288_reg_speed_data = { 480 .rgmii_10 = RK3288_GMAC_CLK_2_5M, 481 .rgmii_100 = RK3288_GMAC_CLK_25M, 482 .rgmii_1000 = RK3288_GMAC_CLK_125M, 483 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 484 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 485 }; 486 487 static int rk3288_set_speed(struct rk_priv_data *bsp_priv, 488 phy_interface_t interface, int speed) 489 { 490 return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data, 491 RK3288_GRF_SOC_CON1, interface, speed); 492 } 493 494 static const struct rk_gmac_ops rk3288_ops = { 495 .set_to_rgmii = rk3288_set_to_rgmii, 496 .set_to_rmii = rk3288_set_to_rmii, 497 .set_speed = rk3288_set_speed, 498 }; 499 500 #define RK3308_GRF_MAC_CON0 0x04a0 501 502 /* RK3308_GRF_MAC_CON0 */ 503 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 504 GRF_BIT(4)) 505 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 506 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 507 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 508 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 509 510 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 511 { 512 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 513 RK3308_GMAC_PHY_INTF_SEL_RMII); 514 } 515 516 static const struct rk_reg_speed_data rk3308_reg_speed_data = { 517 .rmii_10 = RK3308_GMAC_SPEED_10M, 518 .rmii_100 = RK3308_GMAC_SPEED_100M, 519 }; 520 521 static int rk3308_set_speed(struct rk_priv_data *bsp_priv, 522 phy_interface_t interface, int speed) 523 { 524 return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, 525 RK3308_GRF_MAC_CON0, interface, speed); 526 } 527 528 static const struct rk_gmac_ops rk3308_ops = { 529 .set_to_rmii = rk3308_set_to_rmii, 530 .set_speed = rk3308_set_speed, 531 }; 532 533 #define RK3328_GRF_MAC_CON0 0x0900 534 #define RK3328_GRF_MAC_CON1 0x0904 535 #define RK3328_GRF_MAC_CON2 0x0908 536 #define RK3328_GRF_MACPHY_CON1 0xb04 537 538 /* RK3328_GRF_MAC_CON0 */ 539 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 540 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 541 542 /* RK3328_GRF_MAC_CON1 */ 543 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 544 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 545 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 546 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 547 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 548 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 549 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 550 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 551 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 552 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 553 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 554 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 555 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 556 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 557 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 558 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 559 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 560 561 /* RK3328_GRF_MACPHY_CON1 */ 562 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 563 564 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 565 int tx_delay, int rx_delay) 566 { 567 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 568 RK3328_GMAC_PHY_INTF_SEL_RGMII | 569 RK3328_GMAC_RMII_MODE_CLR | 570 RK3328_GMAC_RXCLK_DLY_ENABLE | 571 RK3328_GMAC_TXCLK_DLY_ENABLE); 572 573 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 574 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 575 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 576 } 577 578 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 579 { 580 unsigned int reg; 581 582 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 583 RK3328_GRF_MAC_CON1; 584 585 regmap_write(bsp_priv->grf, reg, 586 RK3328_GMAC_PHY_INTF_SEL_RMII | 587 RK3328_GMAC_RMII_MODE); 588 } 589 590 static const struct rk_reg_speed_data rk3328_reg_speed_data = { 591 .rgmii_10 = RK3328_GMAC_CLK_2_5M, 592 .rgmii_100 = RK3328_GMAC_CLK_25M, 593 .rgmii_1000 = RK3328_GMAC_CLK_125M, 594 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 595 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 596 }; 597 598 static int rk3328_set_speed(struct rk_priv_data *bsp_priv, 599 phy_interface_t interface, int speed) 600 { 601 unsigned int reg; 602 603 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy) 604 reg = RK3328_GRF_MAC_CON2; 605 else 606 reg = RK3328_GRF_MAC_CON1; 607 608 return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg, 609 interface, speed); 610 } 611 612 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 613 { 614 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 615 RK3328_MACPHY_RMII_MODE); 616 617 rk_gmac_integrated_ephy_powerup(priv); 618 } 619 620 static const struct rk_gmac_ops rk3328_ops = { 621 .set_to_rgmii = rk3328_set_to_rgmii, 622 .set_to_rmii = rk3328_set_to_rmii, 623 .set_speed = rk3328_set_speed, 624 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 625 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 626 }; 627 628 #define RK3366_GRF_SOC_CON6 0x0418 629 #define RK3366_GRF_SOC_CON7 0x041c 630 631 /* RK3366_GRF_SOC_CON6 */ 632 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 633 GRF_CLR_BIT(11)) 634 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 635 GRF_BIT(11)) 636 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 637 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 638 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 639 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 640 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 641 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 642 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 643 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 644 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 645 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 646 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 647 648 /* RK3366_GRF_SOC_CON7 */ 649 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 650 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 651 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 652 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 653 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 654 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 655 656 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 657 int tx_delay, int rx_delay) 658 { 659 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 660 RK3366_GMAC_PHY_INTF_SEL_RGMII | 661 RK3366_GMAC_RMII_MODE_CLR); 662 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 663 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 664 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 665 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 666 } 667 668 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 669 { 670 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 671 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 672 } 673 674 static const struct rk_reg_speed_data rk3366_reg_speed_data = { 675 .rgmii_10 = RK3366_GMAC_CLK_2_5M, 676 .rgmii_100 = RK3366_GMAC_CLK_25M, 677 .rgmii_1000 = RK3366_GMAC_CLK_125M, 678 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 679 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 680 }; 681 682 static int rk3366_set_speed(struct rk_priv_data *bsp_priv, 683 phy_interface_t interface, int speed) 684 { 685 return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data, 686 RK3366_GRF_SOC_CON6, interface, speed); 687 } 688 689 static const struct rk_gmac_ops rk3366_ops = { 690 .set_to_rgmii = rk3366_set_to_rgmii, 691 .set_to_rmii = rk3366_set_to_rmii, 692 .set_speed = rk3366_set_speed, 693 }; 694 695 #define RK3368_GRF_SOC_CON15 0x043c 696 #define RK3368_GRF_SOC_CON16 0x0440 697 698 /* RK3368_GRF_SOC_CON15 */ 699 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 700 GRF_CLR_BIT(11)) 701 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 702 GRF_BIT(11)) 703 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 704 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 705 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 706 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 707 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 708 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 709 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 710 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 711 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 712 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 713 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 714 715 /* RK3368_GRF_SOC_CON16 */ 716 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 717 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 718 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 719 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 720 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 721 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 722 723 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 724 int tx_delay, int rx_delay) 725 { 726 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 727 RK3368_GMAC_PHY_INTF_SEL_RGMII | 728 RK3368_GMAC_RMII_MODE_CLR); 729 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 730 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 731 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 732 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 733 } 734 735 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 736 { 737 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 738 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 739 } 740 741 static const struct rk_reg_speed_data rk3368_reg_speed_data = { 742 .rgmii_10 = RK3368_GMAC_CLK_2_5M, 743 .rgmii_100 = RK3368_GMAC_CLK_25M, 744 .rgmii_1000 = RK3368_GMAC_CLK_125M, 745 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 746 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 747 }; 748 749 static int rk3368_set_speed(struct rk_priv_data *bsp_priv, 750 phy_interface_t interface, int speed) 751 { 752 return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data, 753 RK3368_GRF_SOC_CON15, interface, speed); 754 } 755 756 static const struct rk_gmac_ops rk3368_ops = { 757 .set_to_rgmii = rk3368_set_to_rgmii, 758 .set_to_rmii = rk3368_set_to_rmii, 759 .set_speed = rk3368_set_speed, 760 }; 761 762 #define RK3399_GRF_SOC_CON5 0xc214 763 #define RK3399_GRF_SOC_CON6 0xc218 764 765 /* RK3399_GRF_SOC_CON5 */ 766 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 767 GRF_CLR_BIT(11)) 768 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 769 GRF_BIT(11)) 770 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 771 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 772 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 773 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 774 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 775 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 776 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 777 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 778 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 779 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 780 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 781 782 /* RK3399_GRF_SOC_CON6 */ 783 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 784 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 785 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 786 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 787 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 788 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 789 790 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 791 int tx_delay, int rx_delay) 792 { 793 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 794 RK3399_GMAC_PHY_INTF_SEL_RGMII | 795 RK3399_GMAC_RMII_MODE_CLR); 796 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 797 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 798 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 799 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 800 } 801 802 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 803 { 804 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 805 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 806 } 807 808 static const struct rk_reg_speed_data rk3399_reg_speed_data = { 809 .rgmii_10 = RK3399_GMAC_CLK_2_5M, 810 .rgmii_100 = RK3399_GMAC_CLK_25M, 811 .rgmii_1000 = RK3399_GMAC_CLK_125M, 812 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 813 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 814 }; 815 816 static int rk3399_set_speed(struct rk_priv_data *bsp_priv, 817 phy_interface_t interface, int speed) 818 { 819 return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data, 820 RK3399_GRF_SOC_CON5, interface, speed); 821 } 822 823 static const struct rk_gmac_ops rk3399_ops = { 824 .set_to_rgmii = rk3399_set_to_rgmii, 825 .set_to_rmii = rk3399_set_to_rmii, 826 .set_speed = rk3399_set_speed, 827 }; 828 829 #define RK3528_VO_GRF_GMAC_CON 0x0018 830 #define RK3528_VO_GRF_MACPHY_CON0 0x001c 831 #define RK3528_VO_GRF_MACPHY_CON1 0x0020 832 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 833 #define RK3528_VPU_GRF_GMAC_CON6 0x001c 834 835 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 836 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 837 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 838 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 839 840 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 841 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 842 843 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 844 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 845 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 846 847 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 848 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 849 850 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) 851 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) 852 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 853 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 854 855 #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) 856 #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) 857 #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) 858 859 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 860 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 861 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 862 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 863 864 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 865 int tx_delay, int rx_delay) 866 { 867 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 868 RK3528_GMAC1_PHY_INTF_SEL_RGMII); 869 870 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 871 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 872 873 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 874 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 875 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 876 } 877 878 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 879 { 880 if (bsp_priv->id == 1) 881 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 882 RK3528_GMAC1_PHY_INTF_SEL_RMII); 883 else 884 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 885 RK3528_GMAC0_PHY_INTF_SEL_RMII | 886 RK3528_GMAC0_CLK_RMII_DIV2); 887 } 888 889 static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = { 890 .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20, 891 .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2, 892 }; 893 894 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 895 .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50, 896 .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5, 897 .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1, 898 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 899 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 900 }; 901 902 static int rk3528_set_speed(struct rk_priv_data *bsp_priv, 903 phy_interface_t interface, int speed) 904 { 905 const struct rk_reg_speed_data *rsd; 906 unsigned int reg; 907 908 if (bsp_priv->id == 1) { 909 rsd = &rk3528_gmac1_reg_speed_data; 910 reg = RK3528_VPU_GRF_GMAC_CON5; 911 } else { 912 rsd = &rk3528_gmac0_reg_speed_data; 913 reg = RK3528_VO_GRF_GMAC_CON; 914 } 915 916 return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed); 917 } 918 919 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 920 bool input, bool enable) 921 { 922 unsigned int val; 923 924 if (bsp_priv->id == 1) { 925 val = input ? RK3528_GMAC1_CLK_SELECT_IO : 926 RK3528_GMAC1_CLK_SELECT_CRU; 927 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 928 RK3528_GMAC1_CLK_RMII_GATE; 929 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 930 } else { 931 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 932 RK3528_GMAC0_CLK_RMII_GATE; 933 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 934 } 935 } 936 937 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) 938 { 939 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 940 } 941 942 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) 943 { 944 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 945 } 946 947 static const struct rk_gmac_ops rk3528_ops = { 948 .set_to_rgmii = rk3528_set_to_rgmii, 949 .set_to_rmii = rk3528_set_to_rmii, 950 .set_speed = rk3528_set_speed, 951 .set_clock_selection = rk3528_set_clock_selection, 952 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 953 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 954 .regs_valid = true, 955 .regs = { 956 0xffbd0000, /* gmac0 */ 957 0xffbe0000, /* gmac1 */ 958 0x0, /* sentinel */ 959 }, 960 }; 961 962 #define RK3568_GRF_GMAC0_CON0 0x0380 963 #define RK3568_GRF_GMAC0_CON1 0x0384 964 #define RK3568_GRF_GMAC1_CON0 0x0388 965 #define RK3568_GRF_GMAC1_CON1 0x038c 966 967 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 968 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 969 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 970 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 971 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 972 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 973 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 974 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 975 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 976 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 977 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 978 979 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 980 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 981 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 982 983 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 984 int tx_delay, int rx_delay) 985 { 986 u32 con0, con1; 987 988 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 989 RK3568_GRF_GMAC0_CON0; 990 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 991 RK3568_GRF_GMAC0_CON1; 992 993 regmap_write(bsp_priv->grf, con0, 994 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 995 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 996 997 regmap_write(bsp_priv->grf, con1, 998 RK3568_GMAC_PHY_INTF_SEL_RGMII | 999 RK3568_GMAC_RXCLK_DLY_ENABLE | 1000 RK3568_GMAC_TXCLK_DLY_ENABLE); 1001 } 1002 1003 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1004 { 1005 u32 con1; 1006 1007 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1008 RK3568_GRF_GMAC0_CON1; 1009 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1010 } 1011 1012 static const struct rk_gmac_ops rk3568_ops = { 1013 .set_to_rgmii = rk3568_set_to_rgmii, 1014 .set_to_rmii = rk3568_set_to_rmii, 1015 .set_speed = rk_set_clk_mac_speed, 1016 .regs_valid = true, 1017 .regs = { 1018 0xfe2a0000, /* gmac0 */ 1019 0xfe010000, /* gmac1 */ 1020 0x0, /* sentinel */ 1021 }, 1022 }; 1023 1024 /* VCCIO0_1_3_IOC */ 1025 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 1026 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 1027 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 1028 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 1029 1030 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 1031 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 1032 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 1033 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 1034 1035 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1036 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1037 1038 /* SDGMAC_GRF */ 1039 #define RK3576_GRF_GMAC_CON0 0X0020 1040 #define RK3576_GRF_GMAC_CON1 0X0024 1041 1042 #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 1043 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 1044 1045 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 1046 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 1047 1048 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1049 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1050 1051 #define RK3576_GMAC_CLK_RGMII_DIV1 \ 1052 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) 1053 #define RK3576_GMAC_CLK_RGMII_DIV5 \ 1054 (GRF_BIT(6) | GRF_BIT(5)) 1055 #define RK3576_GMAC_CLK_RGMII_DIV50 \ 1056 (GRF_BIT(6) | GRF_CLR_BIT(5)) 1057 1058 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1059 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1060 1061 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 1062 int tx_delay, int rx_delay) 1063 { 1064 unsigned int offset_con; 1065 1066 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1067 RK3576_GRF_GMAC_CON0; 1068 1069 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 1070 1071 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 1072 RK3576_VCCIO0_1_3_IOC_CON2; 1073 1074 /* m0 && m1 delay enabled */ 1075 regmap_write(bsp_priv->php_grf, offset_con, 1076 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1077 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1078 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 1079 1080 /* m0 && m1 delay value */ 1081 regmap_write(bsp_priv->php_grf, offset_con, 1082 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1083 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1084 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 1085 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 1086 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 1087 } 1088 1089 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 1090 { 1091 unsigned int offset_con; 1092 1093 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1094 RK3576_GRF_GMAC_CON0; 1095 1096 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 1097 } 1098 1099 static const struct rk_reg_speed_data rk3578_reg_speed_data = { 1100 .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50, 1101 .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5, 1102 .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1, 1103 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 1104 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 1105 }; 1106 1107 static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, 1108 phy_interface_t interface, int speed) 1109 { 1110 unsigned int offset_con; 1111 1112 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1113 RK3576_GRF_GMAC_CON0; 1114 1115 return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con, 1116 interface, speed); 1117 } 1118 1119 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1120 bool enable) 1121 { 1122 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 1123 RK3576_GMAC_CLK_SELECT_CRU; 1124 unsigned int offset_con; 1125 1126 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 1127 RK3576_GMAC_CLK_RMII_GATE; 1128 1129 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 1130 RK3576_GRF_GMAC_CON0; 1131 1132 regmap_write(bsp_priv->grf, offset_con, val); 1133 } 1134 1135 static const struct rk_gmac_ops rk3576_ops = { 1136 .set_to_rgmii = rk3576_set_to_rgmii, 1137 .set_to_rmii = rk3576_set_to_rmii, 1138 .set_speed = rk3576_set_gmac_speed, 1139 .set_clock_selection = rk3576_set_clock_selection, 1140 .php_grf_required = true, 1141 .regs_valid = true, 1142 .regs = { 1143 0x2a220000, /* gmac0 */ 1144 0x2a230000, /* gmac1 */ 1145 0x0, /* sentinel */ 1146 }, 1147 }; 1148 1149 /* sys_grf */ 1150 #define RK3588_GRF_GMAC_CON7 0X031c 1151 #define RK3588_GRF_GMAC_CON8 0X0320 1152 #define RK3588_GRF_GMAC_CON9 0X0324 1153 1154 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1155 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1156 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1157 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1158 1159 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1160 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1161 1162 /* php_grf */ 1163 #define RK3588_GRF_GMAC_CON0 0X0008 1164 #define RK3588_GRF_CLK_CON1 0X0070 1165 1166 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1167 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1168 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1169 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1170 1171 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1172 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1173 1174 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1175 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1176 1177 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1178 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1179 1180 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1181 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1182 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1183 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1184 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1185 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1186 1187 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1188 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1189 1190 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1191 int tx_delay, int rx_delay) 1192 { 1193 u32 offset_con, id = bsp_priv->id; 1194 1195 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1196 RK3588_GRF_GMAC_CON8; 1197 1198 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1199 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1200 1201 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1202 RK3588_GMAC_CLK_RGMII_MODE(id)); 1203 1204 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1205 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1206 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1207 1208 regmap_write(bsp_priv->grf, offset_con, 1209 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1210 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1211 } 1212 1213 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1214 { 1215 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1216 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1217 1218 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1219 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1220 } 1221 1222 static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, 1223 phy_interface_t interface, int speed) 1224 { 1225 unsigned int val = 0, id = bsp_priv->id; 1226 1227 switch (speed) { 1228 case 10: 1229 if (interface == PHY_INTERFACE_MODE_RMII) 1230 val = RK3588_GMA_CLK_RMII_DIV20(id); 1231 else 1232 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1233 break; 1234 case 100: 1235 if (interface == PHY_INTERFACE_MODE_RMII) 1236 val = RK3588_GMA_CLK_RMII_DIV2(id); 1237 else 1238 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1239 break; 1240 case 1000: 1241 if (interface != PHY_INTERFACE_MODE_RMII) 1242 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1243 else 1244 goto err; 1245 break; 1246 default: 1247 goto err; 1248 } 1249 1250 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1251 1252 return 0; 1253 err: 1254 return -EINVAL; 1255 } 1256 1257 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1258 bool enable) 1259 { 1260 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1261 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1262 1263 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1264 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1265 1266 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1267 } 1268 1269 static const struct rk_gmac_ops rk3588_ops = { 1270 .set_to_rgmii = rk3588_set_to_rgmii, 1271 .set_to_rmii = rk3588_set_to_rmii, 1272 .set_speed = rk3588_set_gmac_speed, 1273 .set_clock_selection = rk3588_set_clock_selection, 1274 .php_grf_required = true, 1275 .regs_valid = true, 1276 .regs = { 1277 0xfe1b0000, /* gmac0 */ 1278 0xfe1c0000, /* gmac1 */ 1279 0x0, /* sentinel */ 1280 }, 1281 }; 1282 1283 #define RV1108_GRF_GMAC_CON0 0X0900 1284 1285 /* RV1108_GRF_GMAC_CON0 */ 1286 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1287 GRF_BIT(6)) 1288 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1289 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1290 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1291 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1292 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1293 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1294 1295 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1296 { 1297 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1298 RV1108_GMAC_PHY_INTF_SEL_RMII); 1299 } 1300 1301 static const struct rk_reg_speed_data rv1108_reg_speed_data = { 1302 .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M, 1303 .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M, 1304 }; 1305 1306 static int rv1108_set_speed(struct rk_priv_data *bsp_priv, 1307 phy_interface_t interface, int speed) 1308 { 1309 return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data, 1310 RV1108_GRF_GMAC_CON0, interface, speed); 1311 } 1312 1313 static const struct rk_gmac_ops rv1108_ops = { 1314 .set_to_rmii = rv1108_set_to_rmii, 1315 .set_speed = rv1108_set_speed, 1316 }; 1317 1318 #define RV1126_GRF_GMAC_CON0 0X0070 1319 #define RV1126_GRF_GMAC_CON1 0X0074 1320 #define RV1126_GRF_GMAC_CON2 0X0078 1321 1322 /* RV1126_GRF_GMAC_CON0 */ 1323 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1324 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1325 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1326 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1327 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1328 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1329 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1330 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1331 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1332 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1333 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1334 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1335 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1336 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1337 1338 /* RV1126_GRF_GMAC_CON1 */ 1339 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1340 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1341 /* RV1126_GRF_GMAC_CON2 */ 1342 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1343 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1344 1345 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1346 int tx_delay, int rx_delay) 1347 { 1348 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1349 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1350 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1351 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1352 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1353 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1354 1355 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1356 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1357 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1358 1359 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1360 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1361 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1362 } 1363 1364 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1365 { 1366 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1367 RV1126_GMAC_PHY_INTF_SEL_RMII); 1368 } 1369 1370 static const struct rk_gmac_ops rv1126_ops = { 1371 .set_to_rgmii = rv1126_set_to_rgmii, 1372 .set_to_rmii = rv1126_set_to_rmii, 1373 .set_speed = rk_set_clk_mac_speed, 1374 }; 1375 1376 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1377 { 1378 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1379 int phy_iface = bsp_priv->phy_iface; 1380 struct device *dev = bsp_priv->dev; 1381 int i, j, ret; 1382 1383 bsp_priv->clk_enabled = false; 1384 1385 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1386 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1387 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1388 1389 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1390 sizeof(*bsp_priv->clks), GFP_KERNEL); 1391 if (!bsp_priv->clks) 1392 return -ENOMEM; 1393 1394 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1395 bsp_priv->clks[i].id = rk_clocks[i]; 1396 1397 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1398 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1399 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1400 } 1401 1402 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1403 bsp_priv->clks); 1404 if (ret) 1405 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1406 1407 if (bsp_priv->clock_input) { 1408 dev_info(dev, "clock input from PHY\n"); 1409 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1410 clk_set_rate(plat->stmmac_clk, 50000000); 1411 } 1412 1413 if (plat->phy_node) { 1414 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1415 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1416 /* If it is not integrated_phy, clk_phy is optional */ 1417 if (bsp_priv->integrated_phy) { 1418 if (ret) 1419 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1420 clk_set_rate(bsp_priv->clk_phy, 50000000); 1421 } 1422 } 1423 1424 return 0; 1425 } 1426 1427 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1428 { 1429 int ret; 1430 1431 if (enable) { 1432 if (!bsp_priv->clk_enabled) { 1433 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1434 bsp_priv->clks); 1435 if (ret) 1436 return ret; 1437 1438 ret = clk_prepare_enable(bsp_priv->clk_phy); 1439 if (ret) 1440 return ret; 1441 1442 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1443 bsp_priv->ops->set_clock_selection(bsp_priv, 1444 bsp_priv->clock_input, true); 1445 1446 mdelay(5); 1447 bsp_priv->clk_enabled = true; 1448 } 1449 } else { 1450 if (bsp_priv->clk_enabled) { 1451 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1452 bsp_priv->clks); 1453 clk_disable_unprepare(bsp_priv->clk_phy); 1454 1455 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1456 bsp_priv->ops->set_clock_selection(bsp_priv, 1457 bsp_priv->clock_input, false); 1458 1459 bsp_priv->clk_enabled = false; 1460 } 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1467 { 1468 struct regulator *ldo = bsp_priv->regulator; 1469 struct device *dev = bsp_priv->dev; 1470 int ret; 1471 1472 if (enable) { 1473 ret = regulator_enable(ldo); 1474 if (ret) 1475 dev_err(dev, "fail to enable phy-supply\n"); 1476 } else { 1477 ret = regulator_disable(ldo); 1478 if (ret) 1479 dev_err(dev, "fail to disable phy-supply\n"); 1480 } 1481 1482 return 0; 1483 } 1484 1485 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1486 struct plat_stmmacenet_data *plat, 1487 const struct rk_gmac_ops *ops) 1488 { 1489 struct rk_priv_data *bsp_priv; 1490 struct device *dev = &pdev->dev; 1491 struct resource *res; 1492 int ret; 1493 const char *strings = NULL; 1494 int value; 1495 1496 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1497 if (!bsp_priv) 1498 return ERR_PTR(-ENOMEM); 1499 1500 bsp_priv->phy_iface = plat->phy_interface; 1501 bsp_priv->ops = ops; 1502 1503 /* Some SoCs have multiple MAC controllers, which need 1504 * to be distinguished. 1505 */ 1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1507 if (res && ops->regs_valid) { 1508 int i = 0; 1509 1510 while (ops->regs[i]) { 1511 if (ops->regs[i] == res->start) { 1512 bsp_priv->id = i; 1513 break; 1514 } 1515 i++; 1516 } 1517 } 1518 1519 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1520 if (IS_ERR(bsp_priv->regulator)) { 1521 ret = PTR_ERR(bsp_priv->regulator); 1522 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1523 return ERR_PTR(ret); 1524 } 1525 1526 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1527 if (ret) { 1528 dev_err(dev, "Can not read property: clock_in_out.\n"); 1529 bsp_priv->clock_input = true; 1530 } else { 1531 dev_info(dev, "clock input or output? (%s).\n", 1532 strings); 1533 if (!strcmp(strings, "input")) 1534 bsp_priv->clock_input = true; 1535 else 1536 bsp_priv->clock_input = false; 1537 } 1538 1539 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1540 if (ret) { 1541 bsp_priv->tx_delay = 0x30; 1542 dev_err(dev, "Can not read property: tx_delay."); 1543 dev_err(dev, "set tx_delay to 0x%x\n", 1544 bsp_priv->tx_delay); 1545 } else { 1546 dev_info(dev, "TX delay(0x%x).\n", value); 1547 bsp_priv->tx_delay = value; 1548 } 1549 1550 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1551 if (ret) { 1552 bsp_priv->rx_delay = 0x10; 1553 dev_err(dev, "Can not read property: rx_delay."); 1554 dev_err(dev, "set rx_delay to 0x%x\n", 1555 bsp_priv->rx_delay); 1556 } else { 1557 dev_info(dev, "RX delay(0x%x).\n", value); 1558 bsp_priv->rx_delay = value; 1559 } 1560 1561 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1562 "rockchip,grf"); 1563 if (IS_ERR(bsp_priv->grf)) { 1564 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1565 "failed to lookup rockchip,grf\n"); 1566 return ERR_CAST(bsp_priv->grf); 1567 } 1568 1569 if (ops->php_grf_required) { 1570 bsp_priv->php_grf = 1571 syscon_regmap_lookup_by_phandle(dev->of_node, 1572 "rockchip,php-grf"); 1573 if (IS_ERR(bsp_priv->php_grf)) { 1574 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1575 "failed to lookup rockchip,php-grf\n"); 1576 return ERR_CAST(bsp_priv->php_grf); 1577 } 1578 } 1579 1580 if (plat->phy_node) { 1581 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1582 "phy-is-integrated"); 1583 if (bsp_priv->integrated_phy) { 1584 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1585 if (IS_ERR(bsp_priv->phy_reset)) { 1586 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1587 bsp_priv->phy_reset = NULL; 1588 } 1589 } 1590 } 1591 dev_info(dev, "integrated PHY? (%s).\n", 1592 bsp_priv->integrated_phy ? "yes" : "no"); 1593 1594 bsp_priv->dev = dev; 1595 1596 return bsp_priv; 1597 } 1598 1599 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1600 { 1601 switch (bsp_priv->phy_iface) { 1602 case PHY_INTERFACE_MODE_RGMII: 1603 case PHY_INTERFACE_MODE_RGMII_ID: 1604 case PHY_INTERFACE_MODE_RGMII_RXID: 1605 case PHY_INTERFACE_MODE_RGMII_TXID: 1606 if (!bsp_priv->ops->set_to_rgmii) 1607 return -EINVAL; 1608 break; 1609 case PHY_INTERFACE_MODE_RMII: 1610 if (!bsp_priv->ops->set_to_rmii) 1611 return -EINVAL; 1612 break; 1613 default: 1614 dev_err(bsp_priv->dev, 1615 "unsupported interface %d", bsp_priv->phy_iface); 1616 } 1617 return 0; 1618 } 1619 1620 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1621 { 1622 struct device *dev = bsp_priv->dev; 1623 int ret; 1624 1625 ret = rk_gmac_check_ops(bsp_priv); 1626 if (ret) 1627 return ret; 1628 1629 ret = gmac_clk_enable(bsp_priv, true); 1630 if (ret) 1631 return ret; 1632 1633 /*rmii or rgmii*/ 1634 switch (bsp_priv->phy_iface) { 1635 case PHY_INTERFACE_MODE_RGMII: 1636 dev_info(dev, "init for RGMII\n"); 1637 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1638 bsp_priv->rx_delay); 1639 break; 1640 case PHY_INTERFACE_MODE_RGMII_ID: 1641 dev_info(dev, "init for RGMII_ID\n"); 1642 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1643 break; 1644 case PHY_INTERFACE_MODE_RGMII_RXID: 1645 dev_info(dev, "init for RGMII_RXID\n"); 1646 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1647 break; 1648 case PHY_INTERFACE_MODE_RGMII_TXID: 1649 dev_info(dev, "init for RGMII_TXID\n"); 1650 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1651 break; 1652 case PHY_INTERFACE_MODE_RMII: 1653 dev_info(dev, "init for RMII\n"); 1654 bsp_priv->ops->set_to_rmii(bsp_priv); 1655 break; 1656 default: 1657 dev_err(dev, "NO interface defined!\n"); 1658 } 1659 1660 ret = phy_power_on(bsp_priv, true); 1661 if (ret) { 1662 gmac_clk_enable(bsp_priv, false); 1663 return ret; 1664 } 1665 1666 pm_runtime_get_sync(dev); 1667 1668 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) 1669 bsp_priv->ops->integrated_phy_powerup(bsp_priv); 1670 1671 return 0; 1672 } 1673 1674 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1675 { 1676 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) 1677 gmac->ops->integrated_phy_powerdown(gmac); 1678 1679 pm_runtime_put_sync(gmac->dev); 1680 1681 phy_power_on(gmac, false); 1682 gmac_clk_enable(gmac, false); 1683 } 1684 1685 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 1686 unsigned long *interfaces) 1687 { 1688 struct rk_priv_data *rk = bsp_priv; 1689 1690 if (rk->ops->set_to_rgmii) 1691 phy_interface_set_rgmii(interfaces); 1692 1693 if (rk->ops->set_to_rmii) 1694 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1695 } 1696 1697 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1698 phy_interface_t interface, int speed) 1699 { 1700 struct rk_priv_data *bsp_priv = bsp_priv_; 1701 1702 if (bsp_priv->ops->set_speed) 1703 return bsp_priv->ops->set_speed(bsp_priv, bsp_priv->phy_iface, 1704 speed); 1705 1706 return -EINVAL; 1707 } 1708 1709 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_) 1710 { 1711 struct rk_priv_data *bsp_priv = bsp_priv_; 1712 1713 /* Keep the PHY up if we use Wake-on-Lan. */ 1714 if (!device_may_wakeup(dev)) 1715 rk_gmac_powerdown(bsp_priv); 1716 1717 return 0; 1718 } 1719 1720 static int rk_gmac_resume(struct device *dev, void *bsp_priv_) 1721 { 1722 struct rk_priv_data *bsp_priv = bsp_priv_; 1723 1724 /* The PHY was up for Wake-on-Lan. */ 1725 if (!device_may_wakeup(dev)) 1726 rk_gmac_powerup(bsp_priv); 1727 1728 return 0; 1729 } 1730 1731 static int rk_gmac_probe(struct platform_device *pdev) 1732 { 1733 struct plat_stmmacenet_data *plat_dat; 1734 struct stmmac_resources stmmac_res; 1735 const struct rk_gmac_ops *data; 1736 int ret; 1737 1738 data = of_device_get_match_data(&pdev->dev); 1739 if (!data) { 1740 dev_err(&pdev->dev, "no of match data provided\n"); 1741 return -EINVAL; 1742 } 1743 1744 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1745 if (ret) 1746 return ret; 1747 1748 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1749 if (IS_ERR(plat_dat)) 1750 return PTR_ERR(plat_dat); 1751 1752 /* If the stmmac is not already selected as gmac4, 1753 * then make sure we fallback to gmac. 1754 */ 1755 if (!plat_dat->has_gmac4) { 1756 plat_dat->has_gmac = true; 1757 plat_dat->rx_fifo_size = 4096; 1758 plat_dat->tx_fifo_size = 2048; 1759 } 1760 1761 plat_dat->get_interfaces = rk_get_interfaces; 1762 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1763 plat_dat->suspend = rk_gmac_suspend; 1764 plat_dat->resume = rk_gmac_resume; 1765 1766 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1767 if (IS_ERR(plat_dat->bsp_priv)) 1768 return PTR_ERR(plat_dat->bsp_priv); 1769 1770 ret = rk_gmac_clk_init(plat_dat); 1771 if (ret) 1772 return ret; 1773 1774 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1775 if (ret) 1776 return ret; 1777 1778 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1779 if (ret) 1780 goto err_gmac_powerdown; 1781 1782 return 0; 1783 1784 err_gmac_powerdown: 1785 rk_gmac_powerdown(plat_dat->bsp_priv); 1786 1787 return ret; 1788 } 1789 1790 static void rk_gmac_remove(struct platform_device *pdev) 1791 { 1792 struct stmmac_priv *priv = netdev_priv(platform_get_drvdata(pdev)); 1793 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv; 1794 1795 stmmac_dvr_remove(&pdev->dev); 1796 1797 rk_gmac_powerdown(bsp_priv); 1798 1799 if (priv->plat->phy_node && bsp_priv->integrated_phy) 1800 clk_put(bsp_priv->clk_phy); 1801 } 1802 1803 static const struct of_device_id rk_gmac_dwmac_match[] = { 1804 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1805 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1806 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1807 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1808 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1809 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1810 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1811 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1812 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1813 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, 1814 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1815 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1816 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1817 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1818 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1819 { } 1820 }; 1821 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1822 1823 static struct platform_driver rk_gmac_dwmac_driver = { 1824 .probe = rk_gmac_probe, 1825 .remove = rk_gmac_remove, 1826 .driver = { 1827 .name = "rk_gmac-dwmac", 1828 .pm = &stmmac_simple_pm_ops, 1829 .of_match_table = rk_gmac_dwmac_match, 1830 }, 1831 }; 1832 module_platform_driver(rk_gmac_dwmac_driver); 1833 1834 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1835 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1836 MODULE_LICENSE("GPL"); 1837