1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/hw_bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/phy.h> 15 #include <linux/of_net.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/delay.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/pm_runtime.h> 24 25 #include "stmmac_platform.h" 26 27 struct rk_priv_data; 28 29 struct rk_clock_fields { 30 u16 gmii_clk_sel_mask; 31 u16 rmii_clk_sel_mask; 32 u16 mac_speed_mask; 33 }; 34 35 struct rk_gmac_ops { 36 int (*init)(struct rk_priv_data *bsp_priv); 37 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 38 int tx_delay, int rx_delay); 39 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 40 int (*set_speed)(struct rk_priv_data *bsp_priv, 41 phy_interface_t interface, int speed); 42 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 43 bool enable); 44 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 46 47 u16 gmac_grf_reg; 48 u16 gmac_phy_intf_sel_mask; 49 u16 gmac_rmii_mode_mask; 50 51 u16 clock_grf_reg; 52 struct rk_clock_fields clock; 53 54 bool gmac_grf_reg_in_php; 55 bool clock_grf_reg_in_php; 56 bool php_grf_required; 57 bool regs_valid; 58 u32 regs[]; 59 }; 60 61 static const char * const rk_clocks[] = { 62 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 63 }; 64 65 static const char * const rk_rmii_clocks[] = { 66 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 67 }; 68 69 enum rk_clocks_index { 70 RK_ACLK_MAC = 0, 71 RK_PCLK_MAC, 72 RK_MAC_CLK_TX, 73 RK_CLK_MAC_SPEED, 74 RK_MAC_CLK_RX, 75 RK_CLK_MAC_REF, 76 RK_CLK_MAC_REFOUT, 77 }; 78 79 struct rk_priv_data { 80 struct device *dev; 81 phy_interface_t phy_iface; 82 int id; 83 struct regulator *regulator; 84 const struct rk_gmac_ops *ops; 85 86 bool clk_enabled; 87 bool clock_input; 88 bool integrated_phy; 89 90 struct clk_bulk_data *clks; 91 int num_clks; 92 struct clk *clk_phy; 93 94 struct reset_control *phy_reset; 95 96 int tx_delay; 97 int rx_delay; 98 99 struct regmap *grf; 100 struct regmap *php_grf; 101 102 u16 gmac_grf_reg; 103 u16 gmac_phy_intf_sel_mask; 104 u16 gmac_rmii_mode_mask; 105 106 u16 clock_grf_reg; 107 struct rk_clock_fields clock; 108 }; 109 110 #define GMAC_CLK_DIV1_125M 0 111 #define GMAC_CLK_DIV50_2_5M 2 112 #define GMAC_CLK_DIV5_25M 3 113 114 static int rk_gmac_rgmii_clk_div(int speed) 115 { 116 if (speed == SPEED_10) 117 return GMAC_CLK_DIV50_2_5M; 118 if (speed == SPEED_100) 119 return GMAC_CLK_DIV5_25M; 120 if (speed == SPEED_1000) 121 return GMAC_CLK_DIV1_125M; 122 return -EINVAL; 123 } 124 125 static int rk_get_phy_intf_sel(phy_interface_t interface) 126 { 127 int ret = stmmac_get_phy_intf_sel(interface); 128 129 /* Only RGMII and RMII are supported */ 130 if (ret != PHY_INTF_SEL_RGMII && ret != PHY_INTF_SEL_RMII) 131 ret = -EINVAL; 132 133 return ret; 134 } 135 136 static u32 rk_encode_wm16(u16 val, u16 mask) 137 { 138 u32 reg_val = mask << 16; 139 140 if (mask) 141 reg_val |= mask & (val << (ffs(mask) - 1)); 142 143 return reg_val; 144 } 145 146 static int rk_write_gmac_grf_reg(struct rk_priv_data *bsp_priv, u32 val) 147 { 148 struct regmap *regmap; 149 150 if (bsp_priv->ops->gmac_grf_reg_in_php) 151 regmap = bsp_priv->php_grf; 152 else 153 regmap = bsp_priv->grf; 154 155 return regmap_write(regmap, bsp_priv->gmac_grf_reg, val); 156 } 157 158 static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val) 159 { 160 struct regmap *regmap; 161 162 if (bsp_priv->ops->clock_grf_reg_in_php) 163 regmap = bsp_priv->php_grf; 164 else 165 regmap = bsp_priv->grf; 166 167 return regmap_write(regmap, bsp_priv->clock_grf_reg, val); 168 } 169 170 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, 171 phy_interface_t interface, int speed) 172 { 173 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 174 long rate; 175 176 rate = rgmii_clock(speed); 177 if (rate < 0) 178 return rate; 179 180 return clk_set_rate(clk_mac_speed, rate); 181 } 182 183 #define GRF_FIELD(hi, lo, val) \ 184 FIELD_PREP_WM16(GENMASK_U16(hi, lo), val) 185 186 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 187 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 188 189 #define DELAY_ENABLE(soc, tx, rx) \ 190 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 191 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 192 193 #define RK_GRF_MACPHY_CON0 0xb00 194 #define RK_MACPHY_ENABLE GRF_BIT(0) 195 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 196 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 197 #define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1) 198 199 #define RK_GRF_MACPHY_CON1 0xb04 200 201 #define RK_GRF_MACPHY_CON2 0xb08 202 #define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234) 203 204 #define RK_GRF_MACPHY_CON3 0xb0c 205 #define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35) 206 207 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) 208 { 209 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 210 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 211 212 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 213 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 214 215 if (priv->phy_reset) { 216 /* PHY needs to be disabled before trying to reset it */ 217 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 218 if (priv->phy_reset) 219 reset_control_assert(priv->phy_reset); 220 usleep_range(10, 20); 221 if (priv->phy_reset) 222 reset_control_deassert(priv->phy_reset); 223 usleep_range(10, 20); 224 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 225 msleep(30); 226 } 227 } 228 229 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) 230 { 231 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 232 if (priv->phy_reset) 233 reset_control_assert(priv->phy_reset); 234 } 235 236 #define RK_FEPHY_SHUTDOWN GRF_BIT(1) 237 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1) 238 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) 239 #define RK_FEPHY_24M_CLK_SEL GRF_FIELD(9, 8, 3) 240 #define RK_FEPHY_PHY_ID GRF_BIT(11) 241 242 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, 243 unsigned int reg) 244 { 245 reset_control_assert(priv->phy_reset); 246 usleep_range(20, 30); 247 248 regmap_write(priv->grf, reg, 249 RK_FEPHY_POWERUP | 250 RK_FEPHY_INTERNAL_RMII_SEL | 251 RK_FEPHY_24M_CLK_SEL | 252 RK_FEPHY_PHY_ID); 253 usleep_range(10000, 12000); 254 255 reset_control_deassert(priv->phy_reset); 256 usleep_range(50000, 60000); 257 } 258 259 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, 260 unsigned int reg) 261 { 262 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); 263 } 264 265 #define PX30_GRF_GMAC_CON1 0x0904 266 267 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 268 { 269 } 270 271 static const struct rk_gmac_ops px30_ops = { 272 .set_to_rmii = px30_set_to_rmii, 273 .set_speed = rk_set_clk_mac_speed, 274 275 .gmac_grf_reg = PX30_GRF_GMAC_CON1, 276 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 277 278 .clock_grf_reg = PX30_GRF_GMAC_CON1, 279 .clock.mac_speed_mask = BIT_U16(2), 280 }; 281 282 #define RK3128_GRF_MAC_CON0 0x0168 283 #define RK3128_GRF_MAC_CON1 0x016c 284 285 /* RK3128_GRF_MAC_CON0 */ 286 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 287 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 288 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 289 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 290 #define RK3128_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 291 #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 292 293 /* RK3128_GRF_MAC_CON1 */ 294 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 295 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 296 297 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 298 int tx_delay, int rx_delay) 299 { 300 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 301 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 302 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 303 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 304 } 305 306 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 307 { 308 } 309 310 static const struct rk_gmac_ops rk3128_ops = { 311 .set_to_rgmii = rk3128_set_to_rgmii, 312 .set_to_rmii = rk3128_set_to_rmii, 313 314 .gmac_grf_reg = RK3128_GRF_MAC_CON1, 315 .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6), 316 .gmac_rmii_mode_mask = BIT_U16(14), 317 318 .clock_grf_reg = RK3128_GRF_MAC_CON1, 319 .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12), 320 .clock.rmii_clk_sel_mask = BIT_U16(11), 321 .clock.mac_speed_mask = BIT_U16(10), 322 }; 323 324 #define RK3228_GRF_MAC_CON0 0x0900 325 #define RK3228_GRF_MAC_CON1 0x0904 326 327 #define RK3228_GRF_CON_MUX 0x50 328 329 /* RK3228_GRF_MAC_CON0 */ 330 #define RK3228_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 331 #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 332 333 /* RK3228_GRF_MAC_CON1 */ 334 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 335 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 336 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 337 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 338 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 339 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 340 341 /* RK3228_GRF_COM_MUX */ 342 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 343 344 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 345 int tx_delay, int rx_delay) 346 { 347 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 348 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 349 350 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 351 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 352 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 353 } 354 355 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 356 { 357 /* set MAC to RMII mode */ 358 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 359 } 360 361 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 362 { 363 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 364 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 365 366 rk_gmac_integrated_ephy_powerup(priv); 367 } 368 369 static const struct rk_gmac_ops rk3228_ops = { 370 .set_to_rgmii = rk3228_set_to_rgmii, 371 .set_to_rmii = rk3228_set_to_rmii, 372 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 373 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 374 375 .gmac_grf_reg = RK3228_GRF_MAC_CON1, 376 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 377 .gmac_rmii_mode_mask = BIT_U16(10), 378 379 .clock_grf_reg = RK3228_GRF_MAC_CON1, 380 .clock.gmii_clk_sel_mask = GENMASK_U16(9, 8), 381 .clock.rmii_clk_sel_mask = BIT_U16(7), 382 .clock.mac_speed_mask = BIT_U16(2), 383 }; 384 385 #define RK3288_GRF_SOC_CON1 0x0248 386 #define RK3288_GRF_SOC_CON3 0x0250 387 388 /*RK3288_GRF_SOC_CON1*/ 389 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 390 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 391 392 /*RK3288_GRF_SOC_CON3*/ 393 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 394 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 395 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 396 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 397 #define RK3288_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 398 #define RK3288_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 399 400 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 401 int tx_delay, int rx_delay) 402 { 403 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 404 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 405 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 406 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 407 } 408 409 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 410 { 411 } 412 413 static const struct rk_gmac_ops rk3288_ops = { 414 .set_to_rgmii = rk3288_set_to_rgmii, 415 .set_to_rmii = rk3288_set_to_rmii, 416 417 .gmac_grf_reg = RK3288_GRF_SOC_CON1, 418 .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6), 419 .gmac_rmii_mode_mask = BIT_U16(14), 420 421 .clock_grf_reg = RK3288_GRF_SOC_CON1, 422 .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12), 423 .clock.rmii_clk_sel_mask = BIT_U16(11), 424 .clock.mac_speed_mask = BIT_U16(10), 425 }; 426 427 #define RK3308_GRF_MAC_CON0 0x04a0 428 429 /* RK3308_GRF_MAC_CON0 */ 430 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 431 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 432 433 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 434 { 435 } 436 437 static const struct rk_gmac_ops rk3308_ops = { 438 .set_to_rmii = rk3308_set_to_rmii, 439 440 .gmac_grf_reg = RK3308_GRF_MAC_CON0, 441 .gmac_phy_intf_sel_mask = GENMASK_U16(4, 2), 442 443 .clock_grf_reg = RK3308_GRF_MAC_CON0, 444 .clock.mac_speed_mask = BIT_U16(0), 445 }; 446 447 #define RK3328_GRF_MAC_CON0 0x0900 448 #define RK3328_GRF_MAC_CON1 0x0904 449 #define RK3328_GRF_MAC_CON2 0x0908 450 #define RK3328_GRF_MACPHY_CON1 0xb04 451 452 /* RK3328_GRF_MAC_CON0 */ 453 #define RK3328_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val) 454 #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 455 456 /* RK3328_GRF_MAC_CON1 */ 457 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 458 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 459 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 460 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 461 462 /* RK3328_GRF_MACPHY_CON1 */ 463 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 464 465 static int rk3328_init(struct rk_priv_data *bsp_priv) 466 { 467 switch (bsp_priv->id) { 468 case 0: /* gmac2io */ 469 bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON1; 470 bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON1; 471 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(12, 11); 472 return 0; 473 474 case 1: /* gmac2phy */ 475 bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2; 476 bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON2; 477 return 0; 478 479 default: 480 return -EINVAL; 481 } 482 } 483 484 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 485 int tx_delay, int rx_delay) 486 { 487 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 488 RK3328_GMAC_RXCLK_DLY_ENABLE | 489 RK3328_GMAC_TXCLK_DLY_ENABLE); 490 491 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 492 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 493 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 494 } 495 496 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 497 { 498 } 499 500 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 501 { 502 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 503 RK3328_MACPHY_RMII_MODE); 504 505 rk_gmac_integrated_ephy_powerup(priv); 506 } 507 508 static const struct rk_gmac_ops rk3328_ops = { 509 .init = rk3328_init, 510 .set_to_rgmii = rk3328_set_to_rgmii, 511 .set_to_rmii = rk3328_set_to_rmii, 512 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 513 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 514 515 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 516 .gmac_rmii_mode_mask = BIT_U16(9), 517 518 .clock.rmii_clk_sel_mask = BIT_U16(7), 519 .clock.mac_speed_mask = BIT_U16(2), 520 521 .regs_valid = true, 522 .regs = { 523 0xff540000, /* gmac2io */ 524 0xff550000, /* gmac2phy */ 525 0, /* sentinel */ 526 }, 527 }; 528 529 #define RK3366_GRF_SOC_CON6 0x0418 530 #define RK3366_GRF_SOC_CON7 0x041c 531 532 /* RK3366_GRF_SOC_CON6 */ 533 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 534 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 535 536 /* RK3366_GRF_SOC_CON7 */ 537 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 538 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 539 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 540 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 541 #define RK3366_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 542 #define RK3366_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 543 544 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 545 int tx_delay, int rx_delay) 546 { 547 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 548 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 549 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 550 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 551 } 552 553 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 554 { 555 } 556 557 static const struct rk_gmac_ops rk3366_ops = { 558 .set_to_rgmii = rk3366_set_to_rgmii, 559 .set_to_rmii = rk3366_set_to_rmii, 560 561 .gmac_grf_reg = RK3366_GRF_SOC_CON6, 562 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), 563 .gmac_rmii_mode_mask = BIT_U16(6), 564 565 .clock_grf_reg = RK3366_GRF_SOC_CON6, 566 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 567 .clock.rmii_clk_sel_mask = BIT_U16(3), 568 .clock.mac_speed_mask = BIT_U16(7), 569 }; 570 571 #define RK3368_GRF_SOC_CON15 0x043c 572 #define RK3368_GRF_SOC_CON16 0x0440 573 574 /* RK3368_GRF_SOC_CON15 */ 575 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 576 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 577 578 /* RK3368_GRF_SOC_CON16 */ 579 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 580 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 581 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 582 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 583 #define RK3368_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 584 #define RK3368_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 585 586 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 587 int tx_delay, int rx_delay) 588 { 589 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 590 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 591 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 592 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 593 } 594 595 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 596 { 597 } 598 599 static const struct rk_gmac_ops rk3368_ops = { 600 .set_to_rgmii = rk3368_set_to_rgmii, 601 .set_to_rmii = rk3368_set_to_rmii, 602 603 .gmac_grf_reg = RK3368_GRF_SOC_CON15, 604 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), 605 .gmac_rmii_mode_mask = BIT_U16(6), 606 607 .clock_grf_reg = RK3368_GRF_SOC_CON15, 608 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 609 .clock.rmii_clk_sel_mask = BIT_U16(3), 610 .clock.mac_speed_mask = BIT_U16(7), 611 }; 612 613 #define RK3399_GRF_SOC_CON5 0xc214 614 #define RK3399_GRF_SOC_CON6 0xc218 615 616 /* RK3399_GRF_SOC_CON5 */ 617 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 618 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 619 620 /* RK3399_GRF_SOC_CON6 */ 621 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 622 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 623 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 624 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 625 #define RK3399_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 626 #define RK3399_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 627 628 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 629 int tx_delay, int rx_delay) 630 { 631 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 632 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 633 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 634 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 635 } 636 637 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 638 { 639 } 640 641 static const struct rk_gmac_ops rk3399_ops = { 642 .set_to_rgmii = rk3399_set_to_rgmii, 643 .set_to_rmii = rk3399_set_to_rmii, 644 645 .gmac_grf_reg = RK3399_GRF_SOC_CON5, 646 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), 647 .gmac_rmii_mode_mask = BIT_U16(6), 648 649 .clock_grf_reg = RK3399_GRF_SOC_CON5, 650 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 651 .clock.rmii_clk_sel_mask = BIT_U16(3), 652 .clock.mac_speed_mask = BIT_U16(7), 653 }; 654 655 #define RK3506_GRF_SOC_CON8 0x0020 656 #define RK3506_GRF_SOC_CON11 0x002c 657 658 #define RK3506_GMAC_RMII_MODE GRF_BIT(1) 659 660 #define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5) 661 #define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5) 662 663 #define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2) 664 #define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2) 665 666 static int rk3506_init(struct rk_priv_data *bsp_priv) 667 { 668 switch (bsp_priv->id) { 669 case 0: 670 bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON8; 671 return 0; 672 673 case 1: 674 bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON11; 675 return 0; 676 677 default: 678 return -EINVAL; 679 } 680 } 681 682 static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv) 683 { 684 unsigned int id = bsp_priv->id, offset; 685 686 offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; 687 regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE); 688 } 689 690 static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv, 691 bool input, bool enable) 692 { 693 unsigned int value, offset, id = bsp_priv->id; 694 695 offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; 696 697 value = input ? RK3506_GMAC_CLK_SELECT_IO : 698 RK3506_GMAC_CLK_SELECT_CRU; 699 value |= enable ? RK3506_GMAC_CLK_RMII_NOGATE : 700 RK3506_GMAC_CLK_RMII_GATE; 701 regmap_write(bsp_priv->grf, offset, value); 702 } 703 704 static const struct rk_gmac_ops rk3506_ops = { 705 .init = rk3506_init, 706 .set_to_rmii = rk3506_set_to_rmii, 707 .set_clock_selection = rk3506_set_clock_selection, 708 709 .clock.rmii_clk_sel_mask = BIT_U16(3), 710 711 .regs_valid = true, 712 .regs = { 713 0xff4c8000, /* gmac0 */ 714 0xff4d0000, /* gmac1 */ 715 0x0, /* sentinel */ 716 }, 717 }; 718 719 #define RK3528_VO_GRF_GMAC_CON 0x0018 720 #define RK3528_VO_GRF_MACPHY_CON0 0x001c 721 #define RK3528_VO_GRF_MACPHY_CON1 0x0020 722 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 723 #define RK3528_VPU_GRF_GMAC_CON6 0x001c 724 725 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 726 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 727 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 728 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 729 730 #define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val) 731 #define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val) 732 733 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) 734 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) 735 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) 736 737 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 738 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 739 740 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 741 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 742 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 743 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 744 745 static int rk3528_init(struct rk_priv_data *bsp_priv) 746 { 747 switch (bsp_priv->id) { 748 case 0: 749 bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON; 750 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3); 751 return 0; 752 753 case 1: 754 bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5; 755 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10); 756 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10); 757 return 0; 758 759 default: 760 return -EINVAL; 761 } 762 } 763 764 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 765 int tx_delay, int rx_delay) 766 { 767 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 768 RK3528_GMAC1_PHY_INTF_SEL_RGMII); 769 770 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 771 DELAY_ENABLE(RK3528, tx_delay, rx_delay)); 772 773 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, 774 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | 775 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); 776 } 777 778 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) 779 { 780 if (bsp_priv->id == 1) 781 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, 782 RK3528_GMAC1_PHY_INTF_SEL_RMII); 783 else 784 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 785 RK3528_GMAC0_PHY_INTF_SEL_RMII); 786 } 787 788 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, 789 bool input, bool enable) 790 { 791 unsigned int val; 792 793 if (bsp_priv->id == 1) { 794 val = input ? RK3528_GMAC1_CLK_SELECT_IO : 795 RK3528_GMAC1_CLK_SELECT_CRU; 796 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : 797 RK3528_GMAC1_CLK_RMII_GATE; 798 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); 799 } else { 800 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : 801 RK3528_GMAC0_CLK_RMII_GATE; 802 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); 803 } 804 } 805 806 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) 807 { 808 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 809 } 810 811 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) 812 { 813 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); 814 } 815 816 static const struct rk_gmac_ops rk3528_ops = { 817 .init = rk3528_init, 818 .set_to_rgmii = rk3528_set_to_rgmii, 819 .set_to_rmii = rk3528_set_to_rmii, 820 .set_clock_selection = rk3528_set_clock_selection, 821 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 822 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, 823 .regs_valid = true, 824 .regs = { 825 0xffbd0000, /* gmac0 */ 826 0xffbe0000, /* gmac1 */ 827 0x0, /* sentinel */ 828 }, 829 }; 830 831 #define RK3568_GRF_GMAC0_CON0 0x0380 832 #define RK3568_GRF_GMAC0_CON1 0x0384 833 #define RK3568_GRF_GMAC1_CON0 0x0388 834 #define RK3568_GRF_GMAC1_CON1 0x038c 835 836 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 837 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 838 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 839 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 840 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 841 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 842 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 843 844 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 845 #define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 846 #define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 847 848 static int rk3568_init(struct rk_priv_data *bsp_priv) 849 { 850 switch (bsp_priv->id) { 851 case 0: 852 bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC0_CON1; 853 return 0; 854 855 case 1: 856 bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC1_CON1; 857 return 0; 858 859 default: 860 return -EINVAL; 861 } 862 } 863 864 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 865 int tx_delay, int rx_delay) 866 { 867 u32 con0, con1; 868 869 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 870 RK3568_GRF_GMAC0_CON0; 871 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 872 RK3568_GRF_GMAC0_CON1; 873 874 regmap_write(bsp_priv->grf, con0, 875 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 876 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 877 878 regmap_write(bsp_priv->grf, con1, 879 RK3568_GMAC_RXCLK_DLY_ENABLE | 880 RK3568_GMAC_TXCLK_DLY_ENABLE); 881 } 882 883 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 884 { 885 } 886 887 static const struct rk_gmac_ops rk3568_ops = { 888 .init = rk3568_init, 889 .set_to_rgmii = rk3568_set_to_rgmii, 890 .set_to_rmii = rk3568_set_to_rmii, 891 .set_speed = rk_set_clk_mac_speed, 892 893 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 894 895 .regs_valid = true, 896 .regs = { 897 0xfe2a0000, /* gmac0 */ 898 0xfe010000, /* gmac1 */ 899 0x0, /* sentinel */ 900 }, 901 }; 902 903 /* VCCIO0_1_3_IOC */ 904 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 905 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c 906 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 907 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 908 909 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 910 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 911 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 912 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 913 914 #define RK3576_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 915 #define RK3576_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 916 917 /* SDGMAC_GRF */ 918 #define RK3576_GRF_GMAC_CON0 0X0020 919 #define RK3576_GRF_GMAC_CON1 0X0024 920 921 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 922 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 923 924 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 925 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 926 927 static int rk3576_init(struct rk_priv_data *bsp_priv) 928 { 929 switch (bsp_priv->id) { 930 case 0: 931 bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON0; 932 bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON0; 933 return 0; 934 935 case 1: 936 bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON1; 937 bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON1; 938 return 0; 939 940 default: 941 return -EINVAL; 942 } 943 } 944 945 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 946 int tx_delay, int rx_delay) 947 { 948 unsigned int offset_con; 949 950 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 951 RK3576_VCCIO0_1_3_IOC_CON2; 952 953 /* m0 && m1 delay enabled */ 954 regmap_write(bsp_priv->php_grf, offset_con, 955 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 956 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 957 DELAY_ENABLE(RK3576, tx_delay, rx_delay)); 958 959 /* m0 && m1 delay value */ 960 regmap_write(bsp_priv->php_grf, offset_con, 961 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 962 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 963 regmap_write(bsp_priv->php_grf, offset_con + 0x4, 964 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | 965 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); 966 } 967 968 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 969 { 970 } 971 972 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 973 bool enable) 974 { 975 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : 976 RK3576_GMAC_CLK_SELECT_CRU; 977 unsigned int offset_con; 978 979 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : 980 RK3576_GMAC_CLK_RMII_GATE; 981 982 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 983 RK3576_GRF_GMAC_CON0; 984 985 regmap_write(bsp_priv->grf, offset_con, val); 986 } 987 988 static const struct rk_gmac_ops rk3576_ops = { 989 .init = rk3576_init, 990 .set_to_rgmii = rk3576_set_to_rgmii, 991 .set_to_rmii = rk3576_set_to_rmii, 992 .set_clock_selection = rk3576_set_clock_selection, 993 994 .gmac_rmii_mode_mask = BIT_U16(3), 995 996 .clock.gmii_clk_sel_mask = GENMASK_U16(6, 5), 997 .clock.rmii_clk_sel_mask = BIT_U16(5), 998 999 .php_grf_required = true, 1000 .regs_valid = true, 1001 .regs = { 1002 0x2a220000, /* gmac0 */ 1003 0x2a230000, /* gmac1 */ 1004 0x0, /* sentinel */ 1005 }, 1006 }; 1007 1008 /* sys_grf */ 1009 #define RK3588_GRF_GMAC_CON7 0X031c 1010 #define RK3588_GRF_GMAC_CON8 0X0320 1011 #define RK3588_GRF_GMAC_CON9 0X0324 1012 1013 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1014 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1015 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1016 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1017 1018 #define RK3588_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val) 1019 #define RK3588_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val) 1020 1021 /* php_grf */ 1022 #define RK3588_GRF_GMAC_CON0 0X0008 1023 #define RK3588_GRF_CLK_CON1 0X0070 1024 1025 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1026 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1027 1028 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1029 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1030 1031 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1032 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1033 1034 static int rk3588_init(struct rk_priv_data *bsp_priv) 1035 { 1036 switch (bsp_priv->id) { 1037 case 0: 1038 bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3); 1039 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2); 1040 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2); 1041 return 0; 1042 1043 case 1: 1044 bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9); 1045 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7); 1046 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7); 1047 return 0; 1048 1049 default: 1050 return -EINVAL; 1051 } 1052 } 1053 1054 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1055 int tx_delay, int rx_delay) 1056 { 1057 u32 offset_con, id = bsp_priv->id; 1058 1059 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1060 RK3588_GRF_GMAC_CON8; 1061 1062 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1063 RK3588_GMAC_CLK_RGMII_MODE(id)); 1064 1065 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1066 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1067 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1068 1069 regmap_write(bsp_priv->grf, offset_con, 1070 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1071 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1072 } 1073 1074 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1075 { 1076 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1077 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1078 } 1079 1080 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1081 bool enable) 1082 { 1083 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : 1084 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); 1085 1086 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1087 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1088 1089 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1090 } 1091 1092 static const struct rk_gmac_ops rk3588_ops = { 1093 .init = rk3588_init, 1094 .set_to_rgmii = rk3588_set_to_rgmii, 1095 .set_to_rmii = rk3588_set_to_rmii, 1096 .set_clock_selection = rk3588_set_clock_selection, 1097 1098 .gmac_grf_reg_in_php = true, 1099 .gmac_grf_reg = RK3588_GRF_GMAC_CON0, 1100 1101 .clock_grf_reg_in_php = true, 1102 .clock_grf_reg = RK3588_GRF_CLK_CON1, 1103 1104 .php_grf_required = true, 1105 .regs_valid = true, 1106 .regs = { 1107 0xfe1b0000, /* gmac0 */ 1108 0xfe1c0000, /* gmac1 */ 1109 0x0, /* sentinel */ 1110 }, 1111 }; 1112 1113 #define RV1108_GRF_GMAC_CON0 0X0900 1114 1115 /* RV1108_GRF_GMAC_CON0 */ 1116 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1117 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1118 1119 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1120 { 1121 } 1122 1123 static const struct rk_gmac_ops rv1108_ops = { 1124 .set_to_rmii = rv1108_set_to_rmii, 1125 1126 .gmac_grf_reg = RV1108_GRF_GMAC_CON0, 1127 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1128 1129 .clock_grf_reg = RV1108_GRF_GMAC_CON0, 1130 .clock.rmii_clk_sel_mask = BIT_U16(7), 1131 .clock.mac_speed_mask = BIT_U16(2), 1132 }; 1133 1134 #define RV1126_GRF_GMAC_CON0 0X0070 1135 #define RV1126_GRF_GMAC_CON1 0X0074 1136 #define RV1126_GRF_GMAC_CON2 0X0078 1137 1138 /* RV1126_GRF_GMAC_CON0 */ 1139 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1140 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1141 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1142 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1143 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1144 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1145 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1146 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1147 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1148 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1149 1150 /* RV1126_GRF_GMAC_CON1 */ 1151 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 1152 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1153 /* RV1126_GRF_GMAC_CON2 */ 1154 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 1155 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1156 1157 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1158 int tx_delay, int rx_delay) 1159 { 1160 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1161 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1162 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1163 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1164 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1165 1166 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1167 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1168 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1169 1170 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1171 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1172 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1173 } 1174 1175 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1176 { 1177 } 1178 1179 static const struct rk_gmac_ops rv1126_ops = { 1180 .set_to_rgmii = rv1126_set_to_rgmii, 1181 .set_to_rmii = rv1126_set_to_rmii, 1182 .set_speed = rk_set_clk_mac_speed, 1183 1184 .gmac_grf_reg = RV1126_GRF_GMAC_CON0, 1185 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1186 }; 1187 1188 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1189 { 1190 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1191 int phy_iface = bsp_priv->phy_iface; 1192 struct device *dev = bsp_priv->dev; 1193 int i, j, ret; 1194 1195 bsp_priv->clk_enabled = false; 1196 1197 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1198 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1199 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1200 1201 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1202 sizeof(*bsp_priv->clks), GFP_KERNEL); 1203 if (!bsp_priv->clks) 1204 return -ENOMEM; 1205 1206 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1207 bsp_priv->clks[i].id = rk_clocks[i]; 1208 1209 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1210 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1211 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1212 } 1213 1214 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1215 bsp_priv->clks); 1216 if (ret) 1217 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1218 1219 if (bsp_priv->clock_input) { 1220 dev_info(dev, "clock input from PHY\n"); 1221 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1222 clk_set_rate(plat->stmmac_clk, 50000000); 1223 } 1224 1225 if (plat->phy_node && bsp_priv->integrated_phy) { 1226 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1227 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1228 if (ret) 1229 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1230 clk_set_rate(bsp_priv->clk_phy, 50000000); 1231 } 1232 1233 return 0; 1234 } 1235 1236 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1237 { 1238 int ret; 1239 1240 if (enable) { 1241 if (!bsp_priv->clk_enabled) { 1242 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1243 bsp_priv->clks); 1244 if (ret) 1245 return ret; 1246 1247 ret = clk_prepare_enable(bsp_priv->clk_phy); 1248 if (ret) 1249 return ret; 1250 1251 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1252 bsp_priv->ops->set_clock_selection(bsp_priv, 1253 bsp_priv->clock_input, true); 1254 1255 mdelay(5); 1256 bsp_priv->clk_enabled = true; 1257 } 1258 } else { 1259 if (bsp_priv->clk_enabled) { 1260 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) { 1261 bsp_priv->ops->set_clock_selection(bsp_priv, 1262 bsp_priv->clock_input, false); 1263 } 1264 1265 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1266 bsp_priv->clks); 1267 clk_disable_unprepare(bsp_priv->clk_phy); 1268 1269 bsp_priv->clk_enabled = false; 1270 } 1271 } 1272 1273 return 0; 1274 } 1275 1276 static int rk_phy_powerup(struct rk_priv_data *bsp_priv) 1277 { 1278 struct regulator *ldo = bsp_priv->regulator; 1279 int ret; 1280 1281 ret = regulator_enable(ldo); 1282 if (ret) 1283 dev_err(bsp_priv->dev, "fail to enable phy-supply\n"); 1284 1285 return ret; 1286 } 1287 1288 static void rk_phy_powerdown(struct rk_priv_data *bsp_priv) 1289 { 1290 struct regulator *ldo = bsp_priv->regulator; 1291 int ret; 1292 1293 ret = regulator_disable(ldo); 1294 if (ret) 1295 dev_err(bsp_priv->dev, "fail to disable phy-supply\n"); 1296 } 1297 1298 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1299 struct plat_stmmacenet_data *plat, 1300 const struct rk_gmac_ops *ops) 1301 { 1302 struct rk_priv_data *bsp_priv; 1303 struct device *dev = &pdev->dev; 1304 struct resource *res; 1305 int ret; 1306 const char *strings = NULL; 1307 int value; 1308 1309 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1310 if (!bsp_priv) 1311 return ERR_PTR(-ENOMEM); 1312 1313 bsp_priv->phy_iface = plat->phy_interface; 1314 bsp_priv->ops = ops; 1315 1316 /* Some SoCs have multiple MAC controllers, which need 1317 * to be distinguished. 1318 */ 1319 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1320 if (res && ops->regs_valid) { 1321 int i = 0; 1322 1323 while (ops->regs[i]) { 1324 if (ops->regs[i] == res->start) { 1325 bsp_priv->id = i; 1326 break; 1327 } 1328 i++; 1329 } 1330 } 1331 1332 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1333 if (IS_ERR(bsp_priv->regulator)) { 1334 ret = PTR_ERR(bsp_priv->regulator); 1335 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1336 return ERR_PTR(ret); 1337 } 1338 1339 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1340 if (ret) { 1341 dev_err(dev, "Can not read property: clock_in_out.\n"); 1342 bsp_priv->clock_input = true; 1343 } else { 1344 dev_info(dev, "clock input or output? (%s).\n", 1345 strings); 1346 if (!strcmp(strings, "input")) 1347 bsp_priv->clock_input = true; 1348 else 1349 bsp_priv->clock_input = false; 1350 } 1351 1352 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1353 if (ret) { 1354 bsp_priv->tx_delay = 0x30; 1355 dev_err(dev, "Can not read property: tx_delay."); 1356 dev_err(dev, "set tx_delay to 0x%x\n", 1357 bsp_priv->tx_delay); 1358 } else { 1359 dev_info(dev, "TX delay(0x%x).\n", value); 1360 bsp_priv->tx_delay = value; 1361 } 1362 1363 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1364 if (ret) { 1365 bsp_priv->rx_delay = 0x10; 1366 dev_err(dev, "Can not read property: rx_delay."); 1367 dev_err(dev, "set rx_delay to 0x%x\n", 1368 bsp_priv->rx_delay); 1369 } else { 1370 dev_info(dev, "RX delay(0x%x).\n", value); 1371 bsp_priv->rx_delay = value; 1372 } 1373 1374 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1375 "rockchip,grf"); 1376 if (IS_ERR(bsp_priv->grf)) { 1377 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), 1378 "failed to lookup rockchip,grf\n"); 1379 return ERR_CAST(bsp_priv->grf); 1380 } 1381 1382 if (ops->php_grf_required) { 1383 bsp_priv->php_grf = 1384 syscon_regmap_lookup_by_phandle(dev->of_node, 1385 "rockchip,php-grf"); 1386 if (IS_ERR(bsp_priv->php_grf)) { 1387 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), 1388 "failed to lookup rockchip,php-grf\n"); 1389 return ERR_CAST(bsp_priv->php_grf); 1390 } 1391 } 1392 1393 if (plat->phy_node) { 1394 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1395 "phy-is-integrated"); 1396 if (bsp_priv->integrated_phy) { 1397 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1398 if (IS_ERR(bsp_priv->phy_reset)) { 1399 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1400 bsp_priv->phy_reset = NULL; 1401 } 1402 } 1403 } 1404 dev_info(dev, "integrated PHY? (%s).\n", 1405 bsp_priv->integrated_phy ? "yes" : "no"); 1406 1407 bsp_priv->dev = dev; 1408 1409 /* Set the default phy_intf_sel and RMII mode register parameters. */ 1410 bsp_priv->gmac_grf_reg = ops->gmac_grf_reg; 1411 bsp_priv->gmac_phy_intf_sel_mask = ops->gmac_phy_intf_sel_mask; 1412 bsp_priv->gmac_rmii_mode_mask = ops->gmac_rmii_mode_mask; 1413 1414 /* Set the default clock control register related parameters */ 1415 bsp_priv->clock_grf_reg = ops->clock_grf_reg; 1416 bsp_priv->clock = ops->clock; 1417 1418 if (ops->init) { 1419 ret = ops->init(bsp_priv); 1420 if (ret) { 1421 reset_control_put(bsp_priv->phy_reset); 1422 dev_err_probe(dev, ret, "failed to init BSP\n"); 1423 return ERR_PTR(ret); 1424 } 1425 } 1426 1427 return bsp_priv; 1428 } 1429 1430 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1431 { 1432 switch (bsp_priv->phy_iface) { 1433 case PHY_INTERFACE_MODE_RGMII: 1434 case PHY_INTERFACE_MODE_RGMII_ID: 1435 case PHY_INTERFACE_MODE_RGMII_RXID: 1436 case PHY_INTERFACE_MODE_RGMII_TXID: 1437 if (!bsp_priv->ops->set_to_rgmii) 1438 return -EINVAL; 1439 break; 1440 case PHY_INTERFACE_MODE_RMII: 1441 if (!bsp_priv->ops->set_to_rmii) 1442 return -EINVAL; 1443 break; 1444 default: 1445 dev_err(bsp_priv->dev, 1446 "unsupported interface %d", bsp_priv->phy_iface); 1447 } 1448 return 0; 1449 } 1450 1451 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1452 { 1453 struct device *dev = bsp_priv->dev; 1454 u32 val; 1455 int ret; 1456 u8 intf; 1457 1458 ret = rk_gmac_check_ops(bsp_priv); 1459 if (ret) 1460 return ret; 1461 1462 ret = rk_get_phy_intf_sel(bsp_priv->phy_iface); 1463 if (ret < 0) 1464 return ret; 1465 1466 intf = ret; 1467 1468 ret = gmac_clk_enable(bsp_priv, true); 1469 if (ret) 1470 return ret; 1471 1472 if (bsp_priv->gmac_phy_intf_sel_mask || 1473 bsp_priv->gmac_rmii_mode_mask) { 1474 /* If defined, encode the phy_intf_sel value */ 1475 val = rk_encode_wm16(intf, bsp_priv->gmac_phy_intf_sel_mask); 1476 1477 /* If defined, encode the RMII mode mask setting. */ 1478 val |= rk_encode_wm16(intf == PHY_INTF_SEL_RMII, 1479 bsp_priv->gmac_rmii_mode_mask); 1480 1481 ret = rk_write_gmac_grf_reg(bsp_priv, val); 1482 if (ret < 0) { 1483 gmac_clk_enable(bsp_priv, false); 1484 return ret; 1485 } 1486 } 1487 1488 /*rmii or rgmii*/ 1489 switch (bsp_priv->phy_iface) { 1490 case PHY_INTERFACE_MODE_RGMII: 1491 dev_info(dev, "init for RGMII\n"); 1492 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1493 bsp_priv->rx_delay); 1494 break; 1495 case PHY_INTERFACE_MODE_RGMII_ID: 1496 dev_info(dev, "init for RGMII_ID\n"); 1497 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1498 break; 1499 case PHY_INTERFACE_MODE_RGMII_RXID: 1500 dev_info(dev, "init for RGMII_RXID\n"); 1501 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1502 break; 1503 case PHY_INTERFACE_MODE_RGMII_TXID: 1504 dev_info(dev, "init for RGMII_TXID\n"); 1505 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1506 break; 1507 case PHY_INTERFACE_MODE_RMII: 1508 dev_info(dev, "init for RMII\n"); 1509 bsp_priv->ops->set_to_rmii(bsp_priv); 1510 break; 1511 default: 1512 dev_err(dev, "NO interface defined!\n"); 1513 } 1514 1515 ret = rk_phy_powerup(bsp_priv); 1516 if (ret) { 1517 gmac_clk_enable(bsp_priv, false); 1518 return ret; 1519 } 1520 1521 pm_runtime_get_sync(dev); 1522 1523 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) 1524 bsp_priv->ops->integrated_phy_powerup(bsp_priv); 1525 1526 return 0; 1527 } 1528 1529 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1530 { 1531 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) 1532 gmac->ops->integrated_phy_powerdown(gmac); 1533 1534 pm_runtime_put_sync(gmac->dev); 1535 1536 rk_phy_powerdown(gmac); 1537 gmac_clk_enable(gmac, false); 1538 } 1539 1540 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 1541 unsigned long *interfaces) 1542 { 1543 struct rk_priv_data *rk = bsp_priv; 1544 1545 if (rk->ops->set_to_rgmii) 1546 phy_interface_set_rgmii(interfaces); 1547 1548 if (rk->ops->set_to_rmii) 1549 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); 1550 } 1551 1552 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i, 1553 phy_interface_t interface, int speed) 1554 { 1555 struct rk_priv_data *bsp_priv = bsp_priv_; 1556 int ret = -EINVAL; 1557 bool is_100m; 1558 u32 val; 1559 1560 if (bsp_priv->ops->set_speed) { 1561 ret = bsp_priv->ops->set_speed(bsp_priv, interface, speed); 1562 if (ret < 0) 1563 return ret; 1564 } 1565 1566 if (phy_interface_mode_is_rgmii(interface) && 1567 bsp_priv->clock.gmii_clk_sel_mask) { 1568 ret = rk_gmac_rgmii_clk_div(speed); 1569 if (ret < 0) 1570 return ret; 1571 1572 val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask); 1573 1574 ret = rk_write_clock_grf_reg(bsp_priv, val); 1575 } else if (interface == PHY_INTERFACE_MODE_RMII && 1576 (bsp_priv->clock.rmii_clk_sel_mask || 1577 bsp_priv->clock.mac_speed_mask)) { 1578 is_100m = speed == SPEED_100; 1579 val = rk_encode_wm16(is_100m, bsp_priv->clock.mac_speed_mask) | 1580 rk_encode_wm16(is_100m, 1581 bsp_priv->clock.rmii_clk_sel_mask); 1582 1583 ret = rk_write_clock_grf_reg(bsp_priv, val); 1584 } 1585 1586 return ret; 1587 } 1588 1589 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_) 1590 { 1591 struct rk_priv_data *bsp_priv = bsp_priv_; 1592 1593 /* Keep the PHY up if we use Wake-on-Lan. */ 1594 if (!device_may_wakeup(dev)) 1595 rk_gmac_powerdown(bsp_priv); 1596 1597 return 0; 1598 } 1599 1600 static int rk_gmac_resume(struct device *dev, void *bsp_priv_) 1601 { 1602 struct rk_priv_data *bsp_priv = bsp_priv_; 1603 1604 /* The PHY was up for Wake-on-Lan. */ 1605 if (!device_may_wakeup(dev)) 1606 rk_gmac_powerup(bsp_priv); 1607 1608 return 0; 1609 } 1610 1611 static int rk_gmac_init(struct device *dev, void *bsp_priv) 1612 { 1613 return rk_gmac_powerup(bsp_priv); 1614 } 1615 1616 static void rk_gmac_exit(struct device *dev, void *bsp_priv_) 1617 { 1618 struct stmmac_priv *priv = netdev_priv(dev_get_drvdata(dev)); 1619 struct rk_priv_data *bsp_priv = bsp_priv_; 1620 1621 rk_gmac_powerdown(bsp_priv); 1622 1623 if (priv->plat->phy_node && bsp_priv->integrated_phy) 1624 clk_put(bsp_priv->clk_phy); 1625 1626 reset_control_put(bsp_priv->phy_reset); 1627 } 1628 1629 static int rk_gmac_probe(struct platform_device *pdev) 1630 { 1631 struct plat_stmmacenet_data *plat_dat; 1632 struct stmmac_resources stmmac_res; 1633 const struct rk_gmac_ops *data; 1634 int ret; 1635 1636 data = of_device_get_match_data(&pdev->dev); 1637 if (!data) { 1638 dev_err(&pdev->dev, "no of match data provided\n"); 1639 return -EINVAL; 1640 } 1641 1642 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1643 if (ret) 1644 return ret; 1645 1646 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1647 if (IS_ERR(plat_dat)) 1648 return PTR_ERR(plat_dat); 1649 1650 /* If the stmmac is not already selected as gmac4, 1651 * then make sure we fallback to gmac. 1652 */ 1653 if (plat_dat->core_type != DWMAC_CORE_GMAC4) { 1654 plat_dat->core_type = DWMAC_CORE_GMAC; 1655 plat_dat->rx_fifo_size = 4096; 1656 plat_dat->tx_fifo_size = 2048; 1657 } 1658 1659 plat_dat->get_interfaces = rk_get_interfaces; 1660 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; 1661 plat_dat->init = rk_gmac_init; 1662 plat_dat->exit = rk_gmac_exit; 1663 plat_dat->suspend = rk_gmac_suspend; 1664 plat_dat->resume = rk_gmac_resume; 1665 1666 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1667 if (IS_ERR(plat_dat->bsp_priv)) 1668 return PTR_ERR(plat_dat->bsp_priv); 1669 1670 ret = rk_gmac_clk_init(plat_dat); 1671 if (ret) 1672 return ret; 1673 1674 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); 1675 } 1676 1677 static const struct of_device_id rk_gmac_dwmac_match[] = { 1678 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1679 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1680 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1681 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1682 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1683 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1684 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1685 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1686 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1687 { .compatible = "rockchip,rk3506-gmac", .data = &rk3506_ops }, 1688 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, 1689 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1690 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, 1691 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1692 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1693 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1694 { } 1695 }; 1696 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1697 1698 static struct platform_driver rk_gmac_dwmac_driver = { 1699 .probe = rk_gmac_probe, 1700 .driver = { 1701 .name = "rk_gmac-dwmac", 1702 .pm = &stmmac_simple_pm_ops, 1703 .of_match_table = rk_gmac_dwmac_match, 1704 }, 1705 }; 1706 module_platform_driver(rk_gmac_dwmac_driver); 1707 1708 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1709 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1710 MODULE_LICENSE("GPL"); 1711