1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /** 3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 4 * 5 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 6 * 7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 8 */ 9 10 #include <linux/stmmac.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/phy.h> 14 #include <linux/of_net.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/delay.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 #include <linux/pm_runtime.h> 23 24 #include "stmmac_platform.h" 25 26 struct rk_priv_data; 27 struct rk_gmac_ops { 28 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 29 int tx_delay, int rx_delay); 30 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 31 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 32 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 33 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, 34 bool enable); 35 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 36 bool regs_valid; 37 u32 regs[]; 38 }; 39 40 static const char * const rk_clocks[] = { 41 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", 42 }; 43 44 static const char * const rk_rmii_clocks[] = { 45 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", 46 }; 47 48 enum rk_clocks_index { 49 RK_ACLK_MAC = 0, 50 RK_PCLK_MAC, 51 RK_MAC_CLK_TX, 52 RK_CLK_MAC_SPEED, 53 RK_MAC_CLK_RX, 54 RK_CLK_MAC_REF, 55 RK_CLK_MAC_REFOUT, 56 }; 57 58 struct rk_priv_data { 59 struct platform_device *pdev; 60 phy_interface_t phy_iface; 61 int id; 62 struct regulator *regulator; 63 bool suspended; 64 const struct rk_gmac_ops *ops; 65 66 bool clk_enabled; 67 bool clock_input; 68 bool integrated_phy; 69 70 struct clk_bulk_data *clks; 71 int num_clks; 72 struct clk *clk_mac; 73 struct clk *clk_phy; 74 75 struct reset_control *phy_reset; 76 77 int tx_delay; 78 int rx_delay; 79 80 struct regmap *grf; 81 struct regmap *php_grf; 82 }; 83 84 #define HIWORD_UPDATE(val, mask, shift) \ 85 ((val) << (shift) | (mask) << ((shift) + 16)) 86 87 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 88 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 89 90 #define DELAY_ENABLE(soc, tx, rx) \ 91 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 92 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 93 94 #define PX30_GRF_GMAC_CON1 0x0904 95 96 /* PX30_GRF_GMAC_CON1 */ 97 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 98 GRF_BIT(6)) 99 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 100 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 101 102 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 103 { 104 struct device *dev = &bsp_priv->pdev->dev; 105 106 if (IS_ERR(bsp_priv->grf)) { 107 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 108 return; 109 } 110 111 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 112 PX30_GMAC_PHY_INTF_SEL_RMII); 113 } 114 115 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 116 { 117 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 118 struct device *dev = &bsp_priv->pdev->dev; 119 int ret; 120 121 if (!clk_mac_speed) { 122 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 123 return; 124 } 125 126 if (speed == 10) { 127 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 128 PX30_GMAC_SPEED_10M); 129 130 ret = clk_set_rate(clk_mac_speed, 2500000); 131 if (ret) 132 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n", 133 __func__, ret); 134 } else if (speed == 100) { 135 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 136 PX30_GMAC_SPEED_100M); 137 138 ret = clk_set_rate(clk_mac_speed, 25000000); 139 if (ret) 140 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n", 141 __func__, ret); 142 143 } else { 144 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 145 } 146 } 147 148 static const struct rk_gmac_ops px30_ops = { 149 .set_to_rmii = px30_set_to_rmii, 150 .set_rmii_speed = px30_set_rmii_speed, 151 }; 152 153 #define RK3128_GRF_MAC_CON0 0x0168 154 #define RK3128_GRF_MAC_CON1 0x016c 155 156 /* RK3128_GRF_MAC_CON0 */ 157 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 158 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 159 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 160 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 161 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 162 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 163 164 /* RK3128_GRF_MAC_CON1 */ 165 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 166 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 167 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 168 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 169 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 170 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 171 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 172 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 173 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 174 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 175 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 176 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 177 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 178 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 179 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 180 181 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 182 int tx_delay, int rx_delay) 183 { 184 struct device *dev = &bsp_priv->pdev->dev; 185 186 if (IS_ERR(bsp_priv->grf)) { 187 dev_err(dev, "Missing rockchip,grf property\n"); 188 return; 189 } 190 191 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 192 RK3128_GMAC_PHY_INTF_SEL_RGMII | 193 RK3128_GMAC_RMII_MODE_CLR); 194 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 195 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 196 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 197 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 198 } 199 200 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 201 { 202 struct device *dev = &bsp_priv->pdev->dev; 203 204 if (IS_ERR(bsp_priv->grf)) { 205 dev_err(dev, "Missing rockchip,grf property\n"); 206 return; 207 } 208 209 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 210 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 211 } 212 213 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 214 { 215 struct device *dev = &bsp_priv->pdev->dev; 216 217 if (IS_ERR(bsp_priv->grf)) { 218 dev_err(dev, "Missing rockchip,grf property\n"); 219 return; 220 } 221 222 if (speed == 10) 223 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 224 RK3128_GMAC_CLK_2_5M); 225 else if (speed == 100) 226 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 227 RK3128_GMAC_CLK_25M); 228 else if (speed == 1000) 229 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 230 RK3128_GMAC_CLK_125M); 231 else 232 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 233 } 234 235 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 236 { 237 struct device *dev = &bsp_priv->pdev->dev; 238 239 if (IS_ERR(bsp_priv->grf)) { 240 dev_err(dev, "Missing rockchip,grf property\n"); 241 return; 242 } 243 244 if (speed == 10) { 245 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 246 RK3128_GMAC_RMII_CLK_2_5M | 247 RK3128_GMAC_SPEED_10M); 248 } else if (speed == 100) { 249 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 250 RK3128_GMAC_RMII_CLK_25M | 251 RK3128_GMAC_SPEED_100M); 252 } else { 253 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 254 } 255 } 256 257 static const struct rk_gmac_ops rk3128_ops = { 258 .set_to_rgmii = rk3128_set_to_rgmii, 259 .set_to_rmii = rk3128_set_to_rmii, 260 .set_rgmii_speed = rk3128_set_rgmii_speed, 261 .set_rmii_speed = rk3128_set_rmii_speed, 262 }; 263 264 #define RK3228_GRF_MAC_CON0 0x0900 265 #define RK3228_GRF_MAC_CON1 0x0904 266 267 #define RK3228_GRF_CON_MUX 0x50 268 269 /* RK3228_GRF_MAC_CON0 */ 270 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 271 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 272 273 /* RK3228_GRF_MAC_CON1 */ 274 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 275 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 276 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 277 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 278 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 279 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 280 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 281 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 282 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 283 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 284 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 285 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 286 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 287 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 288 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 289 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 290 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 291 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 292 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 293 294 /* RK3228_GRF_COM_MUX */ 295 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 296 297 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 298 int tx_delay, int rx_delay) 299 { 300 struct device *dev = &bsp_priv->pdev->dev; 301 302 if (IS_ERR(bsp_priv->grf)) { 303 dev_err(dev, "Missing rockchip,grf property\n"); 304 return; 305 } 306 307 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 308 RK3228_GMAC_PHY_INTF_SEL_RGMII | 309 RK3228_GMAC_RMII_MODE_CLR | 310 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 311 312 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 313 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 314 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 315 } 316 317 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 318 { 319 struct device *dev = &bsp_priv->pdev->dev; 320 321 if (IS_ERR(bsp_priv->grf)) { 322 dev_err(dev, "Missing rockchip,grf property\n"); 323 return; 324 } 325 326 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 327 RK3228_GMAC_PHY_INTF_SEL_RMII | 328 RK3228_GMAC_RMII_MODE); 329 330 /* set MAC to RMII mode */ 331 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 332 } 333 334 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 335 { 336 struct device *dev = &bsp_priv->pdev->dev; 337 338 if (IS_ERR(bsp_priv->grf)) { 339 dev_err(dev, "Missing rockchip,grf property\n"); 340 return; 341 } 342 343 if (speed == 10) 344 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 345 RK3228_GMAC_CLK_2_5M); 346 else if (speed == 100) 347 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 348 RK3228_GMAC_CLK_25M); 349 else if (speed == 1000) 350 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 351 RK3228_GMAC_CLK_125M); 352 else 353 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 354 } 355 356 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 357 { 358 struct device *dev = &bsp_priv->pdev->dev; 359 360 if (IS_ERR(bsp_priv->grf)) { 361 dev_err(dev, "Missing rockchip,grf property\n"); 362 return; 363 } 364 365 if (speed == 10) 366 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 367 RK3228_GMAC_RMII_CLK_2_5M | 368 RK3228_GMAC_SPEED_10M); 369 else if (speed == 100) 370 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 371 RK3228_GMAC_RMII_CLK_25M | 372 RK3228_GMAC_SPEED_100M); 373 else 374 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 375 } 376 377 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 378 { 379 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 380 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 381 } 382 383 static const struct rk_gmac_ops rk3228_ops = { 384 .set_to_rgmii = rk3228_set_to_rgmii, 385 .set_to_rmii = rk3228_set_to_rmii, 386 .set_rgmii_speed = rk3228_set_rgmii_speed, 387 .set_rmii_speed = rk3228_set_rmii_speed, 388 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 389 }; 390 391 #define RK3288_GRF_SOC_CON1 0x0248 392 #define RK3288_GRF_SOC_CON3 0x0250 393 394 /*RK3288_GRF_SOC_CON1*/ 395 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 396 GRF_CLR_BIT(8)) 397 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 398 GRF_BIT(8)) 399 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 400 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 401 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 402 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 403 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 404 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 405 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 406 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 407 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 408 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 409 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 410 411 /*RK3288_GRF_SOC_CON3*/ 412 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 413 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 414 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 415 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 416 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 417 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 418 419 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 420 int tx_delay, int rx_delay) 421 { 422 struct device *dev = &bsp_priv->pdev->dev; 423 424 if (IS_ERR(bsp_priv->grf)) { 425 dev_err(dev, "Missing rockchip,grf property\n"); 426 return; 427 } 428 429 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 430 RK3288_GMAC_PHY_INTF_SEL_RGMII | 431 RK3288_GMAC_RMII_MODE_CLR); 432 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 433 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 434 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 435 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 436 } 437 438 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 439 { 440 struct device *dev = &bsp_priv->pdev->dev; 441 442 if (IS_ERR(bsp_priv->grf)) { 443 dev_err(dev, "Missing rockchip,grf property\n"); 444 return; 445 } 446 447 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 448 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 449 } 450 451 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 452 { 453 struct device *dev = &bsp_priv->pdev->dev; 454 455 if (IS_ERR(bsp_priv->grf)) { 456 dev_err(dev, "Missing rockchip,grf property\n"); 457 return; 458 } 459 460 if (speed == 10) 461 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 462 RK3288_GMAC_CLK_2_5M); 463 else if (speed == 100) 464 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 465 RK3288_GMAC_CLK_25M); 466 else if (speed == 1000) 467 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 468 RK3288_GMAC_CLK_125M); 469 else 470 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 471 } 472 473 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 474 { 475 struct device *dev = &bsp_priv->pdev->dev; 476 477 if (IS_ERR(bsp_priv->grf)) { 478 dev_err(dev, "Missing rockchip,grf property\n"); 479 return; 480 } 481 482 if (speed == 10) { 483 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 484 RK3288_GMAC_RMII_CLK_2_5M | 485 RK3288_GMAC_SPEED_10M); 486 } else if (speed == 100) { 487 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 488 RK3288_GMAC_RMII_CLK_25M | 489 RK3288_GMAC_SPEED_100M); 490 } else { 491 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 492 } 493 } 494 495 static const struct rk_gmac_ops rk3288_ops = { 496 .set_to_rgmii = rk3288_set_to_rgmii, 497 .set_to_rmii = rk3288_set_to_rmii, 498 .set_rgmii_speed = rk3288_set_rgmii_speed, 499 .set_rmii_speed = rk3288_set_rmii_speed, 500 }; 501 502 #define RK3308_GRF_MAC_CON0 0x04a0 503 504 /* RK3308_GRF_MAC_CON0 */ 505 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ 506 GRF_BIT(4)) 507 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 508 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 509 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 510 #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 511 512 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 513 { 514 struct device *dev = &bsp_priv->pdev->dev; 515 516 if (IS_ERR(bsp_priv->grf)) { 517 dev_err(dev, "Missing rockchip,grf property\n"); 518 return; 519 } 520 521 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 522 RK3308_GMAC_PHY_INTF_SEL_RMII); 523 } 524 525 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 526 { 527 struct device *dev = &bsp_priv->pdev->dev; 528 529 if (IS_ERR(bsp_priv->grf)) { 530 dev_err(dev, "Missing rockchip,grf property\n"); 531 return; 532 } 533 534 if (speed == 10) { 535 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 536 RK3308_GMAC_SPEED_10M); 537 } else if (speed == 100) { 538 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 539 RK3308_GMAC_SPEED_100M); 540 } else { 541 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 542 } 543 } 544 545 static const struct rk_gmac_ops rk3308_ops = { 546 .set_to_rmii = rk3308_set_to_rmii, 547 .set_rmii_speed = rk3308_set_rmii_speed, 548 }; 549 550 #define RK3328_GRF_MAC_CON0 0x0900 551 #define RK3328_GRF_MAC_CON1 0x0904 552 #define RK3328_GRF_MAC_CON2 0x0908 553 #define RK3328_GRF_MACPHY_CON1 0xb04 554 555 /* RK3328_GRF_MAC_CON0 */ 556 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 557 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 558 559 /* RK3328_GRF_MAC_CON1 */ 560 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 561 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 562 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 563 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 564 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 565 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 566 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 567 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 568 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 569 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 570 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 571 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 572 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 573 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 574 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 575 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 576 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 577 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 578 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 579 580 /* RK3328_GRF_MACPHY_CON1 */ 581 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 582 583 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 584 int tx_delay, int rx_delay) 585 { 586 struct device *dev = &bsp_priv->pdev->dev; 587 588 if (IS_ERR(bsp_priv->grf)) { 589 dev_err(dev, "Missing rockchip,grf property\n"); 590 return; 591 } 592 593 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 594 RK3328_GMAC_PHY_INTF_SEL_RGMII | 595 RK3328_GMAC_RMII_MODE_CLR | 596 RK3328_GMAC_RXCLK_DLY_ENABLE | 597 RK3328_GMAC_TXCLK_DLY_ENABLE); 598 599 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 600 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 601 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 602 } 603 604 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 605 { 606 struct device *dev = &bsp_priv->pdev->dev; 607 unsigned int reg; 608 609 if (IS_ERR(bsp_priv->grf)) { 610 dev_err(dev, "Missing rockchip,grf property\n"); 611 return; 612 } 613 614 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 615 RK3328_GRF_MAC_CON1; 616 617 regmap_write(bsp_priv->grf, reg, 618 RK3328_GMAC_PHY_INTF_SEL_RMII | 619 RK3328_GMAC_RMII_MODE); 620 } 621 622 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 623 { 624 struct device *dev = &bsp_priv->pdev->dev; 625 626 if (IS_ERR(bsp_priv->grf)) { 627 dev_err(dev, "Missing rockchip,grf property\n"); 628 return; 629 } 630 631 if (speed == 10) 632 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 633 RK3328_GMAC_CLK_2_5M); 634 else if (speed == 100) 635 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 636 RK3328_GMAC_CLK_25M); 637 else if (speed == 1000) 638 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 639 RK3328_GMAC_CLK_125M); 640 else 641 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 642 } 643 644 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 645 { 646 struct device *dev = &bsp_priv->pdev->dev; 647 unsigned int reg; 648 649 if (IS_ERR(bsp_priv->grf)) { 650 dev_err(dev, "Missing rockchip,grf property\n"); 651 return; 652 } 653 654 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 655 RK3328_GRF_MAC_CON1; 656 657 if (speed == 10) 658 regmap_write(bsp_priv->grf, reg, 659 RK3328_GMAC_RMII_CLK_2_5M | 660 RK3328_GMAC_SPEED_10M); 661 else if (speed == 100) 662 regmap_write(bsp_priv->grf, reg, 663 RK3328_GMAC_RMII_CLK_25M | 664 RK3328_GMAC_SPEED_100M); 665 else 666 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 667 } 668 669 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 670 { 671 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 672 RK3328_MACPHY_RMII_MODE); 673 } 674 675 static const struct rk_gmac_ops rk3328_ops = { 676 .set_to_rgmii = rk3328_set_to_rgmii, 677 .set_to_rmii = rk3328_set_to_rmii, 678 .set_rgmii_speed = rk3328_set_rgmii_speed, 679 .set_rmii_speed = rk3328_set_rmii_speed, 680 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 681 }; 682 683 #define RK3366_GRF_SOC_CON6 0x0418 684 #define RK3366_GRF_SOC_CON7 0x041c 685 686 /* RK3366_GRF_SOC_CON6 */ 687 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 688 GRF_CLR_BIT(11)) 689 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 690 GRF_BIT(11)) 691 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 692 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 693 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 694 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 695 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 696 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 697 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 698 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 699 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 700 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 701 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 702 703 /* RK3366_GRF_SOC_CON7 */ 704 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 705 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 706 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 707 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 708 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 709 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 710 711 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 712 int tx_delay, int rx_delay) 713 { 714 struct device *dev = &bsp_priv->pdev->dev; 715 716 if (IS_ERR(bsp_priv->grf)) { 717 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 718 return; 719 } 720 721 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 722 RK3366_GMAC_PHY_INTF_SEL_RGMII | 723 RK3366_GMAC_RMII_MODE_CLR); 724 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 725 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 726 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 727 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 728 } 729 730 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 731 { 732 struct device *dev = &bsp_priv->pdev->dev; 733 734 if (IS_ERR(bsp_priv->grf)) { 735 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 736 return; 737 } 738 739 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 740 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 741 } 742 743 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 744 { 745 struct device *dev = &bsp_priv->pdev->dev; 746 747 if (IS_ERR(bsp_priv->grf)) { 748 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 749 return; 750 } 751 752 if (speed == 10) 753 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 754 RK3366_GMAC_CLK_2_5M); 755 else if (speed == 100) 756 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 757 RK3366_GMAC_CLK_25M); 758 else if (speed == 1000) 759 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 760 RK3366_GMAC_CLK_125M); 761 else 762 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 763 } 764 765 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 766 { 767 struct device *dev = &bsp_priv->pdev->dev; 768 769 if (IS_ERR(bsp_priv->grf)) { 770 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 771 return; 772 } 773 774 if (speed == 10) { 775 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 776 RK3366_GMAC_RMII_CLK_2_5M | 777 RK3366_GMAC_SPEED_10M); 778 } else if (speed == 100) { 779 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 780 RK3366_GMAC_RMII_CLK_25M | 781 RK3366_GMAC_SPEED_100M); 782 } else { 783 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 784 } 785 } 786 787 static const struct rk_gmac_ops rk3366_ops = { 788 .set_to_rgmii = rk3366_set_to_rgmii, 789 .set_to_rmii = rk3366_set_to_rmii, 790 .set_rgmii_speed = rk3366_set_rgmii_speed, 791 .set_rmii_speed = rk3366_set_rmii_speed, 792 }; 793 794 #define RK3368_GRF_SOC_CON15 0x043c 795 #define RK3368_GRF_SOC_CON16 0x0440 796 797 /* RK3368_GRF_SOC_CON15 */ 798 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 799 GRF_CLR_BIT(11)) 800 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 801 GRF_BIT(11)) 802 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 803 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 804 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 805 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 806 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 807 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 808 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 809 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 810 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 811 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 812 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 813 814 /* RK3368_GRF_SOC_CON16 */ 815 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 816 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 817 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 818 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 819 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 820 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 821 822 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 823 int tx_delay, int rx_delay) 824 { 825 struct device *dev = &bsp_priv->pdev->dev; 826 827 if (IS_ERR(bsp_priv->grf)) { 828 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 829 return; 830 } 831 832 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 833 RK3368_GMAC_PHY_INTF_SEL_RGMII | 834 RK3368_GMAC_RMII_MODE_CLR); 835 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 836 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 837 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 838 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 839 } 840 841 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 842 { 843 struct device *dev = &bsp_priv->pdev->dev; 844 845 if (IS_ERR(bsp_priv->grf)) { 846 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 847 return; 848 } 849 850 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 851 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 852 } 853 854 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 855 { 856 struct device *dev = &bsp_priv->pdev->dev; 857 858 if (IS_ERR(bsp_priv->grf)) { 859 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 860 return; 861 } 862 863 if (speed == 10) 864 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 865 RK3368_GMAC_CLK_2_5M); 866 else if (speed == 100) 867 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 868 RK3368_GMAC_CLK_25M); 869 else if (speed == 1000) 870 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 871 RK3368_GMAC_CLK_125M); 872 else 873 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 874 } 875 876 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 877 { 878 struct device *dev = &bsp_priv->pdev->dev; 879 880 if (IS_ERR(bsp_priv->grf)) { 881 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 882 return; 883 } 884 885 if (speed == 10) { 886 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 887 RK3368_GMAC_RMII_CLK_2_5M | 888 RK3368_GMAC_SPEED_10M); 889 } else if (speed == 100) { 890 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 891 RK3368_GMAC_RMII_CLK_25M | 892 RK3368_GMAC_SPEED_100M); 893 } else { 894 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 895 } 896 } 897 898 static const struct rk_gmac_ops rk3368_ops = { 899 .set_to_rgmii = rk3368_set_to_rgmii, 900 .set_to_rmii = rk3368_set_to_rmii, 901 .set_rgmii_speed = rk3368_set_rgmii_speed, 902 .set_rmii_speed = rk3368_set_rmii_speed, 903 }; 904 905 #define RK3399_GRF_SOC_CON5 0xc214 906 #define RK3399_GRF_SOC_CON6 0xc218 907 908 /* RK3399_GRF_SOC_CON5 */ 909 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 910 GRF_CLR_BIT(11)) 911 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 912 GRF_BIT(11)) 913 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 914 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 915 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 916 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 917 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 918 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 919 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 920 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 921 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 922 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 923 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 924 925 /* RK3399_GRF_SOC_CON6 */ 926 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 927 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 928 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 929 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 930 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 931 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 932 933 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 934 int tx_delay, int rx_delay) 935 { 936 struct device *dev = &bsp_priv->pdev->dev; 937 938 if (IS_ERR(bsp_priv->grf)) { 939 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 940 return; 941 } 942 943 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 944 RK3399_GMAC_PHY_INTF_SEL_RGMII | 945 RK3399_GMAC_RMII_MODE_CLR); 946 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 947 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 948 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 949 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 950 } 951 952 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 953 { 954 struct device *dev = &bsp_priv->pdev->dev; 955 956 if (IS_ERR(bsp_priv->grf)) { 957 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 958 return; 959 } 960 961 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 962 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 963 } 964 965 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 966 { 967 struct device *dev = &bsp_priv->pdev->dev; 968 969 if (IS_ERR(bsp_priv->grf)) { 970 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 971 return; 972 } 973 974 if (speed == 10) 975 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 976 RK3399_GMAC_CLK_2_5M); 977 else if (speed == 100) 978 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 979 RK3399_GMAC_CLK_25M); 980 else if (speed == 1000) 981 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 982 RK3399_GMAC_CLK_125M); 983 else 984 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 985 } 986 987 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 988 { 989 struct device *dev = &bsp_priv->pdev->dev; 990 991 if (IS_ERR(bsp_priv->grf)) { 992 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 993 return; 994 } 995 996 if (speed == 10) { 997 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 998 RK3399_GMAC_RMII_CLK_2_5M | 999 RK3399_GMAC_SPEED_10M); 1000 } else if (speed == 100) { 1001 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 1002 RK3399_GMAC_RMII_CLK_25M | 1003 RK3399_GMAC_SPEED_100M); 1004 } else { 1005 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 1006 } 1007 } 1008 1009 static const struct rk_gmac_ops rk3399_ops = { 1010 .set_to_rgmii = rk3399_set_to_rgmii, 1011 .set_to_rmii = rk3399_set_to_rmii, 1012 .set_rgmii_speed = rk3399_set_rgmii_speed, 1013 .set_rmii_speed = rk3399_set_rmii_speed, 1014 }; 1015 1016 #define RK3568_GRF_GMAC0_CON0 0x0380 1017 #define RK3568_GRF_GMAC0_CON1 0x0384 1018 #define RK3568_GRF_GMAC1_CON0 0x0388 1019 #define RK3568_GRF_GMAC1_CON1 0x038c 1020 1021 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 1022 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ 1023 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1024 #define RK3568_GMAC_PHY_INTF_SEL_RMII \ 1025 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1026 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 1027 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1028 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 1029 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1030 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 1031 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1032 1033 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 1034 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1035 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1036 1037 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 1038 int tx_delay, int rx_delay) 1039 { 1040 struct device *dev = &bsp_priv->pdev->dev; 1041 u32 con0, con1; 1042 1043 if (IS_ERR(bsp_priv->grf)) { 1044 dev_err(dev, "Missing rockchip,grf property\n"); 1045 return; 1046 } 1047 1048 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : 1049 RK3568_GRF_GMAC0_CON0; 1050 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1051 RK3568_GRF_GMAC0_CON1; 1052 1053 regmap_write(bsp_priv->grf, con0, 1054 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | 1055 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 1056 1057 regmap_write(bsp_priv->grf, con1, 1058 RK3568_GMAC_PHY_INTF_SEL_RGMII | 1059 RK3568_GMAC_RXCLK_DLY_ENABLE | 1060 RK3568_GMAC_TXCLK_DLY_ENABLE); 1061 } 1062 1063 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 1064 { 1065 struct device *dev = &bsp_priv->pdev->dev; 1066 u32 con1; 1067 1068 if (IS_ERR(bsp_priv->grf)) { 1069 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1070 return; 1071 } 1072 1073 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 1074 RK3568_GRF_GMAC0_CON1; 1075 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); 1076 } 1077 1078 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 1079 { 1080 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1081 struct device *dev = &bsp_priv->pdev->dev; 1082 unsigned long rate; 1083 int ret; 1084 1085 switch (speed) { 1086 case 10: 1087 rate = 2500000; 1088 break; 1089 case 100: 1090 rate = 25000000; 1091 break; 1092 case 1000: 1093 rate = 125000000; 1094 break; 1095 default: 1096 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1097 return; 1098 } 1099 1100 ret = clk_set_rate(clk_mac_speed, rate); 1101 if (ret) 1102 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1103 __func__, rate, ret); 1104 } 1105 1106 static const struct rk_gmac_ops rk3568_ops = { 1107 .set_to_rgmii = rk3568_set_to_rgmii, 1108 .set_to_rmii = rk3568_set_to_rmii, 1109 .set_rgmii_speed = rk3568_set_gmac_speed, 1110 .set_rmii_speed = rk3568_set_gmac_speed, 1111 .regs_valid = true, 1112 .regs = { 1113 0xfe2a0000, /* gmac0 */ 1114 0xfe010000, /* gmac1 */ 1115 0x0, /* sentinel */ 1116 }, 1117 }; 1118 1119 /* sys_grf */ 1120 #define RK3588_GRF_GMAC_CON7 0X031c 1121 #define RK3588_GRF_GMAC_CON8 0X0320 1122 #define RK3588_GRF_GMAC_CON9 0X0324 1123 1124 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) 1125 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) 1126 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) 1127 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) 1128 1129 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) 1130 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) 1131 1132 /* php_grf */ 1133 #define RK3588_GRF_GMAC_CON0 0X0008 1134 #define RK3588_GRF_CLK_CON1 0X0070 1135 1136 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ 1137 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) 1138 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ 1139 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) 1140 1141 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1142 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1143 1144 #define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4) 1145 #define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1146 1147 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1148 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1149 1150 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1151 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) 1152 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1153 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1154 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1155 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) 1156 1157 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1158 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1159 1160 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1161 int tx_delay, int rx_delay) 1162 { 1163 struct device *dev = &bsp_priv->pdev->dev; 1164 u32 offset_con, id = bsp_priv->id; 1165 1166 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { 1167 dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); 1168 return; 1169 } 1170 1171 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1172 RK3588_GRF_GMAC_CON8; 1173 1174 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1175 RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); 1176 1177 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1178 RK3588_GMAC_CLK_RGMII_MODE(id)); 1179 1180 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, 1181 RK3588_GMAC_RXCLK_DLY_ENABLE(id) | 1182 RK3588_GMAC_TXCLK_DLY_ENABLE(id)); 1183 1184 regmap_write(bsp_priv->grf, offset_con, 1185 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | 1186 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); 1187 } 1188 1189 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1190 { 1191 struct device *dev = &bsp_priv->pdev->dev; 1192 1193 if (IS_ERR(bsp_priv->php_grf)) { 1194 dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__); 1195 return; 1196 } 1197 1198 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1199 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); 1200 1201 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1202 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1203 } 1204 1205 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) 1206 { 1207 struct device *dev = &bsp_priv->pdev->dev; 1208 unsigned int val = 0, id = bsp_priv->id; 1209 1210 switch (speed) { 1211 case 10: 1212 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1213 val = RK3588_GMA_CLK_RMII_DIV20(id); 1214 else 1215 val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1216 break; 1217 case 100: 1218 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1219 val = RK3588_GMA_CLK_RMII_DIV2(id); 1220 else 1221 val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1222 break; 1223 case 1000: 1224 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) 1225 val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1226 else 1227 goto err; 1228 break; 1229 default: 1230 goto err; 1231 } 1232 1233 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1234 1235 return; 1236 err: 1237 dev_err(dev, "unknown speed value for GMAC speed=%d", speed); 1238 } 1239 1240 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, 1241 bool enable) 1242 { 1243 unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) : 1244 RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id); 1245 1246 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : 1247 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); 1248 1249 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1250 } 1251 1252 static const struct rk_gmac_ops rk3588_ops = { 1253 .set_to_rgmii = rk3588_set_to_rgmii, 1254 .set_to_rmii = rk3588_set_to_rmii, 1255 .set_rgmii_speed = rk3588_set_gmac_speed, 1256 .set_rmii_speed = rk3588_set_gmac_speed, 1257 .set_clock_selection = rk3588_set_clock_selection, 1258 .regs_valid = true, 1259 .regs = { 1260 0xfe1b0000, /* gmac0 */ 1261 0xfe1c0000, /* gmac1 */ 1262 0x0, /* sentinel */ 1263 }, 1264 }; 1265 1266 #define RV1108_GRF_GMAC_CON0 0X0900 1267 1268 /* RV1108_GRF_GMAC_CON0 */ 1269 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 1270 GRF_BIT(6)) 1271 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1272 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1273 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1274 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1275 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1276 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1277 1278 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1279 { 1280 struct device *dev = &bsp_priv->pdev->dev; 1281 1282 if (IS_ERR(bsp_priv->grf)) { 1283 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1284 return; 1285 } 1286 1287 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1288 RV1108_GMAC_PHY_INTF_SEL_RMII); 1289 } 1290 1291 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 1292 { 1293 struct device *dev = &bsp_priv->pdev->dev; 1294 1295 if (IS_ERR(bsp_priv->grf)) { 1296 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1297 return; 1298 } 1299 1300 if (speed == 10) { 1301 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1302 RV1108_GMAC_RMII_CLK_2_5M | 1303 RV1108_GMAC_SPEED_10M); 1304 } else if (speed == 100) { 1305 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1306 RV1108_GMAC_RMII_CLK_25M | 1307 RV1108_GMAC_SPEED_100M); 1308 } else { 1309 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 1310 } 1311 } 1312 1313 static const struct rk_gmac_ops rv1108_ops = { 1314 .set_to_rmii = rv1108_set_to_rmii, 1315 .set_rmii_speed = rv1108_set_rmii_speed, 1316 }; 1317 1318 #define RV1126_GRF_GMAC_CON0 0X0070 1319 #define RV1126_GRF_GMAC_CON1 0X0074 1320 #define RV1126_GRF_GMAC_CON2 0X0078 1321 1322 /* RV1126_GRF_GMAC_CON0 */ 1323 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ 1324 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 1325 #define RV1126_GMAC_PHY_INTF_SEL_RMII \ 1326 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 1327 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1328 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1329 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) 1330 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 1331 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) 1332 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 1333 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) 1334 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) 1335 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) 1336 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) 1337 1338 /* RV1126_GRF_GMAC_CON1 */ 1339 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1340 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1341 /* RV1126_GRF_GMAC_CON2 */ 1342 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 1343 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 1344 1345 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, 1346 int tx_delay, int rx_delay) 1347 { 1348 struct device *dev = &bsp_priv->pdev->dev; 1349 1350 if (IS_ERR(bsp_priv->grf)) { 1351 dev_err(dev, "Missing rockchip,grf property\n"); 1352 return; 1353 } 1354 1355 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1356 RV1126_GMAC_PHY_INTF_SEL_RGMII | 1357 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1358 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1359 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | 1360 RV1126_GMAC_M1_TXCLK_DLY_ENABLE); 1361 1362 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, 1363 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | 1364 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); 1365 1366 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, 1367 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | 1368 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); 1369 } 1370 1371 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1372 { 1373 struct device *dev = &bsp_priv->pdev->dev; 1374 1375 if (IS_ERR(bsp_priv->grf)) { 1376 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 1377 return; 1378 } 1379 1380 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1381 RV1126_GMAC_PHY_INTF_SEL_RMII); 1382 } 1383 1384 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 1385 { 1386 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1387 struct device *dev = &bsp_priv->pdev->dev; 1388 unsigned long rate; 1389 int ret; 1390 1391 switch (speed) { 1392 case 10: 1393 rate = 2500000; 1394 break; 1395 case 100: 1396 rate = 25000000; 1397 break; 1398 case 1000: 1399 rate = 125000000; 1400 break; 1401 default: 1402 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); 1403 return; 1404 } 1405 1406 ret = clk_set_rate(clk_mac_speed, rate); 1407 if (ret) 1408 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1409 __func__, rate, ret); 1410 } 1411 1412 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 1413 { 1414 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 1415 struct device *dev = &bsp_priv->pdev->dev; 1416 unsigned long rate; 1417 int ret; 1418 1419 switch (speed) { 1420 case 10: 1421 rate = 2500000; 1422 break; 1423 case 100: 1424 rate = 25000000; 1425 break; 1426 default: 1427 dev_err(dev, "unknown speed value for RGMII speed=%d", speed); 1428 return; 1429 } 1430 1431 ret = clk_set_rate(clk_mac_speed, rate); 1432 if (ret) 1433 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", 1434 __func__, rate, ret); 1435 } 1436 1437 static const struct rk_gmac_ops rv1126_ops = { 1438 .set_to_rgmii = rv1126_set_to_rgmii, 1439 .set_to_rmii = rv1126_set_to_rmii, 1440 .set_rgmii_speed = rv1126_set_rgmii_speed, 1441 .set_rmii_speed = rv1126_set_rmii_speed, 1442 }; 1443 1444 #define RK_GRF_MACPHY_CON0 0xb00 1445 #define RK_GRF_MACPHY_CON1 0xb04 1446 #define RK_GRF_MACPHY_CON2 0xb08 1447 #define RK_GRF_MACPHY_CON3 0xb0c 1448 1449 #define RK_MACPHY_ENABLE GRF_BIT(0) 1450 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 1451 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 1452 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 1453 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 1454 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 1455 1456 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) 1457 { 1458 if (priv->ops->integrated_phy_powerup) 1459 priv->ops->integrated_phy_powerup(priv); 1460 1461 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 1462 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 1463 1464 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 1465 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 1466 1467 if (priv->phy_reset) { 1468 /* PHY needs to be disabled before trying to reset it */ 1469 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1470 if (priv->phy_reset) 1471 reset_control_assert(priv->phy_reset); 1472 usleep_range(10, 20); 1473 if (priv->phy_reset) 1474 reset_control_deassert(priv->phy_reset); 1475 usleep_range(10, 20); 1476 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 1477 msleep(30); 1478 } 1479 } 1480 1481 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) 1482 { 1483 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1484 if (priv->phy_reset) 1485 reset_control_assert(priv->phy_reset); 1486 } 1487 1488 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1489 { 1490 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1491 struct device *dev = &bsp_priv->pdev->dev; 1492 int phy_iface = bsp_priv->phy_iface; 1493 int i, j, ret; 1494 1495 bsp_priv->clk_enabled = false; 1496 1497 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); 1498 if (phy_iface == PHY_INTERFACE_MODE_RMII) 1499 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); 1500 1501 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, 1502 sizeof(*bsp_priv->clks), GFP_KERNEL); 1503 if (!bsp_priv->clks) 1504 return -ENOMEM; 1505 1506 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) 1507 bsp_priv->clks[i].id = rk_clocks[i]; 1508 1509 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1510 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) 1511 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; 1512 } 1513 1514 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, 1515 bsp_priv->clks); 1516 if (ret) 1517 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1518 1519 /* "stmmaceth" will be enabled by the core */ 1520 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 1521 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac); 1522 if (ret) 1523 return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n"); 1524 1525 if (bsp_priv->clock_input) { 1526 dev_info(dev, "clock input from PHY\n"); 1527 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1528 clk_set_rate(bsp_priv->clk_mac, 50000000); 1529 } 1530 1531 if (plat->phy_node && bsp_priv->integrated_phy) { 1532 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1533 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); 1534 if (ret) 1535 return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); 1536 clk_set_rate(bsp_priv->clk_phy, 50000000); 1537 } 1538 1539 return 0; 1540 } 1541 1542 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1543 { 1544 int ret; 1545 1546 if (enable) { 1547 if (!bsp_priv->clk_enabled) { 1548 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, 1549 bsp_priv->clks); 1550 if (ret) 1551 return ret; 1552 1553 ret = clk_prepare_enable(bsp_priv->clk_phy); 1554 if (ret) 1555 return ret; 1556 1557 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1558 bsp_priv->ops->set_clock_selection(bsp_priv, 1559 bsp_priv->clock_input, true); 1560 1561 mdelay(5); 1562 bsp_priv->clk_enabled = true; 1563 } 1564 } else { 1565 if (bsp_priv->clk_enabled) { 1566 clk_bulk_disable_unprepare(bsp_priv->num_clks, 1567 bsp_priv->clks); 1568 clk_disable_unprepare(bsp_priv->clk_phy); 1569 1570 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) 1571 bsp_priv->ops->set_clock_selection(bsp_priv, 1572 bsp_priv->clock_input, false); 1573 1574 bsp_priv->clk_enabled = false; 1575 } 1576 } 1577 1578 return 0; 1579 } 1580 1581 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1582 { 1583 struct regulator *ldo = bsp_priv->regulator; 1584 int ret; 1585 struct device *dev = &bsp_priv->pdev->dev; 1586 1587 if (enable) { 1588 ret = regulator_enable(ldo); 1589 if (ret) 1590 dev_err(dev, "fail to enable phy-supply\n"); 1591 } else { 1592 ret = regulator_disable(ldo); 1593 if (ret) 1594 dev_err(dev, "fail to disable phy-supply\n"); 1595 } 1596 1597 return 0; 1598 } 1599 1600 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1601 struct plat_stmmacenet_data *plat, 1602 const struct rk_gmac_ops *ops) 1603 { 1604 struct rk_priv_data *bsp_priv; 1605 struct device *dev = &pdev->dev; 1606 struct resource *res; 1607 int ret; 1608 const char *strings = NULL; 1609 int value; 1610 1611 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1612 if (!bsp_priv) 1613 return ERR_PTR(-ENOMEM); 1614 1615 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface); 1616 bsp_priv->ops = ops; 1617 1618 /* Some SoCs have multiple MAC controllers, which need 1619 * to be distinguished. 1620 */ 1621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1622 if (res && ops->regs_valid) { 1623 int i = 0; 1624 1625 while (ops->regs[i]) { 1626 if (ops->regs[i] == res->start) { 1627 bsp_priv->id = i; 1628 break; 1629 } 1630 i++; 1631 } 1632 } 1633 1634 bsp_priv->regulator = devm_regulator_get(dev, "phy"); 1635 if (IS_ERR(bsp_priv->regulator)) { 1636 ret = PTR_ERR(bsp_priv->regulator); 1637 dev_err_probe(dev, ret, "failed to get phy regulator\n"); 1638 return ERR_PTR(ret); 1639 } 1640 1641 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1642 if (ret) { 1643 dev_err(dev, "Can not read property: clock_in_out.\n"); 1644 bsp_priv->clock_input = true; 1645 } else { 1646 dev_info(dev, "clock input or output? (%s).\n", 1647 strings); 1648 if (!strcmp(strings, "input")) 1649 bsp_priv->clock_input = true; 1650 else 1651 bsp_priv->clock_input = false; 1652 } 1653 1654 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1655 if (ret) { 1656 bsp_priv->tx_delay = 0x30; 1657 dev_err(dev, "Can not read property: tx_delay."); 1658 dev_err(dev, "set tx_delay to 0x%x\n", 1659 bsp_priv->tx_delay); 1660 } else { 1661 dev_info(dev, "TX delay(0x%x).\n", value); 1662 bsp_priv->tx_delay = value; 1663 } 1664 1665 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1666 if (ret) { 1667 bsp_priv->rx_delay = 0x10; 1668 dev_err(dev, "Can not read property: rx_delay."); 1669 dev_err(dev, "set rx_delay to 0x%x\n", 1670 bsp_priv->rx_delay); 1671 } else { 1672 dev_info(dev, "RX delay(0x%x).\n", value); 1673 bsp_priv->rx_delay = value; 1674 } 1675 1676 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1677 "rockchip,grf"); 1678 bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1679 "rockchip,php-grf"); 1680 1681 if (plat->phy_node) { 1682 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1683 "phy-is-integrated"); 1684 if (bsp_priv->integrated_phy) { 1685 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1686 if (IS_ERR(bsp_priv->phy_reset)) { 1687 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1688 bsp_priv->phy_reset = NULL; 1689 } 1690 } 1691 } 1692 dev_info(dev, "integrated PHY? (%s).\n", 1693 bsp_priv->integrated_phy ? "yes" : "no"); 1694 1695 bsp_priv->pdev = pdev; 1696 1697 return bsp_priv; 1698 } 1699 1700 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) 1701 { 1702 switch (bsp_priv->phy_iface) { 1703 case PHY_INTERFACE_MODE_RGMII: 1704 case PHY_INTERFACE_MODE_RGMII_ID: 1705 case PHY_INTERFACE_MODE_RGMII_RXID: 1706 case PHY_INTERFACE_MODE_RGMII_TXID: 1707 if (!bsp_priv->ops->set_to_rgmii) 1708 return -EINVAL; 1709 break; 1710 case PHY_INTERFACE_MODE_RMII: 1711 if (!bsp_priv->ops->set_to_rmii) 1712 return -EINVAL; 1713 break; 1714 default: 1715 dev_err(&bsp_priv->pdev->dev, 1716 "unsupported interface %d", bsp_priv->phy_iface); 1717 } 1718 return 0; 1719 } 1720 1721 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1722 { 1723 int ret; 1724 struct device *dev = &bsp_priv->pdev->dev; 1725 1726 ret = rk_gmac_check_ops(bsp_priv); 1727 if (ret) 1728 return ret; 1729 1730 ret = gmac_clk_enable(bsp_priv, true); 1731 if (ret) 1732 return ret; 1733 1734 /*rmii or rgmii*/ 1735 switch (bsp_priv->phy_iface) { 1736 case PHY_INTERFACE_MODE_RGMII: 1737 dev_info(dev, "init for RGMII\n"); 1738 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1739 bsp_priv->rx_delay); 1740 break; 1741 case PHY_INTERFACE_MODE_RGMII_ID: 1742 dev_info(dev, "init for RGMII_ID\n"); 1743 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1744 break; 1745 case PHY_INTERFACE_MODE_RGMII_RXID: 1746 dev_info(dev, "init for RGMII_RXID\n"); 1747 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1748 break; 1749 case PHY_INTERFACE_MODE_RGMII_TXID: 1750 dev_info(dev, "init for RGMII_TXID\n"); 1751 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1752 break; 1753 case PHY_INTERFACE_MODE_RMII: 1754 dev_info(dev, "init for RMII\n"); 1755 bsp_priv->ops->set_to_rmii(bsp_priv); 1756 break; 1757 default: 1758 dev_err(dev, "NO interface defined!\n"); 1759 } 1760 1761 ret = phy_power_on(bsp_priv, true); 1762 if (ret) { 1763 gmac_clk_enable(bsp_priv, false); 1764 return ret; 1765 } 1766 1767 pm_runtime_get_sync(dev); 1768 1769 if (bsp_priv->integrated_phy) 1770 rk_gmac_integrated_phy_powerup(bsp_priv); 1771 1772 return 0; 1773 } 1774 1775 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1776 { 1777 if (gmac->integrated_phy) 1778 rk_gmac_integrated_phy_powerdown(gmac); 1779 1780 pm_runtime_put_sync(&gmac->pdev->dev); 1781 1782 phy_power_on(gmac, false); 1783 gmac_clk_enable(gmac, false); 1784 } 1785 1786 static void rk_fix_speed(void *priv, unsigned int speed, unsigned int mode) 1787 { 1788 struct rk_priv_data *bsp_priv = priv; 1789 struct device *dev = &bsp_priv->pdev->dev; 1790 1791 switch (bsp_priv->phy_iface) { 1792 case PHY_INTERFACE_MODE_RGMII: 1793 case PHY_INTERFACE_MODE_RGMII_ID: 1794 case PHY_INTERFACE_MODE_RGMII_RXID: 1795 case PHY_INTERFACE_MODE_RGMII_TXID: 1796 if (bsp_priv->ops->set_rgmii_speed) 1797 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 1798 break; 1799 case PHY_INTERFACE_MODE_RMII: 1800 if (bsp_priv->ops->set_rmii_speed) 1801 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 1802 break; 1803 default: 1804 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 1805 } 1806 } 1807 1808 static int rk_gmac_probe(struct platform_device *pdev) 1809 { 1810 struct plat_stmmacenet_data *plat_dat; 1811 struct stmmac_resources stmmac_res; 1812 const struct rk_gmac_ops *data; 1813 int ret; 1814 1815 data = of_device_get_match_data(&pdev->dev); 1816 if (!data) { 1817 dev_err(&pdev->dev, "no of match data provided\n"); 1818 return -EINVAL; 1819 } 1820 1821 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1822 if (ret) 1823 return ret; 1824 1825 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 1826 if (IS_ERR(plat_dat)) 1827 return PTR_ERR(plat_dat); 1828 1829 /* If the stmmac is not already selected as gmac4, 1830 * then make sure we fallback to gmac. 1831 */ 1832 if (!plat_dat->has_gmac4) 1833 plat_dat->has_gmac = true; 1834 plat_dat->fix_mac_speed = rk_fix_speed; 1835 1836 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1837 if (IS_ERR(plat_dat->bsp_priv)) 1838 return PTR_ERR(plat_dat->bsp_priv); 1839 1840 ret = rk_gmac_clk_init(plat_dat); 1841 if (ret) 1842 return ret; 1843 1844 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1845 if (ret) 1846 return ret; 1847 1848 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1849 if (ret) 1850 goto err_gmac_powerdown; 1851 1852 return 0; 1853 1854 err_gmac_powerdown: 1855 rk_gmac_powerdown(plat_dat->bsp_priv); 1856 1857 return ret; 1858 } 1859 1860 static void rk_gmac_remove(struct platform_device *pdev) 1861 { 1862 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 1863 1864 stmmac_dvr_remove(&pdev->dev); 1865 1866 rk_gmac_powerdown(bsp_priv); 1867 } 1868 1869 #ifdef CONFIG_PM_SLEEP 1870 static int rk_gmac_suspend(struct device *dev) 1871 { 1872 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1873 int ret = stmmac_suspend(dev); 1874 1875 /* Keep the PHY up if we use Wake-on-Lan. */ 1876 if (!device_may_wakeup(dev)) { 1877 rk_gmac_powerdown(bsp_priv); 1878 bsp_priv->suspended = true; 1879 } 1880 1881 return ret; 1882 } 1883 1884 static int rk_gmac_resume(struct device *dev) 1885 { 1886 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1887 1888 /* The PHY was up for Wake-on-Lan. */ 1889 if (bsp_priv->suspended) { 1890 rk_gmac_powerup(bsp_priv); 1891 bsp_priv->suspended = false; 1892 } 1893 1894 return stmmac_resume(dev); 1895 } 1896 #endif /* CONFIG_PM_SLEEP */ 1897 1898 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1899 1900 static const struct of_device_id rk_gmac_dwmac_match[] = { 1901 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1902 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1903 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1904 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1905 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops }, 1906 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1907 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1908 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1909 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1910 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, 1911 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, 1912 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1913 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, 1914 { } 1915 }; 1916 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1917 1918 static struct platform_driver rk_gmac_dwmac_driver = { 1919 .probe = rk_gmac_probe, 1920 .remove_new = rk_gmac_remove, 1921 .driver = { 1922 .name = "rk_gmac-dwmac", 1923 .pm = &rk_gmac_pm_ops, 1924 .of_match_table = rk_gmac_dwmac_match, 1925 }, 1926 }; 1927 module_platform_driver(rk_gmac_dwmac_driver); 1928 1929 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1930 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1931 MODULE_LICENSE("GPL"); 1932